JP2009009264A - Semiconductor device and semiconductor device automatic control method - Google Patents

Abstract

A semiconductor device register is controlled in real time.
A plurality of registers, a command buffer that stores a plurality of commands that control the registers, a command execution circuit that sequentially executes commands stored in the command buffer, control from the outside, and control from the command execution circuit An execution unit selection circuit for switching the data, a data read command for reading the data of the bit width and the effective bit from the data of the address register, a data write command for rewriting the effective bit of the data of the address register to the write data, and an external A simple wait command that waits until the number of clock signals from the clock number reaches the number of clocks, and a state wait command that waits until the valid bits of the address register data and the comparison data are equal, and a plurality of commands Combine the above to control the register To.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device including a plurality of registers and a method for automatically controlling the semiconductor device.

  A semiconductor device such as a USB standard controller has a plurality of registers, and realizes operations by holding control information such as transactions and endpoints in the registers. Conventionally, in order to check the operation of reading data from and writing data to a register of these semiconductor devices, the software installed in the PC is processed by the CPU, so that the original semiconductor The operation time is slower than when the device is operated alone, and it is difficult to keep the specified time when time constraints are severe. In particular, when software that does not have a real-time control function, such as a high-function OS, is used, the hardware that requires real-time control cannot be controlled.

  In order to solve this problem, for example, Patent Document 1 describes a method of tracing data between semiconductor devices.

JP 2001-154930 A

  However, the conventional method focuses on tracing transmission / reception data between apparatuses, and there is a problem that it is not suitable for operation confirmation of a single semiconductor device. In addition, when the register is rewritten by software, there is a problem that rewriting cannot be performed in bit units.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

[Application Example 1]
A semiconductor device including a plurality of registers, a command buffer that stores a plurality of commands that control the registers, a command execution circuit that sequentially executes the commands stored in the command buffer, an external control, and the An execution unit selection circuit that switches control from a command execution circuit.

  According to this configuration, the command for controlling the register can be stored and executed in the command buffer inside the semiconductor device, so that waste of operating time due to the difference in operating speed between the semiconductor device and software can be reduced.

[Application Example 2]
In the semiconductor device described above, the plurality of commands specify an address, a data width, and a valid bit of the register, and a value of the data width and the bit indicated by the valid bit from the register indicated by the address The data read command, the register address, the write data, and the valid bit are designated, and the valid bit of the write data indicates the value of the bit indicated by the valid bit of the register indicated by the address Specify the data write command to rewrite to the bit value, the number of clocks to wait until the next command is executed, the simple wait command to wait until the number of external clock signals reaches the number of clocks, and the address of the register , Comparison data, and valid bit, and It includes a state wait command to the valid bit indicates a bit value of the register indicated by the scan and said valid bit indicates a bit value of the comparison data will wait until it equals the semiconductor device, characterized in that.

  According to this configuration, it is possible to reduce waste of operating time due to a difference in operating speed between the semiconductor device and the software by automatically executing reading, writing, and waiting states of register data. In addition, since the semiconductor device reads, writes, and compares the register data for each bit, the processing can be completed in less than half the operation time compared to when the software performs these processes.

[Application Example 3]
A plurality of registers, a command buffer for storing a plurality of commands for controlling the registers, a command execution circuit for sequentially executing the commands stored in the command buffer, an external control, and a control from the command execution circuit And an execution unit selection circuit for switching the register, wherein the register indicates an address, a data width, and a valid bit as the plurality of commands, and the register indicates the address A data read command for reading the data width and the value of the bit indicated by the valid bit, the register address, the write data, and the valid bit are designated, and the valid bit of the register indicated by the address indicates The value of the bit indicated by the valid bit of the write data The data write command to be rewritten, the number of clocks to wait until the next command is executed, the simple wait command to wait until the number of external clock signals reaches the number of clocks, and the register address are compared. A state wait command that specifies data and a valid bit, and waits until the value of the bit indicated by the valid bit of the register indicated by the address is equal to the value of the bit indicated by the valid bit of the comparison data; And controlling the register by combining one or more of the plurality of commands.

  According to this configuration, it is possible to reduce waste of operating time due to a difference in operating speed between the semiconductor device and the software by automatically executing reading, writing, and waiting states of register data. In addition, since the semiconductor device reads, writes, and compares the register data for each bit, the processing can be completed in less than half the operation time compared to when the software performs these processes.

  Hereinafter, embodiments of a semiconductor device will be described with reference to the drawings.

(First embodiment)
<Configuration of semiconductor device>
First, the configuration of the semiconductor device according to the first embodiment will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of the semiconductor device according to the first embodiment.

  As shown in FIG. 1, the semiconductor device 1 includes a register group 100 including a plurality of registers and assigned addresses for accessing the individual registers, an address signal ADRS from the external CPU 200, a control signal CNTL, and a data signal. It comprises a CPU interface 110 that inputs and outputs DATA, a command buffer 120, a command execution circuit 130, an execution unit selection circuit 140, and a RAM 150 that is used as a work storage area for the command execution circuit 130. .

  The CPU interface 110 outputs a command write signal cWE and a command signal CMND in order to write a plurality of commands to the command buffer 120. Further, the CPU interface 110 outputs a data read signal dRE and inputs a data signal DATA in order to read data from the command buffer 120. Further, the CPU interface 110 outputs a command execution signal RUN to the command execution circuit 130 and the execution unit selection circuit 140 in order to execute the command stored in the command buffer 120.

  The command execution circuit 130 outputs a command read signal cRE to the command buffer 120 to execute a plurality of commands in the command buffer 120 when the command execution signal RUN is enabled, and the command buffer 120 receives the command from the command buffer 120. The signal CMND is input. The command execution circuit 130 executes a command based on an external clock signal CLK, and inputs / outputs an address signal ADRS, a control signal CNTL, and a data signal DATA to the register group 100 via the execution unit selection circuit 140.

  When the command execution signal RUN is enabled, the execution unit selection circuit 140 inputs / outputs the address signal ADRS, control signal CNTL, and data signal DATA from the command execution circuit 130 to the register group 100, and the command execution signal RUN is disabled. When (disable), the address signal ADRS, control signal CNTL, and data signal DATA from the CPU interface 110 are input / output to / from the register group 100.

<Composition of command buffer>
Next, the configuration of the command buffer will be described with reference to FIG. FIG. 2A is a block diagram showing the configuration of the command buffer, and FIG. 2B is a block diagram showing the configuration of the command.

  The command buffer 120 is configured by a FIFO (first-in first-out) circuit that reads out the written data in that order. The command buffer 120 includes a command area 121 that stores a plurality of commands, and a data area 122 that stores a plurality of data DO read from the register group 100.

  The command area 121 has four areas AD, DS, VB, and CT for one command. The sizes of the regions AD, DS, VB, and CT are arbitrary. For example, the regions AD, DS, and VB are configured by 16 bits, and the region CT is configured by 2 bits.

  As shown in FIG. 2B, the command includes a data read command, a data write command, a simple wait command, and a state wait command.

  In the data read command, 0 is set in the area CT, the address of the register group 100 is set in the area AD, the data width to be read in the area DS is set, and the effective bit for actually reading is set in the area VB. . The valid bit is set to 1 for the valid bit and 0 for the invalid bit. For example, if the least significant bit is the 0th bit and the area VB is designated as 0x0042 in hexadecimal, the 1st and 6th bits are valid bits. If 0xFFFF is specified, all bits are valid bits.

  In the data write command, 1 is set in the area CT, the address of the register group 100 is set in the area AD, write data is set in the area DS, and a valid bit for actually writing is set in the area VB.

  In the simple wait command, 2 is set in the area CT, the number of clocks to wait until the next command is executed is set in the area AD, and 0x0000 is set in the area DS and the area VB.

  In the status wait command, 3 is set in the area CT, the address of the register group 100 is set in the area AD, the comparison data is set in the area DS, and the effective bit for actually performing the comparison is set in the area VB.

<Operation of command execution circuit>
Next, the configuration of the operation of the command execution circuit will be described with reference to FIG. FIG. 3 is a flowchart showing the operation of the command execution circuit. The command execution circuit 130 sequentially reads and executes commands from the command area 121 of the command buffer 120 configured by a FIFO circuit.

  First, in step S <b> 100, the command execution circuit 130 reads a command from the command area 121 of the command buffer 120.

  Next, in step S110, it is determined whether or not the value of the region CT is 0. If it is 0, the process proceeds to step S200, and if not, the process proceeds to step S210.

  Next, in step S200, a data read command is executed, and the process proceeds to step S100.

  On the other hand, in step S210, it is determined whether or not the value of the region CT is 1. If it is 1, the process proceeds to step S300, and if not, the process proceeds to step S310.

  Next, in step S300, a data write command is executed, and the process proceeds to step S100.

  On the other hand, in step S310, it is determined whether or not the value of the region CT is 2. If it is 2, the process proceeds to step S400, and if not, the process proceeds to step S500.

  Next, in step S400, a simple wait command is executed, and the process proceeds to step S100.

  On the other hand, in step S500, a state wait command is executed, and the process proceeds to step S100.

<Operation of data read command>
Next, the configuration of the operation of the data read command will be described with reference to FIG. FIG. 4 is a flowchart showing the operation of the data read command (step S200 in FIG. 3).

  First, in step S202, the process moves to the register indicated by the address set in the area AD.

  Next, in step S204, the value of the data width set in the area DS from the register value is written in the storage area DI of the RAM 150.

  Next, in step S206, the logical product (and) of the value of the storage area DI and the effective bit set in the area VB is written in the storage area DT of the RAM 150.

  Next, in step S208, the value of the storage area DT is written into the data area 122 of the command buffer 120.

<Operation of data write command>
Next, the configuration of the operation of the data write command will be described with reference to FIG. FIG. 5 is a flowchart showing the operation of the data write command (step S300 in FIG. 3).

  First, in step S302, the process moves to the register indicated by the address set in the area AD.

  In step S304, the register value is written in the storage area DI of the RAM 150.

  In step S306, the logical product (and) of the value of the storage area DI and the value obtained by inverting the value of the area VB (not VB) is written in the storage area D1 of the RAM 150.

  Next, in step S308, the logical product (and) of the value of the region DS and the valid bit set in the region VB is written in the storage area D2 of the RAM 150.

  Next, in step S310, the logical sum (or) of the storage area D1 and the storage area D2 is written in the storage area DT of the RAM 150.

  Next, in step S312, the value of the storage area DT is written into the register.

<Operation of simple wait command>
Next, the configuration of the simple wait command operation will be described with reference to FIG. FIG. 6 is a flowchart showing the operation of the simple wait command (step S400 in FIG. 3).

  First, in step S402, 0 is set to the current clock number i.

  Next, in step S404, 1 is added to the current clock number i.

  Next, in step S406, it is determined whether or not the current clock number i exceeds the value set in the area AD. If it exceeds, the processing of the simple wait command is terminated. The process proceeds to step S404.

<Operation of status wait command>
Next, the configuration of the operation of the state wait command will be described with reference to FIG. FIG. 7 is a flowchart showing the operation of the status wait command (step S500 in FIG. 3).

  First, in step S502, the process moves to the register indicated by the address set in the area AD.

  In step S504, the register value is written in the storage area DI of the RAM 150.

  Next, in step S506, the logical product (and) of the comparison data set in the area DS and the effective bit set in the area VB is written in the storage area D1 of the RAM 150.

  Next, in step S508, the logical product (and) of the value of the storage area DI and the effective bit set in the area VB is written in the storage area D2 of the RAM 150.

  Next, in step S510, it is determined whether or not the value of the storage area D1 and the value of the storage area D2 are equal. If they are equal, the process of the state wait command is terminated. If they are not equal, the process proceeds to step S502.

<Command execution example>
Next, an example of command execution will be described with reference to FIG. FIG. 8 is a block diagram illustrating an example of command execution.

  It is assumed that three commands CMD1 to CMD3 are stored in the command area 121 of the command buffer 120 as shown in FIG. The register group 100 includes data D (1) = 0xFFFF in the register at address 0x0000, data D (2) = 0x0401 in the register at address 0x0001, and data D (3) = 0x000F in the register at address 0x0002, respectively. It is assumed that it is set.

  First, the command CMD1 is read (step S100 in FIG. 3), and since the area CT = 0, the data read command is executed (step S200 in FIG. 3), and the register group 100 address (area AD =) moves to the register at 0x0000. (Step S202 in FIG. 4), the data width (area DS =) 0x0010 = 16 bits and data D (1) = 0xFFFF are written in the storage area DI of the RAM 150 (step S204 in FIG. 4). Since the valid bit is (area VB =) 0x0042, the first and sixth bits of the storage area DI are valid, and the value 0x0042 of the storage area DT is written to DO (1) of the data area 122 of the command buffer 120 (FIG. 4 steps S206 to S208).

  Next, the command CMD2 is read, and since the area CT = 3, the state wait command is executed (step S500 in FIG. 3), and moved to the register at the address (area AD =) 0x0001 of the register group 100 (step S502 in FIG. 7). ), Data D (2) = 0x0401 is written to the storage area DI of the RAM 150 (step S504 in FIG. 7). Since the effective bit is (area VB =) 0x0401 and the comparison data is (area DS =) 0x0001, the next command CMD3 is read when the 10th bit of the storage area DI changes from 1 to 0 (step S504 in FIG. 7). To S510).

  Next, the command CMD3 is read, and since the area CT = 1, the data write command is executed (step S300 in FIG. 3), and the register group 100 is moved to the register at the address (area AD =) 0x0002 (step S302 in FIG. 5). ), Data D (3) = 0x000F is written in the storage area DI of the RAM 150 (step S304 in FIG. 5). Since the effective bit is (area VB =) 0x0028 and the write data is (area DS =) 0x0020, the value 0x0027 of the storage area DT in which the third bit of the storage area DI is set to 0 and the fifth bit is set to 1 is the register group 100. Is written at the address 0x0002 (steps S306 to S312 in FIG. 5).

  According to the embodiment described above, the following effects can be obtained.

  In this embodiment, it is possible to reduce waste of operating time due to a difference in operating speed between the semiconductor device and software by automatically executing the reading, writing, and waiting state of the register data. In addition, since the semiconductor device reads, writes, and compares the register data for each bit, the processing can be completed in less than half the operation time compared to when the software performs these processes.

  As mentioned above, although embodiment of the semiconductor device was described, it is not limited to such embodiment at all, It can implement in various forms within the range which does not deviate from the meaning. Hereinafter, a modification will be described.

  (Modification 1) Modification 1 of the semiconductor device will be described. In the first embodiment, it has been described that the CPU interface 110 outputs the command execution signal RUN to the command execution circuit 130 and the execution unit selection circuit 140. However, the CPU interface 110 outputs the command execution signal RUN to the command execution circuit 130. Then, the command execution circuit 130 may output a switching signal to the execution unit selection circuit 140.

1 is a block diagram showing a configuration of a semiconductor device according to a first embodiment. The block diagram which shows the structure of a command buffer. The flowchart which shows operation | movement of a command execution circuit. The flowchart which shows operation | movement of a data read command. The flowchart which shows operation | movement of a data write command. The flowchart which shows operation | movement of a simple wait command. The flowchart which shows operation | movement of a state wait command. The block diagram which shows the example of execution of a command.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 100 ... Register group, 110 ... CPU interface, 120 ... Command buffer, 121 ... Command area, 122 ... Data area, 130 ... Command execution circuit, 140 ... Execution part selection circuit, 200 ... CPU.

Claims (3)

A semiconductor device including a plurality of registers,
A command buffer for storing a plurality of commands for controlling the register;
A command execution circuit for sequentially executing the commands stored in the command buffer;
An execution unit selection circuit for switching between external control and control from the command execution circuit;
including,
A semiconductor device characterized by that. The semiconductor device according to claim 1,
The plurality of commands are:
A data read command that specifies an address of the register, a data width, and a valid bit, and reads a value of the data width and a bit indicated by the valid bit from the register indicated by the address;
A data write that designates an address of the register, write data, and a valid bit, and rewrites the value of the bit indicated by the valid bit of the register indicated by the address to the value of the bit indicated by the valid bit of the write data Command and
Specify the number of clocks to wait until the next command is executed, a simple wait command to wait until the number of external clock signals reaches the number of clocks, and
The register address, comparison data, and valid bit are specified, and the value of the bit indicated by the valid bit of the register indicated by the address is equal to the value of the bit indicated by the valid bit of the comparison data. A state wait command to wait until
including,
A semiconductor device characterized by that. Multiple registers,
A command buffer for storing a plurality of commands for controlling the register;
A command execution circuit for sequentially executing the commands stored in the command buffer;
An execution unit selection circuit for switching between external control and control from the command execution circuit;
A method for automatically controlling a semiconductor device including:
As the plurality of commands,
A data read command that specifies an address of the register, a data width, and a valid bit, and reads a value of the data width and a bit indicated by the valid bit from the register indicated by the address;
A data write that designates an address of the register, write data, and a valid bit, and rewrites the value of the bit indicated by the valid bit of the register indicated by the address to the value of the bit indicated by the valid bit of the write data Command and
Specify the number of clocks to wait until the next command is executed, a simple wait command to wait until the number of external clock signals reaches the number of clocks, and
The register address, comparison data, and valid bit are specified, and the value of the bit indicated by the valid bit of the register indicated by the address is equal to the value of the bit indicated by the valid bit of the comparison data. A state wait command to wait until
Including
Controlling the register by combining one or more of the plurality of commands;
A method for automatically controlling a semiconductor device.

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