JP2009004005A - Nonvolatile semiconductor memory device and test method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device capable of shortening a test time for high reliability.
SOLUTION: A plurality of voltage supply paths 29 for supplying a selected column voltage at the time of a write operation from a write column voltage generation circuit 20 to column selection circuits 13 and 14, and an external voltage capable of applying a voltage to each voltage supply path from the outside A first switch circuit 22 that separates the application terminal 24, the column voltage generation circuit, and the external voltage application terminal and selects a voltage supplied from one of them, and supplies the voltage to each voltage supply path, and the column voltage generation circuit or external voltage A second switch circuit 23 for individually connecting the application terminal and each voltage supply path is provided, and the column selection circuit simultaneously selects one or a plurality of memory cell blocks 11 in the test mode during a normal write operation. Tests with a voltage drop via the voltage supply paths corresponding to the memory cell terminals connected to each test selection column by selecting the selected test columns more than the number for each voltage supply path. The selected column voltage can be applied.
[Selection] Figure 1

Description

  The present invention relates to a nonvolatile semiconductor memory device and a test method thereof, and more particularly, to a nonvolatile memory cell capable of electrically reading, writing, and erasing data by applying a voltage for each operation mode such as a flash memory. The present invention relates to a test facilitating technique for a nonvolatile semiconductor memory device provided.

  There is a flash memory as a typical nonvolatile semiconductor memory device including a nonvolatile memory cell that can electrically read, write, and erase data by applying a voltage for each operation mode.

  Here, writing, erasing, and reading memory operations in a general flash memory will be briefly described with reference to FIGS. 10 to 12 show voltage application conditions for each terminal (control gate 1, drain 2 and source 3) at the time of each memory operation of writing, erasing and reading to a single flash memory cell, floating gate 5 and each terminal. The flow of electrons (negative charge) between 1 and 3 is schematically shown. In the following description, in the flash memory cell, the floating gate 5 is formed on the channel region between the drain 2 and the source 3 formed on the substrate 4 via the tunnel oxide film 6. A so-called stack gate type flash memory cell in which the control gate 1 is formed via the insulating film 7 is assumed.

  As is well known to those skilled in the art, the flash memory increases the negative charge amount (electron accumulation amount) accumulated in the floating gate 5 by the write operation to increase the threshold voltage above a predetermined value, thereby increasing the data amount. Data is stored by performing writing and erasing data by decreasing the threshold voltage below a predetermined value by reducing the amount of negative charge accumulated in the floating gate 5 by the erasing operation.

  In the write operation, as shown in FIG. 10, a positive voltage of 0 V is applied to the source 3, a positive voltage of, for example, 5 V is applied to the drain 2, and a positive voltage of, for example, 12 V is applied to the control gate 1. As a result, hot electrons generated by passing a current between the source and the drain are injected into the floating gate 5. As a result, the threshold voltage of the memory cell increases.

  Further, in the erase operation, as shown in FIG. 11, a tunnel current flowing in the tunnel oxide film 6 between the source 3 and the floating gate 5 is used. In the erase operation, a voltage of about 6V is applied to the source 3 and a voltage of about −8V is applied to the control gate. The drain 2 is in an open state (a high impedance state in which no voltage is applied). At this time, an FN (Fowler-Nordheim) current flows through the tunnel oxide film 6 due to a very high electric field between the floating gate 5 and the source 3. Thereby, electrons accumulated in the floating gate 6 are extracted to the source 3. The threshold voltage of the flash memory cell in the written state is lowered by the erase operation.

  In the read operation, as shown in FIG. 12, a comparison circuit (not shown) such as a sense amplifier is used, and the current Ids flowing between the drain and the source according to the threshold voltage of the memory cell and the erase state threshold This is realized by comparing the magnitude of a reference current (not shown) corresponding to an intermediate threshold voltage between the voltage and the threshold voltage in the writing state. In FIG. 12A, since electrons are not injected into the floating gate 5, the memory cell current Ids in the erased state with a low threshold voltage is shown, and it is assumed that data “1” is represented. In FIG. 12B, since electrons are injected into the floating gate 5, the memory cell current Ids in a writing state with a high threshold voltage is shown, and it is assumed that data “0” is represented.

  As described above with reference to FIGS. 10 to 12, the voltage application condition to each terminal is different in each memory operation of writing, erasing, and reading. FIG. 13 shows a list of voltage application conditions to each terminal in each memory operation.

  FIG. 14 shows a configuration example of a memory cell block in the NOR type flash memory. As shown in FIG. 14, in the memory cell block 11, a plurality of flash memory cells are arranged in a matrix in the row and column directions, and the control gates of the plurality of memory cells arranged in the same row are extended in the row direction. Are connected to a common bit line BL extending in the column direction, and each source of the plurality of memory cells is connected to a common source line SL. Connected and configured. Here, a voltage is applied to each terminal of the memory cell through the word line WL, the bit line BL, and the source line SL, respectively. In FIG. 13, the voltage values applied to each word WL line, each bit line BL, and the source line are shown as an example during a write operation, and are used in the description of the write drain disturb phenomenon described later. .

  In the configuration example of the memory cell block 11 shown in FIG. 14, the sources of all the memory cells in one block are connected to the common source line SL. This increases the area of the memory cell block 11. Therefore, the erasing operation is performed collectively in units of memory cell blocks. In addition, since the erasing operation using the FN current requires a long time for the erasing operation, the erasing time per memory cell can be shortened by collectively performing the erasing operation for each memory cell block.

  Further, by collecting a plurality of memory cell blocks 11 in units called planes, the degree of freedom of arrangement of the memory cell blocks 11 can be increased, or a write or erase operation can be executed in one plane It is also common to have a function that allows data to be read simultaneously.

  The data rewriting of the flash memory is a series of operations in which new data is written to necessary memory cells after erasing in batches for each memory cell block as an erasing unit. During this write operation, as shown in FIG. 14, high voltage stress is applied not only to the write target memory cell 8 but also to the drains of the non-selected memory cells 9 on the same bit line. This high voltage stress may cause a phenomenon called drain disturb that lowers the threshold voltage of the memory cell. It is necessary to replace a memory cell whose threshold voltage is lowered by drain disturbance as a defective cell with a redundant memory cell before shipment. Therefore, a durability test for the drain disturb is performed in the wafer test. Specifically, a high voltage stress corresponding to drain disturb is applied to the drain of each memory cell, and the threshold voltage fluctuation of the memory cell before and after the stress is confirmed. As a technique for accurately testing the drain disturb stress, a test method disclosed in Patent Document 1 below is known.

  In addition, the drain disturb test is generally performed by applying a high voltage stress to a plurality of bit lines at once as the memory capacity is increased. For example, the drain disturb test is disclosed in Patent Document 2 below. There are known test methods. When applying a high voltage stress all at once, a voltage is usually applied from an external voltage application terminal (VPP terminal). In this case, since a drain voltage drop due to a voltage drop on the voltage application path due to a current flowing through the voltage application path from the external voltage application terminal to the memory cell becomes a problem, this voltage drop was actually taken into account. It is necessary to apply a voltage from the outside. Here, the current flowing through the current path is mainly off-leakage of the memory cell to which the drain voltage is applied. In a memory cell having a floating gate such as a flash memory, the potential of the floating gate electrode is raised when a drain voltage is applied by the coupling capacitance between the drain region and the floating gate even if the control gate is fixed at 0 V. Since the current between the sources is larger than that of a normal transistor, it is necessary to consider such as increasing the externally applied voltage as described above.

JP 2000-174146 A Japanese Patent Laid-Open No. 2004-22013

  By the way, as the miniaturization of the memory cell advances against the background of the increase in capacity of the nonvolatile semiconductor memory device, the off-leak current of the memory cell increases. Off-leakage current of memory cells is becoming a problem even in the current generation manufacturing process, and as described above, it is necessary to consider the leakage current for the stress voltage applied from the outside, but it will surely become a problem as miniaturization progresses in the future. Appropriate response is desired.

  Further, the sheet resistance of metal wiring tends to increase due to miniaturization, and the resistance value of the entire voltage application path described above is larger than that of the previous generation. From these, in order to give a desired high voltage stress to the memory cell, it is necessary to supply a higher voltage from the outside than in the conventional manufacturing process. However, with miniaturization, the withstand voltage of transistors and memory cells also decreases, so it is difficult to increase the stress voltage applied from the outside.

  Hereinafter, it will be described with reference to FIG. 15 that the test time tends to increase because it is necessary to reduce the number of bit lines to which high voltage stress can be applied at a time in future process generations due to the above-mentioned limitations. FIG. 15 shows the relationship between the external stress voltage applied to the external voltage application terminal (VPP terminal) and the selected bit line voltage (drain voltage of the memory cell subject to drain disturb), and the number of bit lines to which high voltage stress is applied. These three types are schematically shown. In FIG. 15, even if the external input voltage from the VPP terminal is applied exceeding the withstand voltage of the transistor, the effective voltage at the VPP terminal side end of the voltage application path is limited by the withstand voltage of the transistor. The input voltage is less than or equal to the withstand voltage, and the external input voltage and the selected bit line voltage are expressed in a proportional relationship. Even if the external input voltage exceeds the withstand voltage, the selected bit line voltage is the voltage value when the external input voltage is at the withstand voltage. It is fixed as it is. In FIG. 15, when all the bit lines of four memory cell blocks are selected and a high voltage stress is applied at once, the external input voltage exceeds the breakdown voltage and a desired high voltage stress (for example, 5V) is applied to the memory cell. Since it cannot be applied, the number of bit lines to which high voltage stress is applied simultaneously must be limited to a maximum of two memory cell blocks, and the test time takes twice as long as the test time of four blocks at a time. Become. The problem of increasing the test time becomes more prominent as the capacity increases. In FIG. 15, when the number of bit lines to which a high voltage stress is applied is the maximum number (for example, 8 or 16) during a normal write operation, the external input voltage is less than the withstand voltage and the desired high voltage stress is This shows that it can be applied to the drain of the memory cell.

  Further, the off-leak current of the memory cell that causes a voltage drop in the voltage application path not only increases as the miniaturization progresses, but also its variation increases. If a plurality of memory cells are collectively stressed when the leak current is larger than expected, there is a risk that the stress applied to the memory cells becomes insufficient and a defective cell cannot be detected.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a nonvolatile semiconductor memory device including a test circuit for high reliability and capable of reducing the test time, and a test method thereof. It is to provide.

In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention includes a first terminal, a second terminal, and a control terminal that controls conduction between the first terminal and the second terminal. A plurality of memory cell blocks are arranged in which a plurality of nonvolatile memory cells that can electrically perform a data read operation, a write operation, and an erase operation by applying a voltage to each terminal in an operation mode are arranged in the row and column directions. In the block group and one of the memory cell blocks, one or more columns of the memory cells are selected, and the operation mode is selected with respect to the first terminal of the memory cells in the selected column. A selected column voltage according to the operation mode is applied, and a non-selected column voltage according to the operation mode is applied to the first terminal of the memory cell in the non-selected column that is not selected. In one of the column selection circuit to be brought into a state and one of the memory cell blocks, one or a plurality of rows of the memory cells are selected in units of rows, and the control terminals of the memory cells in the selected row are selected. A selected row voltage according to the operation mode is applied, and a non-selected row voltage according to the operation mode is applied to the control terminals of the memory cells in the non-selected row that has not been selected. A row selection circuit for applying the non-selected column voltage or a test non-selected row voltage to the control terminal of the memory cell; and generating the selected column voltage during the write operation to the column selection circuit. A nonvolatile semiconductor memory device comprising: a write column voltage generation circuit to be supplied; and a selection row voltage generation circuit that generates the selected row voltage according to the operation mode and supplies the selected row voltage to the row selection circuit. ,
A plurality of voltage supply paths for supplying the selected column voltage during the write operation from the write column voltage generation circuit to the column selection circuit, and an external voltage application capable of applying a test external voltage to the plurality of voltage supply paths A plurality of voltage supplies by separating a terminal, the write column voltage generation circuit, and the external voltage application terminal, and selecting a voltage supplied from either the write column voltage generation circuit or the external voltage application terminal A first switch circuit to be supplied to a path; a second switch circuit for individually connecting the write column voltage generation circuit and the external voltage application terminal selected by the first switch circuit; and the plurality of voltage supply paths; With
The column selection circuit selects, in a predetermined test mode, a selection column for testing that is larger than the number of selection columns simultaneously selected in the normal write operation for one or a plurality of the memory cell blocks. The test selection column is divided for each of the voltage supply paths, and the test is applied from the external voltage application terminal to the first terminal of the memory cell of each of the divided selection columns for test. A first feature is that the selected column voltage for testing, which has been dropped from the external voltage for use via the corresponding voltage supply path, can be applied.

  According to the nonvolatile semiconductor memory device of the first feature, the test selection column is divided and assigned for each voltage supply path, and the first terminals of the memory cells of the divided individual test selection columns (flash memory) In the cell, corresponding to the drain), the selected column voltage for testing can be applied by dropping the voltage from the external voltage for testing applied to the external voltage application terminal via the corresponding individual voltage supply path. Since the total value of off-leakage currents flowing in the memory cells (between the first and second terminals) in the selected column per one voltage supply path is at least half that of the total value of off-leakage currents flowing in the memory cells in all the selected columns. Since the amount of voltage drop per voltage supply path is at least halved, the test external voltage applied from the external voltage application terminal can be reduced. As a result, the number of selected columns to which a test select column voltage can be simultaneously applied can be increased, and data deterioration (drain disturb) caused in non-selected memory cells during a write operation by applying a test select column voltage can be increased. The time required for the test can be shortened.

  In addition to the first feature, the nonvolatile semiconductor memory device according to the present invention further includes a plurality of external voltage application terminals, and the first switch circuit causes the write column voltage generation circuit and the plurality of external devices to be connected. Each of the voltage application terminals is separated from each other, and each of the voltage supply paths is configured to be connectable to any one of the corresponding external voltage application terminals by the second switch circuit. It is characterized by.

  According to the nonvolatile semiconductor memory device of the second feature, since a plurality of external voltage application terminals are provided, even if the total value of the off-leak current of the memory cells in the selected column for each external voltage application terminal varies, For each external voltage application terminal, the selected column voltage for testing can be individually adjusted to the desired voltage value, and data deterioration (drain disturbance) of unselected memory cells can be tested during more precise write operations. It becomes.

  In addition to the first or second feature, the nonvolatile semiconductor memory device according to the present invention further includes a voltage drop applied to the selected column selected by the column selection circuit in the predetermined test mode. A test voltage measurement terminal for measuring the selected column voltage for testing, and an end of the voltage supply path on the column selection circuit side separately for each of the voltage supply paths. And a third switch circuit connected to a specific node between any one of the selected columns selected in the predetermined test mode.

  According to the nonvolatile semiconductor memory device of the third feature, since the voltage of the specific node selected by the third switch circuit can be measured from the outside, the test applied to the external voltage application terminal for each voltage supply path The memory cell block that actually applies the selected column voltage to the test external voltage necessary to obtain the desired selected column voltage because the voltage drop amount of the voltage supply path from the external voltage to the specific node can be measured Thus, it is possible to actually verify the data, and it is possible to test the data deterioration (drain disturbance) of the non-selected memory cell at the time of a more accurate write operation.

  In the nonvolatile semiconductor memory device according to the present invention, in addition to any of the above features, the first switch circuit is configured by a diode circuit, and the write column voltage generation circuit is connected to the anode side of the diode circuit. The fourth feature is that the external voltage application terminal and one end of the second switch circuit are connected to the cathode side of the diode circuit.

  According to the nonvolatile semiconductor memory device of the fourth feature, when the test external voltage is not applied to the external voltage application terminal, the voltage supplied from the write column voltage generation circuit is automatically selected, and the external A first switch circuit that automatically selects a voltage supplied from an external voltage application terminal when a test external voltage equal to or higher than the output voltage of the write column voltage generation circuit is applied to the voltage application terminal. It can be realized by configuration.

  In addition to any one of the above features, the non-volatile semiconductor memory device according to the present invention further includes the selected row voltage generating circuit that performs the test as a non-selected row voltage for testing in an erasing operation in the predetermined test mode. A negative voltage having an absolute value lower than a negative voltage applied as a selected row voltage is generated, and the row selection circuit supplies a non-selected row voltage of the test negative voltage supplied from the selected row voltage generation circuit, A fifth feature is that the voltage is applied to the control terminals of the memory cells in all rows of the selected memory cell block.

  According to the nonvolatile semiconductor memory device of the fifth feature, a test that causes drain disturbance to the same selected column voltage without increasing the voltage value of the test external voltage applied from the external voltage application terminal. The voltage difference between the control terminal of the target memory cell (corresponding to the control gate in the flash memory cell) and the first terminal (corresponding to the drain in the flash memory cell) can be increased. Since the deterioration phenomenon (drain disturb phenomenon) is accelerated, it becomes possible to efficiently find memory cells that are vulnerable to the data deterioration phenomenon. Furthermore, since the voltage at the control terminal of the memory cell can be reduced to reduce the off-leakage current between the first and second terminals of the memory cell, the voltage value of the test external voltage applied from the external voltage application terminal can be reduced. Without increasing, the number of selectable columns connectable to one voltage supply path can be increased, thereby increasing the number of selectable columns that can be tested at the same time. It is possible to further reduce the time required for the data deterioration test occurring in the unselected memory cells.

In order to achieve the above object, a test method for a nonvolatile semiconductor memory device according to the present invention is a test method for evaluating data deterioration of a memory cell accompanying a write operation to the nonvolatile semiconductor memory device according to the third feature. There,
The nonvolatile semiconductor memory device is set to the predetermined test mode, and the row selection circuit is predetermined for the control terminals of the memory cells in all rows for one or a plurality of the memory cell blocks to be tested. The non-selected row voltage is applied to the one or a plurality of memory cell blocks to be tested by the column selection circuit for a test larger than the number of selected columns simultaneously selected during the normal write operation. So that the first switch circuit and the second switch circuit select a voltage supplied from the external voltage application terminal and supply the selected voltage to the plurality of voltage supply paths, The third switch circuit controls each of the test voltage measurement terminal and one specific node of the voltage supply path to connect each other, and applies a voltage to the external voltage application terminal. And measuring the voltage of the specific node output to the test voltage measuring terminal, and the external voltage applying terminal so that the selected column voltage for testing obtained from the voltage of the specific node becomes a predetermined value. The first feature is to control the voltage value applied to the signal voltage within a specified voltage range.

  According to the nonvolatile semiconductor memory device test method of the first feature, the nonvolatile semiconductor memory device is set to a predetermined test mode for testing data deterioration (drain disturb) of unselected memory cells during a write operation. When the row selection circuit, the column selection circuit, and the first to third switch circuits are controlled, a voltage supply path from the external voltage application terminal to the specific node selectively connected by the third switch circuit is established. Since the voltage of a specific node based on the external voltage applied to the voltage application terminal is output to the test voltage measurement terminal, the output voltage is measured so that the selected column voltage for test becomes a predetermined value. The voltage value applied to the external voltage application terminal is controlled within a specified voltage range (for example, the breakdown voltage of the transistor of the nonvolatile semiconductor memory device or less). Theft is possible. As a result, by using a plurality of voltage supply paths, the number of selected columns to which a test column voltage can be applied simultaneously is increased, and a desired test column voltage that becomes a predetermined value by adjusting an external voltage is set for each. It can be applied to the first terminal of the memory cell in the selected column, and a test for data deterioration occurring in the non-selected memory cell during the write operation can be executed with a shortened test time.

  In addition to the first feature, the test method of the nonvolatile semiconductor memory device according to the present invention further includes the predetermined value of the selected column voltage for the test before applying a voltage to the external voltage application terminal. In the step of measuring the predetermined value, the nonvolatile semiconductor memory device is set in the predetermined test mode, and the row selection circuit applies to one of the memory cell blocks to be tested. The column selection circuit applies one selected column for testing to one of the memory cell blocks to be tested so that a predetermined unselected row voltage is applied to the memory cells in all rows. As selected, the first switch circuit and the second switch circuit select a voltage supplied from the write column voltage generation circuit and supply the selected voltage to the voltage supply path connected to the one selected column. And the third switch circuit controls the test voltage measurement terminal so that the specific node of the voltage supply path connected to the one selected column is connected to the test voltage measurement terminal. The second characteristic is that the voltage of the specific node output to the terminal is measured and set to the predetermined value.

  According to the test method for a nonvolatile semiconductor memory device of the second feature, the predetermined value of the selected column voltage for testing used in the test method for the nonvolatile semiconductor memory device of the first feature is set to an actual test target. Since the selected column voltage applied to the first terminal of the non-selected memory cell in the actual write operation is also applied in the predetermined test mode, it can be obtained with higher accuracy. This makes it possible to execute a test for data deterioration occurring in an unselected memory cell at the time of a write operation.

  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a nonvolatile semiconductor memory device and a test method thereof (hereinafter appropriately referred to as “device of the present invention” and “method of the present invention”) will be specifically described below with reference to the drawings.

[First Embodiment]
FIG. 1 schematically shows a schematic block configuration in the first embodiment of the device 10 of the present invention. The device 10 of the present invention includes a block group including a plurality of memory cell blocks 11, a word line selection circuit 12 (corresponding to a row selection circuit), a local bit line selection circuit 13 (corresponding to a column selection circuit), and a global bit line selection. A circuit 14 (corresponding to a column selection circuit), a specific node selection circuit 15 (corresponding to a third switch circuit), a block selection circuit 16, a read circuit 17, a write voltage switch circuit 18, and an operation mode voltage generation circuit 19 (selected row voltage) A bit line voltage generation circuit for write operation 20 (corresponding to a write column voltage generation circuit), a bit line voltage regulator circuit 21, a first switch circuit 22, a second switch circuit 23, and an external voltage for testing External voltage application terminal 24, test voltage measurement terminal 25, output interface circuit 26, input interface circuit 27 And configured to include a control circuit 28, and the like.

  The memory cell block 11 includes a plurality of nonvolatile memory cells arranged in a row direction and a column direction, and each control terminal of the plurality of memory cells arranged in the same row is connected to a common word line extending in the row direction, The first terminals of the plurality of memory cells arranged in the same column are connected to a common bit line (local bit line) extending in the column direction, and the second terminals of the plurality of memory cells are connected in the row direction or the column direction. It is connected to a common source line that extends.

  In the present embodiment, a stack gate type flash memory cell having the element structure illustrated in FIGS. 10 to 12 is assumed as the memory cell. As shown in FIGS. 10 to 12, the memory cell includes a control gate 1 (corresponding to a control terminal), a floating gate 5, a drain 2 (corresponding to a first terminal), and a source 3 (corresponding to a second terminal), A substrate 4 is provided, and memory operations such as data reading, writing, and erasing can be performed electrically by applying voltage to each terminal according to the operation mode. Since the voltage application condition to each terminal of each memory operation (reading, writing, erasing) is as described with reference to FIGS. 10 to 12 in the background art column, the overlapping description is omitted. As described above, in this embodiment, each memory cell block 11 is configured as a so-called NOR type flash memory cell array.

  In addition to the normal operation modes such as the three memory operations described above, the device 10 of the present invention is not subject to high voltage stress applied to unselected memory cells in the same column as the write target selected memory cell during the write operation. A test mode for efficiently evaluating the resulting data degradation (drain disturbance) is provided. In general, a nonvolatile semiconductor memory device such as a flash memory has various test modes for easy test. In this embodiment, the drain disturb evaluation test mode is simply referred to as a test mode. A test in the test mode is simply referred to as a test as appropriate.

  The word line selection circuit 12 is provided for each memory cell block 11 and is selected by selecting one or a plurality of word lines arranged in the memory cell block 11 according to the input row address signal RA. A selected word line voltage (corresponding to the selected row voltage) corresponding to the operation mode is applied to the selected word line, and an unselected word line voltage (non-selected row) corresponding to the operation mode is applied to an unselected word line. (Corresponding to a voltage) is applied. In the erase operation mode, since the erase operation is executed in units of blocks, the word line selection circuit 12 does not execute the selection / non-selection operation in units of word lines. Further, when the test mode is selected, the word line selection circuit 12 does not perform the selection / non-selection operation in units of word lines, as in the erase operation, and sets all the word lines to non-selection for a test to be described later. The unselected word line voltage (corresponding to the unselected row voltage) is applied. The word line selection circuit 12 is controlled by a decode output (block selection signal) from the block selection circuit 16 so as to be activated in the memory cell block 11 selected by the block selection circuit 16.

  The local bit line selection circuit 13 is provided for each memory cell block 11 and selects one or more of the plurality of local bit lines arranged in the memory cell block 11 in accordance with the input lower column address signal CA1. A selected bit line voltage (corresponding to a selected column voltage) corresponding to the operation mode is applied to the selected selected bit line, and an unselected bit line voltage (non-selected) corresponding to the operation mode is applied to an unselected bit line. (Corresponding to a selected column voltage) is applied, or an open state is established. In this embodiment, an unselected bit line is in an open state, but depending on the array configuration of the memory cell block 11 (for example, in the case of a virtual ground line type memory cell array), some or all unselected bits A non-selected bit line voltage may be applied to the line. Further, the local bit line selection circuit 13 accepts the input of the decode output (block selection signal) of the block selection circuit 16 and, when the memory cell block 11 is not selected, opens all the bit lines. In the erase operation mode, since the erase operation is executed in units of blocks, the local bit line selection circuit 13 does not execute the selection / non-selection operation in units of bit lines.

  In the present embodiment, a plurality of memory cell blocks 11 are arranged in a matrix in the row and column directions, and one plane is constituted by the plurality of memory cell blocks 11 arranged in the column direction. Specifically, the local bit line selection circuit 13 of each memory cell block 11 is configured as an aggregate of transfer gates composed of MOSFETs, one end of each transfer gate is connected to the local bit line, and the other end of each transfer gate. Connects to the global bit line. One global bit line is assigned to one or several (for example, 2 or 4) local bit lines, and all the memory cell blocks 11 in the same plane are vertically used in common. If there is one global bit line for one local bit line, the local bit line selection circuit 13 does not perform substantial column selection, and the global bit line selection circuit 14 does not perform substantial column selection. Column selection is performed. In the plane configuration example shown in FIG. 1, the memory cell block 11 is configured by 2 rows × 2 columns, and each plane is configured by two memory cell blocks 11, but the plane configuration is the same as the configuration example shown in FIG. It is not limited.

  The global bit line selection circuit 14 is provided for each plane, and selects one or a plurality of global bit lines that are commonly arranged in a plurality of memory cell blocks 11 in the same column in accordance with an input upper column address signal CA2. Select, apply a selected bit line voltage according to the operation mode to the selected selected global bit line, and apply a non-selected bit line voltage according to the operation mode to an unselected global bit line that is not selected Or configured to be in an open state. In this embodiment, an unselected global bit line is in an open state, but depending on the array configuration of the memory cell block 11 (for example, in the case of a virtual ground line type memory cell array), some or all of the unselected global bit lines are not selected. An unselected bit line voltage may be applied to the global bit line.

  The global bit line selection circuit 14 of each plane is configured as an assembly of transfer gates composed of MOSFETs, one end of each transfer gate is connected to the global bit line, and the other end of each transfer gate is connected to the read circuit 17. Connected to the write voltage switch circuit 18. The global bit line selection circuit 14 receives an input of the plane selection signal PS, and when the plane is not selected, turns off the transfer gate and opens all the global bit lines. In the erase operation mode, since the erase operation is executed in units of blocks, the global bit line selection circuit 14 does not execute the selection / non-selection operation in units of global bit lines.

  The specific node selection circuit 15 is provided for each plane, and the global bit line selection circuit 14 is arranged at one end in the column direction of one plane, and the specific node selection circuit 15 is arranged at the other end. The specific node selection circuit 15 inputs a plane selection signal PS and a specific node selection signal NS with a node on the opposite side of the global bit line selection circuit 14 of one specific global bit line in one plane as a specific node. Accordingly, a specific node of one plane is selected from a plurality of planes and electrically connected to the test voltage measurement terminal 25. As shown in FIG. 2, the specific node selection circuit 15 for each plane includes an AND gate 31 that decodes the plane selection signal PS and the specific node selection signal NS, and a level shift circuit 32 that increases the output voltage level of the AND gate 31. And a transfer gate 33 made of a MOSFET. One end of the transfer gate 33 is connected to a specific node (global bit line), and the other end of the transfer gate 33 is connected to a connection wiring 30 connected to the test voltage measurement terminal 25. As a result, the voltage level of the specific node can be measured from the outside of the inventive device 10 (for example, an external tester) from the test voltage measurement terminal 25 and is selected by the local bit line selection circuit 13 from the voltage level of the specific node. The selected bit line voltage applied to the selected bit line during the write operation can be monitored from the outside (for example, an external tester).

  The block selection circuit 16 is provided for each memory cell block 11, receives a block address signal BA, and receives a block selection signal (not shown) for determining whether or not the corresponding memory cell block 11 is selected in the same memory. The data is output to the word line selection circuit 12 and the local bit line selection circuit 13 in the cell block 11.

  The read circuit 17 is configured to read data in the selected memory cell based on the amount of current flowing through the selected bit line selected by the local bit line selection circuit 13 and the global bit line selection circuit 14 during the read operation. ing. As the circuit configuration of the read circuit 17, one that is suitable for the array configuration of the memory cell block 11 is adopted from various known circuit configurations, and detailed description thereof is omitted.

  The write voltage switch circuit 18 is provided for each plane, and is supplied from the write operation bit line voltage generation circuit 20 or the external voltage application terminal 24 to the selected global bit line selected by the global bit line selection circuit 14. This is a circuit that selectively applies a bit line voltage for a write operation in accordance with a data value of write data. Specifically, the bit line voltage is applied when the data value is “0”, and is not applied when the data value is “1”. In the normal write operation, the write voltage switch circuit 18 is connected to the write operation bit line voltage generation circuit 20 via the first switch circuit 22, the second switch circuit 23, and the bit line voltage supply wiring 29. In the test mode, the external voltage application terminal 24 is connected via the second switch circuit 23 and the bit line voltage supply wiring 29.

  The voltage generation circuit 19 for each operation mode applies a positive selected word line voltage (corresponding to a selected row voltage, for example, 12 V) for a write operation applied to a selected word line connected to a control gate of a selected memory cell during a write operation. A selection word line voltage generation circuit for write operation generated by boosting the power supply voltage, and a positive selection word line voltage for read operation applied to the selected word line during the read operation (corresponding to a selected row voltage, for example, 5V), a selected word line voltage generation circuit for read operation that is generated by boosting the power supply voltage, and a negative selected word line voltage for erase operation that is applied to all the word lines of the selected memory cell block during the erase operation. (Corresponding to the selected row voltage. For example, -8V), and when the test mode is selected, all the memory cell blocks selected as test targets are A negative voltage generating circuit for generating a negative non-selected word line voltage (corresponding to a non-selected row voltage; for example, −2 V) for turning off the memory cell on the line, and a source line of the selected memory cell block during the erasing operation And a source line voltage generation circuit for erasing operation that generates a positive source line voltage for erasing operation by boosting the power supply voltage.

  Here, since the negative voltage generation circuit of the voltage generation circuit 19 for each operation mode generates different negative voltage values during the erase operation and when the test mode is selected, the circuit configuration will be described with reference to FIG. The negative voltage generation circuit of the present embodiment includes a negative voltage pump circuit 40, a comparator 41, and a voltage dividing resistor 42 that divides between the first reference voltage V1 (for example, 2V) and the negative voltage Vneg generated by the negative voltage pump circuit 40. -44 and the N-type MOSFET 45, the P-type MOSFET 46 for switching on / off of the voltage-dividing circuit, the inverter 47 for generating the gate signal of the P-type MOSFET 46 from the activation signal Eneg of the negative voltage generating circuit, the comparator 41 and the activation An AND gate 48 that generates an activation signal for the negative voltage pump circuit 40 from the signal Eeg, and a level shift that generates a gate signal for the N-type MOSFET 45 from the mode selection signal MS that switches the signal level between the erase operation and the test mode selection. A circuit 49 is provided.

  In the circuit configuration shown in FIG. 3, an N-type MOSFET 45 and a level shift circuit 49 are added to the circuit configuration of a general negative voltage generation circuit, so that the voltage level of the negative voltage Vneg is -8V or -2V. Either one can be selected. When the activation signal Eneg is high and the negative voltage generating circuit is activated, the voltage level at the connection point Nc of the voltage dividing resistors 42 and 43 of the voltage dividing circuit is the second reference voltage connected to the inverting input of the comparator 41. When V2 (for example, 1.5V) is exceeded, the output level of the comparator 41 becomes a high level, the negative voltage pump circuit 40 is activated, and the voltage level of the negative voltage Vneg is operated to be a more negative voltage. The voltage dividing ratio of the voltage dividing circuit is such that the negative voltage Vneg is −8V and the voltage level of the connection point Nc is 1.5V during the erase operation when the N-type MOSFET 45 is OFF, and the N-type MOSFET 45 is ON. The resistance values of the voltage dividing resistors 42 to 44 are set so that the negative voltage Vneg is −2 V and the voltage level of the connection point Nc is 1.5 V when the mode is selected. The first reference voltage V1 and the second reference voltage V2 are each generated based on the power supply voltage.

  The write operation bit line voltage generation circuit 20 selects from the write operation bit line voltage generation circuit 20 such that a desired selection bit line voltage (for example, 5 V) is applied to the selection bit line during the write operation. The first switch circuit 22, the second switch circuit 23, the bit line voltage supply wiring 29, and the write voltage switch circuit are generated by generating a boosted voltage in consideration of the voltage drop on the voltage supply path leading to the memory cell. 18, the data is supplied to the selected bit line via the global bit line selection circuit 14, the selected global bit line, and the local bit line selection circuit 13.

  The voltage generation circuit 19 for each operation mode that boosts the power supply voltage to generate a positive voltage is a selected word line voltage generation circuit for write operation and read operation, a source line voltage generation circuit for erase operation, and a write operation As the bit line voltage generation circuit 20, a circuit configuration of each voltage generation circuit that is suitable for the device of the present invention is adopted from various known circuit configurations, and detailed description thereof is omitted.

  The bit line voltage regulator circuit 21 determines the gate level of the second switch circuit 23 composed of a P-type MOSFET interposed between the external voltage application terminal 24 and the bit line voltage supply wiring 29, as the bit line voltage supply wiring 29. By adjusting according to the voltage level, the voltage level of the bit line voltage supply wiring 29 is stabilized in cooperation with the second switch circuit 23.

  The first switch circuit 22 separates the write operation bit line voltage generation circuit 20 and the external voltage application terminal 24, and is supplied from either the write operation bit line voltage generation circuit 20 or the external voltage application terminal 24. A voltage is selected and supplied to each bit line voltage supply wiring 29 via the second switch circuit 23. In the present embodiment, the drain and gate of the N-type MOSFET are connected in common to the output node of the write operation bit line voltage generation circuit 20, and the source is connected to one end of the second switch circuit 23 for writing operation. It is configured as a diode circuit that flows from the bit line voltage generation circuit 20 to the second switch circuit 23 side.

  The second switch circuit 23 individually connects each bit line voltage supply wiring 29 to the bit line voltage generation circuit 20 for write operation and the one selected by the first switch circuit 22 of the external voltage application terminal 24.

  In the present embodiment, the first switch circuit 22, the second switch circuit 23, and the external voltage application terminal 24 are individually provided for each bit line voltage supply wiring 29. Further, the bit line voltage supply wiring 29 is provided for each plane. Since the block configuration example shown in FIG. 1 illustrates two planes, the first switch circuit 22, the second switch circuit 23, the external voltage application terminal 24, and the bit line voltage supply wiring 29 have two independent systems. Exist. The bit line voltage supply wiring 29 is not necessarily provided for each plane. When the number of planes is large (for example, 4 or more), one bit line voltage supply wiring 29 is provided for a plurality of planes. May be assigned. The number of systems defined by the number of bit line voltage supply wirings 29 is not limited to two as long as the number of systems is also plural. Further, when the number of local bit lines in one memory cell block 11 is large, two or more bit line voltage supply wirings 29 may be assigned to one plane. The gist of the present invention is that one bit line voltage supply wiring 29 is provided to suppress a voltage drop in the voltage supply path from the external voltage application terminal 24 to each local bit line of each memory cell block 11. Since the number of local bit lines that can be connected simultaneously is reduced and a plurality of local bit lines are provided, the correspondence between one bit line voltage supply wiring 29 and the global bit line selection circuit 14 is shown in FIG. The circuit configuration is not limited.

  The output interface circuit 26 selects read data output from the read circuit 17 provided for each plane, converts it to a predetermined output voltage level from a data output terminal (not shown), and outputs it to the outside. It is.

  The input interface circuit 27 is an interface circuit that receives various input signals from the outside and supplies them to the internal circuit of the device 10 of the present invention. The input interface circuit 27 receives an address input from an address input terminal (not shown), a data input terminal A data input circuit for receiving data input from (not shown), a control input circuit for receiving various control inputs (chip enable input, output enable input, write enable input, etc.) from a plurality of control input terminals (not shown), etc. It is prepared for. Each circuit configuration of the input interface circuit 27 is the same as that used in a general flash memory, and detailed description and illustration are omitted.

  The control circuit 28 is a circuit that controls each memory operation of reading, writing, and erasing, and in particular, voltage application according to each operation mode to the memory cell in writing and erasing operations, and subsequent writing or erasing of the memory cells. A circuit that executes sequential control for performing a read operation for verifying a state in accordance with a predetermined control algorithm, and is configured by applying a state machine or a simple microprocessor. The operation mode is identified when a control input signal and an operation mode selection command input to the device of the present invention are input to the control circuit 28. An operation mode signal (including a mode selection signal MS and a specific node selection signal NS) indicating the recognized operation mode is transmitted from the control circuit 28 to the word line selection circuit 12, the local bit line selection circuit 13, and the global bit line selection circuit 14. Are output to the specific node selection circuit 15, the block selection circuit 16, the read circuit 17, the write voltage switch circuit 18, the operation mode voltage generation circuit 19, the write operation bit line voltage generation circuit 20, and the like. The control circuit 28 can use a well-known circuit configuration mounted on the flash memory, and thus a detailed description thereof is omitted.

  Next, the circuit operation at the time of writing operation and test mode selection of the device 10 of the present invention will be described.

<During writing operation>
First, the control circuit 18 outputs an operation mode signal indicating that a write operation is being performed to each circuit described above. In this case, since no external voltage is input to the external voltage application terminal 24, the bit line voltage output from the write operation bit line voltage generation circuit 20 is automatically selected by the first switch circuit 22, and the second switch The selected bit line of the selected memory cell block 11 through the circuit 23, the bit line voltage supply wiring 29, the write voltage switch circuit 18, the global bit line selection circuit 14, the selected global bit line, and the local bit line selection circuit 13. To be supplied. Note that the local bit line of the non-selected memory cell block 11 and the non-selected bit line of the selected memory cell block 11 are in an open state or a ground state (0 V applied), and the selected bit line voltage (5 V) is applied only to the selected bit line. The On the other hand, the operation mode voltage generation circuit 19 supplies the selected word line voltage (12 V) for the write operation to the word line selection circuit 12 of the selected memory cell block 11 and applies it to the selected word line. A ground voltage (0 V) is applied to the word lines of the non-selected memory cell block 11 and the non-selected word lines of the selected memory cell block 11, and each non-selected memory cell is turned off. Thereby, each terminal voltage for the write operation shown in FIG. 10 is applied to each terminal of the control gate 1, the drain 2 and the source 3 of the selected memory cell to be written, and the write operation by hot electron injection is executed. . At this time, since the selected bit line voltage (5 V) is also applied to the non-selected memory cells (word line voltage level 0 V) connected to the selected bit line at the same time, the memory cells that are easily erased (in this test mode) In the case of a defective memory cell to be removed by screening), when the non-selected memory cell is in a write state (a state where electrons are injected into the floating gate 5), a part of the injected electrons is on the drain side ( The bit line is weakly pulled out and the write operation on the same bit line is repeated in all memory cells except the non-selected memory cell, so that the electrons injected into the floating gate 5 of the non-selected memory cell are If released to a level that is not determined to be in the write state, an error will occur in the read operation (drain disturb current). ). Further, the operation margin of the read operation is lowered before the read error is reached.

<When test mode is selected>
Therefore, in the test mode, in order to efficiently screen and remove memory cells having low drain disturb tolerance, a plurality of bit lines significantly larger than the number of selected bit lines selected in the normal write operation are simultaneously selected. Then, the selected bit line voltage (5 V) is simultaneously applied to each selected bit line. In this embodiment, all the bit lines of all the memory cell blocks 11 are divided into two systems and selected simultaneously.

  First, the control circuit 18 outputs an operation mode signal indicating that the test mode is selected to each circuit described above. In this case, since an external voltage higher than the bit line voltage output from the write operation bit line voltage generation circuit 20 is input from the two external voltage application terminals 24, the operation state of the write operation bit line voltage generation circuit 20. Regardless of the test voltage, the test external bit line voltage input from each external voltage application terminal 24 is automatically selected by the first switch circuit 22, and the second switch circuit 23, the bit line voltage supply wiring 29, the write voltage, and so on. Via the switch circuit 18, the global bit line selection circuit 14, the selected global bit line, and the local bit line selection circuit 13, it is divided into planes and supplied to all bit lines of all memory cell blocks 11. . When the test mode is selected, the local bit line selection circuit 13 selects all the local bit lines and connects them to each global bit line, and the global bit line selection circuit 14 selects all the global bit lines and selects the write voltage switch circuit 18. The write voltage switch circuit 18 connects all selected global bit lines to the bit line voltage supply wiring 29 with write data “0”. Thereby, the second switch circuit 23, the bit line voltage supply wiring 29, and the write are written in all the bit lines of all the memory cell blocks 11 from the test external bit line voltages inputted from the respective external voltage application terminals 24. The selected bit line voltage dropped through the voltage supply path of the voltage switch circuit 18, the global bit line selection circuit 14, the selected global bit line, and the local bit line selection circuit 13 is applied.

  Here, the selection bit line voltage applied to each local bit line is different from the voltage of the global bit line by a voltage difference between both ends of each transfer gate of the local bit line selection circuit 13. The total off-leakage current of all the memory cells connected to the local bit lines is significantly smaller than the sum of the off-leakage currents of all the memory cells in all the memory cell blocks 11, which is 1 / the number of all the local bit lines. Since the voltage difference is negligible, the selected bit line voltage can be monitored by measuring the voltage level of the specific node selected by the specific node selection circuit 15 from the test voltage measurement terminal 25. Therefore, based on the voltage level of the specific node measured from the test voltage measurement terminal 25, the voltage level becomes a predetermined value at the same voltage level as the selected bit line voltage applied to the selected bit line during the normal write operation. As described above, the voltage level of the test external bit line voltage input from each external voltage application terminal 24 is adjusted. However, the voltage level of the external bit line voltage depends on the breakdown voltage of the transistors used in the device 10 of the present invention, for example, the transistors constituting the first switch circuit 22, the second switch circuit 23, the write voltage switch circuit 18, etc. Restricted to be: When the voltage level of the external bit line voltage exceeds the withstand voltage, the external bit line can be reduced by reducing the number of memory cell blocks simultaneously selected in the same plane or by reducing the number of global bit lines simultaneously selected. It is necessary to adjust so that the voltage level of the voltage is equal to or lower than the withstand voltage.

  On the other hand, the non-selected word line voltage (−2V) when the test mode is selected is supplied from the voltage generation circuit 19 for each operation mode to the word line selection circuits 12 of all the memory cell blocks 11, and all the memory cell blocks 11 are all connected. Applied to the word line. Therefore, although a negative voltage of −2 V is applied to the control gates of all the memory cells, the selected bit line voltage is applied to the drains, and the drains of the unselected memory cells during the normal write operation. The same voltage application conditions are applied.

  Here, as a comparative example, the test external voltage input from the external voltage application terminal 24 is applied to one system of the second switch circuit 23 and the bit line voltage supply wiring by the conventional circuit configuration illustrated in FIG. As shown in FIG. 15, all the bit lines of the four memory cell blocks 11 are provided by the circuit configuration commonly supplied to the write voltage switch circuit 18 and the global bit line selection circuit 14 of two planes When a high voltage stress is applied in a batch and the external input voltage exceeds the breakdown voltage, a desired high voltage stress (for example, 5V) cannot be applied to the memory cell. In the circuit configuration of the device 10 of the present invention in FIG. 1 and the comparative example illustrated in FIG. 4, the corresponding circuits are denoted by the same reference numerals, and the memory cell blocks 11 in both circuit configurations are exactly the same. Suppose there is.

  In contrast to the comparative example illustrated in FIG. 4, in the present embodiment, the first switch circuit 22, the second switch circuit 23, the external voltage application terminal 24, and the bit line voltage supply wiring 29 are each independently 2 for each plane. Since there is a system, even when all the bit lines of the four memory cell blocks 11 are selected and the selected bit line voltage is applied all at once, all the bits of the two memory cell blocks 11 can be applied to each system from one external voltage application terminal 24. Since the selected bit line voltage is applied to each line separately, as shown in FIG. 5, the situation is the same as when the two memory cell blocks 11 of FIG. 15 are simultaneously selected, and the test time is a comparative example illustrated in FIG. In this case, the application of the test external input voltage is performed in two steps. However, the test time can be shortened to one half because only one application is required.

  Hereinafter, the processing procedure of the drain disturb screening test by the method of the present invention using the test mode of the present embodiment will be described with reference to FIG. First, all memory cells in all memory cell blocks 11 are set in a write state by a normal write operation (step # 11). Next, the device 11 of the present invention is set to a test mode, and the voltage generation circuit 19 for each operation mode is controlled to generate a non-selected word line voltage (−2 V) when the test mode is selected. The negative voltage of −2V is applied to the control gates of all the memory cells (step # 12). In parallel with the control of step # 12, the write voltage switch circuit 18, the global bit line selection circuit 14, and the local bit line selection circuit 13 are controlled to thereby control all the local bit lines of all the memory cell blocks 11. However, they are electrically connected to the external voltage application terminals 24 individually through the two systems of the second switch circuit 23 and the bit line voltage supply wiring 29 (step # 13). Further, in parallel with the control of steps # 12 and # 13, the specific node selection circuit 15 is controlled to select a specific node of one of the planes and to electrically connect to the test voltage measurement terminal 25 ( Step # 14). Next, while measuring the voltage level of a specific node and monitoring the selected bit line voltage, an external bit line voltage for test is supplied from each external voltage application terminal 24, and the selected bit line voltage is changed to a normal write operation. Sometimes the voltage level rises to a predetermined value at the same voltage level as the selected bit line voltage applied to the selected bit line, and in this state, the external bit line voltage is applied to the selected bit during normal write operation. More than a period corresponding to a value (N-1) times a value obtained by subtracting 1 from the number (N) of memory cells connected to one local bit line for a line voltage application time (for example, 1 μsec) (for example, (N−1 ) [Mu] sec or more) After continuing, the application is stopped (step # 15). Thereafter, all the memory cells in all the memory cell blocks 11 are sequentially read, and the memory cells that are not determined to be data “0” are extracted as defective memory cells (step # 16). The extracted defective memory cell is replaced with a redundant repair memory cell to repair the defect (step # 17). Here, the processes of steps # 12 to # 14 may be performed in an arbitrary order without being performed in parallel. In step # 15, in the measurement of the voltage level of the specific node, the specific node selection circuit 15 is controlled to switch the specific node so as to confirm that the voltage levels of all the specific nodes have reached the predetermined value. It is also preferable to do this. Further, in step # 15, during the measurement of the voltage level of the specific node, the specific node having the lowest measurement level may be detected and selected as a monitoring target.

  Next, in step # 15 of the screening test shown in FIG. 6, a predetermined value used for controlling the external bit line voltage (the same voltage level as the selected bit line voltage applied to the selected bit line during normal write operation) is acquired in advance. The method of the present invention will be described with reference to FIG.

  First, all memory cells in all memory cell blocks 11 are set in a write state by a normal write operation (step # 21). Next, the device 11 of the present invention is set to a test mode, and the voltage generation circuit 19 for each operation mode is controlled to generate a non-selected word line voltage (−2 V) when the test mode is selected. The negative voltage of −2 V is applied to the control gates of all the memory cells (step # 22). In parallel with the control in step # 22, the write voltage switch circuit 18, the global bit line selection circuit 14, and the local bit line selection circuit 13 are controlled to include a specific node of one memory cell block 11. One local bit line to be connected to the bit line is selected, and the output terminal of the write operation bit line voltage generation circuit 20 via the first switch circuit 22, the second switch circuit 23, and the bit line voltage supply wiring 29. (Step # 23). Further, in parallel with the control of steps # 22 and # 23, the specific node selection circuit 15 is controlled to select the specific node of the plane to which the local bit line selected in step # 23 belongs, and the test voltage measurement terminal 25 (step # 24). Next, the write operation bit line voltage generation circuit 20 is activated to output a high voltage output during a normal write operation, and the selected bit line voltage is applied to the local bit line selected in step # 23 (step #). 25). Next, the voltage level of the specific node is measured, and the measured level is set to a predetermined value (step # 26). Note that the processes of steps # 22 to # 24 may be performed in an arbitrary order without being performed in parallel.

[Second Embodiment]
FIG. 8 schematically shows a schematic block configuration in the second embodiment of the device 10 of the present invention. As shown in FIG. 8, in the second embodiment of the device 10 of the present invention, the first switch circuit 22 and the external voltage application terminal 24 are configured by one each compared to the configuration of the first embodiment shown in FIG. is doing. That is, in the first embodiment, the voltage supply path for the write operation bit line voltage from the write operation bit line voltage generation circuit 20 to the global bit line selection circuit 14 is the output terminal of the write operation bit line voltage generation circuit 20. However, in the second embodiment, the external voltage application terminal 24 is branched into two systems. The other circuit configuration is exactly the same as that of the first embodiment, and a duplicate description is omitted. When the test mode is selected, the voltage supply path of the external bit line voltage supplied from the external voltage application terminal 24 is branched into two systems, so that the same effect as in the first embodiment can be obtained.

[Third Embodiment]
FIG. 9 schematically shows a schematic block configuration in the third embodiment of the device 10 of the present invention. As shown in FIG. 9, in the third embodiment of the device 10 of the present invention, a specific node selection circuit 15, a test voltage measurement terminal 25, and a connection wiring 30 are provided in the configuration of the first embodiment shown in FIG. 1. It is configured without. The other circuit configuration is exactly the same as that of the first embodiment, and a duplicate description is omitted.

  In the third embodiment, a drain disturb screening test is performed without monitoring the voltage level of a specific node from the test voltage measurement terminal 25. Therefore, in step # 15 of the screening test procedure shown in FIG. 6, when supplying an external bit line voltage for testing from each external voltage application terminal 24, the voltage level of a specific node is not monitored. An input voltage level acquired in advance by simulation or experiment is supplied from each external voltage application terminal 24. In this case, it is impossible to cope with variations among chips, wafers or lots, but since the specific node selection circuit 15, the test voltage measurement terminal 25, and the connection wiring 30 are not provided, an increase in chip area can be suppressed. The test procedure can be simplified.

  Next, another embodiment of the device of the present invention will be described.

  <1> In each of the above embodiments, the non-selected word line voltage (−2 V) when the test mode is selected is supplied from the operation mode voltage generation circuit 19 to the word line selection circuits 12 of all the memory cell blocks 11 to be tested. However, the voltage applied to all the word lines of each memory cell block 11 is changed to the normal write operation instead of the unselected word line voltage (-2V). The unselected word line voltage (0V) at the time may be used. In this case, the negative voltage generation circuit of the voltage generation circuit 19 for each operation mode only needs to generate only the selected word line voltage (−8 V) as a negative voltage during the erase operation. Therefore, in the circuit configuration shown in FIG. And the N-type MOSFET 45 becomes unnecessary.

  <2> Furthermore, in the first and second embodiments, when supplying the test external bit line voltage from each external voltage application terminal 24 in step # 15 of the screening test procedure shown in FIG. The voltage level of the specific node is monitored to adjust the external bit line voltage. However, as in the third embodiment, the voltage level of the specific node is not monitored, but the input obtained by simulation or experiment in advance. The voltage level may be supplied from each external voltage application terminal 24. In the first and second embodiments, since the specific node selection circuit 15, the test voltage measurement terminal 25, and the connection wiring 30 are provided, these are used to input the voltage level of the specific node to a predetermined value. The voltage level can be acquired in advance.

  <3> Further, in the third embodiment, the specific node selection circuit 15, the test voltage measurement terminal 25, and the connection wiring 30 are not provided on the basis of the circuit configuration of the first embodiment. A similar circuit configuration may be used on the basis of the circuit configuration of the embodiment.

  <4> Further, in each of the above embodiments, a plurality of memory cell blocks 11 arranged in the column direction form one plane, and the local bit line selection circuit 13 is used to locally connect the memory cell blocks 11 in the same plane. Although the bit line is connected to the global bit line and the global bit line is selected by the global bit line selection circuit 14 in the plane unit, it has a hierarchical bit line selection structure. A configuration may be employed in which a write voltage switch circuit 18 is provided for each memory cell block 11 and is directly connected to the local bit line selection circuit 13 without being provided.

  Also, in the case of configuring a plane, a single plane may be configured by a plurality of memory cell blocks 11 arranged in the row direction. In this case, a hierarchical word line selection structure is obtained.

  <5> Furthermore, in each of the above embodiments, the single bit line voltage regulator circuit 21 is commonly used for the plurality of second switch circuits 23. However, each bit switch voltage 23 is individually provided for each second switch circuit 23. A circuit configuration in which the bit line voltage regulating circuit 21 is provided may be used. In this case, only one of the second switch circuits 23 corresponding to the selected plane is turned on during the normal write operation, and all the second switch circuits 23 are turned on when the test mode is selected. The bit line voltage regulator circuit 21 can be controlled.

  <6> Further, in each of the above embodiments, the memory cell is assumed to be the flash memory cell having the element structure shown in FIGS. 10 to 12. On the other hand, the device of the present invention and the method of the present invention can also be applied to a memory cell having a structure in which data deterioration may occur due to stress applied from the selected bit line side.

  The present invention can be used for a nonvolatile semiconductor memory device, and is particularly useful for a test method for efficiently screening for data deterioration defects accompanying a write operation of a memory cell in a nonvolatile semiconductor memory device.

1 is a block diagram schematically showing a schematic block configuration in a first embodiment of a nonvolatile semiconductor memory device according to the present invention. 4 is a circuit diagram showing a circuit configuration example of a specific node selection circuit of the nonvolatile semiconductor memory device according to the present invention. The circuit diagram which shows the circuit structural example of the negative voltage generation circuit in the voltage generation circuit according to operation mode of the non-volatile semiconductor memory device which concerns on this invention A block diagram schematically showing a schematic block configuration example of a conventional nonvolatile semiconductor memory device The figure which shows typically the relationship between the external stress voltage applied to the external voltage application terminal and the selection bit line voltage in the non-volatile semiconductor memory device which concerns on this invention 6 is a flowchart showing a processing procedure of a drain disturb screening test by a test method for a nonvolatile semiconductor memory device according to the present invention. 10 is a flowchart showing a processing procedure for acquiring a selected bit line voltage applied to a selected bit line during a normal write operation by a test method for a nonvolatile semiconductor memory device according to the present invention. The block diagram which shows typically the schematic block configuration in 2nd Embodiment of the non-volatile semiconductor memory device which concerns on this invention The block diagram which shows typically the schematic block structure in 3rd Embodiment of the non-volatile semiconductor memory device which concerns on this invention Device cross-sectional view schematically showing the voltage application condition for each terminal and the flow of electrons between the floating gate and each terminal during the write operation to the flash memory cell Device sectional view schematically showing the voltage application condition for each terminal and the flow of electrons between the floating gate and each terminal during the erase operation to the flash memory cell Device cross-sectional view schematically showing the voltage application condition for each terminal and the flow of electrons between the floating gate and each terminal during a read operation to the flash memory cell Chart showing a list of voltage application conditions to each terminal in each memory operation of the flash memory cell The figure which shows the structural example of the memory cell block in NOR type flash memory The figure which shows typically the relationship between the external stress voltage applied to the external voltage application terminal and the selection bit line voltage in the conventional non-volatile semiconductor memory device

Explanation of symbols

1: Flash memory cell control gate 2: Flash memory cell drain 3: Flash memory cell source 4: Flash memory cell substrate 5: Flash memory cell floating gate 6: Flash memory cell tunnel oxide film 7: Flash memory Cell insulating film 8: Memory cell to be written 9: Non-selected memory cell 10: Non-volatile semiconductor memory device according to the present invention 11: Memory cell block 12: Word line selection circuit (row selection circuit)
13: Local bit line selection circuit (column selection circuit)
14: Global bit line selection circuit (column selection circuit)
15: Specific node selection circuit (third switch circuit)
16: Block selection circuit 17: Read circuit 18: Write voltage switch circuit 19: Voltage generation circuit for each operation mode 20: Bit line voltage generation circuit for write operation (selected row voltage generation circuit)
21: Bit line voltage regulator 22: First switch circuit 23: Second switch circuit 24: External voltage application terminal 25: Test voltage measurement terminal 26: Output interface circuit 27: Input interface circuit 28: Control circuit 29: Bit Line voltage supply wiring 30: Connection wiring 31: AND gate 32: Level shift circuit 33: Transfer gate 40: Negative voltage pump circuit 41: Comparator 42 to 44: Voltage dividing resistor 45: N-type MOSFET
46: P-type MOSFET
47: Inverter 48: AND gate 49: Level shift circuit BA: Block address signal BL: Bit line CA1, CA2: Column address signal Eeg: Activation signal of negative voltage generation circuit Ids: Memory cell current MS: Mode selection signal NS: Specific node selection signal Nc: Connection point (Non-inverting input of comparator)
PS: Plane selection signal RA: Row address signal SL: Source line V1: First reference voltage V2: Second reference voltage Vneg: Negative voltage VPP: External voltage application terminal WL: Word line

Claims (7)

A first terminal, a second terminal, and a control terminal for controlling conduction between the first terminal and the second terminal, and electrically reading data by applying a voltage to each terminal according to an operation mode; A block group in which a plurality of memory cell blocks are arranged in which a plurality of nonvolatile memory cells capable of writing operation and erasing operation are arranged in the row and column directions;
In one of the memory cell blocks, one or more columns of the memory cells are selected, and a selected column corresponding to the operation mode is selected for the first terminal of the memory cell in the selected selected column. A column selection circuit that applies a voltage and applies a non-selected column voltage corresponding to the operation mode to the first terminal of the memory cell of the non-selected column that is not selected, or sets a voltage non-applied state. When,
In one of the memory cell blocks, one or more rows of the memory cells are selected in units of rows, and a selected row voltage corresponding to the operation mode with respect to the control terminal of the memory cell of the selected selected row. And applying a non-selected row voltage according to the operation mode to the control terminals of the memory cells in the non-selected non-selected rows, and the control terminals of the memory cells in all rows for testing. A row selection circuit for applying the unselected column voltage or the unselected row voltage for testing to
A write column voltage generation circuit that generates the selected column voltage during the write operation and supplies the selected column voltage to the column selection circuit;
A selected row voltage generation circuit that generates the selected row voltage according to the operation mode and supplies the selected row voltage to the row selection circuit, and a nonvolatile semiconductor memory device comprising:
A plurality of voltage supply paths for supplying the selected column voltage during the write operation from the write column voltage generation circuit to the column selection circuit;
An external voltage application terminal capable of applying an external voltage for testing to the plurality of voltage supply paths;
The write column voltage generation circuit and the external voltage application terminal are separated, and a voltage supplied from either the write column voltage generation circuit or the external voltage application terminal is selected and supplied to the plurality of voltage supply paths. A first switch circuit that
The write column voltage generation circuit, the one selected by the first switch circuit of the external voltage application terminal, and a second switch circuit for individually connecting the plurality of voltage supply paths,
The column selection circuit selects, in a predetermined test mode, a selection column for testing that is larger than the number of selection columns simultaneously selected in the normal write operation for one or a plurality of the memory cell blocks. The test selection column is divided for each of the voltage supply paths, and the test is applied from the external voltage application terminal to the first terminal of the memory cell of each of the divided selection columns for test. The nonvolatile semiconductor memory device is configured to be able to apply the selected column voltage for testing that has been dropped from the external voltage for use via the corresponding voltage supply path. A plurality of external voltage application terminals are provided,
The first switch circuit separates each of the write column voltage generation circuit and the plurality of external voltage application terminals,
2. The nonvolatile semiconductor memory according to claim 1, wherein each of the voltage supply paths can be connected to one of the corresponding external voltage application terminals by the second switch circuit. apparatus. In the predetermined test mode, a test voltage measurement terminal for measuring the selected column voltage for a test with a voltage drop applied to the selected column selected by the column selection circuit;
The test voltage measurement terminal is specified for each of the voltage supply paths between the end of the voltage supply path on the column selection circuit side and any one of the selected columns selected in the predetermined test mode. The nonvolatile semiconductor memory device according to claim 1, further comprising a third switch circuit connected to the node. The first switch circuit comprises a diode circuit;
The write column voltage generation circuit is connected to the anode side of the diode circuit, and the external voltage application terminal and one end of the second switch circuit are connected to the cathode side of the diode circuit. The nonvolatile semiconductor memory device according to any one of 1 to 3. The selected row voltage generation circuit generates a negative voltage having an absolute value lower than the negative voltage applied as the selected row voltage during the erasing operation as the unselected row voltage for the test in the predetermined test mode;
The row selection circuit applies a non-selection row voltage of the test negative voltage supplied from the selection row voltage generation circuit to the control terminals of the memory cells in all rows of the selected memory cell block. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is a non-volatile semiconductor memory device. A test method for evaluating data deterioration of a memory cell accompanying a write operation to the nonvolatile semiconductor memory device according to claim 3,
Setting the nonvolatile semiconductor memory device to the predetermined test mode;
The row selection circuit applies a predetermined unselected row voltage to the control terminals of the memory cells in all rows for one or a plurality of the memory cell blocks to be tested.
The column selection circuit selects, for one or a plurality of the memory cell blocks to be tested, more test selection columns than the number of selection columns simultaneously selected during the normal write operation.
The first switch circuit and the second switch circuit select a voltage supplied from the external voltage application terminal and supply the selected voltage to the plurality of voltage supply paths; and
The third switch circuit controls each of the test voltage measurement terminal and the one specific node of the voltage supply path to be connected,
A voltage is applied to the external voltage application terminal, the voltage of the specific node output to the test voltage measurement terminal is measured, and the selected column voltage for testing obtained from the voltage of the specific node is a predetermined value. The method for testing a nonvolatile semiconductor memory device, wherein the voltage value applied to the external voltage application terminal is controlled within a specified voltage range. Measuring the predetermined value of the selected column voltage for the test before applying a voltage to the external voltage application terminal,
In the step of measuring the predetermined value,
Setting the nonvolatile semiconductor memory device to the predetermined test mode;
The row selection circuit applies a predetermined unselected row voltage to the memory cells in all rows for one of the memory cell blocks to be tested.
The column selection circuit selects one selection column for testing for one of the memory cell blocks to be tested.
The first switch circuit and the second switch circuit select a voltage supplied from the write column voltage generation circuit and supply it to the voltage supply path connected to the one selected column; and
The third switch circuit controls each of the specific node of the voltage supply path connected to the one selected column and the test voltage measurement terminal to be connected;
7. The test method for a nonvolatile semiconductor memory device according to claim 6, wherein a voltage of the specific node output to the test voltage measurement terminal is measured and set to the predetermined value.

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