JP2009098335A - Thin film transistor substrate, manufacturing method thereof, and liquid crystal display device - Google Patents

Abstract

An object of the present invention is to reliably achieve both improvement in light transmittance in a transmission region and reduction in capacitance in a wiring intersection region.
A plurality of first wirings extending in parallel to each other, a plurality of second wirings 19a extending in parallel to each other intersecting each first wiring, and provided between each first wiring and each second wiring 19a. A first interlayer insulating film 18 including the formed silicon nitride film 16, a second interlayer insulating film 19 provided on the opposite side of the first interlayer insulating film 18 of each second wiring 19a, and a second interlayer insulating film 19 A plurality of pixel electrodes 21 provided in a matrix on the opposite side of each second wiring 19a, each transmissive region T surrounded by each adjacent first wiring and each adjacent second wiring 19a; A TFT substrate 30 in which a wiring and a wiring intersection region Y where each second wiring 19a intersects is defined, and the film thickness of the silicon nitride film 16 in the transmission region T is the film thickness of the silicon nitride film 16 in the wiring intersection region Y. Thinner than thickness, 130nm or more and 160nm or less It is.
[Selection] Figure 3

Description

  The present invention relates to a thin film transistor substrate, a method for manufacturing the same, and a liquid crystal display device.

  An active matrix liquid crystal display device includes, for example, a thin film transistor (hereinafter referred to as “TFT”) and a pixel electrode connected to the TFT for each sub-pixel constituting each pixel which is the minimum unit of an image. A TFT substrate. In this TFT substrate, since the pixel electrode is formed on the insulating film, the configuration of the insulating film serving as the base film of the pixel electrode affects the light transmittance of the liquid crystal display device.

  For example, Patent Document 1 discloses a liquid crystal display device in which an underlayer existing under a translucent electrode is selectively removed or thinned. According to this, it is described that the light transmittance in the pixel region can be increased, and the brightness and contrast of the display can be improved without changing the aperture ratio.

  Patent Document 2 discloses a display device in which an interlayer insulating film is in direct contact with a substrate in a light transmission portion. According to this, light reflection due to a difference in refractive index at the interface between the substrate and the gate insulating film or at the interface between the passivation film and the interlayer insulating film does not occur, and the light transmittance is improved and a bright display is achieved. It is described that it is obtained.

  Patent Document 3 discloses a liquid crystal display device in which an interlayer insulating film is made of a silicon nitride film, and the silicon nitride film is partially or entirely removed in a pixel electrode formation region. According to this, it is described that a liquid crystal display device with improved transmittance can be realized.

Patent Document 4 discloses a thin film transistor array panel in which a silicon nitride film and a pixel electrode are formed with film thicknesses that satisfy a predetermined interference condition. And according to this, it is described that the transmittance is improved and the display quality is improved accordingly.
JP 10-282530 A Japanese Patent Application Laid-Open No. 11-4003 JP 2000-305111 A JP 2006-171673 A

  By the way, in the TFT substrate, in order to improve the area ratio of a region effective for display in one pixel, that is, the aperture ratio of the pixel, a pixel electrode is formed on an interlayer insulating film, and a gate line, a source line, etc. A high aperture ratio structure has been proposed in which pixel electrodes are also arranged on display wiring.

  FIG. 9 is a plan view of a conventional TFT substrate 130 having a high aperture ratio structure, and FIG. 10 is a cross-sectional view of the TFT substrate 130 taken along line XX in FIG.

  As shown in FIG. 10, in the TFT substrate 130, a first base coat film 111a, a second base coat film 111b, a gate insulating film 113, a first interlayer insulating film 118, and a second interlayer insulating film 120 are sequentially stacked on a glass substrate 110. It has a multilayered structure. A semiconductor layer 112 is provided between the second base coat film 111b and the gate insulating film 113 as shown in FIGS. A gate line 114a and a capacitor line 114b are provided between the gate insulating film 113 and the first interlayer insulating film 115 as shown in FIGS. Further, between the first interlayer insulating film 118 and the second interlayer insulating film 120, as shown in FIGS. 9 and 10, a source line 119a and a drain lead electrode 119b are provided. Furthermore, on the second interlayer insulating film 120, as shown in FIGS. 9 and 10, pixel electrodes 121 are provided in a matrix.

  Here, the first interlayer insulating film 118 is often formed of a stacked film including a silicon nitride film in order to ensure hydrogenation of dangling bonds in the semiconductor layer 112. Since the silicon nitride film has a relatively high refractive index, if it is simply formed thick, the light transmittance will be reduced. Conversely, if it is simply formed thin, the gate line 114a, the capacitor line 114b, the source line 119a, The electric capacity of the wiring crossing region Y increases. For this reason, in the conventional TFT substrate having a high aperture ratio structure, there is a trade-off relationship between an improvement in light transmittance and a reduction in the capacitance of the wiring intersection region, and it has been difficult to achieve both.

  The present invention has been made in view of such a point, and an object of the present invention is to reliably achieve both improvement of the light transmittance of the transmission region and reduction of the capacity of the wiring intersection region.

  In order to achieve the above object, according to the present invention, the thickness of the silicon nitride film in the transmission region is smaller than the thickness of the silicon nitride film in the wiring intersection region, and is 130 nm or more and 160 nm or less.

  Specifically, a thin film transistor substrate according to the present invention includes a plurality of first wirings provided so as to extend in parallel to each other, and a plurality of second wirings provided so as to cross each of the first wirings and extend in parallel with each other. And a first interlayer insulating film including a silicon nitride film provided between the first wirings and the second wirings, and the second wirings on the opposite side of the first interlayer insulating film. Each of the second interlayer insulating film and a plurality of pixel electrodes provided in a matrix on the opposite side of the second wiring of the second interlayer insulating film. A thin film transistor substrate in which a transmission region surrounded by a second wiring and a wiring intersection region where the first wiring and the second wiring intersect are defined, and the film thickness of the silicon nitride film in the transmission region is Silicon nitride in the wiring intersection region Thinner than the thickness of down film, characterized in that more than 130nm and is 160nm or less.

  According to the above configuration, the relatively high refractive index silicon nitride film constituting the first interlayer insulating film between the first wirings and the second wirings has the adjacent first wirings and the adjacent first wirings. In the transmission region surrounded by two wirings, each first wiring and each second wiring are formed thinner than the wiring crossing region where the first wiring and each second wiring intersect, and the film thickness is 130 nm or more and 160 nm or less, and each second wiring and each pixel Since the second interlayer insulating film between the electrodes has the same film thickness in the transmission region and the wiring intersection region, the light transmittance in the transmission region can be improved. Further, since the silicon nitride film is formed relatively thick in the wiring intersection region, the first interlayer insulating film becomes thick and is formed in the first interlayer insulating film between each first wiring and each second wiring. The electric capacity is smaller. Therefore, in the thin film transistor substrate, it is possible to reliably achieve both improvement of the light transmittance of the transmission region and reduction of the capacitance of the wiring intersection region.

  Here, since the light transmittance in the transmissive region periodically changes with respect to the thickness of the silicon nitride film, when the thickness of the silicon nitride film in the transmissive region is smaller than 130 nm or larger than 160 nm. The light transmittance in the transmissive region is reduced. Furthermore, when the film thickness of the silicon nitride film in the transmission region is smaller than 130 nm, there is a possibility that hydrogenation of dangling bonds in the semiconductor layer constituting the thin film transistor may be incomplete.

  Each pixel electrode may have a peripheral edge overlapping each of the first wiring and the second wiring.

  According to the above configuration, since the peripheral edge of each pixel electrode overlaps each first wiring and each second wiring, a thin film transistor substrate having a high aperture ratio is specifically configured.

  Each of the first wirings may be a capacitor line, and each of the second wirings may be a source line.

  According to the above configuration, since each first wiring is a capacitance line and each second wiring is a source line, for example, a gate line extending between each capacitance line is arranged across the intermediate portion of each pixel electrode. A thin film transistor substrate is specifically configured.

  The method of manufacturing a thin film transistor substrate according to the present invention includes a plurality of first wirings provided so as to extend in parallel to each other, and a plurality of first wirings provided so as to cross the first wirings and extend in parallel with each other. Two wirings, a first interlayer insulating film provided between each first wiring and each second wiring, and a second wiring provided on the opposite side of each second wiring to the first interlayer insulating film. An interlayer insulating film and a plurality of pixel electrodes provided in a matrix on the opposite side of the second wiring of the second interlayer insulating film, the adjacent first wirings and the adjacent second wirings A method of manufacturing a thin film transistor substrate in which a transmissive region surrounded by and a wiring intersection region where each of the first wiring and the second wiring intersect is defined, wherein the first wiring is formed on a transparent substrate. First wiring formation step and covering each first wiring In this way, after an inorganic insulating film including a silicon nitride film and a photosensitive resin film are sequentially formed, the photosensitive resin film is exposed with a halftone, whereby a resist pattern in which a concave portion is provided in the region to be the transmission region. Forming a resist, a first etching step for etching the inorganic insulating film exposed from the resist pattern, and thinning the resist pattern by ashing to remove the bottom of the concave portion of the resist pattern, and then thinning the resist pattern A portion of the inorganic insulating film exposed from the resist pattern is etched to make the thickness of the silicon nitride film in the transmission region thinner than the thickness of the silicon nitride film in the wiring intersection region, and at least 130 nm and 160 nm A second etching step for forming the first interlayer insulating film by: After removing the thinned resist pattern, a second wiring forming step of forming the second wirings on the first interlayer insulating film, and the second interlayer insulating film so as to cover the second wirings A second interlayer insulating film forming step to be formed; and a pixel electrode forming step of forming each of the pixel electrodes on the second interlayer insulating film.

  According to the above method, in the first etching process, for example, the contact hole for connecting to the source region of the semiconductor layer provided on the transparent substrate side of each first wiring formed in the first wiring forming process is formed. For this purpose, a part of the inorganic insulating film is etched through a resist pattern having a recess formed in the resist formation step. In the second etching step, first, the resist pattern used in the first etching step is thinned by ashing, and the bottom of the concave portion of the resist pattern is removed, thereby exposing the inorganic insulating film in the region to be the transmission region. . Further, the upper portion of the inorganic insulating film exposed from the thinned resist pattern is etched to form a silicon nitride film thinner than the wiring intersection region in the transmission region, and the film thickness is set to 130 nm or more and 160 nm or less. As a result, a first interlayer insulating film is formed. Thereafter, a thin film transistor substrate is manufactured by performing a second wiring formation step, a second interlayer insulating film formation step, and a pixel electrode formation step. Here, in the manufactured thin film transistor substrate, the relatively high refractive index silicon nitride film constituting the first interlayer insulating film between each first wiring and each second wiring is connected to each adjacent first wiring and each adjacent first wiring. In the transmissive region surrounded by the matching second wirings, the first wirings and the second wirings are formed thinner than the wiring crossing region where the first wirings and the second wirings intersect, and the film thickness is 130 nm or more and 160 nm or less. Since the second interlayer insulating film between each pixel electrode and the pixel electrode has the same film thickness in the transmission region and the wiring intersection region, the light transmittance in the transmission region can be improved. Further, since the silicon nitride film is formed relatively thick in the wiring intersection region, the first interlayer insulating film becomes thick and is formed in the first interlayer insulating film between each first wiring and each second wiring. The electric capacity is smaller. Therefore, in the thin film transistor substrate, it is possible to reliably achieve both improvement of the light transmittance of the transmission region and reduction of the capacitance of the wiring intersection region.

  Further, a liquid crystal display device according to the present invention is a liquid crystal display device comprising a thin film transistor substrate and a counter substrate disposed to face each other, and a liquid crystal layer provided between the thin film transistor substrate and the counter substrate, The thin film transistor substrate includes a plurality of first wirings provided so as to extend in parallel to each other, a plurality of second wirings provided so as to cross each of the first wirings and extend in parallel with each other, and each of the first wirings. A first interlayer insulating film including a silicon nitride film provided between the wiring and each of the second wirings; and a second interlayer insulating film provided on the opposite side of each of the second wirings to the first interlayer insulating film. And a plurality of pixel electrodes provided in a matrix on the opposite side of the second interlayer insulating film from the second interlayer insulating film, and surrounded by the adjacent first wirings and the adjacent second wirings. On the transparent area and above A wiring intersection region where each first wiring and each second wiring intersect is defined, and the film thickness of the silicon nitride film in the transmission region is smaller than the film thickness of the silicon nitride film in the wiring intersection region, and is 130 nm or more. It is characterized by being 160 nm or less.

  According to the above configuration, the relatively high refractive index silicon nitride film constituting the first interlayer insulating film between the first wirings and the second wirings has the adjacent first wirings and the adjacent first wirings. In the transmission region surrounded by two wirings, each first wiring and each second wiring are formed thinner than the wiring crossing region where the first wiring and each second wiring intersect, and the film thickness is 130 nm or more and 160 nm or less, and each second wiring and each pixel Since the second interlayer insulating film between the electrodes has the same film thickness in the transmission region and the wiring intersection region, the light transmittance in the transmission region can be improved. Further, since the silicon nitride film is formed relatively thick in the wiring intersection region, the first interlayer insulating film becomes thick and is formed in the first interlayer insulating film between each first wiring and each second wiring. The electric capacity is smaller. Therefore, in the liquid crystal display device including the thin film transistor substrate, it is possible to reliably achieve both improvement of the light transmittance of the transmission region and reduction of the capacitance of the wiring intersection region.

  According to the present invention, the film thickness of the silicon nitride film in the transmissive region is smaller than the film thickness of the silicon nitride film in the wiring intersection region and is 130 nm or more and 160 nm or less. It is possible to reliably achieve a reduction in the capacity of the area.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited to the following embodiment.

  1 to 8 show one embodiment of a thin film transistor substrate (TFT substrate), a manufacturing method thereof, and a liquid crystal display device according to the present invention. Specifically, FIG. 1 is a cross-sectional view of the liquid crystal display device 50 of the present embodiment. FIG. 2 is a plan view of the TFT substrate 30 constituting the liquid crystal display device 50. 3, 4, and 5 are cross-sectional views of the TFT substrate 30 taken along lines III-III, IV-IV, and VV in FIG. 2, respectively.

  As shown in FIG. 1, the liquid crystal display device 50 includes a TFT substrate 30 and a counter substrate 40 that are arranged to face each other, a liquid crystal layer 35 provided between the TFT substrate 30 and the counter substrate 40, and the TFT substrate 30. And a counter material 40 and a sealing material 36 provided in a frame shape for enclosing the liquid crystal layer 35.

  As shown in FIG. 2, the TFT substrate 30 is provided as a plurality of gate lines 14a provided so as to extend in parallel with each other and first wirings so as to extend in parallel with each other between the gate lines 14a. The plurality of capacitor lines 14b, the plurality of source lines 19a provided as the second wiring, and the gate lines 14a and the sources are provided so as to extend in parallel to each other in a direction intersecting (orthogonal) with each capacitor line 14b. A plurality of TFTs 5 provided at each intersection of the lines 19a and a plurality of pixel electrodes 21 connected to each TFT 5 and provided in a matrix are provided. Here, as shown in FIG. 2, the peripheral edge of the pixel electrode 21 overlaps the capacitor line 14b and the source line 19a. In the TFT substrate 30, as shown in FIGS. 2 to 5, a transmission region T is defined in a region surrounded by each adjacent capacitor line 14 b and each adjacent source line 19 a, and each gate line 14 a and each capacitor A wiring intersection region Y is defined in a region where the line 14b and the source line 19a intersect.

  As shown in FIG. 2, the TFT 5 includes a gate electrode 14c in which a gate line 14a protrudes laterally, and a semiconductor layer 12 provided on the gate electrode 14c via a gate insulating film 13 (see FIGS. 3 to 5). It has. As shown in FIG. 2, the semiconductor layer 12 includes a channel region provided so as to overlap the gate electrode 14c, a source region (source electrode) provided on the right side of the channel region in the drawing, and a left side of the channel region in the drawing. And a storage capacitor region (storage capacitor electrode) provided so as to overlap with the capacitor line 14b.

  As shown in FIGS. 3 to 5, the TFT substrate 30 includes a first base coat film 11 a, a second base coat film 11 b, a gate insulating film 13, a first interlayer insulating film 18, and a second interlayer insulating film on the transparent substrate 10. The film 20 has a multilayer laminated structure in which the films 20 are sequentially laminated.

  As shown in FIGS. 2 to 5, a semiconductor layer 12 is provided between the second base coat film 11 b and the gate insulating film 13.

  As shown in FIGS. 2 to 5, a gate line 14 a, a gate electrode 14 c, and a capacitor line 14 b are provided between the gate insulating film 13 and the first interlayer insulating film 18.

  Between the first interlayer insulating film 18 and the second interlayer insulating film 20, as shown in FIGS. 2 to 5, a contact hole H1 formed in a laminated film of the gate insulating film 13 and the first interlayer insulating film 18 is provided. The source line 19a connected to the source region of the semiconductor layer 12 through the gate electrode and the drain region of the semiconductor layer 12 through the contact hole H2 formed in the stacked film of the gate insulating film 13 and the first interlayer insulating film 18 A drain extraction electrode 19b is provided.

  On the second interlayer insulating film 20, a pixel electrode 21 connected to the drain extraction electrode 19b through a contact hole H3 formed in the second interlayer insulating film is provided.

  As shown in FIGS. 3 to 5, the first interlayer insulating film 18 is a stacked film of a silicon oxide film 15, a silicon nitride film 16, and a silicon oxide film 17. The first interlayer insulating film 18 has a two-layer structure in the lower portion of the silicon oxide film 15 and the silicon nitride film 16 in the transmission region T, and the silicon oxide film 15 and the silicon nitride film in the wiring intersection region Y and the contact region C. 16 and a silicon oxide film 17. Here, the film thickness Ma of the silicon nitride film 16 in the wiring intersection region Y (and the contact region C) is about 250 nm to 280 nm, and the film thickness Mb of the silicon nitride film 16 in the transmission region T is about 130 nm to 160 nm. is there.

  The counter substrate 40 includes a black matrix (not shown) provided in a lattice shape, a color filter layer (not shown) including a red layer, a green layer, and a blue layer provided between the lattices of the black matrix, A common electrode (not shown) provided to cover the color filter layer.

  The liquid crystal layer 35 is made of a nematic liquid crystal material having electro-optical characteristics.

  In the liquid crystal display device 50 configured as described above, when the gate signal from the gate line 14a is sent to the gate electrode 14c of the TFT 5 and the TFT is turned on in the sub-pixel constituting each pixel which is the minimum unit of the image. A source signal from the source line 19a is sent to the TFT 5 and a predetermined charge is written into the pixel electrode 21 through the semiconductor layer 12 of the TFT 5, whereby each pixel electrode 21 of the TFT substrate 30 and the common electrode of the counter substrate 40 are written. And a predetermined voltage is applied to the liquid crystal layer 35. In the liquid crystal display device 50, the transmittance of light incident from the backlight is adjusted by utilizing the change in the alignment state of the liquid crystal layer 35 according to the magnitude of the applied voltage of the liquid crystal layer 35, thereby obtaining an image. Is displayed.

  Next, a method for manufacturing the liquid crystal display device 50 will be described with reference to FIGS. The manufacturing method of the liquid crystal display device of this embodiment includes a TFT substrate manufacturing process, a counter substrate manufacturing process, and a liquid crystal injection process. The TFT substrate manufacturing process includes a first wiring forming process, a resist forming process, and a first etching process. , A second etching step, a second wiring step, a second interlayer insulating film forming step, and a pixel electrode forming step. 6 to 8 are cross-sectional views schematically showing a resist formation process, a first etching process, and a second etching process in the manufacturing process of the TFT substrate 30.

<TFT substrate manufacturing process>
First, a silicon oxide film (thickness of about 100 nm) and a silicon nitride film (thickness of about 100 nm) are sequentially formed on the entire substrate on the transparent substrate 10 such as a glass substrate by a plasma CVD (Chemical Vapor Deposition) method. A first base coat film 11 and a second base coat film 12 are respectively formed.

Subsequently, an amorphous silicon film (thickness of about 50 nm) is formed on the entire substrate on the second base coat film 12 by plasma CVD using disilane (Si ₂ H ₆ ) as a source gas, and then heat treatment. To crystallize (transform into a polysilicon film). Then, the semiconductor layer 12 is formed by patterning by photolithography.

  Further, a gate oxide film 13a is formed by forming a silicon oxide film (about 100 nm thick) on the entire substrate on the base coat film 11b on which the semiconductor layer 12 is formed by plasma CVD.

  Then, a tantalum nitride film (thickness of about 50 nm) and a tungsten film (thickness of about 350 nm) are sequentially formed on the entire substrate on the gate insulating film 13a by sputtering, and then patterned by photolithography to form a gate. A line 14a, a gate electrode 14c, and a capacitor line 14b are formed (first wiring formation step).

  Subsequently, using the gate electrode 14a as a mask, the semiconductor layer 12 is doped with phosphorus through the gate insulating film 13a, a channel region is overlapped with the gate electrode 14a, and a source region and a drain region (auxiliary capacitance region) are formed outside thereof. After that, heat treatment is performed to activate the doped phosphorus. Note that a region overlapping the capacitor line 14b of the semiconductor layer 12 is separately doped with phosphorus before the first wiring formation step. Further, when phosphorus is doped as an impurity element as described above, an N-channel TFT is formed, and when boron is doped, a P-channel TFT is formed.

  Further, a silicon oxide film 15a (about 50 nm thick) and a silicon nitride film 16a (thickness) are formed on the entire substrate on the gate insulating film 13a on which the gate line 14a, the gate electrode 14c, and the capacitor line 14b are formed by plasma CVD. 250 nm to 280 nm) and a silicon oxide film 17a (thickness of about 700 nm) made of TEOS (tetraethylorthosilicate) are sequentially formed to form an inorganic insulating film 18a. Thereafter, as shown in FIG. 6, a photosensitive resin film 22 (having a thickness of about 2000 nm) is formed on the inorganic insulating film 18a by a spin coating method.

  Then, the photosensitive resin film 22 on the inorganic insulating film 18a is exposed through a halftone mask, and then developed and post-baked, thereby forming a first resist pattern R1 having a recess 1 as shown in FIG. Form (resist forming step). Here, the halftone mask has a transmissive part, a light-shielding part, and a semi-transmissive part, and the transmissive part, the light-shielding part, and the semi-transmissive part allow the photosensitive resin film 22 to be exposed as shown in FIG. This is a photomask for performing exposure at three exposure levels of Ef, an unexposed portion Eu, and an intermediate exposed portion Eh.

  Subsequently, the inorganic insulating film 18a and the gate insulating film 13a exposed from the first resist pattern R1 are etched to form contact holes H1 and H2, respectively, as shown in FIGS. 2 and 8 (first etching step). ).

  Further, by thinning the first resist pattern R1 used in the first etching step by ashing, the bottom 2 of the concave portion 1 of the first resist pattern R1 is removed, and as shown in FIG. The pattern R2 is formed and the inorganic insulating film 18a is exposed. Then, the silicon oxide film 17a and the upper portion of the silicon nitride film 16a of the inorganic insulating film 18a exposed from the second resist pattern R2 are etched, and the film thickness Mb of the silicon nitride film 16 in the transmission region T is changed in the wiring intersection region Y. By making it thinner than the film thickness Ma of the silicon nitride film 16 and setting it to 130 nm or more and 160 nm or less, a first interlayer insulating film 18 is formed as shown in FIGS. Process).

  Subsequently, a titanium film (thickness of about 100 nm), an aluminum film (thickness of about 500 nm), and a titanium film (thickness of about 100 nm) are sequentially formed on the entire substrate on the first interlayer insulating film 18 by sputtering. Thereafter, patterning is performed by photolithography to form the source line 19a and the drain lead electrode 19b, respectively (second wiring formation step). Then, heat treatment is performed to hydrogenate the semiconductor layer 12 to terminate the dangling bonds (unbonded hands).

  Further, a resin film (thickness: about 2000 nm) such as an acrylic resin is formed on the entire substrate on the first interlayer insulating film 18 on which the source line 19a and the drain extraction electrode 19b are formed by spin coating. Thereafter, the portion of the formed resin film corresponding to the drain extraction electrode 19b is etched to form a second interlayer insulating film 20 having a contact hole H3 as shown in FIGS. Interlayer insulating film forming step).

  Next, after an ITO (Indium Tin Oxide) film (thickness of about 100 nm) is formed on the entire substrate on the second interlayer insulating film 20 by a sputtering method, as shown in FIGS. The pixel electrode 21 is formed by patterning (pixel electrode forming step).

  Finally, a polyimide resin is applied to the entire substrate on which the pixel electrode 21 is formed by a printing method, and then an alignment film is formed by performing a rubbing process.

  The TFT substrate 30 can be manufactured as described above.

<Opposite substrate manufacturing process>
First, for example, a chromium thin film is formed on the entire transparent substrate such as a glass substrate by sputtering, and then patterned by photolithography to form a black matrix.

  Subsequently, for example, a photosensitive resist material colored in red, green, or blue is applied to each of the lattices of the black matrix, and then patterned by photolithography to form a colored layer of a selected color (for example, Red layer). Thereafter, the same process is repeated for the other two colors to form other colored layers (for example, a green layer and a blue layer), thereby forming a color filter layer.

  Further, on the substrate on which the color filter layer is formed, for example, an ITO film is formed by sputtering to form a common electrode.

  Finally, a polyimide resin is applied to the entire substrate on which the common electrode is formed by a printing method, and then an alignment film is formed by performing a rubbing process.

  The counter substrate 40 can be manufactured as described above.

<Liquid crystal injection process>
First, for example, a sealing material 36 made of a thermosetting resin is formed in a frame shape having a liquid crystal injection port on the counter substrate 40 manufactured in the above counter substrate manufacturing process by a printing method, and the inner side of the sealing material 36 is formed. After spraying the fine particle spacers, the counter substrate 40 and the TFT substrate 30 manufactured in the TFT substrate manufacturing process are bonded together.

  Subsequently, the sealing material 36 is cured by heating the bonded TFT substrate 30 and counter substrate 40.

  Further, after injecting a liquid crystal material between the TFT substrate 30 and the counter substrate 40 by a vacuum injection method, the liquid crystal injection port is sealed with a UV curable resin or the like to form the liquid crystal layer 35.

  The liquid crystal display device 50 can be manufactured as described above.

  As described above, according to the TFT substrate 30 of the present embodiment, the liquid crystal display device 50 including the TFT substrate 30, and the manufacturing method thereof, each capacitor line formed in the first wiring formation step in the first etching step. In order to form a contact hole H1 for connecting to the source region of the semiconductor layer 12 provided on the transparent substrate 10 side of 14b, through the first resist pattern R1 having the recess 1 formed in the resist formation step, A part of the inorganic insulating film 18a is etched. In the second etching step, first, the first resist pattern R1 used in the first etching step is thinned by ashing, and the bottom 2 of the concave portion 1 of the first resist pattern R1 is removed, so that the transmission region T and The inorganic insulating film 18a in the region to be formed is exposed. Further, the thinned resist pattern, that is, the upper portion of the inorganic insulating film 18 exposed from the second resist pattern R2 is etched to form the silicon nitride film 16a thinner than the wiring intersection region Y in the transmission region T. The first interlayer insulating film 18 is formed by setting the film thickness Mb to 130 nm or more and 160 nm or less. Thereafter, the TFT substrate 30 can be manufactured by performing a second wiring formation step, a second interlayer insulating film formation step, and a pixel electrode formation step. Here, in the manufactured TFT substrate 30, the relatively high refractive index silicon nitride film 16 constituting the first interlayer insulating film 18 between each capacitor line 14 b and each source line 19 a is adjacent to each capacitor line. In the transmission region T surrounded by 14b and adjacent source lines 19a, each gate line 14a, each capacitor line 14b and each source line 19a are formed thinner than the wiring intersection region Y, and the film thickness Mb is 130 nm. Since the second interlayer insulating film 20 between each source line 19a and each pixel electrode 21 has the same film thickness in the transmissive region T and the wiring intersection region Y, the light in the transmissive region T can be obtained. The transmittance can be improved. Further, since the silicon nitride film 16 is formed relatively thick in the wiring intersection region Y, the first interlayer insulating film 18 becomes thick, and between the gate lines 14a and the capacitor lines 14b and the source lines 19a. The electric capacity formed in the first interlayer insulating film 18 becomes small. Therefore, in the TFT substrate 30 and the liquid crystal display device 50 including the TFT substrate 30, it is possible to reliably achieve both improvement in light transmittance in the transmission region and reduction in capacitance in the wiring intersection region.

  Here, since the light transmittance in the transmission region T periodically changes with respect to the thickness of the silicon nitride film 16, the thickness of the silicon nitride film 16 in the transmission region T is smaller than 130 nm or from 160 nm. If it is too large, the light transmittance in the transmission region T is lowered. Furthermore, when the thickness of the silicon nitride film 16 in the transmission region T is smaller than 130 nm, there is a possibility that hydrogenation of dangling bonds in the semiconductor layer 12 constituting the TFT 5 may be incomplete.

  In the above-described embodiment, the gate line 1 is disposed across the middle portion of the pixel electrode 21, and the transmissive region T is defined as a region surrounded by the adjacent capacitor lines 14b and the adjacent source lines 19a. Although the configuration of 30 is illustrated, the present invention relates to a TFT substrate in which a capacitor line is disposed across the middle portion of the pixel electrode, and a transmission region is defined in a region surrounded by adjacent gate lines and adjacent source lines. It can also be applied to.

  As described above, according to the present invention, in the liquid crystal display device in which the interlayer insulating film including the silicon nitride film is formed, the improvement of the light transmittance of the transmission region and the reduction of the capacitance of the wiring intersection region can be reliably achieved. Therefore, it is useful for a liquid crystal display device having a high aperture ratio.

It is sectional drawing of the liquid crystal display device 50 which concerns on embodiment of this invention. 4 is a plan view of a TFT substrate 30 that constitutes the liquid crystal display device 50. FIG. FIG. 3 is a cross-sectional view of the TFT substrate 30 taken along line III-III in FIG. 2. It is sectional drawing of the TFT substrate 30 along the IV-IV line in FIG. FIG. 5 is a cross-sectional view of the TFT substrate 30 taken along line VV in FIG. 2. 5 is a first cross-sectional view showing a part of the manufacturing process of the TFT substrate 30. FIG. 6 is a second cross-sectional view showing a part of the manufacturing process of the TFT substrate 30. FIG. 7 is a third cross-sectional view showing a part of the manufacturing process of the TFT substrate 30. FIG. It is a top view of the TFT substrate 130 of the conventional high aperture ratio structure. FIG. 10 is a cross-sectional view of the TFT substrate 130 taken along line XX in FIG. 9.

Explanation of symbols

P concave portion R1 first resist pattern R2 second resist pattern T transmission region Y wiring intersection region 14b capacitance line (first wiring)
16 Silicon nitride film 18 First interlayer insulating film 18a Inorganic insulating film 19a Source line (second wiring)
20 Second interlayer insulating film 21 Pixel electrode 22 Photosensitive resin film 30 TFT substrate (thin film transistor substrate)
35 Liquid crystal layer 40 Counter substrate 50 Liquid crystal display device

Claims (5)

A plurality of first wirings provided to extend in parallel to each other;
A plurality of second wires provided so as to cross the first wires and extend in parallel with each other;
A first interlayer insulating film including a silicon nitride film provided between each first wiring and each second wiring;
A second interlayer insulating film provided on the opposite side of the second interlayer wiring to the first interlayer insulating film;
A plurality of pixel electrodes provided in a matrix on the opposite side of the second wiring of the second interlayer insulating film,
A transmission region surrounded by the adjacent first wirings and the adjacent second wirings;
A thin film transistor substrate in which a wiring intersection region where each of the first wiring and the second wiring intersect is defined,
The thin film transistor substrate, wherein a thickness of the silicon nitride film in the transmission region is 130 nm or more and 160 nm or less, which is smaller than a thickness of the silicon nitride film in the wiring intersection region. The thin film transistor substrate according to claim 1,
A thin film transistor substrate, wherein each pixel electrode has a peripheral edge overlapping each of the first wiring and the second wiring. The thin film transistor substrate according to claim 1,
Each of the first wirings is a capacitor line, and each of the second wirings is a source line. A plurality of first wirings provided to extend in parallel to each other;
A plurality of second wires provided so as to cross the first wires and extend in parallel with each other;
A first interlayer insulating film provided between each first wiring and each second wiring;
A second interlayer insulating film provided on the opposite side of the second interlayer wiring to the first interlayer insulating film;
A plurality of pixel electrodes provided in a matrix on the opposite side of the second wiring of the second interlayer insulating film,
A transmission region surrounded by the adjacent first wirings and the adjacent second wirings;
A method of manufacturing a thin film transistor substrate in which a wiring intersection region where each first wiring and each second wiring intersect is defined,
A first wiring forming step of forming each of the first wirings on a transparent substrate;
An inorganic insulating film including a silicon nitride film and a photosensitive resin film are sequentially formed so as to cover each of the first wirings, and then the photosensitive resin film is exposed with a halftone, thereby forming a region that becomes the transmission region. A resist forming step of forming a resist pattern in which a recess is provided;
A first etching step of etching the inorganic insulating film exposed from the resist pattern;
The resist pattern is thinned by ashing to remove the bottom of the concave portion of the resist pattern, and then a part of the inorganic insulating film exposed from the thinned resist pattern is etched to form a silicon nitride film in the transmission region. A second etching step of forming the first interlayer insulating film by making the film thickness thinner than the film thickness of the silicon nitride film in the wiring crossing region and by making the film thickness 130 nm or more and 160 nm or less;
A second wiring forming step of forming each of the second wirings in the first interlayer insulating film after removing the thinned resist pattern;
A second interlayer insulating film forming step of forming the second interlayer insulating film so as to cover each of the second wirings;
And a pixel electrode forming step of forming each pixel electrode on the second interlayer insulating film. A thin film transistor substrate and a counter substrate disposed to face each other;
A liquid crystal display device comprising a liquid crystal layer provided between the thin film transistor substrate and the counter substrate,
The thin film transistor substrate is
A plurality of first wirings provided to extend in parallel to each other;
A plurality of second wires provided so as to cross the first wires and extend in parallel with each other;
A first interlayer insulating film including a silicon nitride film provided between each first wiring and each second wiring;
A second interlayer insulating film provided on the opposite side of the second interlayer wiring to the first interlayer insulating film;
A plurality of pixel electrodes provided in a matrix on the opposite side of the second wiring of the second interlayer insulating film,
A transmission region surrounded by the adjacent first wirings and the adjacent second wirings;
A wiring intersection region where the first wiring and the second wiring intersect is defined,
The liquid crystal display device, wherein a thickness of the silicon nitride film in the transmission region is 130 nm or more and 160 nm or less, which is smaller than a thickness of the silicon nitride film in the wiring intersection region.

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