JP2009094734A - Cut-off frequency automatic adjusting circuit and personal digital assistant - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To automatically adjust a filter cut-off frequency with a large capacitance ratio, and to shorten the time required for automatic adjustment. <P>SOLUTION: A register for correcting error and a filter cut-off frequency automatic adjusting circuit are provided for each feedback capacitance and non-feedback capacitance (ground capacitance) of a channel filter circuit. Thus, the filter cut-off frequency can be adjusted without enlarging the error caused by a capacitance difference between the feedback capacitance and non-feedback capacitance. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a filter cutoff frequency automatic adjustment circuit, and relates to a filter cutoff frequency automatic adjustment circuit having a large ratio of capacitance values to be used.

  Conventionally, a radio signal processing circuit has been configured using individual components for each functional block (an amplifier that amplifies a signal, a mixer that converts a signal frequency, a filter that passes only a desired band of a signal, and the like). Recent improvements in semiconductor technology have made it possible to incorporate a plurality of functional blocks constituting these wireless signal processing circuits into one semiconductor chip. A radio signal processing circuit built into one or several semiconductor chips converts a high-frequency signal received from an antenna into a signal of a lower frequency band with high quality (low noise, by suppressing signals other than the desired band, etc.) To do.

  In order to realize a wireless signal processing circuit at a low cost, it is desired to incorporate functional blocks constituting a larger number of wireless signal processing circuits in one semiconductor chip. One of the obstacles to this purpose is the incorporation of a filter circuit that suppresses signals in a band other than the desired band into a semiconductor chip. This filter circuit uses a SAW (Surface Acoustic Wave) filter, a dielectric filter, and the like, and suppresses signals present in bands other than the desired band. However, the SAW filter and the dielectric filter cannot be built in the semiconductor chip because of their configurations.

  In general, a radio signal processing circuit with individual components has a configuration called a superheterodyne system and requires a SAW filter or the like. Therefore, when a radio signal processing circuit manufactured by a semiconductor is configured by a superheterodyne system, a SAW filter or a dielectric filter is externally attached outside the semiconductor chip. As a result, the number of parts and the mounting area are increased.

  On the other hand, wireless signal processing circuit methods such as a zero IF method and a low IF method that do not require a SAW filter or a dielectric filter have been proposed. In either case, the absolute values of the component constants between the semiconductor chips vary, but the relative value of the component constants in one semiconductor chip matches with high accuracy, and the SAW filter or dielectric filter is used. It is not necessary, and a signal existing in a band other than a desired band is suppressed by a filter that can be incorporated in a semiconductor.

  In the zero IF method and the low IF method, a filter that removes signals other than a desired channel is arranged on a stage that handles a signal in a low frequency band after frequency conversion by a mixer circuit. Hereinafter, this is called a channel filter.

  The channel filter suppresses signals existing in the adjacent channel and the adjacent channel of the desired channel. However, the received signal quality deteriorates when the cutoff frequency, which is a frequency having a direct gain of minus 3 dB of the channel filter, is shifted due to semiconductor manufacturing variations, element temperature, voltage characteristics, and the like.

  For example, when the cut-off frequency is shifted to the higher side, the degree of suppression of signals existing in the adjacent channel and the adjacent channel is deteriorated. Also, if the cut-off frequency is shifted to the lower side, the signal power of the desired channel is lowered, so that the signal-to-noise ratio is deteriorated and the reception sensitivity is lowered. Also, when receiving a digitally modulated signal, the inter-symbol interference characteristic is degraded, which affects the received data error rate.

  In the invention described in Japanese Patent Application Laid-Open No. 2007-184856 (hereinafter referred to as Patent Document 1), as a correction means for such a filter, a reference signal is generated, the reference signal is supplied to and measured by the receiving unit, and the filter is based on the result. Techniques for making adjustments are described.

A method of using a digital PLL (phase lock loop) circuit for filter adjustment and maintaining the reliability of the filter adjustment signal is also conceivable.
JP 2007-184856 A

  However, in the above document, the condition is that the operation itself is normal as long as it outputs the reference signal, receives it, and adjusts the filter. However, in the first place, it is impossible to compensate for the correct operation of the circuit in the device to be adjusted when the error adjustment is performed at the time of manufacture.

  In addition, if a digital PLL is used, the filter adjustment frequency is certainly maintained at an appropriate value, but the PLL takes time to stabilize.

  An object of the present invention is to automatically adjust a filter cutoff frequency having a large capacity ratio to be used, and to shorten the time required for the automatic adjustment.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A cut-off frequency automatic adjustment circuit according to a representative embodiment of the present invention includes a reference voltage source, a voltage-current conversion circuit, a charging circuit, a discharging circuit, a digital capacitor having a plurality of capacitors, and a capacitance control circuit for controlling the digital capacitance. A voltage-current conversion circuit, a charging circuit, a discharging circuit, and a digital capacitor constitute a first automatic adjustment circuit, the digital capacitor is connected to the charging circuit and the discharging circuit by a switch, and the switch and the capacity control circuit have a clock signal The digital capacitor is connected to the charging circuit or discharging circuit by switching the switch according to the input and the potential of the clock signal, and the digital capacitor is connected to all or a part of the plurality of capacitors in parallel by switching. Based on the result of comparison between the difference in potential between the reference voltage source and the voltage of the reference voltage source, the capacitance control circuit circuit is And controlling the barrel capacity.

  The automatic cut-off frequency adjusting circuit further includes a comparator for comparing the voltage input to the digital capacitor and the voltage of the reference voltage source, and a latch to which the clock signal is input, and latches at a predetermined timing of the clock signal. The output of the comparator may be latched and output to the capacitance control circuit.

  The capacitance control circuit of the cut-off frequency automatic adjustment circuit may be a binary search circuit.

  The capacitance control circuit of the cut-off frequency automatic adjustment circuit controls the digital capacitance in order to make the difference between the potential of the digital capacitance and the potential of the reference voltage source within a predetermined potential difference. Also good.

  The cut-off frequency automatic adjustment circuit may further include a second automatic adjustment circuit including a voltage-current conversion circuit, a charging circuit, a discharging circuit, and a digital capacitor.

  The automatic cut-off frequency adjusting circuit further includes a channel filter circuit. The channel filter circuit includes a feedback capacitor that is a digital capacitor that feeds back and a ground capacitor that is a digital capacitor that is grounded. The feedback capacitor may be set under the control condition of the digital capacity of the automatic adjustment circuit, and the ground capacity may be set under the control condition of the digital capacity of the second automatic adjustment circuit.

  In the automatic cutoff frequency adjusting circuit, the channel filter circuit may be a Butterworth low-pass filter.

  The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, the filter cutoff frequency automatic adjustment circuit according to the representative embodiment of the present invention can automatically and quickly adjust the cutoff frequency of a filter having a large capacity ratio to be used.

  The cut-off frequency automatic adjustment circuit according to the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram of a filter cutoff frequency automatic adjustment circuit according to the first embodiment. This filter cut-off frequency automatic adjustment circuit includes a reference voltage 10, a resistor 20, a voltage-current conversion circuit 30, a discharge circuit 40, a charging circuit 50, a switch 61, a digital capacitor 70, a comparator 80, a latch 90, a clock signal 100, and a reset. The signal 110 includes a binary search circuit 120, a channel filter circuit 150, a feedback digital capacitor 151, a non-feedback digital capacitor 152, and a calibration completion signal 160.

The reference voltage 10 is a DC voltage VBG output from a reference voltage source that does not depend on temperature or power supply voltage. VBG is generated by the voltage-current conversion circuit 30 and the resistor 20 having a resistance value R1,
I = VBG / R1
Convert to DC current.

  The direct current I output from the voltage / current conversion circuit 30 is input to the charging circuit 50.

  The clock signal 100 is a reference operation clock for the latch 90 and the binary search circuit 120. The reset signal 110 is a signal for resetting the contents stored in the latch 90 and the binary search circuit 120. In the present specification, the clock signal 100 is a rectangular wave having a constant frequency Fclk and a duty ratio of 50%.

  In the description of the present specification, when the state becomes High, the reset state is entered, and when the state becomes Low, the internal storage of the latch 90 or the like becomes possible. When the clock signal 100 becomes High after the reset signal 110 becomes Low, the latch 90 and the binary search circuit 120 start to operate, and the filter cutoff frequency automatic adjustment circuit starts to operate.

  The switch 61 is a switch that is switched according to the switch polarity diagram 60. That is, whether the digital capacitor 70 is connected to the discharging circuit 40 or the charging circuit 50 is determined according to High or Low of the clock signal 100.

  The digital capacitor 70 is a set of a plurality of capacitors having different capacities mounted on a semiconductor chip, and these capacitors are connected in parallel and controlled by switching. FIG. 3 is a schematic diagram of the digital capacitor 70.

  The description of the present invention is based on the assumption that a 5-bit digital capacity is used, but this is not necessarily the case. The digital capacity assumed by the present invention can be varied in the range of -32% to + 30%.

  The digital capacitor 70 includes CDcom 331, # 0 capacitor 340, # 1 capacitor 341, # 2 capacitor 342, # 3 capacitor 343, # 4 capacitor 344, # 0 switch 350, # 1 switch 351, # 2 switch 352, # 3 switch. The main components are 353 and # 4 switch 354. Also included are an input terminal 300, an output terminal 310, and a digital value input terminal 320.

  The # 0 switch 350, # 1 switch 351, # 2 switch 352, # 3 switch 353, and # 4 switch 354 are turned on / off according to the 5-bit digital value input from the digital value input terminal 320. That is, when all the switches in the digital capacitor 70 are turned off, the capacity of the CDcom 331 becomes the capacity of the digital capacitor 70. Therefore, the capacity of the CDCom 331 is 68% of the capacity assumed by the digital capacitor 70. Note that “c” in FIG. 3 is the size of the capacity realized by the digital capacity.

  In order to vary the range from −32% to + 30% with 5 bits, the increment is 2%. Accordingly, the capacity of the # 0 capacitor 340 is 32% of the assumed capacity of the digital capacitor 70, the capacity of the # 1 capacitor 341 is 16% of the assumed capacity of the digital capacitor 70, and the capacity of the # 2 capacitor 342 is the assumed capacity of the digital capacitor 70. 8%, the capacity of the # 3 capacitor 343 is 4% of the assumed capacity of the digital capacity 70, and the capacity of the # 4 capacitor 344 is 2% of the assumed capacity of the digital capacity 70. The 5-bit digital value input from the digital value input terminal 320 corresponds to ON / OFF of the # 0 switch 350, # 1 switch 351, # 2 switch 352, # 3 switch 353, and # 4 switch 354, respectively. Yes. The binary search circuit 120 adjusts the digital capacitor 70 by outputting data to the digital value input terminal 320.

  The discharge circuit 40 is a circuit for removing charges accumulated in each capacitor of the digital capacitor 70.

The charging circuit 50 is a circuit for charging each capacitor of the digital capacitor 70. When the digital capacitor 70 and the charging circuit 50 are connected by the switch 61, the direct current I = VBS / R1 that is the output of the voltage-current conversion circuit 30 is supplied from the charging circuit 50. The digital capacitor 70 has a voltage proportional to a time Δt from when the switch 61 is switched and input is started,
V = VBG / R1 / C1 × Δt
Appears between the input terminal 300 and the output terminal 310. Here, C1 is the inter-terminal capacitance of the digital capacitor 70 at the present time.

  The comparator 80 compares the voltage between the reference voltage 10 and the input voltage to the digital capacitor 70. The current flowing through the digital capacitor 70 (VBG / R1 / C1 × Δt) is compared with the current of the reference voltage 10 (VBG / R1).

  In this form, if the current flowing through the digital capacitor 70 is larger than the current of the reference voltage 10, the output of the comparator 80 is High. If the current flowing through the digital capacitor 70 is smaller than the current of the reference voltage 10, the output of the comparator 80 is low. If this is performed five times for the 5-bit digital capacitor which is the condition of the present embodiment, the # 0 switch 350, # 1 switch 351, # 2 switch 352, # 3 switch 353, # 4 switch of the digital capacitor 70 are performed. The digital value to be given to 354 is determined.

  A binary search circuit (capacitance control circuit) 120 controls each switch in the digital capacitor 70 described above. Here, the binary search circuit 120 will be described as a capacity control circuit, but the present invention is not limited to this as long as each switch in the digital capacity 70 can be controlled.

  Hereinafter, the operation of the binary search circuit 120 will be described in detail with reference to FIG. In this figure, P 1 to P 6 are the period names of the clock signal 100. The clock constitutes one cycle from High to Low.

First, at the rising edge of the cycle P1 of the clock signal 100, each switch of the digital capacitor 70 is
# 4 switch = High
# 3 switch = Low
# 2 switch = Low
# 1 switch = Low
# 0 switch = Low
The binary search circuit 120 provides the digital value of.

  During the High level of the clock signal 100 with the period P1, the switch 61 is connected to the discharge circuit 40 according to the polarity of the switch polarity diagram 60. Therefore, the voltage between the terminals of the digital capacitor 70 is 0V.

Since the switch 61 is connected to the charging circuit 50 according to the polarity of the switch polarity diagram 60 during the low level of the clock signal 100 of the period P1, the digital capacitor 70 has the direct current VBG / R1 is supplied. At the rising edge of the cycle P2 of the clock signal 100, the voltage between the terminals of the digital capacitor 70 is proportional to the time Δt from the falling edge of the cycle P1 to the rising edge of the cycle P2,
V = VBG / R1 / C1 × Δt
Appears. C1 is a capacitance value of the digital capacitor 70, and here is (0.68 + 0.02) C which is the capacitance of the CDCom 331 and the # 4 capacitor 344, that is, a capacity of 70% assumed by the digital capacitor 70.

  If this voltage is larger than VBG, the output of the comparator 80 becomes low level at the rising edge of the cycle P2 of the clock signal 100. The output level of the comparator 80 is latched by the latch 90 at the rising edge of the cycle P2 of the clock signal 100, and at the same time, stored as a digital signal value that the binary search circuit 120 supplies to the # 4 switch 354.

Next, at the rising edge of the clock signal 100 of the period P2, each switch of the digital capacitor 70 is
# 4 switch = output level of the comparator 80 at the rising edge of the clock signal 100 with the period P2.
# 3 switch = High
# 2 switch = Low
# 1 switch = Low
# 0 switch = Low
The binary search circuit 120 provides the digital value of.

  During the High level of the clock signal 100 with the period P2, the switch 61 is connected to the discharge circuit 40 according to the polarity of the switch polarity diagram 60. As a result, the voltage between the terminals of the digital capacitor 70 becomes 0V.

Since the switch 61 is connected to the charging circuit 50 according to the polarity of the switch polarity diagram 60 during the low level of the clock signal 100 having the period P2, the digital capacitor 70 has the direct current VBG / R1 is supplied. When the clock signal 100 having the period P3 falls, the voltage between the terminals of the digital capacitor 70 is proportional to the time Δt from the fall of the period P2 to the rise of the period P3.
V = VBG / R1 / C1 × Δt
Appears. Here, C1 is the capacity of the CDCom 331 and # 3 capacitor 343 (0.68 + 0.04) C, that is, 72% of the capacity assumed by the digital capacitor 70 (when the # 4 switch 354 is OFF) or CDCom 331 and # 3 The capacity is 74% (when the # 4 switch 354 is on), which is the total capacity of the capacitor 343 and the # 4 capacitor 344.

  As in the period P1, if this voltage is greater than VBG, the output of the comparator 80 is at the high level at the rising edge of the period P3 of the clock signal 100, and if it is smaller, the output is at the low level at the same time. The output level of the comparator 80 is latched in the latch 90 at the rising edge of the cycle P3 of the clock signal 100, and is simultaneously stored as a digital signal value to be supplied to the # 3 switch 353 of the binary search circuit 120.

Next, at the rising edge of the clock signal 100 of the period P3,
# 4 switch = output level of the comparator 80 at the rising edge of the clock signal 100 with the period P2.
# 3 switch = output level of the comparator 80 at the rising edge of the clock signal 100 with the period P3
# 2 switch = High
# 1 switch = Low
# 0 switch = Low
The binary search circuit 120 provides the digital value of.

  Similarly to the periods P1 and P2, the switch 61 is connected to the discharge circuit 40 according to the polarity of the switch polarity diagram 60 during the high level of the clock signal 100 of the period P3. As a result, the voltage between the terminals of the digital capacitor 70 becomes 0V.

Even during the low level of the clock signal 100 of the period P3, the switch 61 is connected to the charging circuit 50 according to the polarity of the switch polarity diagram 60. Therefore, the digital capacitor 70 has the direct current VBG that is the output of the voltage-current conversion circuit 30. / R1 is supplied. When the clock signal 100 having the period P3 falls, the voltage between the terminals of the digital capacitor 70 is proportional to the time Δt from the fall of the period P3 to the rise of the period P4.
V = VBG / R1 / C1 × Δt
Appears. Similarly to the periods P1 and P2, C1 is a total value of the capacities of the capacitors corresponding to the switches that are turned on.

  If this voltage is higher than VBG, the output of the comparator 80 becomes High level at the rising edge of the period P3 of the clock signal 100, and if it is lower, it becomes Low level at the same time. The output level of the comparator 80 is latched in the latch 90 at the rising edge of the cycle P4 of the clock signal 100 and is simultaneously stored as a digital signal value to be supplied to the # 2 switch 352 of the binary search circuit 120.

Next, at the rising edge of the clock signal 100 with the period P4,
# 4 switch = output level of the comparator 80 at the rising edge of the clock signal 100 with the period P2.
# 3 switch = output level of the comparator 80 at the rising edge of the clock signal 100 with the period P3
# 2 switch = output level of the comparator 80 at the rising edge of the clock signal 100 with the period P4
# 1 switch = High
# 0 switch = Low
The binary search circuit 120 provides the digital value of.

  As before, the switch 61 is connected to the discharge circuit 40 according to the polarity of the switch polarity diagram 60 during the high level of the clock signal 100 of the period P4. As a result, the voltage between the terminals of the digital capacitor 70 becomes 0V.

Even during the low level of the clock signal 100 of the period P4, the switch 61 is connected to the charging circuit 50 according to the polarity of the switch polarity diagram 60, so that the digital capacitor 70 has the direct current VBG that is the output of the voltage-current conversion circuit 30. / R1 is supplied. At the fall of the clock signal 100 with the period P4, the voltage between the terminals of the digital capacitor 70 is proportional to the time Δt from the fall of the period P4 to the rise of the period P5.
V = VBG / R1 / C1 × Δt
Appears. As before, C1 is the sum of the capacities of the capacitors corresponding to the switches that are turned on.

  If this voltage is higher than VBG, the output of the comparator 80 becomes High level at the rising edge of the period P5 of the clock signal 100, and if it is lower, it becomes Low level at the same time. The output level of the comparator 80 is latched by the latch 90 at the rising edge of the cycle P5 of the clock signal 100, and simultaneously stored as a digital signal value to be supplied to the # 1 switch 351 of the binary search circuit 120.

Next, at the rising edge of the clock signal 100 with the period P5,
# 4 switch = output level of the comparator 80 at the rising edge of the clock signal 100 with the period P2.
# 3 switch = output level of the comparator 80 at the rising edge of the clock signal 100 with the period P3
# 2 switch = output level of the comparator 80 at the rising edge of the clock signal 100 with the period P4
# 1 switch = output level of the comparator 80 at the rising edge of the clock signal 100 with the period P5
# 0 switch = High
The binary search circuit 120 provides the digital value of.

  During the high level of the clock signal 100 with the period P5, the switch 61 is connected to the discharge circuit 40 according to the polarity of the switch polarity diagram 60. As a result, the voltage between the terminals of the digital capacitor 70 becomes 0V.

During the low level of the clock signal 100 with the period P5, the switch 61 is connected to the charging circuit 50 according to the polarity of the switch polarity diagram 60. Therefore, the direct current VBG / R1 that is the output of the voltage-current conversion circuit 30 is supplied to the digital capacitor 70. When the clock signal 100 having the period P5 falls, the voltage between the terminals of the digital capacitor 70 is proportional to the time Δt from the fall of the period P5 to the rise of the period P6.
V = VBG / R1 / C1 × Δt
Appears. As before, C1 is the sum of the capacities of the capacitors corresponding to the switches that are turned on.

  If this voltage is higher than VBG, the output of the comparator 80 becomes High level at the rising edge of the period P6 of the clock signal 100, and if it is lower, it becomes Low level at the same time. The output level of the comparator 80 is latched in the latch 90 at the rising edge of the cycle P6 of the clock signal 100, and at the same time stored as a digital signal value to be supplied to the # 0 switch 350 of the binary search circuit 120.

Now, the digital value given to each switch is
# 4 switch = output level of the comparator 80 at the rising edge of the clock signal 100 with the period P2.
# 3 switch = output level of the comparator 80 at the rising edge of the clock signal 100 with the period P3
# 2 switch = output level of the comparator 80 at the rising edge of the clock signal 100 with the period P4
# 1 switch = output level of the comparator 80 at the rising edge of the clock signal 100 with the period P5
# 0 switch = determined to the value of the output level of the comparator 80 at the rising edge of the clock signal 100 of the period P6. This is obtained by correcting the manufacturing variation of the resistance value R1 of the resistor 20 and the capacitance value C1 between the terminals of the digital capacitor 70, and the product of R1 × C1 becomes constant if the above-described digital value is given to each switch.

  After the rising edge of the cycle P6 of the clock signal 100, the digital value is given to the channel filter circuit 150 at the rising edge of the calibration completion signal 160.

  The channel filter circuit 150 is a filter circuit that extracts only radio waves in a necessary frequency band. FIG. 5 shows an example of the channel filter circuit 150. Also in this figure, the same reference numerals as those in FIG.

  This channel filter circuit includes feedback capacitors C11, C21, C31, C41, non-feedback capacitors (grounded capacitors) C12, C22, C32, C42, resistors R11, R12, R21, R22, R31, R32, R41, R42, and an amplifier AMP1. , AMP2, AMP3, and AMP4 are the main components. Further, it has an input terminal 200 and an output terminal 210.

  This channel filter circuit is a positive feedback type low-pass circuit and constitutes an eighth-order Butterworth low-pass filter. The signal input from the input terminal 200 is output from the output terminal 210 after the signals in the frequency band higher than the desired cutoff frequency are suppressed by the low-pass circuits.

  The feedback capacitors C11, C21, C31, and C41 and the non-feedback capacitors C12, C22, C32, and C42 in FIG. 5 are digital capacitors 151 and 152, respectively, and change the size of the capacitor according to a given digital value. Can do.

  Since the binary search circuit 120 determines a digital value for correcting the product of R1 × C1 to be constant, if the same digital value is given, the cutoff frequency is corrected to be constant.

  The calibration completion signal 160 is a signal that rises at an arbitrary time before the input signal is input to the input terminal 200 in FIG. 3 from the rise of the clock signal 100 in the period P6. The digital value given to the # 0 switch to # 4 switch of the digital capacitor 70 to the feedback capacitors [C11, C21, C31, C41] of the channel filter circuit 150 at the rising edge of the calibration completion signal 160 is not fed back to the channel filter circuit 150. The digital value given to the # 0 switch to the # 4 switch of the digital capacitor 70 is given to the capacitors [C12, C22, C32, C42].

  FIG. 6 shows circuit constants for operating the cutoff frequency of 2 MHz for the Butterworth low-pass filter of the channel filter circuit 150.

  With this configuration of the channel filter circuit, the setting of the clock signal can be determined by the number of capacitors plus one clock, and the stable operation of the channel filter circuit can be achieved more quickly than when a PLL circuit or the like is used. .

  This filter cutoff frequency automatic generation circuit has several problems.

  The first is that an error in the cut-off frequency due to an error in the gain of each amplifier in the channel filter circuit 150 cannot be corrected by this filter cut-off frequency automatic generation circuit.

  Second, there is a large capacitance difference between the capacitor capacities used in the Butterworth low-pass filter of the channel filter circuit 150.

  There is a spread of about 26 times from 1.552 pF of C42 having the smallest capacitance value to 40.790 pF of C41 having the largest capacitance value. Therefore, when the center value C of the large difference in the capacitance of the digital capacitor 70 is set to a value close to C42, the error on the C41 side increases and the error of the cut-off frequency increases. Conversely, when the value is close to C41, the error on the C42 side becomes large, and the error of the cut-off frequency also becomes large.

(Second Embodiment)
FIG. 2 is a block diagram of a filter cutoff frequency automatic adjustment circuit according to the second embodiment of the present invention. This filter cut-off frequency automatic adjustment circuit includes a reference voltage 10, resistors 20, 21, voltage-current conversion circuits 30, 31, discharge circuits 40, 41, charging circuits 50, 51, switches 61, 62, digital capacitors 70, 71, Comparators 80 and 81, latches 90 and 91, clock signal 100, reset signal 110, binary search circuit 120, offset register values 130 and 131, adder circuits 140 and 141, channel filter circuit 150, and calibration completion signal 160 The That is, in contrast to the filter cutoff frequency automatic adjustment circuit of the first embodiment shown in FIG. 1, in this embodiment, the frequency automatic adjustment circuit from the voltage / current conversion circuits 30 and 31 to the latches 90 and 91 is used. It is characterized in that the main part has two systems. The configuration of these frequency automatic adjustment circuits is almost the same as that of the first embodiment (except for the parameters of each component). Therefore, description of each part is abbreviate | omitted and it demonstrates below centering on operation | movement of the circuit of an additional part.

  As in the first embodiment, the reference voltage 10 is a DC voltage VBG that does not depend on temperature or power supply voltage. It is converted into a direct current by the voltage-current conversion circuits 30 and 31 as follows.

I1 = VBG / R1
I2 = VBG / R2
First, the reset signal 110 becomes High, the latches 90 and 91 and the binary search circuit 120 are reset, and the internal memory is erased by setting the potential of the latch or the like to Low.

  Next, when the reset signal 110 becomes Low and then the clock signal 100 becomes High, the automatic adjustment circuit starts to operate. As in the first embodiment, it is assumed that the clock signal 100 is a rectangular wave having a constant frequency fclk and a duty ratio of 50%.

  Since the clock signal 100 is high, the switches 61 and 62 are switched according to the polarity of the switch polarity diagram 60, the digital capacitor 70 is discharged by the discharge circuit 40, and the digital capacitor 71 is discharged by the discharge circuit 41. The voltage between the terminals of the capacitor 71 is 0V. Along with this, the outputs of the comparators 80 and 81 also become Low.

  When the clock signal 100 becomes Low, the digital capacitors 70 and 71 are connected to the charging circuits 50 and 51 by the switches 61 and 62. As a result, the direct current I1 = VBG / R1 output from the voltage / current conversion circuit 30 flows through the digital capacitor 70, and the direct current I2 = VBG / R2 output from the voltage / current conversion circuit 31 flows through the digital capacitor 71.

The digital capacitor 70 and the digital capacitor 71 have a voltage proportional to the time Δt from when the clock signal 100 becomes low,
V1 = VBG / R1 / C1 × Δt
V2 = VBG / R2 / C2 × Δt
Appears. Here, V1 is a voltage between terminals of the digital capacitor 70, and V2 is a voltage between terminals of the digital capacitor 71. C1 is a capacitance value between terminals of the digital capacitor 70, and C2 is a capacitance value between terminals of the digital capacitor 71.

  The configuration of the digital capacitor 70 and the digital capacitor 71 is the same as that of the first embodiment, and the configuration shown in FIG.

  As in the first embodiment, if V1 = VBG / R1 / C1 × Δt is larger than VBG, the output of the comparator 80 is High, and if it is smaller, the output of the comparator 80 is Low. Similarly, if V2 = VBG / R2 / C2 × Δt is larger than VBG, the output of the comparator 81 becomes High, and if it is smaller, it becomes Low.

  As in the first embodiment, if this is performed 5 times (for 5 clock cycles) if it is a 5-bit digital capacitor, the digital value to be given to each switch of the digital capacitors 70 and 71 is determined. The binary search circuit 120 controls these.

  The binary search circuit 120 is the same as the binary search circuit 120 of the first embodiment, except that the control target is doubled. Hereinafter, the operation of the binary search circuit 120 will be described with reference to FIG.

  As in the “first embodiment”, the description will be made for each period (P1 to P6).

At the rising edge of the clock signal 100 with the period P1, the switches of the digital capacitors 70 and 71
# 4 switch = High
# 3 switch = Low
# 2 switch = Low
# 1 switch = Low
# 0 switch = Low
The binary search circuit 120 provides the digital value of.

  While the clock signal 100 of the period P1 is at the high level, the switches 61 and 62 are switched according to the polarity shown in FIG. 60, so that the digital capacitor 70 is discharged by the discharge circuit 40 and the digital capacitor 71 is discharged by the discharge circuit 41. The voltage between the terminals of the capacitors 70 and 71 is 0V. Therefore, the outputs of the comparators 80 and 81 are Low.

  When the clock signal 100 of the period P1 falls to the low level, the switches 61 and 62 are connected to the digital capacitor 70 by the charging circuit 50 and the DC current I1 = VBG / R1 output from the voltage-current conversion circuit 30 is changed to the digital capacitor. 71 is supplied with the direct current I2 = VBG / R2 which is the output of the voltage-current conversion circuit 31 by the charging circuit 51.

A voltage proportional to a time Δt from the falling edge of the clock signal 100 in the period P1 to the rising edge of the signal in the period P2 between the terminals of the digital capacitor 70 at the rising edge of the clock signal 100 in the period P2.
V1 = VBG / R1 / C1 × Δt
Appears. Between the terminals of the digital capacitor 71
V2 = VBG / R2 / C2 × Δt
Appears. Here, C1 is a capacitance value between terminals of the digital capacitor 70, and C2 is a capacitance value between terminals of the digital capacitor 71.

  If the voltage V1 is larger than VBG, the output of the comparator 80 is at the high level at the rising edge of the clock signal 100 in the period P2, and if the voltage V1 is smaller than VBG, the output of the comparator 80 is the rising edge of the period P2 of the clock signal 100. It becomes Low level at the time. Similarly, if the voltage V2 is larger than VBG, the output of the comparator 81 is at a high level at the rising edge of the clock signal 100 in the period P2, and if the voltage V2 is smaller than VBG, the output of the comparator 81 is the clock signal in the period P2. It becomes Low level at the time of 100 rise.

  The output levels of the comparators 80 and 81 are latched by the latches 90 and 91 at the rising edge of the clock signal 100 in the period P2, respectively, and at the same time, the digital signals that the binary search circuit 120 supplies to the # 4 switches of the digital capacitors 70 and 71, respectively. Stored as a value.

At the rise of the clock signal 100 of the period P2, the # 0 switch to the # 4 switch of the digital capacitor 70 are
# 4 switch = output level of the comparator 80 at the rising edge of the clock signal 100 in the period P2.
# 3 switch = High
# 2 switch = Low
# 1 switch = Low
# 0 switch = Low
Is provided by the binary search circuit 120. Also, on the # 0 switch or # 4 switch of the digital capacitor 71,
# 4 switch = output level of the comparator 81 at the rising edge of the clock signal 100 in the period P2.
# 3 switch = High
# 2 switch = Low
# 1 switch = Low
# 0 switch = Low
Is provided by the binary search circuit 120.

  While the clock signal 100 in the period P2 is at a high level, the switches 61 and 62 are switched according to the polarity of the switch polarity diagram 60, the digital capacitor 70 is discharged by the discharge circuit 40, and the digital capacitor 71 is discharged by the discharge circuit 41. The voltage between the terminals of the capacitors 70 and 71 is 0V. Therefore, the outputs of the comparators 80 and 81 are Low.

  When the clock signal 100 in the period P2 becomes low level, the digital capacitors 70 and 71 are connected to the charging circuits 50 and 51 by the switches 61 and 62, respectively. As a result, the direct current I1 = VBG / R1 output from the voltage / current conversion circuit 30 is supplied to the digital capacitor 70, and the direct current I2 = VBG / R2 output from the voltage / current conversion circuit 31 is supplied to the digital capacitor 71.

As a result, a voltage proportional to the time Δt between the falling edge of the clock signal 100 of the period P2 and the rising edge of the period P3 between the terminals of the digital capacitor 70 when the clock signal 100 of the period P3 rises.
V1 = VBG / R1 / C1 × Δt
Appears. Between the terminals of the digital capacitor 71
V2 = VBG / R2 / C2 × Δt
Appears.

  If the voltage V1 is higher than VBG, the output of the comparator 80 is High level at the rising edge of the clock signal 100 in the period P3, and if it is lower, the output of the comparator 80 is Low level. Similarly, if the voltage V2 is greater than VBG, the output of the comparator 81 is at a high level at the rising edge in the period P3 of the clock signal 100, and if it is smaller, the output of the comparator 81 is at a low level.

  The output levels of the comparators 80 and 81 are latched in the latches 90 and 91, respectively, at the rising point of the clock signal 100 of the period P3, and the digital signal value that the binary search circuit 120 gives to the # 3 switch of the digital capacitors 70 and 71 Is remembered as

At the rise of the clock signal 100 of the period P3, the # 0 switch to the # 4 switch of the digital capacitor 70 are
# 4 switch = output level of the comparator 80 at the rising edge of the clock signal 100 in the period P2.
# 3 switch = output level of the comparator 80 at the rising edge of the clock signal 100 in the period P3
# 2 switch = High
# 1 switch = Low
# 0 switch = Low
Is provided by the binary search circuit 120. In addition, to the # 0 switch or # 4 switch of the digital capacitor 71,
# 4 switch = output level of the comparator 81 at the rising edge of the clock signal 100 in the period P2.
# 3 switch = output level of the comparator 81 at the rising edge of the clock signal 100 in the period P3
# 2 switch = High
# 1 switch = Low
# 0 switch = Low
Is provided by the binary search circuit 120.

  During the high level of the clock signal 100 in the period P3, the digital capacitors 70 are discharged by the discharge circuit 40 and the digital capacitor 71 is discharged by the discharge circuit 41 by the switches 61 and 62, and the digital capacitors 70 and 71 are connected between the terminals. Becomes 0V. Therefore, the outputs of the comparators 80 and 81 are Low.

  When the clock signal 100 in the period P3 becomes low level, the digital capacitor 70 is connected to the charging circuits 50 and 51 by the switches 61 and 62. As a result, the digital capacitor 70 is supplied with the direct current I1 = VBG / R1 that is the output of the voltage-current conversion circuit 30, and the digital capacitor 71 is supplied with the direct-current I2 = VBG / R2 that is the output of the voltage-current conversion circuit 31. The

As a result, a voltage proportional to the time Δt between the falling edge of the clock signal 100 of the period P3 and the rising edge of the period P4 between the terminals of the digital capacitor 70 when the clock signal 100 of the period P4 rises.
V1 = VBG / R1 / C1 × Δt
Appears. Between the terminals of the digital capacitor 71
V2 = VBG / R2 / C2 × Δt
Appears.

  If the voltage V1 is higher than VBG, the output of the comparator 80 is at a high level at the rising edge of the clock signal 100 in the period P4, and if lower, the output of the comparator 80 is at a low level. Similarly, if the voltage V2 is greater than VBG, the output of the comparator 81 is at a high level at the rising edge in the period P4 of the clock signal 100, and if it is smaller, the output of the comparator 81 is at a low level.

  The output levels of the comparators 80 and 81 are latched in the latches 90 and 91 at the rising edge of the clock signal 100 in the period P4, respectively, and at the same time, the digital signal value that the binary search circuit 120 gives to the # 2 switch of the digital capacitors 70 and 71 Is remembered as

Furthermore, at the rising edge of the clock signal 100 of the period P4, the # 0 switch to the # 4 switch of the digital capacitor 70 are
# 4 switch = output level of the comparator 80 at the rising edge of the clock signal 100 in the period P2.
# 3 switch = output level of the comparator 80 at the rising edge of the clock signal 100 in the period P3
# 2 switch = output level of the comparator 80 at the rising edge of the clock signal 100 in the period P4
# 1 switch = High
# 0 switch = Low
Is provided by the binary search circuit 120. In addition, to the # 0 switch or # 4 switch of the digital capacitor 71,
# 4 switch = output level of the comparator 81 at the rising edge of the clock signal 100 in the period P2.
# 3 switch = output level of the comparator 81 at the rising edge of the clock signal 100 in the period P3
# 2 switch = output level of the comparator 81 at the rising edge of the clock signal 100 in the cycle P4
# 1 switch = High
# 0 switch = Low
Is provided by the binary search circuit 120.

  During the high level of the clock signal 100 in the period P4, the digital capacitors 70 are discharged by the discharge circuit 40 and the digital capacitor 71 is discharged by the discharge circuit 41 by the switches 61 and 62, and the terminals of the digital capacitors 70 and 71 are discharged. Becomes 0V. Therefore, the outputs of the comparators 80 and 81 are Low.

  When the clock signal 100 in the period P4 becomes low level, the digital capacitor 70 is connected to the charging circuits 50 and 51 by the switches 61 and 62. As a result, the digital capacitor 70 is supplied with the direct current I1 = VBG / R1 that is the output of the voltage-current conversion circuit 30, and the digital capacitor 71 is supplied with the direct-current I2 = VBG / R2 that is the output of the voltage-current conversion circuit 31. The

As a result, a voltage proportional to the time Δt between the falling edge of the clock signal 100 of the period P4 and the rising edge of the period P5 between the terminals of the digital capacitor 70 when the clock signal 100 of the period P5 rises.
V1 = VBG / R1 / C1 × Δt
Appears. Between the terminals of the digital capacitor 71
V2 = VBG / R2 / C2 × Δt
Appears.

  If the voltage V1 is higher than VBG, the output of the comparator 80 is High level at the rising edge of the clock signal 100 in the period P5, and if it is lower, the output of the comparator 80 is Low level. Similarly, if the voltage V2 is greater than VBG, the output of the comparator 81 is at a high level at the rising edge in the period P5 of the clock signal 100, and if it is smaller, the output of the comparator 81 is at a low level.

  The output levels of the comparators 80 and 81 are latched in the latches 90 and 91 at the rising edge of the clock signal 100 in the period P5, respectively, and at the same time, the digital signal value that the binary search circuit 120 gives to the # 2 switch of the digital capacitors 70 and 71 Is remembered as

At the rising edge of the clock signal 100 of the period P5, the # 0 switch to the # 4 switch of the digital capacitor 70 are
# 4 switch = output level of the comparator 80 at the rising edge of the clock signal 100 in the period P2.
# 3 switch = output level of the comparator 80 at the rising edge of the clock signal 100 in the period P3
# 2 switch = output level of the comparator 80 at the rising edge of the clock signal 100 in the period P4
# 1 switch = output level of the comparator 80 at the rising edge of the clock signal 100 in the period P5
# 0 switch = High
Is provided by the binary search circuit 120. In addition, to the # 0 switch or # 4 switch of the digital capacitor 71,
# 4 switch = output level of the comparator 81 at the rising edge of the clock signal 100 in the period P2.
# 3 switch = output level of the comparator 81 at the rising edge of the clock signal 100 in the period P3
# 2 switch = output level of the comparator 81 at the rising edge of the clock signal 100 in the cycle P4
# 1 switch = output level of the comparator 81 at the rising edge of the clock signal 100 in the period P5
# 0 switch = High
Is provided by the binary search circuit 120.

  During the high level of the clock signal 100 in the period P5, the digital capacitors 70 are discharged by the discharge circuit 40 and the digital capacitor 71 is discharged by the discharge circuit 41 by the switches 61 and 62, and the digital capacitors 70 and 71 are connected between the terminals. Becomes 0V. Therefore, the outputs of the comparators 80 and 81 are Low.

  When the clock signal 100 in the period P5 becomes the Low level, the digital capacitor 70 is connected to the charging circuits 50 and 51 by the switches 61 and 62. As a result, the digital capacitor 70 is supplied with the direct current I1 = VBG / R1 that is the output of the voltage-current conversion circuit 30, and the digital capacitor 71 is supplied with the direct-current I2 = VBG / R2 that is the output of the voltage-current conversion circuit 31. The

As a result, a voltage proportional to the time Δt between the falling edge of the clock signal 100 in the period P5 and the rising edge in the period P6 between the terminals of the digital capacitor 70 when the clock signal 100 in the period P6 rises.
V1 = VBG / R1 / C1 × Δt
Appears. Between the terminals of the digital capacitor 71
V2 = VBG / R2 / C2 × Δt
Appears.

  If the voltage V1 is higher than VBG, the output of the comparator 80 is High level at the rising edge of the clock signal 100 in the period P6, and if it is lower, the output of the comparator 80 is Low level. Similarly, if the voltage V2 is greater than VBG, the output of the comparator 81 is at a high level at the rising edge in the period P6 of the clock signal 100, and if it is smaller, the output of the comparator 81 is at a low level.

  The output levels of the comparators 80 and 81 are latched in the latches 90 and 91 at the rising edge of the clock signal 100 in the period P5, respectively, and at the same time, the digital signal value that the binary search circuit 120 gives to the # 2 switch of the digital capacitors 70 and 71 Is remembered as

The digital value given to each switch of the digital capacitor 70 is now
# 4 switch = output level of the comparator 80 at the rising edge of the clock signal 100 in the period P2.
# 3 switch = output level of the comparator 80 at the rising edge of the clock signal 100 in the period P3
# 2 switch = output level of the comparator 80 at the rising edge of the clock signal 100 in the period P4
# 1 switch = output level of the comparator 80 at the rising edge of the clock signal 100 in the period P5
# 0 switch = determined to the value of the output level of the comparator 80 at the rising edge of the clock signal 100 in the period P6. The digital value given to each switch of the digital capacitor 71 is
# 4 switch = output level of the comparator 81 at the rising edge of the clock signal 100 in the period P2.
# 3 switch = output level of the comparator 81 at the rising edge of the clock signal 100 in the period P3
# 2 switch = output level of the comparator 81 at the rising edge of the clock signal 100 in the cycle P4
# 1 switch = output level of the comparator 81 at the rising edge of the clock signal 100 in the period P5
# 0 switch = determined to the value of the output level of the comparator 81 at the rising edge of the clock signal 100 in the period P6.

  This is a correction of the manufacturing variation of the resistance value R1 of the resistor 20 and the capacitance value C1 between the terminals of the digital capacitor 70 and the manufacturing variation of the resistance value R2 of the resistor 21 and the capacitance value C2 between the terminals of the digital capacitor 71. Thus, the product of R1 × C1 and the product of R2 × C2 becomes constant when the above digital values are given to the # 0 switch to the # 4 switch.

  After the rising edge of the clock signal 100 of the period P6, the digital value is given to the channel filter circuit 150 at the rising edge of the calibration completion signal 160.

  In this embodiment, the adder circuit 140 adds the first offset value of the offset register 130 to the digital value given to each switch of the digital capacitor 70 to the digital capacitor 151 with respect to the feedback capacitor of the channel filter circuit 150. Further, the adder circuit 141 adds the second offset value of the offset register 131 to the digital value given to each switch of the digital capacitor 71 to the digital capacitor 152 related to the non-feedback capacitor of the channel filter circuit 150.

  In this way, the feedback capacitors C11, C21, C31, and C41 and the non-feedback capacitors C12, C22, C32, and C42 of the eighth-order Butterworth low-pass filter of the channel filter circuit 150 are respectively used with different structures. Even if it is manufactured, it is possible to correct an error in the cut-off frequency.

  That is, the automatic adjustment circuit including the digital capacitor 70 and the automatic adjustment circuit including the digital capacitor 71 are individually associated with the feedback capacitors C11, C21, C31, and C41 and the non-feedback capacitors C12, C22, C32, and C42, respectively. By doing so, it is possible to prevent the occurrence of an error to the other due to matching with either the feedback capacitance or the non-feedback capacitance as shown in FIG.

  Here, the offset registers 130 and 131 are registers for evaluating a completed semiconductor chip and setting an appropriate value later. The offset registers 130 and 131 can correct the cutoff frequency when the gain of the amplifiers AMP1 to AMP4 has an error from 1.

  When the filter cut-off frequency automatic adjustment circuit of FIG. 2 and the eighth-order Butterworth low-pass filter of FIG. 3 are laid out on the semiconductor chip under the conditions of FIG. 6, resistors R41 and R42, feedback capacitance C41, non-feedback capacitance Resistors 20 and 21 and digital capacitors 70 and 71 are arranged near C42. This is because a block having a large ratio between the feedback capacitance and the non-feedback capacitance has the highest Q, so that accuracy is required.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention relates to an automatic cut-off frequency adjusting circuit, and relates to an automatic cut-off frequency adjusting circuit for a filter having a large ratio of capacitance values to be used. The digital value determined by the automatic cut-off frequency adjusting circuit of the present invention functions to keep the product of the resistance and the capacitance constant, so that not only the filter cut-off frequency automatic adjusting circuit but also the phase compensation of the operational amplifier, the CR oscillator It can also be used as a correction value for an arbitrary circuit in which the product of resistance and capacitance is related to behavior, such as center frequency correction. Moreover, application to portable information terminals, such as a mobile phone using them, is also considered.

It is a block diagram of the filter cutoff frequency automatic adjustment circuit of the 1st Embodiment of this invention. It is a block diagram of the filter cutoff frequency automatic adjustment circuit of the 2nd Embodiment of this invention. It is a schematic diagram of the digital capacity assumed in the present invention. It is a timing chart about filter cut-off frequency automatic adjustment. It is a circuit diagram of a channel filter circuit assumed in the present invention. This is the value of the circuit constant of the internal element of the channel filter circuit assuming a cutoff frequency of 2 MHz.

Explanation of symbols

10 ... reference voltage, 20, 21 ... resistor, 30, 31 ... voltage-current conversion circuit,
40, 41 ... discharge circuit, 50, 51 ... charging circuit, 61, 62 ... switch,
70, 71 ... Digital capacity, 80, 81 ... Comparator, 90, 91 ... Latch,
100 ... clock signal 110 ... reset signal 120 ... binary search circuit
130, 131 ... offset value, 150 ... channel filter circuit,
151: Feedback digital capacity, 152: Non-feedback digital capacity,
160: Calibration completion signal C11, C21, C31, C41 ... Feedback capacitance,
C12, C22, C32, C42 ... non-feedback capacity,
R11, R12, R21, R22, R31, R32, R41, R42 ... resistors,
AMP1, AMP2, AMP3, AMP4 ... Amplifier

Claims (8)

A cut-off frequency automatic adjustment circuit including a reference voltage source, a voltage-current conversion circuit, a charging circuit, a discharging circuit, a digital capacitor having a plurality of capacitors, and a capacitance control circuit for controlling the digital capacitance,
The voltage-current conversion circuit, the charging circuit, the discharging circuit, and the digital capacitor constitute a first automatic adjustment circuit,
The digital capacitor is connected to the charging circuit and the discharging circuit by a switch,
A clock signal is input to the switch and the capacity control circuit,
The digital capacitor is connected to the charging circuit or the discharging circuit by switching the switch according to the potential of the clock signal,
The digital capacitor is connected in parallel by switching all or part of the plurality of capacitors,
An automatic cut-off frequency adjusting circuit, wherein the capacitance control circuit controls the digital capacitance based on a comparison result of a difference between a terminal potential of the digital capacitance and a voltage of the reference voltage source. The automatic cut-off frequency adjusting circuit according to claim 1, further comprising a comparator for comparing a voltage input to the digital capacitor and a voltage of the reference voltage source, and a latch to which the clock signal is input.
An automatic cutoff frequency adjusting circuit, wherein the latch latches an output of the comparator at a predetermined timing of the clock signal and outputs the latched output to the capacitance control circuit.   3. The automatic cut-off frequency adjusting circuit according to claim 1, wherein the capacitance control circuit is a binary search circuit.   4. The automatic cutoff frequency adjustment circuit according to claim 1, wherein a difference between a potential of the digital capacitor and a potential of the reference voltage source falls within a predetermined potential difference. 5. A cut-off frequency automatic adjustment circuit, wherein a control circuit controls the digital capacitance.   2. The cutoff frequency automatic adjustment circuit according to claim 1, further comprising a second automatic adjustment circuit including a voltage-current conversion circuit, a charging circuit, a discharging circuit, and a digital capacitor. The automatic cut-off frequency adjusting circuit according to claim 5, further comprising a channel filter circuit,
The channel filter circuit has a feedback capacitor which is a digital capacitor for feedback and a ground capacitor which is a digital capacitor for grounding.
The capacitance control circuit sets the feedback capacitance under a control condition for the digital capacitance of the first automatic adjustment circuit, and sets the ground capacitance under a control condition for the digital capacitance of the second automatic adjustment circuit. Cutoff frequency automatic adjustment circuit characterized by   7. The automatic cut-off frequency adjusting circuit according to claim 6, wherein the channel filter circuit is a Butterworth low-pass filter.   A personal digital assistant using the cut-off frequency automatic adjustment circuit according to any one of claims 1 to 7.

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