JP2009094782A - Semiconductor system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To avoid the occurrence of a fault by precisely predicting the signal quality degradation in a high-speed transmission line during operation of a device. <P>SOLUTION: An output adjustment value of an adjustment value control logic which outputs the most suitable impedance adjustment value in accordance with the impedance variance of a buffer due to temperature changes during operation of the device is collated with an already set impedance adjustment value, and the collation result is used as a prediction report to control the use of a line including the related buffer, thereby avoiding the occurrence of a fault in the line. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor system, and more particularly to a failure predicting technique in an information processing apparatus such as a computer having an impedance adjustment function and equipped with a semiconductor device.

  As the transfer speed in a transmission path connecting a plurality of LSIs including a processor bus of a computer increases, it is more important to ensure the signal quality of the transmission path. Technologies for ensuring computer signal quality include error suppression technology that reduces the occurrence of errors with an impedance adjustment circuit that corrects variations in the characteristics of the LSI output buffer, and retransmission processing using CRC error detection. Error correction technology that performs recovery in the event of an error by ECC 1-bit error correction processing, etc. In addition, it is equipped with a temperature sensor, etc., observes environmental fluctuations of the device, and predicts error occurrence by detecting unexpected conditions -There is a failure predictor technology that implements response control.

The error suppression technique using the impedance adjustment circuit suppresses the occurrence of a failure factor such as reflection due to mismatch between the output impedance of the output buffer and the impedance of the transmission path. Normally, the impedance of the output buffer and the impedance of the transmission line on the board are all designed to match the same value, but the impedance of the output buffer varies due to variations in process conditions, etc. Therefore, it is expected that the impedance can be adjusted with high accuracy.
For example, Japanese Patent Laid-Open No. 11-31960 discloses a technique for automatically adjusting the impedance of a transmission line in a system using an LSI.

Japanese Patent Laid-Open No. 11-31960

  With conventional impedance adjustment circuits for ensuring the quality of transmission lines and information processing equipment with failure predictor logic, it is possible to observe static characteristic factors such as process variations associated with the output buffer itself, and to observe with a temperature sensor It is effective as a predictive measure performed with accuracy. However, this causes a mismatch with the impedance of the transmission line, such as a change in impedance characteristic due to a temperature change during operation of the apparatus, and there is a problem in dealing with a dynamic characteristic factor that requires better observation accuracy.

  The impedance adjustment value for the output buffer during operation is fixed to the value of the setting register that is stored when the device is started up.Therefore, if the impedance characteristics fluctuate due to temperature changes during device operation, the value of the setting register will change accordingly. It is not the optimum value to match the impedance of the transmission line. When the difference between the value of the setting register and the optimum adjustment value that changes during operation increases, this indicates the degree of signal quality degradation as it is, and the failure rate increases.

  Although it is possible to mount a temperature sensor against this dynamic characteristic factor that accompanies this temperature change and indirectly predict the failure caused by the difference between the adjustment values, the difference between the adjustment values is clearly Since it is not detected, the failure sign cannot be accurately performed, and the failure sign by the temperature sensor is hardly a level used for dealing with the failure caused by the difference.

  An object of the present invention is to accurately predict signal quality degradation of a high-speed transmission line during operation of the apparatus and to avoid occurrence of a failure.

According to the present invention, the cause of the failure caused by the difference between the adjustment values is directly observed during the operation of the apparatus, and the observation result can be used as a predictor report, so that the predictor can be handled with very high accuracy.
In addition, the present invention can manage the sign detection range and determination criteria, suppress the overhead for performance corresponding to the sign, and avoid the occurrence of a failure.

  According to a preferred embodiment of the present invention, in a semiconductor system having an LSI including a main logic, a buffer that holds a signal of the main logic output to the transmission path or a signal input from the transmission path, and a buffer with a certain adjustment value. An impedance adjustment unit that corrects the characteristics of the adjustment value, an adjustment value detection unit that detects a difference between the adjustment value and an optimum adjustment value that varies during operation of the apparatus (or a matching unit), and an output of the adjustment value detection unit And a failure predictor for predicting a failure that may occur, and the use of the line including the buffer is controlled based on the output of the failure predictor Configured as a system.

  Further, in a preferred example, the impedance adjustment unit is adjustable in the same manner as the buffer, and an input or output of the replica buffer is connected to an external reference resistor corresponding to the characteristic impedance of the transmission line, and the output of the replica buffer A voltage comparison circuit that compares a potential with a reference potential; an adjustment value control logic that outputs, as an instruction, an adjustment value that controls impedance so as to eliminate and converge the difference between the potentials from the comparison result of the voltage comparison circuit; Write selection logic for controlling storage of the adjustment value output from the adjustment value control logic, a setting register for storing the adjustment value and outputting the adjustment value to the buffer, and controlling the buffer by the converged adjustment value And the adjustment value detection unit detects a difference by comparing the adjustment value output from the adjustment value control logic with the adjustment value output from the setting register. .

  Preferably, the adjustment value detection unit includes a storage unit that stores an allowable range of differences between adjustment values, a determination unit that determines whether the difference is within or outside the allowable range, and a result of determination by the determination unit. The failure predictor performs predictive control according to a signal received via the determination path.

  According to another preferred example, the present invention is a semiconductor system having an LSI including a main logic having a plurality of input signals or output signals, and is arranged on an input line or an output line of the main logic. A plurality of buffers for holding signals output from or input to the transmission path from the main logic, a plurality of impedance adjusting units for correcting characteristics of the buffers by a certain adjustment value, and a plurality of the main logic Predictive failure that may occur based on the input signal or output signal based on the detection signal from the path switch unit that switches the path to be the input line or output line and the sensor that detects the temperature in the device. And a path switch unit that switches an input line or an output line according to an output of the failure sign unit. Configured as a semiconductor system comprising and.

  According to a preferred embodiment of the present invention, a dynamic characteristic factor that causes a mismatch with the impedance of the transmission line, such as an impedance characteristic variation of the input or output buffer due to a temperature change or the like during operation of the apparatus, It can be directly detected as the difference between the adjustment value and the optimum adjustment value that varies during operation of the apparatus, and can be used for a failure sign. As a result, it is possible to efficiently cope with a sign and avoid the occurrence of a failure.

Embodiments of the present invention will be described below in detail with reference to the drawings.
[Example 1]
FIG. 1 is a configuration block diagram of an information processing apparatus to which a semiconductor system according to an embodiment is applied.
This information processing apparatus has an LSI 600 and a plurality of external reference resistors 601 and 602 on a board 1100. The LSI 600 includes a main logic 51, a plurality of output buffers 37 and 47 mounted on a plurality of output paths 262 and 266 of the main logic 51, and a plurality of impedances for adjusting the impedance of each of the plurality of output buffers 37 and 47. The path switching unit 57 that switches the output paths of the output signals 261 and 265 of the main logic 51, the failure predictor logic 53 that performs failure predictor response, the path control signal 251 from the main logic 51, and the failure The switch control logic 52 that performs path switching control of the path switch unit 57 by the path switching signal 253 from the predictive logic 53 is included. In addition, since the impedance adjustment parts 55 and 56 are the same structures, hereafter, the code | symbol on the impedance adjustment part 55 side is quoted and demonstrated.

  The impedance adjustment unit 55 can be adjusted in the same manner as the output buffer. The replica buffer 34 has an output connected to the external reference resistor 601 corresponding to the characteristic impedance of the transmission line, the output potential 234 of the replica buffer 34, and the reference potential generation circuit. The voltage comparison circuit 32 that compares the reference potential 231 of 31 and outputs the comparison result, and the adjustment value 233 that controls the impedance so as to cancel the difference between the potentials from the comparison result of the voltage comparison circuit 32 and converge, Adjustment value control logic 33 to be output, write selection logic 35 to control writing of the adjustment value to the setting register 36, setting register 36 to store the adjustment value 236 to be output to the output buffers 37 and 47, and adjustment value The adjustment value 233 output from the control logic 33 and the adjustment value 236 output from the setting register 36 are compared, and the difference Having an adjustment value comparison detection logic 38 to be detected.

  The failure sign logic 53 performs a failure sign according to the difference detection output 238, 248 between the adjustment values from the adjustment value comparison detection logic 38 of the plurality of impedance adjustment units 55, 56, and sends a path switching signal 253 to the switch control logic 52. Output. That is, the main logic signal output for the output path is based on the difference output between the adjustment values (that is, information indicating the possibility of failure of the corresponding output path) and the sign permission signal for instructing permission or inhibition of sign execution. Implement the control to prevent the occurrence of possible failures.

Next, the operation of impedance adjustment and failure sign will be described.
During the start-up sequence of the information processing apparatus, the impedance adjustment unit 55 uses the output potential of the replica buffer 34 connected to the external reference resistor 601 set so as to match the impedance of the transmission line, and the reference potential to the voltage comparison circuit 32. Then, the adjustment value control logic 33 eliminates the difference between the potentials from the comparison result, and outputs the adjustment value so as to converge to a value that can be matched. The adjustment value converges when the output impedance of the replica buffer 34 matches the impedance of the external reference resistor 601, and the optimum adjustment value is stored in the setting register 36 by the write selection logic 35. The output buffer 37 is impedance-adjusted according to the value stored in the setting register 36, and is matched with the impedance of the external reference resistor 601 and matched with the impedance of the transmission line.

  When the write selection logic 35 stores in the setting register 36, the adjustment value output from the adjustment value control logic 33 and the adjustment value output from the setting register 36 match, and the adjustment value comparison detection logic 38, since there is no difference, it can be determined that the probability of occurrence of a failure due to impedance mismatching is low, and no predictive report is executed to the predictive failure logic 53.

  For the output buffer 47, the impedance adjustment unit 56 independently performs the same impedance adjustment as described above. When the device after the impedance adjustment is started up and is in an operating state, output data from the main logic 21 passes through the path switch unit 57 controlled by the switch control logic 52 and is output from the adjusted output buffer 37 and the output buffer 47 to the outside. Will be sent to.

  When the apparatus enters the operating state and the temperature of the output buffer 37 rises, the impedance characteristics of the output buffer 37 change accordingly. However, since the impedance adjustment value for the output buffer 37 is fixed to the value of the setting register 36 stored when the apparatus is started up, the probability of mismatching with the impedance of the transmission path is high. When the impedance characteristic of the output buffer 37 fluctuates, the adjustment value output from the adjustment value control logic 33 also fluctuates to a value that takes into account fluctuations due to temperature rise. The adjustment value output from the adjustment value control logic 33 and the adjustment value output from the setting register 36 do not match, and the adjustment value comparison detection logic 38 detects the difference. Then, when the adjustment value comparison detection logic 38 detects that the difference exceeds a certain value, the adjustment value comparison detection logic 38 determines that the occurrence probability of the failure due to the impedance mismatch is high, and reports the prediction to the failure prediction logic 53. .

  The failure sign logic 53 that has received the sign report outputs a path switching signal 253 to the switch control logic 52. The switch control logic 52 controls the path switch unit 57 based on the path control signal 251 and the path switching signal 253 so as not to use the path including the output buffer 37. For example, the output path 262 is disabled and switched to another output path.

  The adjustment value comparison detection logic 38 that compares the adjustment value output from the adjustment value control logic 33 and the adjustment value output from the setting register 36 observes with the same accuracy as directly observing the cause of the failure due to the impedance mismatch. be able to. Then, by using the output of the adjustment value comparison detection logic 38 for the failure predictor and the switching of the output path of the main logic, it is possible to implement a highly accurate failure predictor in the information processing apparatus.

[Example 2]
FIG. 2 is a configuration block diagram of an information processing apparatus according to another embodiment.
The difference between the second embodiment and the first embodiment is that in the impedance adjustment unit 55, the adjustment value comparison / detection logic 38 stores the allowable range X of the difference between the adjustment values, and the difference is within the allowable range X. In other respects, the configuration is the same. This determination logic can be realized by using, for example, a comparison logic circuit that compares whether the difference value w between the detected adjustment values exceeds the allowable range X.

When the apparatus enters an operating state and the output buffer 37 rises in temperature, the adjustment value comparison / detection logic 38 adjusts the adjustment value output from the adjustment value control logic 33 following the temperature rise and the setting register stored at the time of start-up. A difference between the adjustment values output by 36 is detected, and it is determined whether or not the difference value between the detected adjustment values is within a preset allowable range X. As a result of the determination, if the allowable range X is exceeded, predictive reports 239 and 249 are sent to the failure predictive logic 53. The failure predictor logic 53 having received the predictor report outputs a path switching signal 253 to the switch control logic 52 and uses an output path including an output buffer that may cause a failure, as in the above embodiment. Control to prohibit.
As a result, the information processing apparatus including the adjustment value comparison detection logic 38 and the failure predictor logic 53 can manage the detection range and determination criteria of the predictor, and can control the overhead for the performance corresponding to the predictor.

[Example 3]
FIG. 3 is a configuration block diagram of an information processing apparatus according to another embodiment.
In this example, unlike the first and second embodiments, the impedance adjustment units 55 'and 56' do not have the adjustment value comparison and detection logic 38, and an output in which a failure may occur due to the inherent failure predictor logic 53 '. Control to disconnect the path.
That is, the failure predictor logic 53 'controls a failure predictor corresponding to the failure predictor by a detection signal from a temperature sensor, for example, provided at a predetermined location of the information processing apparatus. The failure predictor logic 53 ′ determines whether or not the temperature detection signal exceeds a predetermined value set in advance, and if it exceeds, it determines that the temperature is abnormal and outputs a path switching signal 253 ′. The impedance matching of the output buffer 37 is the same as in the above embodiment.

  In a normal case where there is no sign of failure, output data from the main logic 51 in the LSI is transmitted to the outside via the path switch unit 57 and the output buffers 37 and 47 whose impedance adjustment has been completed.

On the other hand, when there is a failure sign, that is, when a temperature abnormality is detected by the sensor detection signal, the path switch signal 253 ′ is output from the failure sign logic 53 ′ to the new site control logic 52, and the path switch unit 57 has a failure. Control to isolate paths that may occur.
Thereby, although the failure does not actually occur, predictive control is performed so as not to cause a failure in transmission of output data by switching and changing the output path by the path switch unit 57 with an overhead on performance. be able to.

  The present invention applies not only to the output buffer having an adjustable termination resistor in the above embodiment, but also to adjusting the impedance of the input buffer or the input / output buffer to which the adjustable termination resistor is connected. Can be applied to.

The block diagram of the configuration of the semiconductor system according to one embodiment, The block diagram of the configuration of the semiconductor system according to one embodiment, 1 is a configuration block diagram of a semiconductor system according to an embodiment.

Explanation of symbols

1100: Board 600: LSI 601, 602: External reference resistor
31: Reference potential generation circuit 32: Voltage comparison circuit 33: Adjustment value control logic 34: Replica buffer 35: Write selection logic 36: Setting register 37, 47: Output buffer 38: Adjustment value comparison detection logic
51: Main logic 52: Switch control logic 53: Failure predictor logic
231: Reference potential 233: Impedance adjustment value 234, 244: Divided potential 236: Adjustment value setting register output 237: LSI output signal 238, 248: Difference detection output between adjustment values 251: Path control signal 253: Path switching signal 261 265: Output signal 262, 266: Output path.

Claims (8)

  In a semiconductor system having an LSI including a main logic, a buffer for holding a signal of the main logic to be output to a transmission path or a signal input from the transmission path, an impedance adjustment unit for correcting the characteristics of the buffer by a certain adjustment value, An adjustment value detection unit that detects a difference between the adjustment value and an optimum adjustment value that varies during operation of the apparatus, and a failure predictor that predicts a failure that may occur based on the output of the adjustment value detection unit And controlling the use of the line including the buffer based on the output of the failure predictor. The impedance adjustment unit can be adjusted in the same manner as the buffer, and a replica buffer having an input or output connected to an external reference resistor corresponding to the characteristic impedance of the transmission line, and an output potential and a reference potential of the replica buffer. A voltage comparison circuit to be compared, an adjustment value control logic for outputting an adjustment value for controlling impedance so as to cancel and converge the difference between potentials from the comparison result of the voltage comparison circuit, and output from the adjustment value control logic Write selection logic for controlling storage of the adjustment value, a setting register for storing the adjustment value and outputting the adjustment value to the buffer, and means for controlling the buffer by the converged adjustment value,
2. The semiconductor system according to claim 1, wherein the adjustment value detection unit detects a difference by comparing an adjustment value output from the adjustment value control logic with an adjustment value output from the setting register.   The adjustment value detection unit includes a storage unit that stores an allowable range of a difference between adjustment values, a determination unit that determines whether the difference is within or outside the allowable range, and a result of determination by the determination unit 3. The semiconductor system according to claim 1, wherein the failure predictor performs predictive control according to a signal received through the report line. The main logic includes a plurality of input signals or output signals, and
A plurality of buffers arranged on an input line or an output line, a plurality of impedance adjusting units corresponding to the plurality of buffers, and a plurality of input signals or output signals of the main logic, the input lines or outputs thereof 4. The semiconductor system according to claim 1, further comprising: a path switch unit that switches a line, wherein the path switch unit switches the input line or the output line according to an output of the failure sign unit. The semiconductor system according to claim 1, wherein the impedance adjustment unit includes the adjustment value detection unit.   In a semiconductor system having a main logic, a buffer that holds the signal of the main logic that is output to or input from the transmission line, an impedance adjustment unit that adjusts the impedance of the buffer by a certain adjustment value, and the apparatus is in operation A means for collating the output adjustment value of the adjustment value control logic for outputting an optimum impedance adjustment value following the impedance fluctuation of the buffer due to a change in the environment, and a collation means A failure predictor for predicting a failure that may occur based on the result of the comparison, and controlling the use of the line including the buffer based on the output of the failure predictor A semiconductor system. 7. The semiconductor system according to claim 6, wherein the collating means detects the difference by comparing the adjustment value output from the adjustment value control logic with the adjustment value output from the setting register. In a semiconductor system having an LSI including a main logic having a plurality of input signals or output signals,
A plurality of buffers arranged on the input line or output line of the main logic and holding signals output from the main logic to the transmission path or input from the transmission path, and the characteristics of the plurality of buffers are corrected by a certain adjustment value. Detection from a plurality of impedance adjustment units, a path switch unit that switches a path as an input line or an output line for a plurality of input signals or output signals of the main logic, and a sensor that detects a temperature in the apparatus A failure predictor that predicts a failure that may occur based on the signal, and the path switch unit switches its input line or output line according to the output of the failure predictor Semiconductor system.

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