JP2009094193A - Nonvolatile semiconductor storage device, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device and a manufacturing method thereof, which can be improved in operation efficiency in respective processes of design, manufacture and inspection. <P>SOLUTION: In a nonvolatile memory, respective drains D21 to D25 of cell transistors 21 to 25 are connected in common by a bit line BL1 formed in a first wiring layer LY2 through contact holes CH1, CH3 and CH5, and a bit line BL2 disposed to be connected to the bit line BL1 through via holes VH1, VH3 and VH5 is formed in a second wiring layer LY4. Further, respective sources S21 to S25 of the cell transistors 21 to 25 are connected in common by a source line SL1 formed in the first wiring layer LY2 through contact holes CH2, CH4 and CH6, and a source line SL2 disposed to be connected to the source line SL1 through via holes VH2, VH4 and VH6 is formed in the second wiring layer LY4. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same.

  As a method of storing data in a nonvolatile semiconductor memory device, a method of electrically writing data to a MOS transistor having a floating gate such as an EEPROM or a flash memory, and a method of connecting a MOS transistor during a wafer process like a mask ROM There is a method of writing data by the presence or absence of wiring, or a method of writing data by setting the threshold voltage of the MOS transistor higher than the gate voltage at the time of reading during the manufacturing process.

For example, as an example of an EEPROM or a flash memory, there is a non-volatile semiconductor memory device disclosed in Patent Document 1 and a manufacturing method thereof, and as an example of a mask ROM, there is a mask ROM disclosed in Patent Document 2 below.
JP 9-129755 A JP 11-2322892 A

  By the way, such EEPROM, flash memory, and mask ROM have different configurations of MOS transistors (hereinafter referred to as “memory cell transistors”) that constitute memory cells, and therefore have the same specifications, such as configurations of word lines and bit lines. Even so, they cannot be manufactured in the same semiconductor manufacturing process. In addition, while EEPROM and flash memory can electrically write and erase data, mask ROM cannot be rewritten or erased after the data has been written during the manufacturing process. Therefore, both cannot be inspected in the same inspection process.

  For this reason, even if other specifications are the same depending on whether or not data has been written in advance, it is necessary to prepare a plurality of dedicated photomasks in the manufacturing process, and also in the inspection process. Inspection must be performed in the process, and circuit design, photomask, or setup of the inspection process must be prepared individually, and there is a problem that work efficiency is low in each process of design, manufacturing, and inspection.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a nonvolatile semiconductor memory device and a method for manufacturing the same that can improve work efficiency in each process of design, manufacturing, and inspection. It is to provide.

  To achieve the above object, in the nonvolatile semiconductor memory device according to claim 1, the first surface of the first conductivity type semiconductor substrate is formed symmetrically in the plane direction with the channel formation region interposed therebetween. A first well region and a second well region of two conductivity types, a floating gate formed on the main surface of the channel formation region via a gate oxide film, and an oxide film formed on the floating gate A non-volatile semiconductor memory device having a plurality of memory cell transistors having a MOS structure, and formed on a first wiring layer stacked on the semiconductor substrate. A first main wiring commonly connected to the first well region and a first sub-distribution disposed and formed on the second wiring layer stacked on the semiconductor substrate so as to be connectable to the first main wiring. A second main wiring formed in a third wiring layer stacked on the semiconductor substrate and connected in common to the second well region of the plurality of memory cell transistors; and a fourth main wiring stacked on the semiconductor substrate. A second sub-wiring that is disposed and formed in the wiring layer so as to be connectable to the second main wiring, and when the data stored by the memory cell transistor is configured to be electrically rewritable, A first via hole connecting the first main wiring and the first sub wiring and a second via hole connecting the second main wiring and the second sub wiring correspond to each of the plurality of memory cell transistors. When the data stored in the memory cell transistor is electrically rewritable, the second memory cell transistor corresponding to the memory cell transistor to be written is formed. Without forming a via hole or the second via holes, and technical features that form the first via holes and the second via holes corresponding to the memory cell transistors that do not written.

  In the nonvolatile semiconductor memory device according to claim 2, the first wiring layer and the third wiring layer are the same wiring layer in the nonvolatile semiconductor memory device according to claim 1. A technical feature is that the second wiring layer and the fourth wiring layer are the same wiring layer.

  In order to achieve the above object, in the method for manufacturing a nonvolatile semiconductor memory device according to claim 3, the nonvolatile semiconductor memory device is formed symmetrically in the plane direction with the channel formation region sandwiched between the main surface of the first conductivity type semiconductor substrate. A first well region and a second well region of a second conductivity type, a floating gate formed on the main surface of the channel formation region via a gate oxide film, and an oxide film on the floating gate A plurality of memory cell transistors having a MOS structure, and formed in a first wiring layer stacked on the semiconductor substrate and common to the first well region of the plurality of memory cell transistors. A first main wiring connected to the semiconductor substrate, a first sub-wiring arranged and connected to the second wiring layer stacked on the semiconductor substrate, and stacked on the semiconductor substrate. A second main wiring formed in a third wiring layer connected in common to the second well region of the plurality of memory cell transistors, and a fourth wiring layer stacked on the semiconductor substrate. A non-volatile semiconductor memory device manufacturing method comprising a second sub-wiring that is disposed and formed so as to be connectable to a wiring, wherein the data stored by the memory cell transistor is configured to be electrically rewritable A plurality of memory cell transistors including: a first via hole connecting the first main wiring and the first sub wiring; and a second via hole connecting the second main wiring and the second sub wiring. In the case where the data stored by the memory cell transistor is configured so as not to be electrically rewritable, a target for writing is included. Forming the first via hole or the second via hole corresponding to the memory cell transistor not to be written without forming the first via hole or the second via hole corresponding to the memory cell transistor. The via hole forming step and the data writing step are distinguished by a difference in mask pattern capable of forming the first via hole and the second via hole. This is a technical feature.

  4. The method for manufacturing a nonvolatile semiconductor memory device according to claim 4, wherein the first wiring layer and the third wiring layer in the method for manufacturing the nonvolatile semiconductor memory device according to claim 3 are: A technical feature is that the second wiring layer and the fourth wiring layer are the same wiring layer.

  The method for manufacturing a nonvolatile semiconductor memory device according to claim 5 includes the step of forming a capacitor on the semiconductor substrate in the method for manufacturing a nonvolatile semiconductor memory device according to claim 3 or 4. In this case, the plurality of memory cell transistors are technically characterized in that they are formed simultaneously in this step.

  According to the first aspect of the present invention, when the data stored by the memory cell transistor is configured to be electrically rewritable (for example, in the case of configuring an EEPROM or a flash memory), the first main wiring and the first sub wiring are provided. A first via hole to be connected and a second via hole to connect the second main wiring and the second sub wiring are formed corresponding to each of the plurality of memory cell transistors. Therefore, when writing data, the threshold voltage of the memory cell transistor to be written can be set to a predetermined voltage or higher by injecting charges into the floating gate using the first main wiring or the second main wiring. Data can be written to the memory cell transistor. On the other hand, when reading data, by applying a gate voltage lower than a predetermined voltage to the control gate of the memory cell transistor to be read, the on / off operation of the memory cell transistor according to the set state of the threshold voltage is controlled by the first sub-wiring. Alternatively, since it is possible to grasp whether or not a current flows through the second sub-wiring, it is possible to read data stored in the memory cell transistor by this current. At the time of erasing data, a gate voltage lower than the potential of the first main wiring or the second main wiring is applied to the control gate of the memory cell transistor to be erased, and charges are transferred from the floating gate to the first main wiring or the first main wiring. 2 By pulling out to the main wiring side, the threshold voltage of the memory cell transistor is made lower than a predetermined voltage, so that data can be erased from the memory cell transistor.

  On the other hand, when the data stored by the memory cell transistor is configured so as not to be electrically rewritable (for example, when configuring a mask ROM), charges are injected into the floating gates of a plurality of memory cell transistors and applied to the control gate. The first voltage corresponding to the memory cell transistor not to be written without setting the threshold voltage lower than the applied voltage and without forming the first via hole or the second via hole corresponding to the memory cell transistor to be written. A hole or a second via hole is formed. Therefore, when data is read, even if a gate voltage higher than the threshold voltage is applied to the control gate of the memory cell transistor to be read, the first via hole or the second via hole corresponding to the memory cell transistor is formed. Current does not flow through the first sub-wiring or the second sub-wiring, and current flows through the first sub-wiring or the second sub-wiring when the first via hole or the second via hole is formed. Data can be stored in the memory cell transistor depending on the presence or absence of such current, and the stored data can be read.

  Thus, in the design process of the nonvolatile semiconductor memory device, when the data stored by the memory cell transistor is configured to be electrically rewritable (for example, when configuring an EEPROM or a flash memory), the first If all the via holes and the second via holes are formed, and the data stored by the memory cell transistor is not electrically rewritable (for example, when a mask ROM is configured), a memory to which data is written Except for the first via hole or the second via hole corresponding to the cell transistor, all of the first via hole and the second via hole corresponding to the other memory cell transistors may be formed. For example, an EEPROM or flash memory circuit And the difference between the mask ROM circuit and the first It can be absorbed by the difference in the presence or absence of 2 via hole. Therefore, since these circuit designs are facilitated, work efficiency in the design process can be improved.

  In the manufacturing process of the nonvolatile semiconductor memory device, when data stored by the memory cell transistor is configured to be electrically rewritable (for example, when configuring an EEPROM or a flash memory), the first buyer is used. A photomask capable of forming all of the holes and the second via holes may be prepared, and when data stored by the memory cell transistor is configured to be electrically unrewritable (for example, when configuring a mask ROM). If a photomask capable of forming all of the first via hole and the second via hole corresponding to other memory cell transistors is prepared except for the first via hole or the second via hole corresponding to the memory cell transistor into which data is written. So, for example, EEPROM or flash memory The difference between the production of concrete and mask ROM, first, can be absorbed by the type of controllable photomask formation of the second via hole. Therefore, only the photomask for the via hole in these semiconductor manufacturing processes is changed, and all the processing steps can be shared, so that the working efficiency in the manufacturing steps can be improved.

  Further, in the inspection process of the nonvolatile semiconductor memory device, since the plurality of memory cell transistors have a MOS structure having a floating gate, the data stored by the memory cell transistors is configured to be electrically rewritable ( For example, in the case of configuring an EEPROM or a flash memory) and in the case of configuring the data stored by the memory cell transistor so as not to be electrically rewritable (for example, configuring a mask ROM), for example, the floating gate is placed in the middle. While the process of summing and the process of inspecting circuit functions other than the memory cell transistor are required, the data rewriting function is inspected when the data stored by the memory cell transistor is configured so as not to be electrically rewritable. Inspection work related to data writing and erasing Need of is eliminated. As a result, it is not necessary when the data stored by the memory cell transistor is configured to be electrically non-rewritable based on the inspection process when the data stored by the memory cell transistor is configured to be electrically rewritable. For example, the difference between the inspection of the EEPROM or flash memory and the inspection of the mask ROM can be absorbed by the presence or absence of the inspection item. Therefore, since the inspection line can be made common, work efficiency in the inspection process can be improved from labor saving in the preparation of the inspection process.

  In the invention of claim 2, the first wiring layer and the third wiring layer are made the same wiring layer, and the second wiring layer and the fourth wiring layer are made the same wiring layer. Since the total number is reduced, it is possible to reduce the manufacturing process and the manufacturing cost associated therewith. Further, the thickness (height) of the nonvolatile semiconductor memory device can be reduced (lower) by reducing the total number of wiring layers.

  In the invention of claim 3, the first via hole and the second via hole are formed when the data stored by the memory cell transistor is configured to be electrically rewritable (for example, when configuring an EEPROM or a flash memory). The via hole forming step and the first via hole corresponding to the memory cell transistor to be written in the case where the data stored in the memory cell transistor is configured to be electrically unrewritable (for example, when configuring a mask ROM) A data writing step for forming a first via hole or a second via hole corresponding to the memory cell transistor not to be written without forming a two via hole is to form a first via hole and a second via hole. Differentiated by possible mask pattern differences That. Accordingly, when the data stored in the memory cell transistor is configured to be electrically rewritable, a photomask capable of forming all of the first via hole and the second via hole may be prepared. When the data stored by the transistor is configured so as not to be electrically rewritable, the first memory cell transistor corresponding to the other memory cell transistor except for the first via hole or the second via hole corresponding to the memory cell transistor into which the data is written. It is sufficient to prepare a photomask that can form both the via hole and the second via hole. For example, the formation of the first and second via holes is controlled by the difference between the manufacture of the EEPROM and the flash memory and the manufacture of the mask ROM. Absorption is possible depending on the type of possible photomask. Therefore, since these semiconductor manufacturing processes can be shared in the same manner as in the first aspect of the present invention, work efficiency in the manufacturing process can be improved.

  Further, when the data stored by the memory cell transistor is configured to be electrically rewritable (for example, when configuring an EEPROM or a flash memory), the first main wiring and the first sub wiring are formed by a via hole forming step. And a second via hole for connecting the second main wiring and the second sub-wiring are formed corresponding to each of the plurality of memory cell transistors. Therefore, when writing data, the threshold voltage of the memory cell transistor to be written can be set to a predetermined voltage or higher by injecting charges into the floating gate using the first main wiring or the second main wiring. Data can be written to the memory cell transistor. On the other hand, when reading data, by applying a gate voltage lower than a predetermined voltage to the control gate of the memory cell transistor to be read, the on / off operation of the memory cell transistor according to the set state of the threshold voltage is controlled by the first sub-wiring. Alternatively, since it is possible to grasp whether or not a current flows through the second sub-wiring, it is possible to read data stored in the memory cell transistor by this current. At the time of erasing data, a gate voltage lower than the potential of the first main wiring or the second main wiring is applied to the control gate of the memory cell transistor to be erased, and charges are transferred from the floating gate to the first main wiring or the first main wiring. 2 By pulling out to the main wiring side, the threshold voltage of the memory cell transistor is made lower than a predetermined voltage, so that data can be erased from the memory cell transistor.

  On the other hand, when the data stored in the memory cell transistor is configured so as not to be electrically rewritable (for example, in the case of configuring a mask ROM), the first corresponding to the memory cell transistor to be written is performed by the data writing process. No via hole or second via hole is formed. For this reason, when the threshold voltage is set lower than the voltage applied to the control gate by injecting charges into the floating gates of the plurality of memory cell transistors, the memory cell transistor to be read is controlled when reading data. Even if a gate voltage higher than the threshold voltage is applied to the gate, if the first via hole or the second via hole corresponding to the memory cell transistor is not formed, a current flows through the first sub wiring or the second sub wiring. First, when the first via hole or the second via hole is formed, a current flows through the first sub-wiring or the second sub-wiring, so that the data stored in the memory cell transistor can be read by this current. Become.

  Thus, in the design process of the nonvolatile semiconductor memory device, when the data stored by the memory cell transistor is configured to be electrically rewritable (for example, when configuring an EEPROM or a flash memory), a via hole is used. The formation process may be set so that all of the first via hole and the second via hole are formed, and the data stored by the memory cell transistor is configured to be electrically unrewritable (for example, a mask ROM is configured). 1), the first via hole and the second via hole corresponding to the other memory cell transistors except the first via hole or the second via hole corresponding to the memory cell transistor into which data is written by the data writing process. Can be set to form all , The difference between the circuit of the EEPROM and circuits of the flash memory and a mask ROM, first, can be absorbed by the difference in the presence or absence of the second via hole. Therefore, since these circuit designs are facilitated, work efficiency in the design process can be improved.

  In the inspection process of the nonvolatile semiconductor memory device, since a plurality of memory cell transistors have a MOS structure having a floating gate, the data stored by the memory cell transistors is configured to be electrically rewritable ( For example, in the case of configuring an EEPROM or a flash memory) and in the case of configuring the data stored by the memory cell transistor so as not to be electrically rewritable (for example, configuring a mask ROM), for example, the floating gate is placed in the middle. While the process of summing and the process of inspecting circuit functions other than the memory cell transistor are required, the data rewriting function is inspected when the data stored by the memory cell transistor is configured so as not to be electrically rewritable. Inspection process for data writing and erasing It is no longer necessary. As a result, it is not necessary when the data stored by the memory cell transistor is configured to be electrically non-rewritable based on the inspection process when the data stored by the memory cell transistor is configured to be electrically rewritable. For example, the difference between the inspection of the EEPROM or flash memory and the inspection of the mask ROM can be absorbed by the presence or absence of the inspection item. Therefore, since the inspection line can be made common, work efficiency in the inspection process can be improved from labor saving in the preparation of the inspection process.

  In the invention of claim 4, the first wiring layer and the third wiring layer are made the same wiring layer, and the second wiring layer and the fourth wiring layer are made the same wiring layer. Since the total number is reduced, it is possible to reduce the manufacturing process and the manufacturing cost associated therewith. Further, the thickness (height) of the nonvolatile semiconductor memory device can be reduced (lower) by reducing the total number of wiring layers.

  In the invention of claim 5, when the step of forming a capacitor on the semiconductor substrate is included, a plurality of memory cell transistors are formed simultaneously in this step. Thus, for example, when an analog circuit or the like that requires such a capacitor is formed on a semiconductor substrate on which the memory transistor is formed, the memory transistor is removed by the same process when the capacitor is formed. Since they can be formed at the same time, it is not necessary to add a new semiconductor manufacturing process to form the memory transistor. Therefore, it is possible to improve work efficiency in each process of design, manufacturing, and inspection as described above, while suppressing an increase in manufacturing cost.

Hereinafter, embodiments in which a nonvolatile semiconductor memory device of the present invention is applied to a nonvolatile memory will be described with reference to the drawings. First, a configuration example of a nonvolatile memory will be described as a first embodiment to a third embodiment.
[First Embodiment]
As shown in FIG. 1A, the nonvolatile memory according to the first embodiment is formed as a memory cell transistor (hereinafter referred to as “cell transistor”) via a floating gate and a gate oxide film on the floating gate. A MOS transistor having a MOS structure provided with a control gate is connected in series, and FIG. 1 (A) typically shows five cell transistors 21, 22, 23, 24, 25. Has been. FIG. 2A shows a layout example on the semiconductor substrate plane in which the circuit in the one-dot chain line shown in FIG. 2B is a cross-sectional view taken along the line 2B-2B (dashed line) shown in FIG.

  As shown in FIG. 2A, these cell transistors 21 to 25 are formed on the main surface of a P-conductivity type (first conductivity type) silicon substrate (semiconductor substrate) 20. For example, the cell transistor 21 In this case, as shown in FIG. 2B, an N conductivity type drain diffusion region (second conductivity type first well) D21 and an N conductivity type source diffusion region (first surface) are formed on the surface layer (main surface). The second conductivity type second well) S21 is formed symmetrically in the plane direction with a channel formation region at a predetermined interval. A floating gate FG21 is formed on the surface of the silicon substrate 20 corresponding to the channel formation region via a gate oxide film (a tunnel film of 70 to 200 mm) GX21. Further, an interlayer insulating layer IL21 is formed on the floating gate FG21. A control gate CG23 is formed via Note that the gate oxide film GX21 need not be a tunnel film in the case of an EPROM that does not perform electrical erasure. The film thickness at that time may be 200 mm or more, for example, 350 mm.

  The cell transistors 22 to 25 are also configured in the same manner as the cell transistor 21 (for example, symbols FG22 and CG22 shown in FIG. 2A indicate the floating gate and the control gate of the cell transistor 22, and are also shown in FIG. Reference numerals FG23 and CG23 denote a floating gate and a control gate of the cell transistor 23). Symbols S and D shown in FIG. 2A indicate examples of the source and drain diffusion layers in the silicon substrate 20.

  In the cell transistors 21 to 25 thus configured, the bit line BL1 is connected to the drain, and the source line SL1 is connected to the source via the contact holes. The word line WL1 is connected to the control gate CG21. For example, the drain D21 of the cell transistor 21 is connected to the bit line BL1 through the contact hole CH1. Similarly, the drains D22 and D23 of the cell transistors 22 and 23 are connected to the bit line BL1 through the contact hole CH3, and the drains of the cell transistors 24 and 25 are connected to the bit line BL1 through the contact hole CH5. ing.

  The sources S21 and S22 of the cell transistors 21 and 22 are connected to the source line SL1 through the contact hole CH2. Similarly, the sources S23 and S24 of the cell transistors 23 and 24 are connected to the source line SL1 through the contact hole CH4, and the source S25 of the cell transistor 25 is connected to the source line SL1 through the contact hole CH6. Yes. Word lines WL2 to WL5 are connected to the control gates CG22 to CG25 of the cell transistors 22 to 25, respectively.

  Thus, the bit line BL1 commonly connected to the drains of the cell transistors 21 to 25 and the source line SL1 commonly connected to the sources are aluminum wirings made of, for example, aluminum, both of which are in the first wiring layer LY2. Is formed. For example, in the planar layout example shown in FIG. 2 (A), as shown in FIG. 2 (B), it is located via a contact formation layer LY1 formed by being laminated on the substrate layer LY0 which is the silicon substrate 20. A bit line BL1 and a source line SL1 are stacked on the first wiring layer LY2. The contact holes CH1 to CH6 are respectively formed in the contact formation layer LY1.

  In addition to the bit line BL1 and the source line SL1, the nonvolatile memory according to the first embodiment includes a bit line BL2 and a source line SL2 formed in different wiring layers in parallel therewith. . That is, as shown in FIG. 1A, similarly to the bit line BL1, via the via hole VH1 to the drain D21 of the cell transistor 21, and via the via hole VH3 to the drains D22 and D23 of the cell transistors 22 and 23, Further, the bit line BL2 is connected to the drains D24 and D25 of the cell transistors 24 and 25 through the via holes VH5, respectively. The bit line BL2 is different from the first wiring layer LY2 in which the bit line BL1 is formed. It is formed in the second wiring layer LY4.

  Similarly to the source line SL1, the sources S21 and S22 of the cell transistors 21 and 22 are connected via the via hole VH2, the sources S23 and S24 of the cell transistors 23 and 24 are connected via the via hole VH4, and the source of the cell transistor 25 is further displayed. The source line SL2 is connected to S25 via the via hole VH6, and is formed in the second wiring layer LY4 different from the first wiring layer LY2 in which the source line SL1 is formed.

  As shown in FIG. 1A, these via holes VH1 to VH6 are interposed between the bit line BL1 and the bit line BL2 on the circuit, but in the layout of the silicon substrate 20, FIG. ), For example, the via hole VH1 is disposed in the vicinity of the specific contact hole, such as in the vicinity of the contact hole CH1.

  That is, the via hole VH1 is arranged at a position that can be connected to the contact hole CH1 connected to the drain D21 of the cell transistor 21 with a shorter wiring length than any of the other via holes VH2 to VH6. Similarly, a via hole VH3 is connected to the contact hole CH3 connected to the drains D22 and D23 of the cell transistors 22 and 23, and a via hole is connected to the contact hole CH5 connected to the drains D24 and D25 of the cell transistors 24 and 25. The holes VH5 are arranged so that they can be connected to the contact holes with the shortest wiring lengths than other via holes.

  Similarly, the contact hole CH2 connected to the sources S21 and S22 of the cell transistors 21 and 22 is connected to the via hole VH2, and the contact hole CH4 connected to the sources S23 and S24 of the cell transistors 23 and 24 is connected. Is arranged so that via hole VH6 can be connected to the contact hole with the shortest wiring length than other via holes with respect to via hole VH4 and contact hole CH6 connected to source S25 of cell transistor 25. . Hereinafter, the via hole VHx arranged at a position connectable to the contact hole CHx with the shortest wiring length (x is an integer of 1 to 6) is referred to as “a via hole VHx corresponding to (corresponding to) the contact hole CHx”. That's it.

  Such via holes VH1 to VH6 are formed on the first wiring layer LY2 as described above, as shown in FIG. 2C, for example, in the planar layout example shown in FIG. It is formed in the formation layer LY3, and the bit line BL2 and the source line SL2 are stacked on the via formation layer LY3. FIG. 2 (C) shows a cross section taken along line 2C-2C (two-dot chain line) shown in FIG. 2 (A).

  The bit line BL1 is “first main wiring” described in the claims, the bit line BL2 is “first sub-wiring” described in the claims, and the source line SL1 is “ The “second main wiring” and the source line SL2 can respectively correspond to “second sub-wiring” recited in the claims. The first wiring layer LY2 is “first wiring layer” and “third wiring layer” described in the claims, and the second wiring layer LY4 is “second wiring layer” described in the claims. And “fourth wiring layer”. Further, the via holes VH1, VH3, and VH5 are defined as “first via holes” recited in the claims, and the via holes VH2, VH4, and VH6 are defined as “second via holes” recited in the claims, respectively. It can be equivalent.

  As described above, when the nonvolatile memory according to the first embodiment is configured so that the data stored in the cell transistors 21 to 25 can be electrically rewritten, that is, the nonvolatile memory is configured as an EEPROM or a flash memory. (Hereinafter referred to as “EEPROM etc.”), as described above with reference to FIG. 1A and FIG. 2, via holes VH1, VH3 connecting the bit line BL1 and the bit line BL2. , VH5, and via holes VH2, VH4, VH6 connecting the source lines SL1 and SL2 are formed corresponding to the respective contact holes CH1 to CH6 connected to the cell transistors 21-25.

  On the other hand, when the data stored by the cell transistors 21 to 25 is configured so as not to be electrically rewritable, that is, when the nonvolatile memory is configured as a mask ROM, for example, FIG. 3, for example, without forming the via hole VH1 corresponding to the contact hole CH1 connected to the drain D21 of the cell transistor 21 to be written (inside the broken line α shown in FIG. 1B), Other via holes VH2 to VH6 are formed. In this case, the plane layout corresponding to FIG. 2A is shown in FIG. 3A, and the cross-sectional views corresponding to FIGS. 2B and 2C are FIG. 3B and FIG. Each is shown in (C).

<Data writing (when nonvolatile memory is configured to be rewritable)>
As a result, when the nonvolatile memory is configured as an EEPROM or the like, when data is written, for example, when the cell transistor 21 is set as the write target, as shown in FIG. The source S21 of 21 is set to 0V through the source line SL1, and 6V is applied to the drain D21 through the bit line BL1, and 10V is applied to the control gate CG21 through the word line WL1. The bit line BL2 and the source line SL2 are opened (OPEN), and the word lines WL2 to WL5 of the other cell transistors 22 to 25 are set to 0V, respectively. As a result, electrons move from the source S21 toward the drain D21, and some of the electrons are injected into the floating gate FG21 as hot electrons in a high energy state, and a control gate voltage (for example, 5 V) applied at the time of reading. The threshold voltage Vt of the cell transistor 21 is set to a higher voltage (hereinafter referred to as “Vt = H”). In other words, since the cell transistor 21 is kept off even during reading, no current flows through the source line SL1, and writing of data in which this state is defined as “1” is completed.

<Data writing (when nonvolatile memory is configured to be non-rewritable)>
On the other hand, when the nonvolatile memory is configured as a mask ROM, as described above, data is written in the via hole VH1 corresponding to the contact hole CH1 connected to the cell transistor 21 to be written, etc. This is done by not forming. As shown in FIG. 4B, for example, when the cell transistor 21 is to be written, another via hole VH1 corresponding to the contact hole CH1 connected to the drain D21 of the cell transistor 21 is not formed. Holes VH2 to VH6 are formed. As a result, the electrical connection between the drain D21 of the cell transistor 21 and the bit line BL2 is cut off, so that the cell transistor 21 is turned off in the same manner as when the threshold voltage Vt = H is set. Is completed.

  In both cases where the nonvolatile memory is writable or impossible, the floating voltage of each cell transistor is controlled so that the threshold voltage Vt is applied at the time of reading in the floating gate neutralization process in the manufacturing process, as will be described later. A voltage lower than the gate voltage (for example, 5V) is set (hereinafter referred to as “Vt = L”). For this reason, in the above-described example, the cell transistors 22 to 25 that are not to be written are all shifted from the off state to the on state by the control gate voltage (for example, 5 V) applied to the control gates CG22 to CG25 at the time of reading. Therefore, data defining a state in which current flows through the source line SL1 or the like as “0” is written.

<Reading data (when nonvolatile memory is configured to be rewritable)>
When the nonvolatile memory is configured as an EEPROM or the like, when data is read, as shown in FIG. 5A, for example, when the read target is the cell transistor 21, the control of the cell transistor 21 is performed. 5V is applied as the control gate voltage Vcg to the word line WL1 to which the gate CG21 is connected, and the other word lines WL2 to WL5 are set to 0V. Further, a voltage V1, for example, 1V is applied to the bit line BL2, and a voltage V2, for example, 0V, lower than the voltage V1 of the bit line BL2 is applied to the source line SL1. Then, the control gate CG21 of the cell transistor 21 is set to 5V, the drain D21 is set to 1V, and the source S21 is set to 0V. Note that the bit line BL1 and the source line SL2 are set to an open state (OPEN).

  Similarly, as shown in FIG. 5C, for example, when the read target is the cell transistor 23, 5V is applied as the control gate voltage Vcg to the word line WL3 to which the control gate CG23 of the cell transistor 23 is connected. The other word lines WL1, WL2, WL4, WL5 are set to 0V. Further, a voltage V1, for example, 1V is applied to the bit line BL2, and a voltage V2, for example, 0V, lower than the voltage V1 of the bit line BL2 is applied to the source line SL1. Then, the control gate CG23 of the cell transistor 23 is set to 5V, the drain D23 is set to 1V, and the source S23 is set to 0V. Note that the bit line BL1 and the source line SL2 are set to an open state (OPEN).

  Accordingly, for example, in the example described with reference to FIG. 4A, the threshold voltage Vt of the cell transistor 21 is set to a voltage Vt = H, which is higher than 5 V of the control gate voltage Vcg at the time of reading. Even when the control gate voltage Vcg is applied to the control gate CG21, the cell transistor 21 is not turned on and no current flows through the source line SL1. Therefore, in the above definition, data “1” is read from the cell transistor 21. On the other hand, since the threshold voltage Vt of the cell transistor 23 is set to a voltage Vt = L lower than 5 V of the control gate voltage Vcg at the time of reading, when the control gate voltage Vcg is applied to the control gate CG23, The cell transistor 23 shifts from the off state to the on state, and a current flows through the source line SL1. Therefore, in the previous definition, data “0” is read from the cell transistor 23.

  At the time of reading data, as shown in FIG. 5B, for example, when the reading target is the cell transistor 22 adjacent to the cell transistor 21, the voltages V2 and V1 are applied with the potentials reversed. That is, a voltage V1, for example, 0V is applied to the bit line BL1, and a voltage V2, for example, 1V, higher than the voltage V1 of the bit line BL1 is applied to the source line SL2. Further, 5V is applied as the control gate voltage Vcg to the word line WL2 to which the control gate CG22 of the cell transistor 22 is connected, and the other word lines WL1, WL3 to WL5 are set to 0V. Then, the control gate CG22 of the cell transistor 22 is set to 5V, the drain D22 is set to 0V, and the source S22 is set to 1V. Note that the bit line BL1 and the source line SL2 are set to an open state (OPEN).

  Similarly, as shown in FIG. 5D, for example, when the read target is the cell transistor 24, 5V is applied as the control gate voltage Vcg to the word line WL4 to which the control gate CG24 of the cell transistor 24 is connected. The other word lines WL1 to WL3 and WL5 are set to 0V. Further, a voltage V1, for example, 0V is applied to the bit line BL1, and a voltage V2, for example, 1V, higher than the voltage V1 of the bit line BL1 is applied to the source line SL2. Then, the control gate CG24 of the cell transistor 24 is set to 5V, the drain D24 is set to 0V, and the source S24 is set to 1V. Note that the bit line BL1 and the source line SL2 are set to an open state (OPEN).

  Thus, for example, in the example described with reference to FIG. 4A, the threshold voltage Vt of the cell transistors 22 and 24 is set to a voltage Vt = L lower than 5 V of the control gate voltage Vcg at the time of reading. Therefore, when the control gate voltage Vcg is applied to the control gate CG22, the cell transistor 22 shifts from the off state to the on state, and a current flows through the bit line BL1. Similarly, when the control gate voltage Vcg is applied to the control gate CG24, the cell transistor 24 shifts from the off state to the on state, and a current flows through the bit line BL1. Therefore, in the above definition, data “0” is read from these cell transistors 22 and 24.

  When the adjacent cell transistor 22 is to be read as described above, the current is output from the bit line BL1 by applying the voltage V2 and the voltage V1 with the potential reversed, as described above. This is because the drain and source of these cell transistors are formed symmetrically (target in the plane direction) across the channel formation region, and the higher applied potential functions as the drain and the lower applied as the source. The same applies to data reading when the nonvolatile memory is configured to be non-rewritable.

<Reading data (when nonvolatile memory is configured to be non-rewritable)>
On the other hand, when the nonvolatile memory is configured as a mask ROM, each voltage is applied when reading data, as shown in FIG. 6A, as in the case where the nonvolatile memory is configured as an EEPROM or the like. Is done. Then, for example, when the read target is the cell transistor 21, the control gate CG21 of the cell transistor 21 is set to 5V, the drain D21 is set to 1V, and the source S21 is set to 0V. Similarly, as shown in FIG. 6C, for example, when the reading target is the cell transistor 23, the control gate CG23 of the cell transistor 23 is set to 5V, the drain D23 is set to 1V, and the source S23 is set to 0V. The

  Accordingly, for example, in the example described with reference to FIG. 4B, even if the control gate voltage Vcg at the time of reading is applied to the cell transistor 21, the drain D21 and the bit line BL2 of the cell transistor 21 are not Since they are not electrically connected (within the broken line α shown in FIG. 6A), no current flows through the source line SL1. Therefore, in the above definition, data “1” is read from the cell transistor 21. On the other hand, in the cell transistor 23, the drain D23 of the cell transistor 23 and the bit line BL2 are electrically connected (within the broken line γ shown in FIG. 6C), so that the control gate voltage Vcg is controlled. When applied to the gate CG23, the cell transistor 23 shifts from the off state to the on state, and a current flows through the source line SL1. Therefore, in the previous definition, data “0” is read from the cell transistor 23.

  At the time of data reading, as shown in FIG. 6B, for example, when the reading target is the cell transistor 22 adjacent to the cell transistor 21, as in the case of the above-described EEPROM or the like. The voltage V2 and the voltage V1 are applied in reverse. Then, the control gate CG22 of the cell transistor 22 is set to 5V, the drain D22 is set to 0V, and the source S22 is set to 1V. Similarly, as shown in FIG. 6D, for example, when the reading target is the cell transistor 24, the control gate CG24 of the cell transistor 24 is set to 5V, the drain D24 is set to 0V, and the source S24 is set to 1V. .

  Accordingly, for example, in the example described with reference to FIG. 4B, the source transistors S22 and S24 and the source line SL2 are electrically connected to each other in the cell transistors 22 and 24 (FIG. 6 ( When the control gate voltage Vcg is applied to the control gates CG22 and CG24, the cell transistors 22 and 24 change from the off state to the on state. Thus, a current flows through the bit line BL1. Therefore, in the above definition, data “0” is read from the cell transistors 22 and 24.

  Whether the nonvolatile memory is writable or not, the data stored in the cell transistors 21 to 25 is read by sequentially detecting the presence or absence of current flowing through the bit line BL1 or the source line SL1. Are performed sequentially.

  Note that such voltage application to the bit line BL2 and source line SL2 and detection of current flowing through the bit line BL1 and source line SL1 are performed by, for example, a peripheral circuit according to a block diagram as shown in FIG.

  That is, as shown in FIG. 7, the nonvolatile memory according to the first embodiment has an X address decoder centered on a memory cell transistor matrix 100 configured by arranging the cell transistors 21 and the like arranged in a matrix. 110, a Y gate 120, a Y address decoder 130, an address buffer 140, a write circuit 150, a sense amplifier 160, an input / output buffer 170, and the like.

  An X address decoder 110 and a Y gate 120 are connected to the memory cell matrix 100. The X address decoder 110 is connected to the row of the memory cell matrix 100, that is, the word lines WL1 to WL5 and the like, and applies the control gate voltage Vcg (for example, 5 V) as described above to the selected word line WL1 and the like. It has a function.

  On the other hand, the Y gate 120 is connected to the column of the memory cell transistor matrix 100, that is, the bit lines BL1, BL2, etc. and the source lines SL1, SL2, etc., and is connected to the selected bit line BL2, source line SL2, etc. It has a function of applying the voltages V1 and V2 and detecting a current flowing through the selected bit line BL1, source line SL1, and the like.

  The Y address decoder 130 is connected to the Y gate 120 and has a function of outputting a column selection signal to the Y gate 120. The address buffer 140 is connected to the X address decoder 110 and the Y address decoder 130, and has a function of temporarily storing address information input from the outside and outputting address information thereto.

  The write circuit 150 is connected between the Y gate 120 and the input / output buffer 170 so that the input data inputted from the input / output buffer 170, that is, the write data can be written by the Y gate 120. The Y gate 120 has a function capable of generating a write signal.

  The sense amplifier 160 is also connected to both the Y gate 120 and the input / output buffer 170 so as to be “0” from the output data output from the Y gate 120, that is, the current value flowing at the time of data output. It has a function of determining “1”.

  The input / output buffer 170 has a function of temporarily storing input data input from the outside and output data output from the outside. The address buffer 140 and the input / output buffer 170 are controlled by a control signal output from a control device (not shown).

  As described above, in the nonvolatile memory according to the first embodiment, the drains D21 to D21 of the cell transistors 21 to 25 are connected via the contact holes CH1, CH3, and CH5 by the bit line BL1 formed in the first wiring layer LY2. D25 is connected in common, and the bit line BL2 arranged so as to be connectable to the bit line BL1 via via holes VH1, VH3, and VH5 is formed in the second wiring layer LY4. Further, the sources S21 to S25 of the cell transistors 21 to 25 are connected in common via the contact holes CH2, CH4 and CH6 by the source line SL1 formed in the first wiring layer LY2, and the via hole VH2 is connected to the source line SL1. , VH4, VH6 so as to be connectable via the source line SL2 is formed in the second wiring layer LY4.

  Thereby, in the design process of the nonvolatile memory, when the data stored in the cell transistors 21 to 25 is configured to be electrically rewritable, all the via holes VH1 to VH6 may be formed. When the data stored by the cell transistors 21 to 25 is configured so as not to be electrically rewritable, for example, vias corresponding to the other cell transistors 22 to 25 except for the via hole VH1 corresponding to the cell transistor 21 to which data is written. Since all the holes VH2 to VH6 may be formed, for example, the difference between the circuit such as the EEPROM and the circuit of the mask ROM can be absorbed by the difference in the presence or absence of the via holes VH1 to VH6. Therefore, since these circuit designs are facilitated, work efficiency in the design process can be improved.

  In the manufacturing process of the nonvolatile memory, when the data stored in the cell transistors 21 to 25 is configured to be electrically rewritable, a photomask capable of forming all the via holes VH1 to VH6 should be prepared. In addition, when the data stored in the cell transistors 21 to 25 is configured so as not to be electrically rewritable, for example, the other cell transistors 22 to 22 except for the via hole VH1 corresponding to the cell transistor 21 to which data is written. Since it is sufficient to prepare a photomask capable of forming all the via holes VH2 to VH6 corresponding to 25, for example, the formation of the via holes VH1 to VH6 can be controlled by the difference between the manufacture of the EEPROM or the like and the manufacture of the mask ROM. Absorption can be achieved depending on the type of photomask. Therefore, since many of these semiconductor manufacturing processes can be shared, work efficiency in the manufacturing process can be improved.

  Further, in the nonvolatile memory, since the total number of wiring layers is reduced by forming the bit line BL2 and the source line SL2 in the same second wiring layer LY4, it is possible to reduce the manufacturing process and the manufacturing cost associated therewith. Become. Further, the thickness (height) of the nonvolatile memory can be reduced (decreased) by reducing the total number of wiring layers. In the first embodiment, the bit line BL2 and the source line SL2 may be formed in the same second wiring layer LY4, but the bit line BL2 and the source line SL2 may be formed in different wiring layers.

  Further, since the cell transistors 21 to 25 have a MOS structure provided with the floating gates FG21 to FG25, the data stored by the cell transistors 21 to 25 is configured to be either electrically rewritable or not electrically rewritable. However, for example, while a step of neutralizing the floating gates FG21 to FG25 and a step of inspecting circuit functions other than the cell transistors 21 to 25 are necessary, the data stored by the cell transistors 21 to 25 is electrically stored. In the case of a non-rewritable configuration, there is no need for an inspection process relating to data writing or erasing such as a process of inspecting the data rewriting function.

  That is, as shown in FIG. 8A, the data stored in the cell transistors 21 to 25 can be electrically rewritten, that is, when the nonvolatile memory is configured as an EEPROM or the like, the cell transistors 21 to 25 are When the manufacturing process of the formed wafer is completed, first, in the floating gate neutralization process in step S101, the floating gates FG21 to FG25 are irradiated with ultraviolet rays so that the number of electrons and donors in the floating gates FG21 to FG25 is the same, that is, neutralized. To do.

  Next, in a circuit function verification process other than the memory in step S103, an X address decoder 110, a Y gate 120, a Y address decoder 130, an address buffer 140, other than the memory cell transistor matrix 100 composed of the cell transistors 21 to 25, etc. It is verified that the functions of the write circuit 150, sense amplifier 160, input / output buffer 170, etc. are normal.

  Next, in the memory rewrite performance evaluation process in step S105, for example, predetermined test data is written in the cell transistors 21 to 25 and the like, and then read to verify and evaluate the coincidence of both data, and then the data write process in step S107. Thus, data stored in advance at the time of shipment from the factory is written in the nonvolatile memory (EPROM or the like), and charges are held in the floating gates FG21 to 25 such as the cell transistors 21 to 25 and the like to be written. This is inspected by the charge retention test process in step S109.

  Since each process from step S101 to step S109 is performed in a wear state, the chip is divided into chips by the chip cutting process at the next step S111, and then each chip is packaged by a resin mold or the like at the packaging process at step S113. Note that a chip that has failed in the inspection process before the chip cutting process is not packaged.

  The charges held in the floating gates FG21 to 25, etc. by the data writing process of the previous step S107 have been reduced by the charge holding test of step S109. Therefore, at the time of shipment from the factory, the data rewriting process of the next step S115. The data stored in advance is written again in the nonvolatile memory (EPROM or the like), and the coincidence between the written data and the read data is verified by the data content verification step in step S117. Thereby, the inspection of the nonvolatile memory is completed.

  On the other hand, as shown in FIG. 8B, when the data stored by the cell transistors 21 to 25 cannot be electrically rewritten, that is, when the nonvolatile memory is configured as a mask ROM, the above-described step S101 is performed. ˜S117, the nonvolatile memory is inspected in the steps except steps S105 to S109 and S115.

  That is, after verifying that each function by the X address decoder 110 and the like other than the memory cell transistor matrix 100 including the cell transistors 21 to 25 is normal by the circuit function verification process other than the memory in step S103, Without going through the memory rewrite performance evaluation process in step S105, the data writing process in step S107, and the charge retention test process in step S109, the process proceeds to the chip cut process in step S111. Further, after the packaging process in step S113, it is verified that the data read out in the data content verification process in step S117 matches the data to be written without going through the data rewriting process in step S115.

  This is because, when the nonvolatile memory is configured as a mask ROM, as described above, data is written by a photomask that determines the presence or absence of via holes VH1 to VH6, that is, the formation of via holes VH1 to VH6. Then, the processes of steps S105 to S109 and S115, which are processes related to data writing, are skipped, and the inspection of the nonvolatile memory is completed.

  This makes it impossible to electrically rewrite the data stored by the cell transistors 21 to 25 based on the inspection process in the case where the data stored by the cell transistors 21 to 25 is configured to be electrically rewritable. Since it is sufficient to skip the inspection process (S105 to S109, S115) related to data writing that is not necessary in the case of configuration, for example, the difference between the inspection of the EEPROM or the like and the inspection of the mask ROM Can be absorbed. Therefore, since the inspection line can be made common, work efficiency in the inspection process can be improved from labor saving in the preparation of the inspection process.

  Note that the data content verification process in step S117 shown in FIG. 8B may be placed before the chip cutting process in step S111, for example. As a result, only the chip that has passed the data content verification process is packaged by the packaging process of step S113, so that the fail chip can be prevented from being packaged.

[Second Embodiment]
The nonvolatile memory according to the second embodiment is one in which the nonvolatile semiconductor memory device of the present invention is applied when the source line is composed of three or more layers. Here, for example, in addition to the source lines SL1 and SL2, a case where the source line SL3 arranged orthogonal to these is formed in the buyer formation layer LY3 will be described as an example. For this reason, components substantially the same as those of the nonvolatile memory according to the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIGS. 9A and 10A, the non-volatile memory according to the second embodiment is similar to the non-volatile memory of the first embodiment described above, and the source lines SL1, A source line SL3 arranged orthogonal to these is provided for SL2. Via holes VH2, VH4, and VH6 may be interposed between the source line SL3 and the source line SL1, and via holes VH2 ′, VH4 ′, and VH6 ′ may be interposed between the source line SL3 and the source line SL2. As such, they are formed. In FIG. 10A, a planar layout corresponding to FIG. 9A is shown.

  That is, two source lines SL1 connected to the sources S21 and S22 of the cell transistors 21 and 22 via the contact hole CH2 and the source line SL2 are connected in series via the source line SL3. Source lines SL1 to SL3 and via holes VH2 and VH2 ′ are arranged so as to connect via holes VH2 and VH2 ′.

  Similarly, 2 connected in series with the source line SL3 interposed between the source line SL1 and the source line SL2 connected to the sources S23, 24 of the cell transistors 23, 24 via the contact hole CH4. The source line SL3 is interposed between the source line SL1 and the source line SL2 connected to the source S25 of the cell transistor 25 through the contact hole CH6 so that the two via holes VH4 and VH4 ′ can be connected. The source lines SL1 to SL3 and the via holes VH4, VH4 ′, VH6, and VH6 ′ are arranged so that the two via holes VH6 and VH6 ′ connected in series can be connected.

  When the nonvolatile memory according to the second embodiment is configured as described above, the data stored by the cell transistors 21 to 25 is configured to be electrically rewritable, that is, the nonvolatile memory is configured as an EEPROM or the like. In this case, via holes VH1, VH3, and VH5 that connect the bit line BL1 and the bit line BL2, and via holes VH2, VH2 ′, VH4, VH4 ′, and VH6 that connect the source line SL1 and the source line SL2 are used. VH6 ′ is formed corresponding to each contact hole CH1 to CH6 connected to cell transistors 21 to 25.

  On the other hand, when the data stored by the cell transistors 21 to 25 is configured to be electrically unrewritable, that is, when the nonvolatile memory is configured as a mask ROM, for example, FIG. 9B and FIG. As shown in FIG. 10B, for example, without forming the via hole VH1 corresponding to the contact hole CH1 connected to the drain D21 of the cell transistor 21 to be written (broken line α shown in FIG. 9B) And the via hole VH4 corresponding to the contact hole CH4 connected to the source S24 of the cell transistor 24 to be written (inside the broken line δ shown in FIG. 9B), other vias are formed. Holes VH2, VH2 ′, VH3, VH4 ′, VH5, VH6 and VH6 ′ are formed. In this case, a plan layout diagram corresponding to FIG. 9B is shown in FIG.

  As a result, when the nonvolatile memory is configured as an EEPROM or the like, or when configured as a mask ROM, data is read as follows. As in the nonvolatile memory according to the first embodiment described above, when the nonvolatile memory is configured as an EEPROM or the like, data is written by hot electrons injected into the floating gate FG21 or the like of the cell transistor 21 or the like. When the nonvolatile memory is configured as a mask ROM, the via hole VH1 corresponding to the contact hole CH1 connected to the cell transistor 21 to be written, etc., is not formed. Is done.

  In both cases where the nonvolatile memory is writable or impossible, the floating gate of each cell transistor has a control gate voltage (for example, 5 V) applied at the time of reading in the floating gate neutralization process during the manufacturing process. ) (Hereinafter referred to as “Vt = L”).

<Reading data (when nonvolatile memory is configured to be rewritable)>
When the nonvolatile memory is configured as an EEPROM or the like, when data is read, as shown in FIG. 11A, for example, when the read target is the cell transistor 21, the control gate CG21 of the cell transistor 21 is read. 5V is applied as the control gate voltage Vcg to the word line WL1 to which is connected, and the other word lines WL2 to WL5 are set to 0V. Further, a voltage V1, for example, 1V is applied to the bit line BL2, and a voltage V2, for example, 0V, lower than the voltage V1 of the bit line BL2 is applied to the source line SL1. Then, the control gate CG21 of the cell transistor 21 is set to 5V, the drain D21 is set to 1V, and the source S21 is set to 0V. Note that the bit line BL1 and the source lines SL2 and SL3 are set to an open state (OPEN).

  Thus, when the threshold voltage Vt of the cell transistor 21 is set to a voltage Vt = H higher than 5 V of the control gate voltage Vcg at the time of reading, even if the control gate voltage Vcg is applied to the control gate CG21, the cell transistor 21 is not turned on and no current flows through the source line SL1. For this reason, if the definition is the same as in the first embodiment, data “1” is read from the cell transistor 21.

  At the time of data reading, as shown in FIG. 11B, for example, when the reading target is the cell transistor 22 adjacent to the cell transistor 21, the voltages V2 and V1 are applied with the potentials reversed. That is, a voltage V1, for example, 0V is applied to the bit line BL1, and a voltage V2, for example, 1V, higher than the voltage V1 of the bit line BL1 is applied to the source line SL2. Further, 5V is applied as the control gate voltage Vcg to the word line WL2 to which the control gate CG22 of the cell transistor 22 is connected, and the other word lines WL1, WL3 to WL5 are set to 0V. Then, the control gate CG22 of the cell transistor 22 is set to 5V, the drain D22 is set to 0V, and the source S22 is set to 1V. Note that the bit line BL1 and the source lines SL2 and SL3 are set to an open state (OPEN).

  Thereby, when the threshold voltage Vt of the cell transistor 22 is set to a voltage Vt = L lower than 5 V of the control gate voltage Vcg at the time of reading, the cell transistor is applied when the control gate voltage Vcg is applied to the control gate CG22. 22 shifts from the off state to the on state, and a current flows through the bit line BL1. Therefore, in the above definition, data “0” is read from these cell transistors 22 and 24.

<Reading data (when nonvolatile memory is configured to be non-rewritable)>
On the other hand, when the nonvolatile memory is configured as a mask ROM, each voltage is applied when reading data, as shown in FIG. Is done. Then, for example, when the read target is the cell transistor 21, the control gate CG21 of the cell transistor 21 is set to 5V, the drain D21 is set to 1V, and the source S21 is set to 0V.

  Accordingly, in the example shown in FIGS. 9B and 10B, even if the control gate voltage Vcg at the time of reading is applied to the cell transistor 21, the drain D21 of the cell transistor 21 and the bit line BL2 Are not electrically connected (within the broken line α shown in FIG. 9A), no current flows through the source line SL1. Therefore, in the above definition, data “1” is read from the cell transistor 21.

  At the time of data reading, as shown in FIG. 12B, for example, when the reading target is the cell transistor 22 adjacent to the cell transistor 21, as in the case of the above-described EEPROM or the like. The voltage V2 and the voltage V1 are applied in reverse. Then, the control gate CG22 of the cell transistor 22 is set to 5V, the drain D22 is set to 0V, and the source S22 is set to 1V. Similarly, for example, when the reading target is the cell transistor 24, the control gate CG24 of the cell transistor 24 is set to 5V, the drain D24 is set to 0V, and the source S24 is set to 1V.

  Accordingly, in the example shown in FIG. 9B or FIG. 10B, the source S22 and the source line SL2 are electrically connected to the cell transistor 22 (the broken line shown in FIG. 12B). In β), when the control gate voltage Vcg is applied to the control gate CG22, the cell transistor 22 shifts from the off state to the on state, and a current flows through the bit line BL1. Therefore, in the above definition, data “0” is read from the cell transistor 22. On the other hand, in the cell transistor 24, since the source S24 and the source line SL2 are not electrically connected (within the broken line δ shown in FIG. 12B), no current flows through the bit line BL1. Therefore, in the previous definition, data “1” is read from the cell transistor 24.

  Even when the source line has a three-layer structure as described above, it is stored by the cell transistors 21 to 25 in the design process of the nonvolatile memory as in the nonvolatile memory of the first embodiment described above. When the data to be stored is electrically rewritable, all the via holes VH1 to VH6, VH2 ′, VH4 ′, and VH6 ′ are formed, and the data stored by the cell transistors 21 to 25 is electrically In the case where the rewritable configuration is impossible, for example, without forming the via hole VH4 corresponding to the cell transistor 24 to be written, the other via holes VH1, VH2, VH2 ', VH3, VH4', VH5 Since all of VH6 and VH6 ′ may be formed, for example, a circuit such as an EEPROM and a circuit of a mask ROM The difference of, via holes VH1~VH6, VH2 ', VH4', can be absorbed by the difference in the presence or absence of VH6 '. Therefore, since these circuit designs are facilitated, work efficiency in the design process can be improved.

  Similarly, in the manufacturing process of the nonvolatile memory, when the data stored in the cell transistors 21 to 25 is configured to be electrically rewritable, a photomask capable of forming all the via holes VH1 to VH6. In addition, when the data stored in the cell transistors 21 to 25 is configured so as not to be electrically rewritable, for example, the via hole VH4 corresponding to the cell transistor 24 to be written is not formed. Since it is sufficient to prepare a photomask capable of forming all other via holes VH1, VH2, VH2 ′, VH3, VH4 ′, VH5, VH6, and VH6 ′, for example, manufacturing of an EEPROM or the like and manufacturing of a mask ROM The difference in the formation of via holes VH1 to VH6, VH2 ′, VH4 ′, and VH6 ′ It can be absorbed by the type of controllable photomask. Therefore, since many of these semiconductor manufacturing processes can be shared, work efficiency in the manufacturing process can be improved.

  Further, in the manufacturing process of the nonvolatile memory as well, since the cell transistors 21 to 25 have the MOS structure including the floating gates FG21 to FG25, the data stored by the cell transistors 21 to 25 is the same as in the first embodiment. However, it is necessary to have a step of neutralizing the floating gates FG21 to FG25, a step of inspecting circuit functions other than the cell transistors 21 to 25, etc. On the other hand, in the case where the data stored by the cell transistors 21 to 25 is configured so as not to be electrically rewritable, there is no need for an inspection process relating to data writing or erasing such as a process of inspecting the data rewriting function. Therefore, since the inspection line can be made common, work efficiency in the inspection process can be improved from labor saving in the preparation of the inspection process.

  In the above-described example, when the nonvolatile memory is configured as a mask ROM, data writing is realized depending on whether or not the via holes VH2, VH4, and VH6 are formed, but the via hole VH2 ′ connected to these is provided. , VH4 ′, VH6 ′ may be used to write data, and in this case, the same operation and effect as described above can be obtained.

  In the above-described example, the example in which the nonvolatile semiconductor memory device of the present invention is applied when the source line is composed of three or more layers has been described. However, the bit line is composed of three or more layers. Even in the case, the bit lines BL1 and BL2 formed in parallel to the bit lines BL1 and BL2 formed in parallel to the nonvolatile memory of the first embodiment are provided with the bit lines BL3 and the bit lines BL3 and the bit lines. Via holes VH1, VH3 and VH5 are interposed between the line BL1 and via holes VH1 ′, VH3 ′ and VH5 ′ can be interposed between the bit line BL3 and the bit line BL2. Thus, the same operations and effects as described above can be obtained.

[Third Embodiment]
The nonvolatile memory according to the third embodiment is one in which the nonvolatile semiconductor memory device of the present invention is applied when a common source line is provided for each set of two adjacent cell transistors. Here, for example, the source lines SL1a and SL1b and the source line SL1c that are provided in common for each set of two adjacent cell transistors 21 and 22 and each set of cell transistors 23 and 24 are connected to the bit lines BL1 and BL2. A case where the wiring layer is arranged in another wiring layer orthogonal to the source line SL2 will be described as an example. For this reason, components substantially the same as those of the nonvolatile memory according to the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 13, the nonvolatile memory according to the third embodiment is similar to the nonvolatile memory of the first embodiment described above, with respect to the bit lines BL1, BL2 and the source line SL2 formed in parallel. Source lines SL1a to SL1c arranged orthogonal to these (in parallel with the word lines WL1 to WL6) are provided. The source line SL1a is commonly connected to the source S21 of the cell transistor 21 and the source S22 of the cell transistor 22, and the source line SL1b is commonly connected to the source S23 of the cell transistor 23 and the source S24 of the cell transistor 24. . The source line SL1c is commonly connected to the source S25 of the cell transistor 25 and the source of a cell transistor (not shown) adjacent thereto.

  In addition, via holes VH1, VH3, and VH5 are interposed between the bit line BL1 and the bit line BL2 as in the nonvolatile memory of the first embodiment described above, and the bit line BL2 and the source line SL2 Via holes VH1 ′, VH3 ′, and VH5 ′ are interposed between them.

  That is, two via holes VH1, which are connected in series with the bit line BL2 interposed between the bit line BL1 connected to the drain D21 of the cell transistor 21 via the contact hole CH1 and the source line SL2. Bit lines BL1 and BL2, source line SL2, and via holes VH1 and VH1 ′ are arranged to connect VH1 ′.

  Similarly, the bit line BL1 connected to the drains D22 and D23 of the cell transistors 22 and 23 via the contact hole CH3 and the source line SL2 are connected in series with the bit line BL2 interposed therebetween. Between the bit line BL1 connected to the drains D24 and D25 of the cell transistors 24 and 25 via the contact hole CH5 and the source line SL2 so that the two via holes VH3 and VH3 ′ can be connected. Bit lines BL1, BL2, source line SL2, and via holes VH3, VH3 ′, VH5, VH5 ′ are arranged so that two via holes VH5, VH5 ′ connected in series via line BL2 can be connected. Has been.

  When the nonvolatile memory according to the third embodiment is configured as described above, the data stored in the cell transistors 21 to 25 is configured to be electrically rewritable, that is, the nonvolatile memory is configured as an EEPROM or the like. In this case, via holes VH1, VH3, and VH5 that connect the bit line BL1 and the bit line BL2 and via holes VH1 ′, VH3 ′, and VH5 ′ that connect the bit line BL2 and the source line SL2 are connected to the cell transistors. It is formed corresponding to each contact hole CH1, CH3, CH5 connected to 21-25.

  On the other hand, when the data stored by the cell transistors 21 to 25 is configured to be electrically unrewritable, that is, when the nonvolatile memory is configured as a mask ROM, for example, as shown in FIG. For example, without forming the via holes VH1 and VH1 ′ corresponding to the contact hole CH1 connected to the drain D21 of the cell transistor 21 to be written (within the broken line α shown in FIG. 14A), Via holes VH3, VH3 ', VH5, VH5' are formed.

  As a result, when the nonvolatile memory is configured as an EEPROM or the like, or when configured as a mask ROM, data is read as follows. As in the nonvolatile memory according to the first embodiment described above, when the nonvolatile memory is configured as an EEPROM or the like, data is written by hot electrons injected into the floating gate FG21 or the like of the cell transistor 21 or the like. When the nonvolatile memory is configured as a mask ROM, the via hole VH1 corresponding to the contact hole CH1 connected to the cell transistor 21 to be written, etc., is not formed. Is done.

  In both cases where the nonvolatile memory is writable or impossible, the floating gate of each cell transistor has a control gate voltage (for example, 5 V) applied at the time of reading in the floating gate neutralization process during the manufacturing process. ) (Hereinafter referred to as “Vt = L”).

<Reading data (when nonvolatile memory is configured to be rewritable)>
When the nonvolatile memory is configured as an EEPROM or the like, when data is read, as shown in FIG. 13A, for example, when the read target is the cell transistor 21, the control gate CG21 of the cell transistor 21 is read. 5V is applied as the control gate voltage Vcg to the word line WL1 to which is connected, and the other word lines WL2 to WL5 are set to 0V. Further, a voltage V1, for example, 1V is applied to the bit line BL2, and a voltage V2, for example, 0V, lower than the voltage V1 of the bit line BL2 is applied to the source line SL1a. Then, the control gate CG21 of the cell transistor 21 is set to 5V, the drain D21 is set to 1V, and the source S21 is set to 0V. Note that the bit line BL1 and the source line SL2 are opened (OPEN), and the other source lines SL1b and SL1c are set to 0V.

  Thus, when the threshold voltage Vt of the cell transistor 21 is set to a voltage Vt = H higher than 5 V of the control gate voltage Vcg at the time of reading, even if the control gate voltage Vcg is applied to the control gate CG21, the cell transistor 21 is not turned on and no current flows through the source line SL1. For this reason, if the definition is the same as in the first embodiment, data “1” is read from the cell transistor 21.

  At the time of data reading, as shown in FIG. 13B, for example, when the reading target is the cell transistor 22 adjacent to the cell transistor 21, the voltage V1, for example, 1V is applied to the source line SL2, and the source A voltage V2 lower than the voltage V1 of the source line SL2, for example, 0 V, is applied to the line SL1a. Further, 5V is applied as the control gate voltage Vcg to the word line WL2 to which the control gate CG22 of the cell transistor 22 is connected, and the other word lines WL1, WL3 to WL5 are set to 0V. Then, the control gate CG22 of the cell transistor 22 is set to 5V, the drain D22 is set to 1V, and the source S22 is set to 0V. The bit line BL1 and the source lines SL2 and SL3 are set in an open state (OPEN), and the other source lines SL1b and SL1c are set to 0V.

  Thereby, when the threshold voltage Vt of the cell transistor 22 is set to a voltage Vt = L lower than 5 V of the control gate voltage Vcg at the time of reading, the cell transistor is applied when the control gate voltage Vcg is applied to the control gate CG22. 22 shifts from the off state to the on state, and a current flows through the source line SL1a. Therefore, in the above definition, data “0” is read from these cell transistors 22 and 24.

<Reading data (when nonvolatile memory is configured to be non-rewritable)>
On the other hand, when the nonvolatile memory is configured as a mask ROM, each voltage is applied when reading data, as shown in FIG. Is done. Then, for example, when the read target is the cell transistor 21, the control gate CG21 of the cell transistor 21 is set to 5V, the drain D21 is set to 1V, and the source S21 is set to 0V.

  Accordingly, in the example shown in FIG. 14A, even when the control gate voltage Vcg at the time of reading is applied, the drain D21 of the cell transistor 21 and the bit line BL2 are not electrically connected (FIG. 14). No current flows through the source line SL1a. Therefore, in the above definition, data “1” is read from the cell transistor 21.

  At the time of data reading, as shown in FIG. 14B, for example, when the reading target is the cell transistor 22 adjacent to the cell transistor 21, as in the case of the above-described EEPROM or the like. A voltage V1, for example, 1V is applied to the source line SL2, and a voltage V2, for example, 0V, lower than the voltage V1 of the source line SL2 is applied to the source line SL1a. Further, 5V is applied as the control gate voltage Vcg to the word line WL2 to which the control gate CG22 of the cell transistor 22 is connected, and the other word lines WL1, WL3 to WL5 are set to 0V. Then, the control gate CG22 of the cell transistor 22 is set to 5V, the drain D22 is set to 1V, and the source S22 is set to 0V.

  Accordingly, in the example shown in FIG. 14B, the drain D22 and the source line SL2 are electrically connected (within the broken line β shown in FIG. 14B), so that the control gate voltage Vcg is equal to the control gate CG22. Is applied to the cell transistor 22, the cell transistor 22 shifts from the off state to the on state, and a current flows through the bit line BL1. Therefore, in the above definition, data “0” is read from the cell transistor 22.

  Even in the case where a common source line is provided for each set of two adjacent cell transistors in this way, the design process of the nonvolatile memory is similar to the nonvolatile memory of the first embodiment described above. In the case where the data stored in the cell transistors 21 to 25 is configured to be electrically rewritable, all of the via holes VH1, VH1 ′, VH3, VH3 ′, VH5, VH5 ′ may be formed. Further, when the data stored by the cell transistors 21 to 25 is configured to be electrically unrewritable, for example, the via holes VH1 and VH1 ′ corresponding to the cell transistor 21 to be written are not formed, Since all the via holes VH3, VH3 ′, VH5, VH5 ′ may be formed, for example, an EEPROM or the like The difference between the circuit of the road and mask ROM, via holes VH1, VH1 ', VH3, VH3', can be absorbed by the difference in the presence or absence of VH5, VH5 '. Therefore, since these circuit designs are facilitated, work efficiency in the design process can be improved.

  Similarly, in the manufacturing process of the nonvolatile memory, when the data stored by the cell transistors 21 to 25 is configured to be electrically rewritable, via holes VH1, VH1 ′, VH3, VH3 ′, A photomask capable of forming all of VH5 and VH5 ′ may be prepared, and in the case where the data stored in the cell transistors 21 to 25 is not electrically rewritable, for example, the cell transistor 21 to be written is written. It is sufficient to prepare a photomask that can form all other via holes VH3, VH3 ', VH5, and VH5' without forming via holes VH1 and VH1 'corresponding to the above. The difference from the manufacture of the mask ROM is that the via holes VH1, VH1 ′, VH3, VH3 ′, H5, can be absorbed by the type of controllable photomask formation VH5 '. Therefore, since many of these semiconductor manufacturing processes can be shared, work efficiency in the manufacturing process can be improved.

  Further, in the manufacturing process of the nonvolatile memory as well, since the cell transistors 21 to 25 have the MOS structure including the floating gates FG21 to FG25, the data stored by the cell transistors 21 to 25 is the same as in the first embodiment. However, it is necessary to have a step of neutralizing the floating gates FG21 to FG25, a step of inspecting circuit functions other than the cell transistors 21 to 25, etc. On the other hand, in the case where the data stored by the cell transistors 21 to 25 is configured so as not to be electrically rewritable, there is no need for an inspection process relating to data writing or erasing such as a process of inspecting the data rewriting function. Therefore, since the inspection line can be made common, work efficiency in the inspection process can be improved from labor saving in the preparation of the inspection process.

[Reference example]
In the nonvolatile memories according to the first to third embodiments described so far, via holes VH1, VH3, VH5 that can connect the bit line BL1 (first main wiring) and the bit line BL2 (first sub wiring), The via hole VH2, VH4, VH6 that can connect the source line SL1 (second main wiring) and the source line SL2 (second sub wiring) are all provided to form an EEPROM or the like without providing a part thereof. Although a mask ROM is configured, here, as a reference example, without providing the bit line BL2 (first sub-wiring), the source line SL2 (second sub-wiring), the via holes VH1 to VH6, the EEPROM and the mask A configuration of a nonvolatile memory in which any of the ROMs can be configured will be described.

  As shown in FIG. 15, the nonvolatile memory according to the reference example includes cell transistors 21 to 23 as cell transistors including floating gates, as in the above-described embodiments. 23, the drain is connected to the bit line BL1 and the source is connected to the source line SL1 via contact holes. Further, word lines WL1 to WL3 are individually connected to these control gates.

  For example, in the case of the cell transistor 21, the drain D21 is connected to the bit line BL1 via the contact hole CH1, the source S21 is connected to the source line SL1 via the contact hole CH2, and the control gate CG21 is connected to the word line WL1. Similarly, in the cell transistor 22, the drain D22 is connected to the bit line BL1 via the contact hole CH3, the source S22 is connected to the source line SL1 via the contact hole CH4, and the control gate CG22 is connected to the word line WL2.

  Further, the bit line BL1 and the source line SL1 are aluminum wirings made of, for example, aluminum, and both are formed in the first wiring layer LY2. Both wirings may be formed in the same first wiring layer LY2 as described above, or may be formed in different wiring layers.

  By configuring the nonvolatile memory in this way, data writing is performed when the nonvolatile memory is configured as an EEPROM or the like, similar to the nonvolatile memory according to the first to third embodiments described above. This is done by injecting hot electrons into the floating gate FG21 such as the cell transistor 21.

  In the case where the nonvolatile memory is configured as a mask ROM, data is written by not forming the contact hole CH1 or the like connected to the cell transistor 21 or the like to be written. This is different from, for example, the nonvolatile memories of the first to third embodiments described above in which the via hole VH1 corresponding to the contact hole CH1 connected to the drain D21 of the cell transistor 21 to be written is not formed.

  In both cases where the nonvolatile memory is writable or impossible, the floating gate of each cell transistor has a control gate voltage (for example, 5 V) applied at the time of reading in the floating gate neutralization process during the manufacturing process. ) (Hereinafter referred to as “Vt = L”). Data is read as follows.

<Reading data (when nonvolatile memory is configured to be rewritable)>
When the nonvolatile memory is configured as an EEPROM or the like, when data is read, as shown in FIG. 15A, for example, when the read target is the cell transistor 21, the control gate CG21 of the cell transistor 21 is read. 5V is applied as the control gate voltage Vcg to the word line WL1 to which is connected, and the other word lines WL2 and WL3 are set to 0V. Further, a voltage V1, for example, 1V is applied to the bit line BL1, and a voltage V2, for example, 0V, lower than the voltage V1 of the bit line BL1 is applied to the source line SL1. Then, the control gate CG21 of the cell transistor 21 is set to 5V, the drain D21 is set to 1V, and the source S21 is set to 0V.

  Thus, when the threshold voltage Vt of the cell transistor 21 is set to a voltage Vt = H higher than 5 V of the control gate voltage Vcg at the time of reading, even if the control gate voltage Vcg is applied to the control gate CG21, the cell transistor 21 is not turned on and no current flows through the source line SL1. For this reason, if the definition is the same as in the first embodiment, data “1” is read from the cell transistor 21.

  At the time of data reading, as shown in FIG. 15B, for example, when the reading target is the cell transistor 22 adjacent to the cell transistor 21, the voltage V1, for example, 1V is applied to the bit line BL1, and the source A voltage V2 lower than the voltage V1 of the bit line BL1, for example, 0 V, is applied to the line SL1. Then, the control gate CG22 of the cell transistor 22 is set to 5V, the drain D22 is set to 1V, and the source S22 is set to 0V.

  Thereby, when the threshold voltage Vt of the cell transistor 22 is set to a voltage Vt = L lower than 5 V of the control gate voltage Vcg at the time of reading, the cell transistor is applied when the control gate voltage Vcg is applied to the control gate CG22. 22 shifts from the off state to the on state, and a current flows through the source line SL1. Therefore, in the above definition, data “0” is read from these cell transistors 22 and 24.

<Reading data (when nonvolatile memory is configured to be non-rewritable)>
On the other hand, when the nonvolatile memory is configured as a mask ROM, each voltage is applied when reading data, as shown in FIG. Is done. Then, for example, when the read target is the cell transistor 21, the control gate CG21 of the cell transistor 21 is set to 5V, the drain D21 is set to 1V, and the source S21 is set to 0V.

  Accordingly, in the example shown in FIG. 16A, even when the control gate voltage Vcg at the time of reading is applied, the contact hole CH1 is not formed between the drain D21 of the cell transistor 21 and the bit line BL1. Since they are not electrically connected (within the broken line α shown in FIG. 16A), no current flows through the source line SL1. Therefore, in the above definition, data “1” is read from the cell transistor 21.

  At the time of data reading, as shown in FIG. 16B, for example, when the reading target is the cell transistor 22 adjacent to the cell transistor 21, it is the same as the case where it is configured as the above-described EEPROM or the like. A voltage V1, for example, 1V is applied to the bit line BL1, and a voltage V2, for example, 0V, lower than the voltage V1 of the bit line BL1 is applied to the source line SL1. Then, the control gate CG22 of the cell transistor 22 is set to 5V, the drain D22 is set to 1V, and the source S22 is set to 0V.

  Accordingly, in the example shown in FIG. 16B, the contact hole CH3 is formed between the drain D22 and the source line SL2, and is electrically connected (the broken line β shown in FIG. 16B). ), When the control gate voltage Vcg is applied to the control gate CG22, the cell transistor 22 shifts from the off state to the on state, and a current flows through the source line SL1. Therefore, in the above definition, data “0” is read from the cell transistor 22.

  Even when the bit line BL2, the source line SL2, and the via holes VH1 to VH6 are not provided as described above, in the design process of the nonvolatile memory, the cell transistor 21 is provided as in the nonvolatile memory according to the first embodiment. In the case where the data stored by ˜25 is configured to be electrically rewritable, all of the contact holes CH1 to CH6 may be formed, and the data stored by the cell transistors 21 to 25 cannot be electrically rewritable. For example, all the contact holes CH2 to CH6 may be formed without forming the contact hole CH1 corresponding to the cell transistor 21 to be written, for example. The difference between the mask ROM circuit and the contact holes CH1 to C It can be absorbed by the difference of 6 presence or absence of. Therefore, since these circuit designs are facilitated, work efficiency in the design process can be improved.

  Similarly, in the manufacturing process of the nonvolatile memory, when the data stored by the cell transistors 21 to 25 is configured to be electrically rewritable, a photomask capable of forming all of the contact holes CH1 to CH6. In addition, when the data stored in the cell transistors 21 to 25 is configured so as not to be electrically rewritable, for example, without forming the contact hole CH1 corresponding to the cell transistor 21 to be written. Since it is sufficient to prepare a photomask capable of forming all other contact holes CH2 to CH6, for example, the formation of the contact holes CH1 to CH6 can be controlled by the difference between the manufacture of the EEPROM or the like and the manufacture of the mask ROM. Absorption can be achieved depending on the type of photomask. Therefore, since many of these semiconductor manufacturing processes can be shared, work efficiency in the manufacturing process can be improved.

  Further, in the manufacturing process of the nonvolatile memory as well, since the cell transistors 21 to 25 have the MOS structure including the floating gates FG21 to FG25, the data stored by the cell transistors 21 to 25 is the same as in the first embodiment. However, it is necessary to have a step of neutralizing the floating gates FG21 to FG25, a step of inspecting circuit functions other than the cell transistors 21 to 25, etc. On the other hand, in the case where the data stored by the cell transistors 21 to 25 is configured so as not to be electrically rewritable, there is no need for an inspection process relating to data writing or erasing such as a process of inspecting the data rewriting function. Therefore, since the inspection line can be made common, work efficiency in the inspection process can be improved from labor saving in the preparation of the inspection process.

  Next, an embodiment of a method for manufacturing a nonvolatile semiconductor memory device of the present invention will be described with reference to each drawing. Here, a process example for manufacturing the above-described nonvolatile memory according to the first embodiment will be described as manufacturing methods 1 and 2. 17 and 18 are schematic cross-sectional views of the cell transistor manufactured by the manufacturing method 1 according to this embodiment. 19 and 20 are schematic cross-sectional views of the cell transistor manufactured by the manufacturing method 2 according to this embodiment.

<Manufacturing method 1>
In the manufacturing method 1 according to the present embodiment, a cell transistor of the nonvolatile memory, its peripheral transistor, and the like are formed from polycrystalline silicon with a two-layer structure (two-layer poly structure). Here, the step of forming the cell transistor 21 is exemplified, and as the peripheral transistor, for example, a step of forming a low voltage transistor for processing a logic signal or a high voltage transistor for processing an analog signal is illustrated. explain.

  First, as shown in FIG. 17A, a gate oxide film 32 is formed on the surface of the silicon substrate 20 by the thermal oxidation method in the first oxide film forming step, and further, the element is formed by the LOCOS method in the element isolation region forming step. An inter-space separation region 31 is formed.

  Next, as shown in FIG. 17B, a first polycrystalline silicon layer 33 is formed on the element isolation region 31 and the gate oxide film 32 by the first polycrystalline silicon layer forming step, and an interlayer insulating film forming step is performed. Thus, an interlayer insulating film 34 is formed thereon. Then, a region in which the cell transistor 21 is formed is covered with a photoresist 41 by a photomask exposure / development process.

  As shown in FIG. 17C, the exposed interlayer insulating film 34 and the underlying first polycrystalline silicon layer 33 are removed by physical or chemical etching by an etching process, and then the photomask is removed. According to the process, the photoresist 41 is removed by ashing using oxygen plasma or the like. Further, the gate oxide film 32 in the range where the low voltage transistor is formed is removed.

  As shown in FIG. 17D, a gate oxide film 32 'is newly formed in a range where a low voltage transistor is formed by the second oxide film forming step. The gate oxide film 32 'is formed thinner than the gate oxide film 32 in the range where the high voltage transistor is formed.

  As shown in FIG. 18A, the second polycrystalline silicon layer 35 is formed on the inter-element isolation region 31, the gate oxide films 32 and 32 ', and the interlayer insulating film 34 by the second polycrystalline silicon layer forming step. Form. Then, a photomask exposure / development process covers a region where a low voltage transistor and a high voltage transistor are formed and a region where the floating gate FG21 of the cell transistor 21 is formed with a photoresist 42.

  As shown in FIG. 18B, the exposed second polycrystalline silicon layer 35, the underlying interlayer insulating film 34 and the first polycrystalline silicon layer 33 are etched physically or chemically by an etching process. Then, the photoresist 42 is removed by ashing using oxygen plasma or the like in a photomask removing process. Then, the photo-mask exposure / development process covers the area where the cell transistor 21 is formed and the area where the low voltage transistor and the gate electrode of the high voltage transistor are formed with the photoresist 43.

  As shown in FIG. 18C, after the exposed second polycrystalline silicon layer 35 is removed by physical or chemical etching by an etching process, the photoresist 42 is removed by oxygen by a photomask removing process. It is removed by ashing using plasma or the like. Then, the drain D21 and the source S21 of the cell transistor 21, and the drain D and the source S of the low voltage transistor and the high voltage transistor are formed by the impurity implantation process and the diffusion process.

  The gate oxide film 32 of the cell transistor 21 shown in FIG. 18C corresponds to the gate oxide film GX21 shown in FIG. 2B, and the first polycrystal of the cell transistor 21 shown in FIG. 18C. The silicon layer 33 corresponds to the floating gate FG21 shown in FIG. An interlayer insulating film 34 of the cell transistor 21 shown in FIG. 18C corresponds to the interlayer insulating layer IL21 shown in FIG. 2B, and the second polycrystalline silicon of the cell transistor 21 shown in FIG. The layer 35 corresponds to the control gate CG21 shown in FIG.

  As shown in FIG. 18D, the wafer (silicon substrate 20) on which the cell transistor 21, the low-voltage transistor and the high-voltage transistor are formed is covered with a thick interlayer insulating film 20 ′ by a wiring formation process. After flattening the surface, a contact hole 36 is formed in the interlayer insulating film 20 ′ by an etching process or the like, and an aluminum electrode 38 is formed on the interlayer insulating film 20 ′ by a sputtering method or the like. Similarly, a thick interlayer insulating film 20 ″ is formed thereon by a wiring formation process, and a via hole 37 is formed in the interlayer insulating film 20 ″ by an etching process or the like, and then an aluminum electrode 39 is formed.

  Note that the contact hole 36 of the cell transistor 21 shown in FIG. 18D corresponds to the contact holes CH1 and CH2 shown in FIG. 2B, and the via hole 37 shown in FIG. C) corresponds to the via hole VH1 shown in FIG. Further, the aluminum electrode 38 of the cell transistor 21 shown in FIG. 18D corresponds to the bit line BL1 and the source line SL1 shown in FIG. 2B, and the aluminum electrode 39 shown in FIG. This corresponds to the bit line BL2 shown in 2 (B) and (C).

<Manufacturing method 2>
Next, manufacturing method 2 will be described. In the manufacturing method 2 according to the present embodiment, a cell transistor of the nonvolatile memory, its peripheral transistor, a capacitor, and the like are formed from polycrystalline silicon with a two-layer structure (two-layer poly structure).

  Here, the step of forming a split gate structure transistor is illustrated as the cell transistor 21, and as the peripheral transistor, for example, a low voltage transistor for processing a logic signal or a high voltage transistor for processing an analog signal is used. The step of forming will be exemplified, and the step of forming the capacitor constituting the A / D conversion circuit will be exemplified and described.

  First, as shown in FIG. 19A, a gate oxide film 32 is formed on the surface of the silicon substrate 20 by the thermal oxidation method in the first oxide film formation step, and further the element is formed by the LOCOS method in the element isolation region formation step. An inter-space separation region 31 is formed.

  Next, as shown in FIG. 19B, a first polycrystalline silicon layer 33 is formed on the inter-element isolation region 31 and the gate oxide film 32 by a first polycrystalline silicon layer forming step, and an interlayer insulating film forming step. Thus, an interlayer insulating film 34 is formed thereon. Then, the region where the capacitor is formed and the photoresist 41 which forms the floating gate FG21 of the cell transistor 21 are covered by a photomask exposure / development process.

  As shown in FIG. 19C, the exposed interlayer insulating film 34 and the first polycrystalline silicon layer 33 and the gate oxide film 32 thereunder are removed by physical or chemical etching by an etching process. . Further, the gate oxide film 32 in a range where a low voltage transistor is formed is removed.

  As shown in FIG. 20A, after the photoresist 41 is removed by ashing using oxygen plasma or the like in the photomask removal process, a low voltage transistor is formed in the second oxide film formation process. A new gate oxide film 32 ′ is formed, and sidewall oxide films are formed on the side surfaces of the first polycrystalline silicon layer 33 and the interlayer insulating film 34. The gate oxide film 32 'is formed thinner than the gate oxide film 32 in the range where the high voltage transistor is formed.

  As shown in FIG. 20B, the second polycrystalline silicon layer 35 is formed on the inter-element isolation region 31, the gate oxide films 32 and 32 'and the interlayer insulating film 34 by the second polycrystalline silicon layer forming step. Form. Then, by the photomask exposure / development process, the range in which the gate electrode of the low voltage transistor or the high voltage transistor is formed, the range in which the floating gate FG21 of the cell transistor 21 is formed, and the range in which the capacitor electrode is formed are defined in Cover with.

  As shown in FIG. 20C, after the exposed second polycrystalline silicon layer 35 is removed by physical or chemical etching by an etching process, the photoresist 43 is removed by oxygen by a photomask removing process. It is removed by ashing using plasma or the like. Then, the drain D21 and the source S21 of the cell transistor 21, and the drain D and the source S of the low voltage transistor and the high voltage transistor are formed by the impurity implantation process and the diffusion process.

  Note that the gate oxide film 32 of the cell transistor 21 shown in FIG. 20C corresponds to the gate oxide film GX21 shown in FIG. 2B, and the first polycrystal of the cell transistor 21 shown in FIG. 20C. The silicon layer 33 corresponds to the floating gate FG21 shown in FIG. The interlayer insulating film 34 of the cell transistor 21 shown in FIG. 20C corresponds to the interlayer insulating layer IL21 shown in FIG. 2B, and the second polycrystalline silicon of the cell transistor 21 shown in FIG. The layer 35 corresponds to the control gate CG21 shown in FIG.

  As shown in FIG. 20D, the wafer (silicon substrate 20) on which the cell transistor 21, the low-voltage transistor and the high-voltage transistor are formed is covered with a thick interlayer insulating film 20 ′ by a wiring formation process. After flattening the surface, a contact hole 36 is formed in the interlayer insulating film 20 ′ by an etching process or the like, and an aluminum electrode 38 is formed on the interlayer insulating film 20 ′ by a sputtering method or the like.

  As shown in FIG. 18D described in the manufacturing method 1 described above, a thick interlayer insulating film 20 ″ is formed on the interlayer insulating film 20 ′ by the wiring forming process, and then the etching process or the like is further performed. Note that the via hole 37 and the aluminum electrode 39 are formed, but are omitted in FIG.

  The contact hole 36 of the cell transistor 21 shown in FIG. 20D corresponds to the contact holes CH1 and CH2 shown in FIG. 2B, and the aluminum electrode 38 of the cell transistor 21 shown in FIG. This corresponds to the bit line BL1 and the source line SL1 shown in FIG.

  When the capacitor forming step is included as in the manufacturing method 2, the manufacturing step of the interlayer insulating film 34 for forming the inter-electrode insulating layer of the capacitor (interlayer insulating film forming step in FIG. 19B) is performed. The interlayer insulating layer IL21 on the floating gate FG21 of the cell transistor 21 can be formed at the same time, and the manufacturing process of the second polycrystalline silicon layer 35 for forming the electrode of the capacitor (the second polycrystalline silicon in FIG. 20B). The control gate CG21 of the cell transistor 21 can be formed at the same time by the layer forming step and the etching step of FIG. For this reason, since the nonvolatile memory can be configured without separately providing a step of forming the cell transistor 21 and the like, an increase in manufacturing cost can be suppressed.

  Note that, as shown in FIG. 21, by adopting a configuration in which the drain D21 of the cell transistor 21 is wrapped in the pocket of the p + layer, the writing speed is improved, and the erase voltage is prevented from being lowered when hot holes are injected. , The performance can be improved.

  In each of the embodiments and reference examples described above, the silicon substrate 20 is set to the P conductivity type, and the drains D21 to D25 and the sources S21 to S25 are set to the N conductivity type. Even if 20 is set to the N conductivity type and the drains D21 to D25 and the sources S21 to S25 are set to the P conductivity type, the same operations and effects as described above can be obtained. In this case, it should be noted that each of the embodiments and reference examples described above and each potential, sign, etc. are reversed in polarity.

1A and 1B are circuit diagrams showing connection examples of cell transistors constituting a nonvolatile memory according to the first embodiment of the present invention. FIG. 1A is configured as an EEPROM or the like, and FIG. 1B is configured as a mask ROM. Is the case. FIG. 2A is an explanatory diagram showing a planar layout in the case where the cell transistor of the nonvolatile memory according to the first embodiment is configured as an EEPROM or the like, and FIG. 2B is a diagram illustrating the 2B- shown in FIG. 2B is a sectional view taken along line 2B, and FIG. 2C is a sectional view taken along line 2C-2C shown in FIG. FIG. 3A is an explanatory diagram showing a planar layout when the cell transistor of the nonvolatile memory according to the first embodiment is configured as a mask ROM, and FIG. 3B is a schematic diagram of 3B- shown in FIG. 3B is a cross-sectional view taken along line 3B, and FIG. 3C is a cross-sectional view taken along line 3C-3C shown in FIG. FIG. 4A is an explanatory diagram showing a voltage relationship when data is written to the cell transistor of the nonvolatile memory according to the first embodiment. FIG. 4A is configured as an EEPROM or the like, and FIG. 4B is configured as a mask ROM. If so. FIGS. 5A to 5D are explanatory diagrams showing voltage relationships when data is read when the cell transistor of the nonvolatile memory according to the first embodiment is configured as an EEPROM or the like. FIG. 6A to FIG. 6D are explanatory diagrams illustrating voltage relationships when data is read when the cell transistor of the nonvolatile memory according to the first embodiment is configured as a mask ROM. It is a block diagram which shows the structural example of the non-volatile memory which concerns on 1st Embodiment. FIG. 8A is an explanatory diagram showing a flow of testing / inspection of the cell transistor of the nonvolatile memory according to the first embodiment, and FIG. 8A shows the case of an EEPROM or the like, and FIG. 8B shows the case of a mask ROM. FIG. 9A is a circuit diagram showing an example of connection of cell transistors constituting a nonvolatile memory according to the second embodiment of the present invention, and FIG. 9A is configured as an EEPROM or the like, and FIG. 9B is configured as a mask ROM. Is the case. FIG. 10A is an explanatory diagram showing a planar layout in the case where the cell transistor of the nonvolatile memory according to the second embodiment is configured as an EEPROM or the like, and FIG. 10B is the nonvolatile memory according to the second embodiment. It is explanatory drawing which shows the planar layout in case a memory is comprised as mask ROM. FIG. 11A is an explanatory diagram showing a voltage relationship when data is read when the cell transistor of the nonvolatile memory according to the second embodiment is configured as an EEPROM or the like. FIG. 11A shows a high threshold voltage of the cell transistor to be read. FIG. 11B shows the case where the threshold voltage of the cell transistor to be read is low. FIG. 12A is an explanatory diagram showing a voltage relationship when data is read when the cell transistor of the nonvolatile memory according to the second embodiment is configured as a mask ROM. FIG. 12A is a via hole corresponding to the cell transistor to be read. 12B is a case where a via hole corresponding to the cell transistor to be read is formed. FIG. 13A is an explanatory diagram showing a voltage relationship when data is read when the cell transistor constituting the nonvolatile memory according to the third embodiment of the present invention is configured as an EEPROM or the like. FIG. In the case of the state, FIG. 13B shows the case where the read target cell is on. FIG. 14A is an explanatory diagram showing a voltage relationship when data is read when the cell transistor of the nonvolatile memory according to the third embodiment is configured as a mask ROM. FIG. 14A is a via hole corresponding to the cell transistor to be read. 14B is a case where a via hole corresponding to the cell transistor to be read is formed. FIG. 15A is an explanatory diagram showing a voltage relationship when data is read when the cell transistor constituting the nonvolatile memory according to the reference example is configured as an EEPROM or the like. FIG. 15 (B) is the case where the read target cell is in the ON state. FIG. 16A is an explanatory diagram showing a voltage relationship when data is read when the cell transistor constituting the nonvolatile memory according to the reference example is configured as a mask ROM. FIG. 16 (B) shows a case where the read target cell is on. FIG. 19 is a schematic cross-sectional view showing the method for manufacturing the cell transistor that constitutes the nonvolatile memory according to the first embodiment of the present invention, and shows a step before that shown in FIG. 18. FIG. 18 is a schematic cross-sectional view showing the method for manufacturing the cell transistor constituting the nonvolatile memory according to the first embodiment of the present invention, and shows a step subsequent to that shown in FIG. 17. FIG. 21 is a schematic cross-sectional view showing another example of the method for manufacturing the cell transistor that constitutes the nonvolatile memory according to the first embodiment of the present invention, and shows a step before that shown in FIG. 20. FIG. 20 is a schematic cross-sectional view showing another example of the method for manufacturing the cell transistor constituting the nonvolatile memory according to the first embodiment of the present invention, and shows a step subsequent to that shown in FIG. 19. FIG. 6 is a schematic cross-sectional view showing another configuration example of the cell transistor that constitutes the nonvolatile memory according to the first embodiment of the present invention.

Explanation of symbols

20 ... Silicon substrate (second conductivity type semiconductor substrate)
21 to 25 ... cell transistors (memory cell transistors)
31 ... Inter-element isolation region 32 ... Gate oxide film 33 ... First polycrystalline silicon layer 34 ... Interlayer insulating film 35 ... Second polycrystalline silicon layer 36 ... Contact hole 37 ... Via hole 38, 39 ... Aluminum electrode 41, 42, 43 ... Photoresist 100 ... Memory cell transistor matrix 110 ... X address decoder 120 ... Y gate 130 ... Y address decoder 140 ... Address buffer 150 ... Write circuit 160 ... Sense amplifier 170 ... Input / output buffer BL1 ... Bit line (first main wiring) )
BL2 ... Bit line (first sub-wiring)
CG21 to CG23 ... control gates CH1 to CH6 ... contact holes D21 to D23 ... drain (first conductivity type first well)
S21 to S23... Source (second conductivity type second well)
FG21 to FG23 ... floating gate GX21 ... gate oxide film IL21 ... interlayer insulating layer LY0 ... substrate layer LY1 ... contact formation layer LY2 ... first wiring layer (first wiring layer)
LY3 ... buyer forming layer LY4 ... second wiring layer (second wiring layer)
VH1, VH3, VH5 ... Via hole (first via hole)
VH2, VH4, VH6 ... Via hole (second via hole)
WL1 to WL5 ... word line SL1 ... source line (second main wiring)
SL2 ... Source line (second sub-wiring)

Claims (5)

A first well region and a second well region of the second conductivity type formed symmetrically in a plane direction across the channel formation region on the main surface of the first conductivity type semiconductor substrate; and on the main surface of the channel formation region Nonvolatile semiconductor memory device comprising a plurality of memory cell transistors having a MOS structure comprising a floating gate formed through a gate oxide film and a control gate formed on the floating gate through an oxide film Because
A first main wiring formed in a first wiring layer stacked on the semiconductor substrate and connected in common to the first well regions of the plurality of memory cell transistors;
A first sub-wiring that is disposed and formed in a second wiring layer stacked on the semiconductor substrate so as to be connectable to the first main wiring;
A second main wiring formed in a third wiring layer stacked on the semiconductor substrate and connected in common to the second well regions of the plurality of memory cell transistors;
A second sub-wiring that is disposed and formed in a fourth wiring layer stacked on the semiconductor substrate so as to be connectable to the second main wiring;
When the data stored by the memory cell transistor is configured to be electrically rewritable, a first via hole connecting the first main wiring and the first sub-wiring, the second main wiring, and the second A second via hole connecting two sub-wirings, corresponding to each of the plurality of memory cell transistors,
When the data stored by the memory cell transistor is configured so as not to be electrically rewritable, without forming the first via hole or the second via hole corresponding to the memory cell transistor to be written, The nonvolatile semiconductor memory device, wherein the first via hole or the second via hole corresponding to the memory cell transistor not to be written is formed.   2. The first wiring layer and the third wiring layer are the same wiring layer, and the second wiring layer and the fourth wiring layer are the same wiring layer. Nonvolatile semiconductor memory device. A first well region and a second well region of the second conductivity type formed symmetrically in a plane direction across the channel formation region on the main surface of the first conductivity type semiconductor substrate; and on the main surface of the channel formation region A plurality of memory cell transistors having a MOS structure including a floating gate formed through a gate oxide film and a control gate formed on the floating gate through an oxide film;
A first main wiring formed in a first wiring layer stacked on the semiconductor substrate and connected in common to the first well regions of the plurality of memory cell transistors;
A first sub-wiring that is disposed and formed in a second wiring layer stacked on the semiconductor substrate so as to be connectable to the first main wiring;
A second main wiring formed in a third wiring layer stacked on the semiconductor substrate and connected in common to the second well regions of the plurality of memory cell transistors;
A second sub-wiring that is arranged and formed in a fourth wiring layer stacked on the semiconductor substrate so as to be connectable to the second main wiring;
A method for manufacturing a nonvolatile semiconductor memory device comprising:
When the data stored by the memory cell transistor is configured to be electrically rewritable, a first via hole connecting the first main wiring and the first sub-wiring, the second main wiring, and the second A via hole forming step of forming a second via hole connecting two sub-wirings corresponding to each of the plurality of memory cell transistors;
When the data stored by the memory cell transistor is configured so as not to be electrically rewritable, without forming the first via hole or the second via hole corresponding to the memory cell transistor to be written, A data writing step of writing the data by forming the first via hole or the second via hole corresponding to the memory cell transistor not to be written;
The method of manufacturing a nonvolatile semiconductor memory device, wherein the via hole forming step and the data writing step are distinguished by a difference in mask pattern capable of forming the first via hole and the second via hole. .   4. The first wiring layer and the third wiring layer are the same wiring layer, and the second wiring layer and the fourth wiring layer are the same wiring layer. Manufacturing method of the non-volatile semiconductor memory device.   5. The method of manufacturing a nonvolatile semiconductor memory device according to claim 3, wherein when a step of forming a capacitor on the semiconductor substrate is included, the plurality of memory cell transistors are simultaneously formed in this step. .

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