JP2009081989A - System and method for cell balancing - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a system and a method, which prevent permanent damage to a weakest cell even if unbalance exists between cells. <P>SOLUTION: A cell balancing circuit comprises a first cell having a first voltage, a second cell in series with the first cell and having a second voltage greater than the first voltage, and a bypass path in parallel with the second cell for enabling a bypass current for the second cell if a difference between the first voltage and the second voltage is greater than a predetermined threshold. The bypass current is enabled for a balancing time period that is proportional to the difference between the first voltage and the second voltage. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a battery protection system, and more particularly to a cell balance system.

RELATED APPLICATIONS This is a continuation-in-part of the co-pending US application filed September 25, 2007 under the title “Systems and Methods for Cell Balancing”.

  In a multi-cell battery pack, the cells may be different from each other due to cell aging and different cell temperatures. The voltage difference between cells may increase as the number of charge / discharge cycles increases, which may lead to an imbalance between cells and may shorten battery life.

  If the imbalance between cells reaches a certain limit during the period when the battery pack is discharged at a relatively high current, the voltage reversal in the weakest cell will permanently damage the weakest cell. Might bring.

  In one embodiment, the cell balance circuit includes a first cell having a first voltage, a second cell having a second voltage greater than the first voltage in series with the first cell, and the first cell Including a bypass path in parallel with the second cell to enable the bypass current for the second cell if the difference between the voltage of the second and the second voltage is greater than a predetermined threshold . The bypass current is enabled for a balance time that is proportional to the difference between the first voltage and the second voltage.

  The features and advantages of embodiments of the claimed subject matter will become apparent as the following detailed description proceeds, and upon reference to the drawings, in which like numerals represent like parts.

  Reference to embodiments of the invention will now be made in detail. While the invention will be described in conjunction with these embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims.

  Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention.

  FIG. 1 shows a block diagram of a cell balancing system 100 according to one embodiment of the invention. As shown in the embodiment of FIG. 1, the cell balance system 100 includes a battery pack 102 having a plurality of cells 102_1-102_N. For simplicity and clarity, not all of the cells are shown in FIG. Each of the plurality of cells 102_1 to 102_N has a corresponding bypass path in parallel with the corresponding cell. For example, the cell 102_1 has a bypass path including a resistor 106_1, a resistor 106_2, and a switch 104_1. The cell 102_2 has a bypass path including a resistor 106_2, a resistor 106_3, and a switch 104_2. The cell 102_N has a bypass path including a resistor 106_N, a resistor 106_N + 1, and a switch 104_N.

  The cell balance system 100 also includes a balance controller 110, a monitoring circuit 120, and a logic core 130 in one embodiment. Balance controller 110 controls the bypass path for each cell 102_1-102_N by controlling the corresponding switch 104_1-104_N (for simplicity and clarity, not all switches are shown in FIG. Absent). The monitoring circuit 120 can monitor cell voltages for the cells 102_1 to 102_N. The logic core 130 can receive the monitoring signal from the monitoring circuit 120 and control the balance controller 110. In one embodiment, logical core 130 can be a processor (eg, a microprocessor) or a state machine.

  In one embodiment, the monitoring circuit 120 includes an analog to digital converter (ADC) 120. During each ADC cycle, ADC 120 examines the cell voltages for all cells 102_1-102_N, and logic core 130 that receives the monitor signal from ADC 120 will determine whether any cell satisfies the unbalance condition. Advantageously, if a cell satisfies an unbalance condition, the corresponding bypass path will be conducted so that bypass (or bleeding) current can flow through the corresponding bypass path.

  FIG. 2 shows a flowchart 200 of operations performed by the cell balance system 100 according to one embodiment of the invention. FIG. 2 is described in combination with FIG.

  In one embodiment, the battery pack includes a first cell having a first voltage and a second cell having a second voltage greater than the first voltage in series with the first cell. A bypass path in parallel with the second cell is bypassed (or bleeding) for the second cell if the difference between the first voltage and the second voltage is greater than a predetermined threshold. ) Can conduct to enable current. Advantageously, the bypass (or bleeding) current for the second cell is enabled for a balance time proportional to the difference between the first voltage and the second voltage.

  In block 202, the cell voltage for each cell 102_1-102_N is monitored. In one embodiment, the monitoring circuit 120 coupled to the plurality of cells 102_1-102_N monitors the cell voltage and generates a monitoring signal indicating the cell voltage for each cell. In one embodiment, the monitoring signal is then sent to logic core 130. In block 204, the cell voltages for cells 102_1-102_N are compared, for example, by logic core 130.

  In one embodiment, if the difference between the minimum cell voltage and the maximum cell voltage is greater than a predetermined threshold at block 206, the flowchart 200 proceeds to block 210. Otherwise, the flowchart 200 returns to block 202. For example, if the first cell 120_1 has the minimum voltage Vcell_min, the second cell 102_2 has the maximum voltage Vcell_max, and the difference between Vcell_min and Vcell_max is greater than a predetermined threshold, then the flow chart 200 proceeds to block 210.

In block 210, the predetermined balance time T_balancing is set to an amount proportional to the difference between the minimum voltage Vcell_min and the maximum voltage Vcell_max. In one embodiment, the balance time T_balancing is determined by a controller (eg, logic core 130), which can be given by:
T_balancing = (Vcell_max-Vcell_min) * Tcd / Vcell_full (1)
Here, Vcell_full represents a nominal voltage for a fully charged cell, and Tcd represents a discharge time for depleting a fully charged cell. As shown in equation (1), the balance time T_balancing is proportional to the difference between Vcell_min and Vcell_max.

  In block 212, bypass current is enabled for the cell having the maximum cell voltage Vcell_max. More specifically, the balance controller 110 can turn on the corresponding switch to conduct the corresponding bypass path in parallel with the cell having the maximum cell voltage Vcell_max for a time T_balancing. At block 214, if the balance time T_balancing expires, the flowchart 200 returns to block 202 to begin a new cycle. Otherwise, the flowchart 200 returns to block 214.

  Thus, the bypass path will be conducted to enable bypass current for the cell having the maximum cell voltage Vcell_max. In one embodiment, the bypass current is enabled for a time T_balancing that is proportional to the difference between Vcell_min and Vcell_max so that the cell that initially has the maximum cell voltage Vcell_max gradually reaches the minimum cell voltage Vcell_min. . The algorithm as shown in FIG. 2 can be performed at different stages, such as, in one embodiment, battery charging, discharging, or idle stage.

  FIG. 3 shows a flowchart 300 of operations performed by the cell balance system 100 according to one embodiment of the invention. FIG. 3 is described in combination with FIG.

  In one embodiment, the cell balance system 100 can not only enable cell balance for one cell, but can also enable cell balance for two or more cells simultaneously. . For example, a first bypass path in parallel with the first cell can enable a first bypass (bleeding) current for the first cell. A second bypass path in parallel with the second cell can enable the second bypass current for the second cell coupled in series with the first cell. In one embodiment, if both the first cell and the second cell satisfy the unbalance condition, the first bypass current and the second bypass current can be enabled simultaneously for a predetermined period of time. The first bypass current flows through the first bypass path, and the second bypass current flows through the second bypass path.

  In one embodiment, if the first voltage of the first cell is greater than a predetermined threshold and the second voltage of the second cell is also greater than the predetermined threshold, the first cell and Both second cells satisfy the unbalance condition. In an alternative embodiment, the first difference between the first voltage of the first cell and the third voltage of the third cell is greater than a predetermined threshold, and the second voltage of the second cell If the second difference between the voltage and the third voltage is also greater than the predetermined threshold, both the first cell and the second cell satisfy the unbalance condition.

  At block 302, a new ADC cycle begins. In block 304, cell 102_i (i = 1) is selected. At block 306, if the selected cell 102_i is in the balance phase (ie, there is a bypass current flowing through a bypass path in parallel with the cell 102_i), the flowchart 300 proceeds to block 310.

  In block 310, cell balance will be temporarily disabled for cell 102_i and the cell (s) adjacent to cell 102_i (i.e. for cell (s) adjacent to cell 102_i and cell 102_i). The bypass current flowing through the corresponding bypass path will be temporarily disabled). For example, if cell 102_1 is selected, then cell balance will be temporarily disabled for cell 102_1 and cell 102_2. If cell 102_2 is selected, then cell balance will be temporarily disabled for cell 102_1, cell 102_2, and cell 102_3. If cell 102_N is selected, then cell balance will be temporarily disabled for cell 102_N-1 and cell 102_N.

  In block 312, the monitoring circuit 120 will obtain the cell voltage for the selected cell 102_i. More specifically, the ADC converter in the monitoring circuit 120 will in one embodiment convert an analog signal indicative of the cell voltage for the cell 102 — i into a digital signal and send the digital signal to the logic core 130. In block 314, balancing in cell 102_i and the cell (s) adjacent to cell 102_i is resumed and flow diagram 300 proceeds to block 316.

  Returning to block 306, if the selected cell 102_i is not in the balancing phase, the flowchart 300 proceeds to block 308. The monitoring circuit 120 will obtain the cell voltage for the selected cell 102_i. More specifically, the ADC converter in the monitoring circuit 120 will in one embodiment convert an analog signal indicative of the cell voltage for the cell 102 — i into a digital signal and send the digital signal to the logic core 130. The flowchart 300 proceeds to block 316.

  At block 316, if i is less than the total number of cells N in the battery pack, the flowchart 300 proceeds to block 318. In block 318, i is incremented by 1 so that the next cell is selected. The flowchart 300 returns to block 306. The blocks following block 306 described above will not be repeated here for clarity and brevity.

  In block 316, if i is not less than the total number of cells N in the battery pack, the flowchart 300 proceeds to block 320. In block 320, logic core 130 compares the cell voltages for cells 102_1-102_N, in one embodiment. At block 322, the balance will be temporarily disabled for all cells 102_1-102_N. At block 324, the logic core 130 can check whether any cell satisfies the unbalance condition. In one embodiment, the cell satisfies an unbalance condition if the cell voltage is greater than a predetermined threshold. In one embodiment, a cell satisfies an unbalanced condition if the difference between the cell voltage and the voltage of another cell in the same battery pack is greater than a predetermined threshold. Advantageously, the cell balance system 100 can balance one cell at a time, or can balance multiple (eg, two or more) cells simultaneously. For example, for a battery having N cells, the cell balance system 100 can simultaneously balance up to N-1 cells according to system power tolerance and battery pack thermal considerations. In other words, the cell balance system 100 can simultaneously enable the bypass current for N−1 cells. In one embodiment, the number of cells to balance simultaneously can be determined by the logical core 130 and / or predetermined / programmable by the user.

  At block 324, if one or more cells satisfy the unbalance condition, the flowchart 300 proceeds to block 326. At block 326, bypass current is enabled for one or more cells that satisfy the unbalance condition. The flow chart then proceeds to block 302 after delay 328 to begin a new ADC cycle. Delay 328 can be predetermined and can be set to zero. In block 324, if there are no cells that satisfy the unbalance condition, the flowchart 300 proceeds directly to block 302 and begins a new ADC cycle.

  Advantageously, in one embodiment, the cell balance system 100 can perform cell balance in real time by continuously monitoring the cell voltage in the battery pack 102. The unbalanced cell is balanced for a predetermined period of time. After the unbalanced cell has been balanced for a predetermined period of time, the cell voltage in the battery pack is measured again to check again whether any cell meets the unbalance. The predetermined fixed period can be determined by the ADC cycle, for example, smaller than the ADC cycle. The predetermined fixed period can also be determined by the user by setting the delay time of the delay element 328.

  The algorithm as shown in FIG. 3 can be implemented in one embodiment when cells in the battery pack are in a charge phase, a discharge phase, or an idle phase.

  FIG. 4 shows a flowchart 400 of operations performed by the cell balance system 100, according to one embodiment of the invention. FIG. 4 is described in combination with FIG.

  In one embodiment, the cell balance system 100 may perform cell balance according to the state of charge (SOC) of the cells 102_1-102_N. In one embodiment, the logic core 130 can measure a first SOC that indicates a first charge level of a first cell, and a second SOC that indicates a second charge level of a second cell. Can be measured. In one embodiment, the second SOC is greater than the first SOC. Advantageously, if the difference between the first SOC and the second SOC is greater than a predetermined threshold, a bypass path in parallel with the second cell enables a bypass current for the second cell. can do. In one embodiment, the bypass current for the second cell is enabled during the balance time. In one embodiment, the balance time can be set to an amount proportional to the difference between the first SOC and the second SOC. In an alternative embodiment, the balance time can be set to an amount equal to a predetermined fixed period.

  In block 402, the battery pack 102 is in the charging phase. At block 404, the logic core 130 will determine if there are any cells currently in balance. If there are no cells currently in balance, the logic core 130, in one embodiment, may record the full charge capacity (FCC) recorded in the previous charge / discharge cycle for each cell 102_1-102_N, as indicated by block 406. Would read.

  If there is one or more cells that are currently in the balance phase, the logic core 130 will, in one embodiment, examine a corresponding timer that determines the balance (bleeding) time, as indicated by block 410. At block 412, if the timer does not expire, the flowchart 400 returns to block 404. At block 412, if the timer expires, the flowchart 400 proceeds to block 414. At block 414, in one embodiment, balance is temporarily disabled. The flowchart 400 proceeds to block 408.

  At block 408, the logic core 130 may calculate the current state of charge (SOC) for each cell 102_1-102_N in the battery pack 102. In one embodiment, the SOC for each cell is determined by the ratio of the current cell capacity to the full charge capacity (FCC). In one embodiment, the cell balance system 100 can predict in advance which (multiple) cells need to be balanced by calculating the SOC for each cell.

  At block 416, the SOC for all cells is compared, eg, by the logic core 130. In one embodiment, the logic core 130 may search for the minimum SOC and the maximum SOC among the cells 102_1-102_N in the battery pack 102. At block 418, if the difference between the minimum SOC and the maximum SOC is greater than a predetermined threshold, the flowchart 400 proceeds to block 420. Otherwise, the flowchart 400 returns to block 408. The blocks that follow the block 408 described above will not be repeated here for clarity and brevity.

  In block 420, the balance time T can be determined by the logical core 130. In one embodiment, the balance time is proportional to the difference between the minimum SOC and the maximum SOC. At block 422, the cell with the maximum SOC begins to balance (eg, by enabling its bypass current through the corresponding bypass path) and the corresponding timer is started. Flow diagram 400 returns to block 404 to begin a new cycle. Advantageously, the cell balance system 100 can determine which cell (s) to balance according to the charge state of each cell instead of the cell voltage of each cell.

  The algorithm as shown in FIG. 4 can be implemented in one embodiment when cells in the battery pack are in a charge phase, a discharge phase, or an idle phase.

  FIG. 5A shows a cell balance circuit 500A for enabling look-ahead cell balance according to one embodiment of the invention. Elements labeled the same as in FIG. 1 have similar functions and will not be repeated here for brevity and clarity.

  Advantageously, the cell balance system 500A enables cell balance before the cell reaches a predetermined maximum cell charge voltage (full cell charge voltage). For example, bypass current can be enabled for cells that reach a cell voltage equal to 90% of the maximum cell charge voltage. By starting the balance before the cell reaches a predetermined maximum cell charge voltage, in one embodiment, the unbalanced cell will have a longer balance time and thus further extend battery life. In one embodiment, the look-ahead cell balance circuit 500A as shown in FIG. 5A can be used in the charging process of the battery pack 102, but is not limited thereto.

  The cell balance system 500A includes charging and balance controllers 510_1 to 510_N for the respective cells 102_1 to 102_N in the battery pack 102. For brevity and clarity, not all charge and balance controllers are shown in FIG. 5A. Each charge and balance controller 510_1-510_N, in one embodiment, monitors the cell voltage of the corresponding cell 102_1-102_N and generates a balance control signal for each cell 102_1-102_N. Each charge and balance controller 510_1-510_N is smaller than a reference signal 522 representing a predetermined maximum cell charge voltage and a predetermined maximum cell charge voltage (full cell charge voltage), for example 90% of the predetermined maximum cell charge voltage A reference signal 520 representing a predetermined balance threshold is received. Each charge and balance controller 510_1-510_N also receives a cell voltage for the corresponding cell 102_1-102_N.

  In one embodiment, each charge and balance controller 510_1-510_N includes a charge end signal 540_1-- to suspend charging power to the battery pack 102 when the cell voltage of any cell reaches a predetermined maximum cell charge voltage. 540_N (for simplicity and clarity, not all of the end-of-charge signals are shown in FIG. 5A). In one embodiment, OR gate 540 receives charge termination signals 540_1-540_N. If any of the charge termination signals 540_1-540_N has a high level, the OR gate 540 will generate a control signal 542 in one embodiment to suspend charging power to the battery pack 102. Further, each charge and balance controller 510_1-510_N, in one embodiment, flows through a corresponding bypass path when the cell voltage of the corresponding cell reaches a predetermined balance threshold that is less than a predetermined maximum cell charge voltage. In order to enable the bypass current, a cell balance signal is generated. The bypass current is enabled by turning on the corresponding switches 104_1-104_N.

  The algorithm as shown in FIG. 5A can be implemented in one embodiment when cells in the battery pack are in a charge phase, a discharge phase, or an idle phase.

  FIG. 5B shows an example circuit diagram for the charge and balance controller in FIG. 5A, according to one embodiment of the invention. Elements labeled the same as in FIG. 5A have similar functions and will not be repeated here for the sake of brevity and clarity.

  Each charge and balance controller 510_1-510_N in FIG. 5A has a structure similar to that shown in FIG. 5B. In one embodiment, each charge and balance controller 510_1-510_N includes a first comparator 504 for comparing the cell voltage with a predetermined maximum cell charge voltage 522 and for generating a charge termination signal 540 according to the comparison result. Including. Each charge and balance controller 510_1-510_N further generates a cell balance signal 534 for comparing the cell voltage with a predetermined balance threshold 520 (eg, 90% of a predetermined maximum cell charge voltage) and according to the comparison result. A second comparator 502 is included. Signals Vcell + and Vcell− are respectively coupled to the positive terminal and the negative terminal of the corresponding cell.

  Accordingly, in one embodiment, a cell balance system is provided. The cell balance system can be used to balance battery packs according to different cell balance algorithms, thereby reducing unbalance between cells and extending battery life. Advantageously, the balance / bleeding accuracy of the cell balance system can be predetermined (programmed). For example, if the cell voltage difference between any two cells is less than a predetermined (programmable) threshold, or the cell capacity difference between any two cells is a predetermined (programmable) threshold The cell balance can be terminated.

  While the foregoing description and drawings represent embodiments of the invention, various additions, modifications, and substitutions may be made therein without departing from the spirit and scope of the principles of the invention as defined in the appended claims. It will be understood that this may be done. The present invention may be used with many variations of shapes, structures, arrangements, proportions, materials, elements, and parts used in the practice of the present invention, and others, which depart from the principles of the present invention. Without having to, those skilled in the art will appreciate that they are specifically adapted to specific environmental and operational requirements. The presently disclosed embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims and their legal equivalents, It is not limited to the description.

1 is a block diagram of a cell balance system according to an embodiment of the present invention. 3 is a flow diagram of operations performed by a cell balance system, according to one embodiment of the invention. 3 is a flow diagram of operations performed by a cell balance system, according to one embodiment of the invention. 3 is a flow diagram of operations performed by a cell balance system, according to one embodiment of the invention. 1 is a block diagram of a cell balance system according to an embodiment of the present invention. FIG. 5B is an example circuit diagram of the charge and balance controller in FIG. 5A, according to one embodiment of the invention.

Explanation of symbols

100 cell balance system
102 battery pack
102_1-102_N cells
104_1 ~ 104_N switch
106_1 ~ 106_N + 1 resistors
110 Balance controller
120 Supervisory circuit
130 logical cores
200 Flow chart
202 to 214 Each block in flowchart 200
300 Flow chart
302 to 328 Each block of flowchart 300
400 Flow chart
402 to 422 Each block of flowchart 400
500A cell balance circuit
502 second comparator
504 First comparator
510_1 ~ 510_N Charge and balance controller
520 Pre-set balance threshold
522 Predetermined maximum cell charging voltage
534 cell balance signal
540 OR gate
540_1 ~ 540_N Charging end signal
542 Control signal

Claims (24)

A first cell having a first voltage and a second cell in series with the first cell and having a second voltage greater than the first voltage;
When the difference between the first voltage and the second voltage is greater than a predetermined threshold, the second cell for enabling a bypass current for the second cell; A parallel bypass path,
The cell balance circuit, wherein the bypass current flows through the bypass path and is enabled for a balance time proportional to the difference.   Further comprising a logic core operable to receive a first monitoring signal indicative of the first voltage and a second monitoring signal indicative of the second voltage and to determine the balance time. The cell balance circuit according to 1.   2. The cell balance circuit according to claim 1, further comprising a balance controller for conducting the bypass path during the balance time when the difference is greater than the predetermined threshold.   The cell balance circuit of claim 1, further comprising a monitoring circuit operable to monitor the first voltage and the second voltage. A first bypass path operable in parallel with the first cell to enable a first bypass current for the first cell;
A second bypass path operable in parallel with a second cell to enable a second bypass current to the second cell coupled in series with the first cell;
The cell balance, wherein both the first cell and the second cell satisfy the unbalance condition, the first bypass current and the second bypass current are simultaneously enabled for a predetermined period of time. circuit.   6. The cell balance circuit according to claim 5, wherein the first bypass current flows through the first bypass path, and the second bypass current flows through the second bypass path.   When the first voltage of the first cell is greater than a predetermined threshold and the second voltage of the second cell is greater than the predetermined threshold, the first cell and the first cell 6. The cell balance circuit according to claim 5, wherein both of the two cells satisfy the unbalance condition.   The first difference between the first voltage of the first cell and the third voltage of the third cell is greater than a predetermined threshold, the second voltage of the second cell and the When the second difference between the third voltage and the third voltage is greater than the predetermined threshold, both the first cell and the second cell satisfy the unbalance condition, the third cell 6. The cell balance circuit according to claim 5, wherein is in series with the first cell and the second cell.   6. The cell balance circuit according to claim 5, further comprising a monitoring circuit for monitoring a first voltage of the first cell and a second voltage of the second cell.   6. The cell balance circuit according to claim 5, wherein the first cell and the second cell are in a charging stage.   6. The cell balance circuit according to claim 5, wherein the first cell and the second cell are in an idle stage.   6. The cell balance circuit according to claim 5, wherein the cell balance circuit has a predetermined balance accuracy. A second for measuring a first state of charge (SOC) indicative of a first charge level of the first cell and indicative of a second charge level of a second cell in series with the first cell; A logical core for measuring the SOC of the second, wherein the second SOC is larger than the first SOC;
The second cell for enabling a bypass current for the second cell when the difference between the first SOC and the second SOC is greater than a predetermined threshold; A parallel bypass path,
A cell balance circuit, wherein the bypass current is enabled during a balance time.   14. The cell balance circuit according to claim 13, wherein the balance time is proportional to the difference.   14. The cell balance circuit according to claim 13, wherein the balance time is equal to a predetermined constant period.   14. The cell balance circuit according to claim 13, wherein the first SOC is determined by a ratio of a cell capacity of the first cell to a full charge capacity of the first cell.   14. The cell balance circuit according to claim 13, wherein the second SOC is determined by a ratio of a cell capacity of the second cell to a full charge capacity of the second cell. Measuring a first state of charge (SOC) indicating a first charge level of the first cell;
Measuring a second SOC indicating a second charge level of a second cell in series with the first cell, wherein the second SOC is greater than the first SOC;
Enabling a bypass current for the second cell if the difference between the first SOC and the second SOC is greater than a predetermined threshold;
The cell balancing method, wherein the bypass current is enabled for a balance time.   The method of claim 18, wherein the balance time is proportional to the difference.   The method of claim 18, wherein the balance time is equal to a predetermined fixed period.   19. The method of claim 18, wherein the first SOC is determined by a ratio of a cell capacity of the first cell to a fully charged capacity of the first cell.   The method of claim 18, wherein the second SOC is determined by a ratio of a cell capacity of the second cell to a full charge capacity of the second cell. A bypass path in parallel with the cells in the battery pack;
Coupled to the cell and operable to generate a charge end signal to suspend charging power to the battery pack when the cell voltage of the cell reaches a predetermined maximum cell charge voltage; A charge and balance controller operable to generate a cell balance signal to enable bypass current through the bypass path when a predetermined threshold value less than the predetermined maximum cell charge voltage is reached. Including cell balance circuit.   The charge and balance controller is operable to compare the cell voltage with the predetermined maximum cell charge voltage and is operable to generate the charge end signal; and 24. The cell balance circuit of claim 23, comprising a second comparator operable to compare to the predetermined threshold and operable to generate the cell balance signal.

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