JP2009081777A - Power transistor drive circuit - Google Patents

Abstract

A power transistor drive circuit having a protection function and easy to downsize is provided.
An output terminal that outputs a control signal of a power transistor, an abnormality detection terminal that receives an abnormality signal of the power transistor, an IV conversion circuit that converts a current flowing through an external resistor into a voltage, and an AD conversion circuit; A storage circuit for holding a digital signal, and a soft shutdown circuit including at least two shutdown resistors selected by using the storage circuit, wherein the first shutdown resistor is selected in the off state of the power transistor The power transistor is characterized in that the abnormality detection terminal is turned to a low level by the inputted abnormality signal, the control signal for switching off the power transistor is output, and a soft shutdown of the power transistor is executed. A drive circuit is provided.
[Selection] Figure 2

Description

  The present invention relates to a power transistor drive circuit.

  When a power transistor such as an IGBT is switched, current supply to the coils of each phase of the motor can be controlled. When an abnormal situation such as a short circuit of a load occurs, if the power transistor is turned off rapidly, the power transistor as a load is easily destroyed.

  In order to suppress the destruction of the power transistor, a drive circuit having a protection function by soft shutdown may be used. For example, when an abnormality is detected, two MOSFETs constituting the output stage of the drive circuit are turned off and the output terminal is set in a floating state. By gradually extracting the charge accumulated in the output terminal via the soft shutdown circuit, it becomes easy to suppress the destruction of the IGBT. However, if the soft shutdown function is configured by an external circuit, the shape becomes large.

There is a technology disclosure example relating to a switching circuit with a protective function and a protective circuit, which can be easily downsized by IC integration (Patent Document 1). In this disclosed example, a soft shutdown circuit is provided in which the IGBT switch is gently shut down when the IGBT goes out of saturation. However, it cannot be said that the drive circuit is small enough.
JP 2006-295326 A

  Provided is a power transistor drive circuit which has a soft shutdown protection function and can be easily miniaturized.

  According to one aspect of the present invention, an output terminal that outputs a control signal that switches a power transistor on or off based on an input signal, an abnormality detection terminal that receives an abnormality signal generated when the power transistor is on, An IV conversion circuit that converts a current flowing in an external resistor provided between the abnormality detection terminal and the ground into a voltage, an AD conversion circuit that ranks the converted voltage and converts it into a digital signal, and the digital signal A memory circuit that retains the digital signal when a trigger signal is input in a state where the signal is input, and a soft shutdown circuit that includes at least two shutdown resistors selected by using the memory circuit, and the power In the off state of the transistor, the current flowing through the external resistor is detected and the memory circuit The first shutdown resistor is selected by inputting a digital signal, and the abnormality detection terminal is turned to a low level by the inputted abnormality signal, and the control signal for turning off the power transistor is output and held. The power transistor, wherein the first shutdown resistor whose selection is maintained by the digital signal is electrically connected between the output terminal and the ground, and a soft shutdown of the power transistor is executed. A drive circuit is provided.

  A power transistor drive circuit that has a soft shutdown protection function and is easy to downsize is provided.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a circuit diagram of a power transistor drive circuit according to an embodiment of the present invention. The power transistor drive circuit 10 includes an IV conversion circuit 30, an AD conversion circuit 32, a monitor circuit 33, a storage circuit 34, a switching circuit 35, a soft shutdown circuit 36, output stage transistors Q1 and Q2, and a driver 38 that drives Q1 and Q2. including. The power transistor drive circuit 10 includes an input (Vin) terminal 12, a power supply (Vcc) terminal 14, an output (Vo) terminal 16, a ground (GND) terminal 18, and an abnormality detection terminal 20.

  When the power transistor Q4 that is a load is an IGBT, a MOSFET, or the like, a control voltage is applied to the control electrode G via the Vo terminal 16. When an excessive current is detected in the on state of the IGBT, an abnormal signal is input to the reset set flip-flop (RS-FF), and the output is transmitted to the abnormality detection terminal 20 via the diode D5. A control signal for switching the power transistor Q4 on and off is input to the Vin terminal 12.

  The power transistor drive circuit 10 may include a coupling means 50 by light or electromagnetic from a coil in the preceding stage. This facilitates stable operation of the electronic device because the signal is transmitted in an electrically insulated state. In FIG. 1, the light coupling unit 50 includes a light emitting unit 52 and a light receiving unit 54. The power transistor drive circuit 10 provided with the light coupling means 50 is mounted on, for example, a surface mount package and can be called an optical coupling device. In this case, if the power transistor drive circuit 10 and the light receiving unit 54 are integrated into one chip, the size can be easily reduced.

  Next, blocks constituting the power transistor drive circuit 10 and their operations will be described. A high level (H level) signal or a low level (L level) signal from the light receiving unit 54 is input to the driver 38 via the Vin terminal 12. A signal from the abnormality detection terminal 20 is further input to the driver 38, and an output is connected to the gates of the output stage MOSFETs (Q1, Q2). The connection point between the source of Q1 and the drain of Q2 is the Vo terminal 16. The drain of Q1 is connected to the Vcc terminal 14, and the source of Q2 is connected to the GND terminal 18.

  In this embodiment, for example, three shutdown resistors are provided, and any one of them can be selected depending on the IGBT (Q4) to be used. Corresponding to these three shutdown resistors, an IV conversion circuit 30, an AD conversion circuit 32, a storage circuit 34, a soft shutdown circuit 36, and the like are provided in parallel.

  FIG. 1 shows a state in which no signal is input to the light emitting unit 52, the control signal from the driver 38 to Q1 is at L level, and Q1 is OFF. Further, it is assumed that the control signal to Q2 is at H level, Q2 is on, and the Vo terminal 16 is at L level. That is, since the control signal is at the L level, IGBT (Q4) is off.

  The IV conversion circuit 30 includes a current mirror CM and resistors R3 and R4. The internal voltage V1 is supplied to the current mirror CM and the external resistor R2, and the abnormality detection terminal 20 is at the H level.

  The AD conversion circuit 32 compares the analog voltage with the comparison voltage, ranks the analog voltage and outputs a digital signal voltage, AD converters A1 and A2, a resistance R5, R6, and R7 that generate the comparison voltage, and 3 bits if necessary. And an encoder (Encorder) for converting to. The current J1 flowing through the external resistor R2 is converted into a voltage by the current mirror CM and the resistor R4, and input to the positive input terminals of the AD converters A1 and A2. The internal voltage V1 is 5 to 6 V, for example, and is divided by resistors R5, R6, and R7. The voltages at the connection point P1 between R5 and R6 and the connection point P2 between R6 and R7 are AD converter A1, Each is input to the negative input terminal of A2.

  The voltage by the resistor R4 and the voltage at P1 are input to the AD converter A1, the voltage by the resistor R4 and the voltage at P2 are input to the AD converter A2, and the shutdown resistors R1A, A2 are compared by comparing the voltages at A1 and A2, respectively. One is selected from the group of R1B and R1C. In FIG. 1, the output of A1 is L level and the output of A2 is H level. That is, the shutdown resistor can be selected by changing the value of the external resistor R2, and the soft shutdown can be adjusted. Thus, the abnormality detection terminal 20 has a soft shutdown adjustment function in addition to the abnormality detection.

  The monitor circuit 33 transmits a signal from the abnormality detection terminal 20 to the soft shutdown circuit 36. In FIG. 1, the input signal to the monitor circuit 33 is at the H level. Note that the output (Q−) of the RS-FF is at the H level, and the current from the RS-FF does not flow into the external resistor R2 because of the diode D5.

  The memory circuit 34 includes three delay flip-flops (D-FF) D1, D2, and D3. The value of the input D becomes the output Q when the first trigger (or clock) signal is input to the CP terminal of the D-FF, and the value of the input D is output until the second trigger signal is input to the CP terminal. Held in Q. Therefore, between the first trigger signal and the second trigger signal, D1 is “1”, D2 is “0”, and D3 is “0”. In the embodiment of FIG. 1, since the value to be stored is 2 bits, the number of D-FFs may be two. However, since there are three shutdown resistors, the configuration can be simplified by providing three D-FFs.

  The switching circuit 35 includes MOSFETs (S1, S2, S3) and inverters (IN3, IN4, IN5). Switching from the output Q of the D-FF and the output of the monitor circuit 33 to the shutdown resistor to be connected is performed.

  The soft shutdown circuit 36 includes soft shutdown transistors Q3A, Q3B, Q3C made of MOSFET or the like, and shutdown resistors (R1A, R1B, R1C). One of Q3A, Q3B, and Q3C is turned on by the output from the switching circuit 35, and soft shutdown is performed.

  FIG. 2 is a circuit diagram for explaining the operation by abnormality detection. In the ON state of the IGBT (Q4) with the Vo terminal 16 at the H level, when an abnormality such as a short circuit occurs in the IGBT (Q4), an abnormality is detected, and the input S of the RS-FF becomes the H level. The output (Q−) becomes L level, and the abnormality detection terminal 20 changes from H level to L level by the diode D5. This transition is transmitted to the driver 38, and the control signal to Q1, which has been at H level, is changed to L level to turn off Q1. Since Q2 is off, the Vo terminal 16 is in a floating state.

  When the abnormality detection terminal 20 transitions from the H level to the L level, the sources of the MOSFETs (S1, S2, S3) are set to the L level via the inverters IN1, IN2. Only the output of the inverter IN5 turns to the H level via S3 which is on, the soft shutdown transistor Q3C is turned on, and the shutdown resistor R1C is connected between the Vo terminal 16 and the GND terminal 18. For this reason, the charge accumulated in the gate of the IGBT (Q4) is gradually pulled out to enable a soft shutdown. In this way, rapid turn-off can be suppressed, and the destruction of IGBT (Q4) can be suppressed.

  Note that the voltage at the abnormality detection terminal 20 at the L level decreases to about the forward voltage of the diode D5, and the current J1 ′ flowing through the current mirror CM is larger than the current J1 when the abnormality detection terminal 20 is at the H level. Then, it flows into the ground via the external resistance R2 and the (Q−) terminal of the RS-FF which has become the L level. The voltage change of the abnormality detection terminal 20 is transmitted through the IV conversion circuit 30 and the AD conversion circuit 32, and the output of A1 becomes H level. For this reason, the input D of D1 changes from “1” to “0”, and the input D of D2 changes from “0” to “1”. However, since the second trigger signal is not input to the D-FF, the output Q of the D-FF that is the memory circuit 34 is held, and the on / off states of the MOSFETs (S1, S2, S3) are not changed. The selection of the shutdown resistor R1C is maintained without being changed, and the soft shutdown is continued.

  In this figure, the UVLO (Undervoltage Lockout) output is used for the trigger signal input to the CP terminal of the D-FF. When Vcc is lower than the guaranteed operating range, the function of forcing the Vo terminal 16 to L is called UVLO. For example, a trigger signal can be generated and used as an input signal to the CP terminal of the D-FF when Vcc reaches around 10 V, which is the guaranteed operating range, at the start of system operation. If V1 (for example, 5 to 6 V) lower than the guaranteed operating range is applied to the current mirror CM and the resistors R5, R6, and R7, the input D is D− when the trigger signal is input to the CP terminal. Input to FF.

  FIG. 3 is a power transistor drive circuit diagram according to a comparative example. This comparative example is a power transistor drive circuit including an optical coupling means, and can also be called an optical coupling device 110. The light emitting unit 152 is driven, and the driver 138 can control the MOSFETs (Q11, Q12) by an output signal from the light receiving unit 154. For example, when the light emitting unit 152 emits light, the driver 138 turns on Q11, turns off Q12, turns the Vo terminal 116 to H level, and turns on the IGBT (Q14).

  A diode D 10 connected between the drain and the load 144 is connected to the positive input terminal of the comparator 142. The reference voltage Vref is input to the negative input terminal of the comparator 142, and when an abnormality such as a short circuit of the IGBT (Q14) is detected, the input S that is at the H level is input to the RS-FF. RS-FF transmits an output (Q−) at L level to the inverter IN11 and turns off Q11, so that the Vo terminal 116 is in a floating state. On the other hand, the RS-FF turns on the external transistor Q13 with the output Q being H level, gradually pulls out the charge accumulated in the gate of the IGBT (Q14) via the shutdown resistor R11, and destroys the IGBT (Q14). Suppress. The microcomputer 156 receives the FAULT signal from the output Q of the RS-FF, and the RESET output from the microcomputer 156 becomes the input R to the RS-FF.

  If such soft shutdown Q13 is, for example, an external MOSFET, the size is close to the outer dimensions of the optical coupling device 110, the mounting substrate becomes large, and the gate drive line becomes long. In the case where a plurality of IGBTs (Q14) are arranged in parallel, if the gate drive line is long, the operation tends to be unbalanced, and there is a problem that the characteristics are deteriorated or broken.

  In addition, the system requires that the soft shutdown waveform can be adjusted by changing the resistance value of R11 depending on the IGBT to be used. If a MOSFET is incorporated in the optical coupling device 110 as indicated by a broken line Q13a, the size can be easily reduced, but a shutdown terminal 122 as indicated by a broken line is newly added to the optical coupling device 110 in order to externally attach a shutdown resistor R11. There is a need to provide it, and there is a limit to downsizing.

  On the other hand, in this embodiment, the soft shutdown transistors Q3A, Q3B, and Q3C are integrated into one chip in the power transistor drive circuit 10 to facilitate downsizing, and the gate drive line can be shortened to suppress the unbalance operation. Further, the resistance values of the shutdown resistors R1A, R1B, and R1C can be selected in accordance with the use state. For example, a resistance ratio of 80: 100: 120 is preferable because a common power transistor drive circuit having a soft shutdown protection function can be used for several types of IGBTs. Note that the number of shutdown resistors is not limited to three. If at least two shutdown resistors are provided, the number of shutdown resistors can be set appropriately in consideration of allowable geometric dimensions and system requirements. Further, the number of parts of the power transistor drive circuit can be reduced, and the mounting can be simplified.

  FIG. 4 is a circuit diagram illustrating a modified example of generating a trigger signal transmitted to the CP terminal of the D-FF. For example, an output signal of the light receiving unit 54 that receives a signal from the light emitting unit 52 and an output of UVLO are input to the NAND circuit, and a trigger signal is input to the CP terminal via the inverter IN6. This modification makes it easy to suppress IGBT breakdown when the system becomes hot, for example.

  The embodiments of the present invention have been described above with reference to the drawings. However, the present invention is not limited to these embodiments. A person skilled in the art has made a design change with respect to the soft shutdown circuit, memory circuit, AD conversion circuit, IV conversion circuit, monitor circuit, switching circuit, driver, output stage transistor, coupling means arrangement, connection, etc. constituting the power transistor drive circuit Even if it is a thing, unless it deviates from the main point of this invention, it is included in the scope of the present invention.

Circuit diagram of power transistor drive circuit according to an embodiment Circuit diagram explaining operation by abnormality detection Circuit diagram of power transistor drive circuit according to comparative example Circuit diagram showing a modified example for generating a trigger signal

Explanation of symbols

10 power transistor drive circuit, 16 Vo terminal, 20 abnormality detection terminal, 30 IV conversion circuit, 32 AD conversion circuit, 34 storage circuit, 36 soft shutdown circuit, 50 coupling means, R1A, R1B, R1C shutdown resistor, Q3A, Q3B, Q3C soft shutdown transistor, D1, D2, D3 delay flip-flop, R2 external resistor, Q4 power transistor

Claims (5)

An output terminal for outputting a control signal for switching the power transistor on or off based on the input signal;
An anomaly detection terminal to which an anomaly signal generated in the ON state of the power transistor is input;
An IV conversion circuit that converts a current flowing in an external resistor provided between the abnormality detection terminal and the ground into a voltage;
An AD converter circuit that ranks the converted voltages and converts them into digital signals;
A storage circuit that holds the digital signal when a trigger signal is input in a state in which the digital signal is input;
A soft shutdown circuit including at least two shutdown resistors selected using the memory circuit;
With
In the OFF state of the power transistor, a current flowing through the external resistor is detected, and the first shutdown resistor is selected by inputting the digital signal to the memory circuit,
The abnormality detection terminal is turned to a low level by the inputted abnormality signal, the control signal for turning off the power transistor is outputted, and the selection is maintained by the held digital signal. Is electrically connected between the output terminal and the ground, and a soft shutdown of the power transistor is executed.   The first shutdown resistor is connected to the ground via a transistor based on the output of the memory circuit, or is connected to the output terminal via the transistor based on the output of the memory circuit. The power transistor drive circuit according to claim 1.   The power transistor drive circuit according to claim 1, wherein the AD conversion circuit further includes an encoder that converts the number of bits of the digital signal.   The power transistor drive circuit according to any one of claims 1 to 3, wherein the trigger signal is generated when a power supply voltage reaches an operation guarantee range. It further comprises electrically insulating and coupling means using light or electromagnetics,
The power transistor drive circuit according to claim 1, wherein an output signal of the coupling means is the input signal.

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