JP2009080326A - Active matrix type display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active matrix type display device which has little display unevenness without being influenced by characteristic variance of a drive thin film transistor even when it is a low-gradation image. <P>SOLUTION: The active matrix type display device is equipped with a display part, a signal supply part 101, a pixel selection part 130 and a control part 120. The signal supply part includes a voltage holding part ROM to hold voltage, a gradation voltage output part to output gradation voltage Vsig corresponding to a video signal, and a gradation current output part to output gradation current Isig corresponding to the image signal. The control part 120 generates a voltage writing period when the held voltage and the gradation voltage output by the gradation voltage output part are added and applied to the gate terminal of a drive transistor DTr for a first predetermined time t0, a current writing period when the gradation current from the gradation current output part is supplied to a signal line for a second predetermined time t1, and a correction period when the drive transistor is diode-connected for a third predetermined period t2. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an active matrix display device, and more particularly to an active matrix display device in which video signals are written with high accuracy.

Active matrix display devices using organic EL elements have been developed. In this apparatus, it is required that the characteristics of a thin film transistor for driving an organic EL element, that is, a drive transistor, be substantially the same between pixels.
However, since the thin film transistor is usually formed on an insulator such as a glass substrate, the characteristics of the drive transistor often vary between pixels.

Patent Document 1 describes an active matrix organic EL display device that employs a current copy type circuit as a pixel circuit. In this display device, a current signal is supplied to each pixel as a video signal, and a driving current having a magnitude corresponding to the current signal is supplied to the organic EL element to cause the organic EL element to emit light. According to this technique, it is possible to minimize the influence of the variation in the characteristics of the drive transistor on the magnitude of the drive current.
US Pat. No. 6,373,454

  By the way, in this current copy type circuit, before the video signal is written to the pixel circuit via the signal line, the potential of the signal line and the gate terminal of the driving thin film transistor of the selected pixel circuit is once set to the reference potential. .

  Normally, the potential of the lowest gradation level is written from the constant voltage source to the signal line and the gate terminal of the driving thin film transistor of the selected pixel circuit regardless of the video signal for each line. The supplied minimum gradation level potential is the same potential in each pixel circuit. That is, the supplied minimum gradation level potential is not a potential obtained by correcting the variation in the threshold value of the driving thin film transistor of each pixel. For this reason, due to the variation in the threshold value of the driving thin film transistor, the brightness of each pixel is different and display unevenness occurs in the minimum gradation raster display.

  When low gradation display is performed, the potential of the signal line and the gate terminal of the driving thin film transistor of the selected pixel circuit is set to the lowest gradation level potential, and then the video signal current corresponding to the low gradation is used. The potential for low gradation display is used. However, it is difficult to correct the characteristic variation of the driving thin film transistor within one horizontal period with a small video signal current corresponding to a low gradation. Therefore, display unevenness has occurred even when low gradation display is performed.

  The present invention has been made in view of such problems, and provides an active matrix display device with little display unevenness without being affected by variations in characteristics of driving thin film transistors even for low gradation images. For the purpose.

  In order to solve the above problems, the present invention provides a display unit in which a pixel unit including a driving transistor for driving a display element is arranged in a matrix on a substrate, a pixel unit provided for each column, The pixel unit is selected through a signal supply unit that supplies a signal to a signal line to be connected and a selection line that is provided for each row and connects to each pixel unit in each column. The pixel selection unit that switches the internal circuit of the pixel unit for taking in the signal from the control unit, the operation of the pixel selection unit, and the signal supply from the signal supply unit are controlled and displayed on the pixel unit. The signal supply unit includes a voltage holding unit that holds a voltage, a gradation voltage output unit that outputs a gradation voltage corresponding to the video signal, and a level that corresponds to the video signal. Gradation current output to output regulated current And the control unit adds the held voltage and the grayscale voltage output from the grayscale voltage output unit and applies the voltage to the gate terminal of the drive transistor for a first predetermined time. An active period for generating a period, a current writing period for supplying a gradation current from the gradation current output unit to the signal line for a second predetermined period, and a correction period for diode-connecting the driving transistor for a third predetermined period It is a matrix type display device.

  According to the present invention, it is possible to provide an active matrix display device with little display unevenness without being affected by variations in characteristics of driving thin film transistors even for low gradation images.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, in each figure, the same referential mark is attached | subjected to the component which exhibits the same or similar function, and the overlapping description is abbreviate | omitted.
In the following embodiments, an organic EL display device will be described among the active matrix display devices, but the present invention is not limited to the organic EL.

  FIG. 1 is a block diagram schematically showing a display device according to an embodiment of the present invention. The display device 10 is a bottom emission organic EL display device that employs an active matrix driving method.

On the insulating support substrate 100 such as glass of the display device 10, pixel portions PX (1,1), PX (2,1),..., A plurality of pixel selection scanning lines S1a to S1b, S2a to S2b, ..., a plurality of light control scanning lines S1c, S2c, ..., a plurality of signal lines DL1, DL2, ... are provided.
Further, on the insulating support substrate 100, a signal line driving circuit 101, a pixel selection scanning line driving circuit 130, a dimming scanning line driving circuit 140, and a system control unit 120 are provided as driving circuits.

  The pixel unit PX includes an organic EL element and a pixel drive circuit, and is disposed in the vicinity of the intersection of the pixel selection scanning line (dimming scanning line) and the signal line. Details of the configuration of the pixel unit PX will be described later.

  The signal line driver circuit 101 is connected to signal lines DL1, DL2, DL3,... Provided for each pixel column. As shown in FIG. 1, each of the signal lines DL1, DL2,... Extends in the column direction (Y direction) of the pixel portion PX, and is alternately arranged in the pixel portion PX and the row direction (X direction). ing. These signal lines DL1, DL2,... Are connected to the signal line driving circuit 101 and the pixel portion PX in each column.

  The pixel selection scanning line driving circuit 130 is connected to a pixel selection scanning line provided for each pixel row. As shown in FIG. 1, each of the pixel selection scanning lines S1a to S1b, S2a to S2b,... Extends in the row direction (X direction) of the pixel portion PX, and the pixel portion PX and the column direction (Y direction). ) Are alternately arranged. These pixel selection scanning lines S1a to S1b, S2a to S2b,... Are connected to the pixel selection scanning line driving circuit 130 and the pixel portion PX of each row.

  The dimming scanning line driving circuit 140 is connected to a dimming scanning line provided for each pixel row. As shown in FIG. 1, each of the light control scanning lines S1c, S2c,... Extends in the row direction (X direction) of the pixel portion PX, and alternately in the pixel portion PX and the column direction (Y direction). Arranged.

  The signal line driving circuit 101, the pixel selection scanning line driving circuit 130, and the dimming scanning line driving circuit 140 are driven by timing pulses from the system control unit 120. A timing signal and a clock signal synchronized with the video signal are supplied to the system control unit 120 via the input terminals 103 and 104. Therefore, the system control unit 120 can give various timing pulses synchronized with the video signal to the signal line driving circuit 101, the pixel selection scanning line driving circuit 130, and the dimming scanning line driving circuit 140.

  The pixel selection scanning line driving circuit 130 selects a plurality of pixel units PX arranged in the row direction (X direction) in order to store the video signal. When the pixel selection scanning line driving circuit 130 controls the pixel selection scanning lines S1a to S1b, S2a to S2b,... To be in an active state, a plurality of pixel units PX connected to the pixel selection scanning line that is in the active state Executes a series of operations for storing a video signal (may be referred to as image data).

The signal line driver circuit 101 takes in a video signal via the input terminal 102. The captured video signal is converted into a video signal current and a video signal voltage for each pixel unit PX in the row direction (X direction), and is output to corresponding signal lines DL1, DL2,. The The pixel portion PX in the active state captures and stores the video signal via the corresponding signal lines DL1, DL2,.
When the video signal required for the nth line is supplied to each pixel unit PX of the nth line via the corresponding signal lines DL1, DL2,..., the video required for the next n + 1th line A signal is supplied to each pixel unit PX of the (n + 1) th line via corresponding signal lines DL1, DL2,. The pixel selection scanning lines S1a to S1b, S2a to S2b,... Are selected by the pixel selection scanning line driving circuit 130.

The dimming scanning line driving circuit 140 designates a timing for supplying a light emission current corresponding to the video signal stored in each pixel unit PX to the organic EL element.
A timing signal and a clock signal synchronized with the video signal are supplied to the system control unit 120 via the input terminals 103 and 104. Based on the timing signal and the clock signal, the system control unit 120 performs various timing signals for causing the signal line driving circuit 101, the pixel selection scanning line driving circuit 130, and the dimming scanning line driving circuit 140 to display an image. Is output.

Although not shown, the signal line drive circuit 101, the pixel selection scanning line drive circuit 130, the dimming scanning line drive circuit 140, and the system control unit 120 are also led to a power supply line for supplying power. .
Further, the signal line driver circuit 101, the pixel selection scanning line driving circuit 130, the dimming scanning line driving circuit 140, and the system control unit 120 may be formed on the substrate 100 or provided as an external IC outside the substrate 100. May be.

Next, the operation of the active matrix display device will be described.
FIG. 2 shows a configuration example of a pixel portion PX (1,1) connected to the signal line DL1 and a driver circuit connected to the pixel portion PX (1,1). Hereinafter, the pixel portion PX (1, 1) will be described as a representative.

The pixel unit PX (1, 1) includes a pixel circuit and a display element OLED.
The display element OLED includes a photoactive layer between a pair of opposed electrodes. The cathode of the display element OLED is connected to the earth line, and the anode is connected to the power supply line PVDD via a pixel circuit for driving the element. Here, the display element is an organic EL element including at least an organic light emitting layer as a photoactive layer. For example, organic EL elements that emit red, green, and blue light are arranged in a predetermined order on the substrate 100.

  The pixel circuit includes a drive thin film transistor DTr, a correction switch SW2, a pixel selection switch SW3, and an output switch SW4, which are constituted by p-channel thin film transistors, for example. In addition, a capacitor C0 that holds a voltage between the gate of the driving thin film transistor DTr and the power supply line PVDD is provided.

  The organic EL element is connected to the drain of the driving thin film transistor DTr via the output switch SW4, and the source of the driving thin film transistor DTr is connected to the power supply line PVDD. The gate of the driving thin film transistor DTr is connected to the capacitor C0 and the drain of the correction switch SW2. The correction switch SW2 is connected between the gate and drain of the driving thin film transistor DTr, and the gate thereof is connected to the pixel selection scanning line Sla.

  The pixel selection switch SW3 is connected between the signal line DL1 and the drain of the driving thin film transistor DTr, and the gate thereof is connected to the pixel selection scanning line S1b. The output switch SW4 is connected between the drain of the driving thin film transistor DTr and the organic EL element, and the gate thereof is connected to the dimming scanning line S1c.

The driver circuit is provided in the signal line driver circuit 101, and includes a gradation signal current source, a gradation signal voltage source, an A / D conversion circuit, and a ROM. The gradation signal current source supplies the gradation signal current Isig to the signal line DL1 via the output switch SW6. The gradation signal voltage source supplies the gradation signal voltage Vsig to the signal line DL1 through the output switch SW5. The A / D conversion circuit takes in an analog voltage signal via the input switch SW7 and converts it into a digital voltage signal. The ROM stores a digital voltage signal.
The digital voltage signal stored in the ROM is added to the gradation signal voltage Vsig and supplied to the signal line DL1 via the output switch SW5.

  The SW2 to SW7 are controlled to be turned on and off by the system control unit 120.

  Next, an operation of taking an analog voltage signal into the A / D conversion circuit, converting it into a digital voltage signal, and storing it in the ROM will be described.

FIG. 3 is a diagram for explaining the operation of the pixel portion and the driver circuit when the gate terminal voltage of the driving thin film transistor DTr is taken. In FIG. 3, a constant current source is newly connected to the signal line DL1 via the output switch SW8. In FIG. 3, the switches marked with “x” are opened, indicating that no signal is connected.
During this period, the output switch SW8 is turned on. Accordingly, the constant current Iconst can be supplied from the pixel circuit to the signal line DL1, and can flow to the signal line driver circuit 101. In the pixel PX (1, 1), the correction switch SW2 and the pixel selection switch SW3 are turned on to supply the constant current Iconst to the signal line DL1, and connect the gate and drain of the driving thin film transistor DTr. As a result, the capacitor C0 accumulates charges capable of holding the gate-source voltage of the driving thin film transistor DTr so that the constant current Iconst flows. At this time, the potential of the gate terminal (node A) of the driving thin film transistor DTr has a value reflecting variation in characteristics of the driving thin film transistor DTr.

  On the other hand, in the driver circuit, the input switch SW7 is turned on after a predetermined time has elapsed. Thus, the voltage value Vbase reflecting the potential of the node A, that is, the variation in the characteristics of the driving thin film transistor DTr, is input to the A / D conversion circuit, converted into a digital value, and stored in the ROM.

Note that the operation of taking in the gate terminal voltage of the driving thin film transistor DTr described above is executed, for example, in an adjustment stage before shipping the active matrix display device. The ROM stores a voltage value Vbase captured as digital data.
As described above, by storing the potential of the node A that has been captured in advance as digital data in the ROM, an operation of capturing the potential of the node A every horizontal period becomes unnecessary, and the drive circuit can be configured at low cost.

  However, the gate terminal voltage stored in the ROM is used in common for at least a plurality of driving thin film transistors DTr arranged in the column direction. Therefore, the constant current Iconst is preferably applied to a plurality of driving thin film transistors DTr by a test or the like and adopts a value that reduces variation in display.

  Next, a driving method for reducing display unevenness using the potential read in this way will be described.

FIG. 4 is a diagram for explaining the operation of the pixel portion and the driver circuit shown in FIG. FIG. 4 shows the states of the switches SW2 to SW6 and the transition of the potential of the node A in each period for displaying an image.
Here, n (H) represents one horizontal period, and n + 1 (H) represents a subsequent horizontal period. In one horizontal period of n (H), a voltage writing period, a current writing period, and a DTr correction period are provided, and the subsequent one horizontal period after n + 1 (H) is a video display period.

  Subsequently, the operation of the pixel portion PX in the voltage writing period, the current writing period, the DTr correction period, and the video display period will be described with reference to FIGS.

FIG. 5 is a diagram showing signal connections in the voltage writing period. In FIG. 5, the switches marked with a cross are opened, indicating that no signal is connected.
In the voltage writing period, the output switch SW5 is turned on. As a result, the gradation voltage Vsig and the voltage Vbase stored in the ROM are added from the signal line driver circuit 101 and supplied to the signal line DL1. In the pixel PX (1, 1), the correction switch SW2 and the pixel selection switch SW3 are turned on, and the voltage (Vsig + Vbase) supplied from the signal line DL1 is written in the capacitor C0 that can be held as the gate terminal voltage of the driving thin film transistor DTr. It is.

Here, Vbase is the potential of the node A when the constant current Iconst flows. Therefore, if the gate-source voltage of the driving thin film transistor DTr when the constant current Iconst is supplied is Vgs, Vbase is expressed by the equation (1).
Vbase = PVDD−Vgs (1)
On the other hand, Vgs is expressed by Expression (2) using the threshold voltage Vth of the driving thin film transistor DTr.
Vgs = Vth + α (2)
Α is a value determined by the constant current Iconst and the mobility of the driving thin film transistor DTr.

Therefore, the potential of the node A in the voltage writing period is expressed by Expression (3).
Vsig + Vbase = Vsig + PVDD−Vth−α Equation (3)
The threshold voltage Vth that causes the display variation is taken into the expression (3) representing the potential of the node A. This indicates that the threshold characteristic of the driving thin film transistor DTr can be canceled in the display.

However, the threshold voltage Vth in the expression (3) is a value obtained in advance as described above, and is different from the threshold voltage Vth ′ of the driving thin film transistor DTr to be actually applied. Furthermore, since the mobility of the drive thin film transistor DTr to be applied is also different from the value obtained in advance, it is conceivable that α also has an error.
For this reason, as shown in FIG. 4, even after the voltage writing period has elapsed, a difference is generated between the set potential of the node A and the target potential of the node A. However, since the voltage value Vbase stored in the ROM adopts an optimum value determined by performing a test, this difference is kept small. Therefore, this difference can be corrected in a short time during the current writing period.

FIG. 6 is a diagram illustrating signal connections in the current writing period. In FIG. 6, the switches marked with a cross are opened, indicating that no signal is connected.
In the current writing period, the output switch SW6 is turned on. Thus, the gradation signal current Isig is supplied from the pixel circuit to the signal line DL1, and can flow to the signal line driver circuit 101. In the pixel PX (1, 1), the correction switch SW2 and the pixel selection switch SW3 are turned on to supply the gradation signal current Isig to the signal line DL1, and the gate and drain of the driving thin film transistor DTr are connected. As a result, the capacitor C0 accumulates charges capable of holding the gate-source voltage of the driving thin film transistor DTr so that the gradation signal current Isig flows.
With this operation, the potential of the node A should be set to a target value at which the gradation signal current Isig flows through the display element OLED in the video display period.

However, in reality, there may be a deviation for each pixel that does not match the target potential. The cause is considered to be that the target potential is different for each driving thin film transistor DTr because the characteristics are different for each driving thin film transistor DTr. That is, although the time required for current writing differs for each driving thin film transistor DTr, it is considered that the current writing is performed at a common time as a cause of deviation.
Therefore, in the DTr correction period, the difference for each driving thin film transistor DTr is corrected.

FIG. 7 is a diagram illustrating signal connections in the DTr correction period. In FIG. 7, the switches marked with “X” are opened, indicating that no signal is connected.
In the DTr correction period, the correction switch SW2 is turned on and the pixel selection switch SW3 is turned off in the pixel PX (1, 1). As a result, the gate and drain of the driving thin film transistor DTr are connected. As a result, a current corresponding to the characteristics of the driving thin film transistor DTr flows between the gate and drain of the driving thin film transistor DTr, and electric charge capable of holding the gate-source voltage of the driving thin film transistor DTr is accumulated in the capacitor C0.

Here, when the mobility of the driving thin film transistor DTr is high, the target potential is high and the deviation is large, and when the mobility is low, the deviation is small because the target potential is low. On the other hand, the current that flows when the gate and drain of the driving thin film transistor DTr are connected is large when the mobility is high, and small when the mobility is low.
Therefore, even when the correction switch SW2 is turned on and the pixel selection switch SW3 is turned off for a fixed time (t2) common to all the pixels as the DTr correction period, the deviation from the target value is reduced according to the characteristics of each driving thin film transistor DTr. Can be made.
In addition, what is necessary is just to select suitable time by a test etc. for fixed time (t2). Further, the output switch SW5 is turned on during the DTr correction period, in order to prevent the signal line DL1 from falling into a floating state.

FIG. 8 is a diagram illustrating signal connections in the video display period. In FIG. 8, the switches marked with “X” are opened, indicating that no signal is connected.
In the video display period after the next one horizontal period, in the pixel PX (1, 1), the correction switch SW2 and the pixel selection switch SW3 are turned off. The dimming scanning line driving circuit 140 activates the dimming scanning line S1c and turns on the output switch SW4 connected to the dimming scanning line S1c. Then, a light emission current corresponding to the gate-source voltage of the driving thin film transistor DTr flows to the display element OLED, and the display element OLED emits light with a luminance corresponding to the light emission current.
Note that the output switch SW5 is also turned on during this video display period in order to prevent the signal line DL1 from entering a float state.

[Second Embodiment]
The second embodiment is different from the first embodiment in that a constant current source is provided in the driver circuit and a gate terminal voltage reading period is further provided in one horizontal period. Accordingly, the same parts are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the second embodiment, in a gate terminal voltage reading period in one horizontal period, a constant current Iconst is supplied from a constant current source, a gate terminal voltage of a driving thin film transistor is taken in, converted into a digital signal, and stored in a ROM. . Since this operation has been described with reference to FIG. 3 in the first embodiment, the description thereof will be omitted.

  Then, in the remaining one horizontal period following the gate terminal voltage reading period, the operations of the voltage writing period, the current writing period, and the DTr correction period are performed. Since this operation has been described with reference to FIGS. 4 to 8 in the first embodiment, the description thereof will be omitted.

  In this embodiment, since the voltage stored in the ROM is the gate terminal voltage of the driving thin film transistor to which the gradation signal is to be written, the deviation from the target potential in the subsequent voltage writing period is the first embodiment. Can be made smaller. Accordingly, the gradation signal can be written with high accuracy by the operation in the subsequent current writing period and DTr correction period.

  In the present embodiment, the constant current source is provided separately, but may be configured to be shared with the gradation signal current source.

According to each embodiment described above, in the function of writing the video signal to the gate terminal of the driving thin film transistor via the signal line, the gradation voltage signal in which the characteristic variation of the driving thin film transistor is corrected is written, and then the current writing is performed. Even when an error occurs, display unevenness due to variation in mobility of the driving thin film transistor for each pixel can be effectively suppressed by diode-connecting the driving thin film transistor for a predetermined time.
By providing the voltage writing period, the current writing period, and the DTr correction period in this way, display unevenness can be reduced without being affected by variations in characteristics of the driving thin film transistor even in a low gradation image. .

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment.

1 is a block diagram schematically showing a display device according to an embodiment of the present invention. FIG. 6 is a diagram illustrating a pixel portion connected to a signal line and a driver circuit connected to the pixel portion. 4A and 4B are diagrams for explaining operations of a pixel portion and a driver circuit when capturing a gate terminal voltage of a driving thin film transistor. 4A and 4B illustrate operation of a pixel portion and a driver circuit. The figure which shows the connection of the signal in a voltage writing period. The figure which shows the connection of the signal in an electric current writing period. The figure which shows the connection of the signal in a DTr correction period. The figure which shows the connection of the signal in an image | video display period.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Display apparatus, 101 ... Signal line drive circuit, 130 ... Pixel selection scanning line drive circuit, 140 ... Dimming scanning line drive circuit, 120 ... System control part, C0 ... Capacitor, DL, DL1, DL2 ... Signal line, DTr ... driving thin film transistor, OLED ... display element, PX ... pixel unit, S1a to S1b ... pixel selection scanning line, S1c ... dimming scanning line, SW2 ... correction switch, SW3 ... pixel selection switch, SW4 ... output switch, SW5 ... Output switch, SW6 ... Output switch, SW7 ... Input switch, t0 ... Voltage write period, t1 ... Current write period, t2 ... DTr correction period, 1H ... 1 horizontal period, 1V ... 1 vertical period, Vth ... Threshold voltage, Isig ... Gradation signal current, Vsig: gradation signal voltage.

Claims (6)

A display unit in which pixel units including a driving transistor for driving a display element are arranged in a matrix on a substrate;
A signal supply unit that is provided for each column and supplies a signal to a signal line connected to each pixel unit of each column;
An internal circuit of the pixel unit for selecting the pixel unit via a selection line provided for each row and connecting to each pixel unit of each column and for the pixel unit to capture the signal from the signal line A pixel selection section to be switched;
A control unit that controls the operation of the pixel selection unit and the signal supply from the signal supply unit to control the display so that the display is performed on the pixel unit;
The signal supply unit includes a voltage holding unit that holds a voltage, a grayscale voltage output unit that outputs a grayscale voltage corresponding to the video signal, and a grayscale current output unit that outputs a grayscale current corresponding to the video signal. Have
The controller is
A voltage writing period in which the held voltage and the gradation voltage output from the gradation voltage output unit are added and applied to the gate terminal of the driving transistor for a first predetermined time;
A current writing period for supplying a gradation current from the gradation current output unit to the signal line for a second predetermined time;
An active matrix display device characterized by generating a correction period in which the drive transistor is diode-connected for a third predetermined period.   2. The active matrix display device according to claim 1, wherein the control unit controls one horizontal period so as to sequentially configure the voltage writing period, the current writing period, and the correction period. The signal supply unit is
3. The active matrix display device according to claim 2, wherein the voltage holding section, the gradation voltage output section, and the gradation current output section are provided for each signal line.   4. The active matrix display device according to claim 3, wherein the voltage held in the voltage holding unit is based on a gate terminal voltage of the driving transistor acquired in a state where a constant current is applied to the signal line. 5. The signal supply unit further includes a constant current output unit that outputs a constant current to the drive transistor,
The control unit generates a voltage holding period in which the gate terminal voltage of the driving transistor is acquired and held in the voltage holding unit in a state where the constant current is applied to the signal line, and one horizontal period is sequentially added to the signal line. 2. The active matrix display device according to claim 1, wherein the active matrix display device is controlled to include a voltage holding period, the voltage writing period, a current writing period, and a correction period.   6. The active matrix display device according to claim 5, wherein the gradation current output unit also serves as the constant current output unit.

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