JP2009077450A - Signal processing apparatus and semiconductor device testing apparatus using its apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase a sampling frequency of a ΣΔ modulator or the like to do over-sampling. <P>SOLUTION: A signal processing apparatus 20 includes a frequency compensating unit 28 and a modulation unit 30. The frequency compensating unit 28 includes a first waveform shaper 22 and a second waveform shaper 52. The modulation unit 30 is configured by 2-way-interleaving primary ΣΔ modulators. Two ΣΔ modulators process either an even signal line Xk (k: even number) of an input signal X or an odd signal line Xk (k: odd number) each. The frequency compensating unit 28 operates a transmission characteristic so as that quantization noises are correctly sampled at reference frequencies fs of the entire apparatus by the ΣΔ modulators. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a signal processing apparatus and a semiconductor device test apparatus. In particular, the present invention relates to a signal processing apparatus that processes and transmits a signal at a predetermined reference frequency and a semiconductor device testing apparatus that can use the apparatus.

  The process of modulating an analog signal into a digital signal has a quantization stage, and so-called quantization noise is mixed in that stage. The noise shaping technique reduces quantization noise in a necessary band by changing the characteristic of quantization noise and biasing it to a high frequency band. One such technique is ΣΔ (sigma delta) modulation.

  FIG. 1 shows a configuration of a conventional general primary ΣΔ modulator. The modulator includes two adders 10 and 12, two delay units 14 and 16, and a binarization circuit 18. The input signal X is input to one terminal of the first adder 10, and the output of the first adder 10 is input to one terminal of the second adder 12.

  The output of the second adder 12 is input to the first delay device 14, and the output of the delay device 14 is input to the other terminal of the second adder 12. The output of the second adder 12 is binarized by the binarization circuit 18, and an output signal Y is generated.

  The output signal Y is input to the second delay device 16, and the output of the second delay device 16 is input to the other terminal of the first adder 10. However, this is an input for subtraction. The first delay device 14 and the second delay device 16 each delay the input signal by one sampling period. Hereinafter, the sampling period of this modulator is denoted as fs.

  FIG. 2 shows the operation of the ΣΔ modulator of FIG. In this modulator, the input signal X is sampled at the sampling frequency fs, and as a result, sampling is performed at times t0, t1, t2,. The binarization circuit 18 outputs “0” or “1”. The difference between “0” and “1” corresponds to Δ. In the case of FIG. 2, Yi corresponding to each code Xi (i = 0, 1,...) Of the input signal is

1, 1, 1, 0, 1, 0, 1
Thus, the output signal Y follows the change in the input signal X. When the output signal Y takes “1”, “1” is subtracted from the input signal X by the second delay unit 16 and the first adder 10. When the output signal Y takes “0”, nothing is subtracted from the input signal X. Therefore, if the output signal Y completely matches the input signal X at each sampling timing, the result of subtraction in the first adder 10 is always zero. However, since there is actually an error accompanying quantization, that is, a quantization noise component, the first delay unit 14 and the second adder 12 integrate the noise. As long as the result of integration exceeds the threshold value of the binarization circuit 18, for example, a value such as 0.5, the output signal Y is “1”. On the other hand, if the result of the integration does not exceed the threshold value, the output signal Y is “0”.

  Here, “0” and “1” are considered as the output of the binarization circuit 18, but the output is a binary value of “1” and “−1” or a ternary value of “0” with them. Is used.

  ΣΔ modulation is widely used for processing audio signals and the like, and uses oversampling. In the case of audio signal processing, sampling is often performed at a frequency that is two orders of magnitude faster than the frequency of the required signal band. There is a high demand for sampling an extremely high-speed analog signal at an extremely high sampling frequency in accordance with an improvement in performance of not only an audio signal but also a semiconductor device. In particular, in an apparatus for testing a state-of-the-art semiconductor device, the highest possible analog signal must be digitized with as little quantization noise as possible and analyzed.

  The present invention has been made in view of the above problems, and an object thereof is to provide a technique capable of raising a reference frequency for data processing and transmission. This object is achieved by a combination of features described in the independent claims. The dependent claims define specific and useful forms of the present invention.

  The signal processing apparatus of the present invention is an apparatus for processing and transmitting a signal at a predetermined reference frequency, for example, a predetermined sampling frequency. This apparatus is provided in parallel on a signal transmission path, and includes a modulation unit including a plurality of modulators each having a function of shaping quantization noise generated when a signal is quantized, and the modulation unit on the transmission path. And a frequency compensation unit provided in series. With this configuration, the modulation unit performs modulation based on a second frequency lower than the reference frequency. On the other hand, the frequency compensation unit performs a frequency compensation process so that the quantization noise is shaped based on the reference frequency.

  The frequency compensation unit may include a first waveform shaper and a second waveform shaper, and the transfer function of the first waveform shaper and the transfer function of the second waveform shaper may be inverse numbers. .

  Another form of the signal processing device of the present invention is provided in series with a frequency reduction unit including a plurality of sub-paths provided by multiplexing a part of a signal transmission path, and the frequency reduction unit on the transmission path. Frequency compensation unit. The plurality of sub-paths transmit the signal at different timings based on a second frequency lower than the reference frequency. On the other hand, the frequency compensation unit integrates the signals transmitted at the different timing into a form in which the transmission is performed based on the reference frequency.

  Each of the plurality of sub-paths may include a different number of delay elements in a state where none of the two sub-paths is shared, and the timing may be determined according to the number of the delay elements.

  The frequency compensation unit includes an adder that adds a plurality of signals appearing at the ends of the plurality of sub-paths in an analog manner, an arithmetic unit that obtains an exclusive OR thereof, a multiplier that obtains a logical product thereof, and the like. Also good.

  An interference control unit that controls interference between the plurality of sub-paths of the signal may be further provided.

  The semiconductor device test apparatus of the present invention includes a main test unit that applies a test signal to the device under test and inspects the signal output from the device under test. In the main test unit, a part of the path for processing the test signal is multiplexed, and the frequency for processing the test signal at the multiplexed location is the same as the test signal for the main test unit as a whole. It is set lower than the reference frequency for processing.

  The main test unit may include a preprocessing unit that generates a test signal to be supplied to the device under test. The preprocessing unit may include a pattern generator that generates the test signal as a digital signal, and a D / A conversion unit that converts the digital signal generated by the pattern generator into an analog signal. The D / A conversion unit may include a plurality of interleaved D / A converters and a frequency compensation unit that receives outputs of the plurality of D / A converters. With this configuration, due to the action of the frequency compensation unit, the frequency at which the D / A conversion unit as a whole transmits signals is set higher than the frequency at which each of the plurality of D / A converters transmits signals.

  The preprocessing unit may further include a signal path multiplexing device that multiplexes a part of the transmission path of the analog signal obtained by the D / A conversion. The signal path multiplexing apparatus may include a frequency reduction unit including a plurality of sub paths, and a frequency compensation unit provided in series with the frequency reduction unit on the transmission path. Here, due to the action of the frequency compensation unit, the frequency at which signals are transmitted as a whole of the signal path multiplexing apparatus is set higher than the frequency at which signals are transmitted in the plurality of sub-paths.

  It should be noted that the above summary of the invention does not enumerate all the features necessary for the present invention, and of course, a sub-combination of these feature groups can also be an invention.

  According to the signal processing device of the present invention, signal transmission or processing can be accelerated. According to the semiconductor device test apparatus of the present invention, a high-speed device test can be realized.

It is a block diagram of a conventional general primary ΣΔ modulator. FIG. 2 is a diagram illustrating an operation of the ΣΔ modulator of FIG. 1. 1 is a configuration diagram of a signal processing device according to Embodiment 1. FIG. It is a figure which shows a part of signal processing apparatus of FIG. 3 in the form closer to an actual circuit element. It is a block diagram of the signal processing apparatus which is a modification of the structure of FIG. It is a figure which shows a part of signal processing apparatus of FIG. 5 in the form nearer to an actual circuit element. It is a block diagram of the 1st waveform shaper of the signal processing apparatus which implement | achieves N way interleaving. It is a block diagram of the modulation | alteration unit of the signal processing apparatus which implement | achieves N way interleaving. It is a block diagram of the 2nd waveform shaper of the signal processing apparatus which implement | achieves N way interleaving. It is a block diagram of the signal processing apparatus which carried out 2 way interleaving of the secondary sigma-delta modulator. FIG. 3 is a circuit diagram of a signal processing device according to a second embodiment. It is explanatory drawing of the signal transmission method using a partial response. It is a schematic block diagram of the signal processing apparatus which combined the idea of the partial response system and the interleaving of a signal path. It is a block diagram of the signal processing apparatus which implement | achieves 4 way interleaving using a partial response system. FIG. 6 is a configuration diagram of a semiconductor device test apparatus according to a third embodiment.

  Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention described in the claims, and all combinations of features described in the embodiments are essential for the solution of the invention. Is not limited.

Embodiment 1
FIG. 3 shows the configuration of the signal processing apparatus according to the first embodiment. The signal processing device 20 mainly includes a frequency compensation unit 28 and a modulation unit 30. The frequency compensation unit 28 includes a first waveform shaper 22 and a second waveform shaper 52.

  The first waveform shaper 22 includes a delay unit 24 that delays the input signal X by one sampling period, and an adder 26 that adds the input signal X and the output of the delay unit 24. The output of the adder 26 is added to the dither signal 50 by the adder 58. The dither signal 50 is added to make the operation of the modulation unit 30 more stable. As such, it is a known technique.

  The modulation unit 30 includes a first adder 32, a second adder 34, a first delay device 36, a second delay device 38, a third delay device 40, a fourth delay device 42, and a binarization circuit. 44. The output of the second delay unit 38 is input to the first delay unit 36, and the output of the fourth delay unit 42 is input to the third delay unit 40. The first adder 32 subtracts the output of the third delay unit 40 from the output of the adder 58 for the dither signal. The second adder 34 adds the output of the first adder 32 and the output of the first delay unit 36. The output of the second adder 34 is input to the second delay unit 38 and the binarization circuit 44. The output of the binarization circuit 44 (assumed to be named intermediate signal Y ′) is input to the second waveform shaper 52 and the fourth delay unit 42.

  The second waveform shaper 52 includes an adder 54 and a delay unit 56. The adder 54 subtracts the output of the delay unit 56 from the output of the binarization circuit 44. The output of the adder 54 is an output signal Y, and this signal is input to the delay unit 56.

  FIG. 4 shows a part of the configuration of FIG. 3 rewritten in a form closer to an actual circuit element. 4, the same elements as those in FIG. 3 are given the same reference numerals. The modulation unit 30 in FIG. 3 corresponds to two ΣΔ modulators 60 and 62 that function as A / D converters and an interleave circuit 64 that interleaves them as shown in FIG. Because two delay devices are included in the feedback paths given to the first adder 32 and the second adder 34, the modulation action of the modulation unit 30 is the code Xi of the input signal X.

X0, X2, X4 ...
An even code string, and
X1, X3, X5 ...
This is because it is given independently to the odd code string. Since each delay unit of the modulation unit 30 in FIG. 3 delays the signal by one sampling period, the sampling of the two first-order ΣΔ modulators 60 and 62 is performed at a conventional half frequency, that is, fs / 2. Is called. This is because each of the ΣΔ modulators 60 and 62 processes only one of the even code string and odd code string of the input signal X.

  Since the final output of the modulation unit 30 in FIG. 3 is one system regardless of the even code string and the odd code string, this corresponds to the interleave circuit 64 in an actual circuit. The interleave circuit 64 is a selector for switching the output of the two ΣΔ modulators 60 and 62 at the sampling frequency fs.

  The reason why the frequency compensation unit 28 is necessary is that the configuration of the modulation unit 30 is changed from that of FIG. Assuming that there is no frequency compensation unit 28, and assuming that the input signal X is given to the modulation unit 30 and the output signal Y is output from the modulation unit 30, the transfer characteristic of the modulation unit 30 is

Y = X + Q (1-z ⁻² ) (Formula 1)
It becomes. However,

z ⁻ⁿ = exp (−j2πf · nT)
j = √−1
T = 1 / fs
Where fs is the sampling frequency and f is the signal frequency. Q is quantization noise.

  As can be seen from this equation, with the modulation unit 30 alone, the quantization noise is sampled at fs / 2 and does not perform the original function of the ΣΔ modulator. Originally, the quantization noise must be sampled at fs.

  On the other hand, consider the case where the frequency compensation unit 28 is provided. First, the transfer function H1 (z) of the first waveform shaper 22 is

H1 (z) = 1 + z ⁻¹ (Formula 2)
Can be written. On the other hand, the transfer function H2 (z) of the second waveform shaper 52 is

H2 (z) = 1 / (1 + z ⁻¹ ) (Formula 3)
Can be written. By combining Equation 1, Equation 2, and Equation 3, the transfer characteristic of the entire signal processing device 20 is

Y = X + Q (1-z ⁻¹ )
Thus, the quantization noise is also correctly sampled at the sampling frequency fs.

  As described above, according to the signal processing device 20, the ΣΔ modulator can be 2-way interleaved, and the sampling frequency can be reduced to half. Conversely, if the upper limit of the sampling frequency of ΣΔ modulation is fsu, the signal processing or signal transmission frequency of the entire signal processing apparatus 20 can be up to 2 fsu. A device for interleaving over two ways and a device using a second or higher order ΣΔ modulator will be described later.

  FIG. 5 shows a signal processing device 70 which is a modification of the configuration of FIG. FIG. 6 shows the signal processing device 70 in a form closer to an actual circuit element. In FIG. 3, the first waveform shaper 22 is disposed in front of the modulation unit 30 on the signal transmission line, and the second waveform shaper is disposed behind the modulation unit 30. 5 and FIG. 6 further includes a low-pass filter 72. On the signal transmission path, the second waveform shaper 52, the low-pass filter 72, and the first waveform shaper 22 are arranged in this order after the modulation unit 30. Is done. In this configuration, after the quantization noise Q is cut by the low-pass filter 72, only a desired signal component is subjected to waveform shaping by the first waveform shaper 22. This signal processing device 70 also has the same transfer characteristics as in FIG. 3, and the same effect can be obtained.

  A further advantage of the signal processing device 70 of FIGS. 5 and 6 is that it is suitable for digital processing. That is, in the signal processing device 20 of FIGS. 3 and 4, the first waveform shaper 22 is an analog filter that acts on an analog signal, but the first waveform shaper 22 in the signal processing device 70 of FIGS. 5 and 6 is A digital filter may be used. Therefore, for example, all the frequency compensation units 28 in FIG. 6 can be incorporated in a DSP (digital signal processor) or the like.

7, 8, and 9 show the configuration of a signal processing apparatus in which N-way interleaving, that is, N modulators are provided in parallel. 7 shows the configuration of the first waveform shaper 22, FIG. 8 shows the configuration of the modulation unit 30, and FIG. 9 shows the configuration of the second waveform shaper 52. However, N = 2 ⁿ (n is a natural number).

As shown in FIG. 7, the first waveform shaper 22 includes a first waveform sub-shaper 80 composed of an adder and one delay device, a second waveform sub-shape shaper 82 composed of an adder and two delay devices, Similarly, an ^n- th waveform sub-shaping device 84 including an adder and 2 ⁿ⁻¹ delay devices is included. Between the second waveform sub-shaped device 82 and the n-th waveform sub-shaped device 84, an ^i- th waveform sub-shaped device comprising an adder and 2 ⁱ⁻¹ delay devices (where i = 3, 4,..., n-1) exists.

In any waveform sub-shaper, the delay device closest to the input side and the adder input the same signal, and the output of the delay device farthest from the input side is given to the adder. The first waveform shaper 22 receives the input signal X and outputs an intermediate signal X ′. The transfer function H1 (z) of the first waveform shaper 22 is
H1 (z) = (1 + z ⁻¹ ) (1 + z ⁻² ) (1 + z ^{−N / 2} ) (Formula 4)
Can be written.

As shown in FIG. 8, in the modulation unit 30, a first delay group 90 composed of 2 ⁿ delay units is placed between the output and the input of the second adder 34. A second delay group 92 composed of 2 ⁿ delay units is placed between the output of the binarization circuit 44 and the first adder 32. The modulation unit 30 receives the intermediate signal X ′ and outputs another intermediate signal Y ′. The transfer characteristic of the modulation unit 30 is

Y ′ = X ′ + Q (1−z− ^N ) (Formula 5)
It is. Note that an adder relating to a dither signal placed in front of the modulation unit 30 is omitted in the drawing.

As shown in FIG. 9, the second waveform shaper 52 includes a first waveform sub shaper 100 including an adder and one delay device, a second waveform sub shaper 102 including an adder and two delay devices, Similarly, an ^n- th waveform sub-shaping device 104 including an adder and 2 ⁿ⁻¹ delay devices is included. Between the second waveform sub-shaping device 102 and the n-th waveform sub-shaping device 104, an ^i- th waveform sub-shaping device comprising an adder and 2 ⁱ⁻¹ delay devices (where i = 3, 4,..., n-1) exists. In any waveform sub-shaper, the adder first inputs a signal. Also, the output of the adder is applied to the first one of the series of delay devices, and the output of the last delay device is applied to the adder. The second waveform shaper 52 receives the intermediate signal Y ′ and outputs an output signal Y. The transfer function H2 (z) of the second waveform shaper 52 is
H2 (z) = 1 / (1 + z ⁻¹ ) (1 + z ⁻² ) (1 + z ^{−N / 2} ) (Formula 6)
Can be written.

As described above, when Expression 4, Expression 5, and Expression 6 are combined, the transfer characteristic of the entire signal processing apparatus is still
Y = X + Q (1-z ⁻¹ )
Thus, the quantization noise is correctly sampled at the sampling frequency fs. According to this apparatus, the ΣΔ modulator can be N-way interleaved, and the processing frequency of that portion can be reduced to fs / N.

  Similar to the configuration of FIG. 5 with respect to the configuration of FIG. 3, other configurations are possible for the configurations of FIGS. That is, a low-pass filter is added, and the second waveform shaper 52, the low-pass filter 72, and the first waveform shaper 22 may be arranged in this order after the modulation unit 30 on the signal transmission path.

  FIG. 10 shows a configuration of a signal processing apparatus in which two second-order ΣΔ modulators 120 and 122 are provided in parallel. The first waveform shaper 22 of this apparatus has two sets of delay units and adders, and similarly, the second waveform shaper 52 has two sets of delay units and adders. The number of these sets may be the same as the order of the ΣΔ modulator. Therefore, in general, when m-order (m is a natural number) ΣΔ modulator is N-way interleaved, the transfer function H1 (z) of the first waveform shaper 22 is

H1 (z) = (1 + z ⁻¹ ) ^m (1 + z ⁻² ) ^m (1 + z ^{−N / 2} ) ^m
And the transfer function of the second waveform shaper 52 is H2 (z)
H2 (z) = 1 / (1 + z ⁻¹ ) ^m (1 + z ⁻² ) ^m (1 + z ^{−N / 2} ) ^m
And it is sufficient.

  As described above, according to each signal processing device of the first embodiment, for example, a high-precision and high-speed A / D converter can be realized.

Embodiment 2
In the first embodiment, modulator interleaving is considered. In the second embodiment, signal transmission path interleaving is considered more broadly. Since very high-speed sampling is performed in the first embodiment, when transmitting a signal subjected to noise shaping in the first embodiment, it is conceivable to place the apparatus according to the second embodiment on the path.

  FIG. 11 shows a circuit of the signal processing device 130 according to the second embodiment. This signal processing device 130 inputs the output signal of the first embodiment or other high-speed ΣΔ modulator, particularly the ΣΔ D / A converter. This signal simulates an analog signal, but takes digital values such as “0” and “1” at each sampling timing. In the figure, the signal is represented as an input signal “X”.

  The signal processing device 130 interleaves the signal transmission path four ways. The signal processing apparatus 130 mainly includes a frequency reduction unit 150 including a plurality of sub paths provided by multiplexing a part of a signal transmission path, and a frequency compensation unit 172 provided in series with the frequency reduction unit 150 on the transmission path. And a low-pass filter 174 provided at the subsequent stage of the frequency compensation unit 172.

  The frequency reduction unit 150 includes a distributor 180 that distributes the input signal X to four paths, and four flip-flops 182, 184, 186, and 188 that latch the input signal X distributed to the four paths at different timings. Clocks CK1, CK2, CK3, and CK4 are input to the four flip-flops 182, 184, 186, and 188, respectively. The frequencies of these four clocks are each ¼ of the signal transmission frequency fs, and the clock phases are shifted by 90 °. Therefore, each of the four flip-flops 182, 184, 186, 188 includes a code Xi (i = 0, 1, 2,...) Of the input signal X.

X0, X4, X8, ...
X1, X5, X9, ...
X2, X6, X10, ...
X3, X7, X11, ...
Any one of them.

  The frequency compensation unit 172 includes resistors 192, 194, 196, 198 having one end connected to the outputs of flip-flops 182, 184, 186, 188, respectively. The other ends of these four resistors 192, 194, 196, 198 are coupled and connected to the negative input of the amplifier 200. A capacitor 202 and a resistor 204 are connected between the output of the amplifier 200 and the negative input. Therefore, the entire frequency compensation unit 172 functions as an adder that adds the outputs of the four flip-flops 182, 184, 186, and 188 in an analog manner.

  The output of the amplifier 200 is input to the low pass filter 174. The low-pass filter 174 cuts quantization noise biased toward the high frequency side. The output of the low-pass filter 174 becomes the output signal Y.

  According to this configuration, the signal transmission path is interleaved and divided into four sub-paths, and the transmission frequency in each sub-path can be reduced to 1/4 of the conventional frequency. The input signal X and the output signal Y do not coincide with each other in waveform, and in particular, the output signal Y takes one of 0, 1, 2, 3, and 4. The frequency characteristic of the output signal Y is obtained by adding a characteristic known as an aperture effect related to a quarter frequency to the frequency characteristic of quantization noise due to ΣΔ modulation, and has some influence on the noise shaping function of the ΣΔ modulator. give. However, the S / N ratio in the frequency band of the actually required signal is not much affected, and there are often no practical problems.

  This signal processing device 130 is very useful when, for example, the frequency reduction unit 150 and the frequency compensation unit 172 are physically far apart and high-speed signal transmission is not desirable. Actually, in the semiconductor device test apparatus, for example, the frequency reduction unit 150 may be disposed on the test apparatus main body side, the frequency compensation unit 172 may be disposed on the semiconductor device mounter side, and both may be connected by a cable or a connector. This embodiment is optimal for such applications.

  FIGS. 12, 13, and 14 show modifications that can remove the aperture effect appearing in the signal processing device 130 of FIG.

  FIG. 12 shows a signal transmission system generally known as “partial response”. The reason why the aperture effect occurs in the signal processing device 130 of FIG. 11 is intersymbol interference. That is, one of the four flip-flops 182, 184, 186, 188 is independent of the other flip-flops,

X0, X4, X8, ...
However, when the outputs of the four flip-flops 182, 184, 186, and 188 are simply analog-added as shown in FIG. 11, other codes such as X3 or X5 affect the transmission of X4. . This is intersymbol interference.

  In the partial response system, intersymbol interference is allowed during signal transmission, and the intersymbol interference is canceled at the end of the transmission path. As shown in FIG. 12, this system includes a first adder 220, a first delay unit 222, a second adder 226, and a second delay unit 224. Here, it is assumed that the input signal X takes a binary value of “1” and “0”. The first adder 220 receives the input signal X and the output of the first delay unit 222. However, an exclusive OR is calculated here. When the input signal X takes “1” and “−1”, the first adder 220 may calculate the logical product of the two inputs instead of the exclusive logical sum. The same applies to the second adder 226.

  The output of the first adder 220 is input to the first delay unit 222, the second adder 226, and the second delay unit 224. The output of the second delay device 224 is input to the second adder 226. The output of the second adder 226 becomes the output signal Y.

  In this configuration, first, the first adder 220 and the first delay unit 222 perform a kind of integration on the input signal X. This causes intersymbol interference. On the other hand, the transmission path has a kind of differential characteristic composed of the second adder 226 and the second delay 224. As a result, components due to intersymbol interference are removed from the output signal Y.

  The partial response method of FIG. 12 focuses on the removal of intersymbol interference, and does not consider frequency reduction. That is, the first adder 220, the first delay device 22, the second adder 226, and the second delay device 224 all operate at a constant sampling frequency fs.

  FIG. 13 is a schematic configuration diagram of a signal processing apparatus that combines the concept of the partial response method and two-way interleaving of signal paths. In the figure, an interleave circuit 230 is newly provided, and the output of the first adder 220 is 2-way interleaved. As the interleave circuit 230, a circuit in which the frequency reduction unit 150 of FIG. One interleaved code string Xk (k: even number) is input to the second adder 226, and the other code string Xk (k: odd number) is input to the second adder 226 via the second delay unit 224. Entered.

  With this configuration, the signal transmission frequency in the transmission path from the interleave circuit 230 to the second adder 226 can be reduced to half that in FIG. 12, that is, fs / 2, and there is no aperture effect. Is realized.

  FIG. 14 shows a configuration of a 4-way signal processing apparatus 250 using a partial response system. The signal processing apparatus 250 mainly includes a plurality of sub-paths provided by multiplexing a part of the signal transmission path, here, four sub-paths 152, 156, 160, 164 corresponding to four ways. A unit 150 and a frequency compensation unit 172 provided in series with the frequency reduction unit 150 are included. An interference control unit 132 that controls interference between a plurality of sub-paths of the signal is provided in front of the frequency reduction unit 150. A low-pass filter 174 is provided after the interference control unit 132.

  The interference control unit 132 corresponds to an integration circuit including the first adder 220 and the first delay unit 222 shown in FIG. The interference control unit 132 includes a first adder 134, a second adder 136, a third adder 138, a first delay unit 140, a second delay unit 142, and a third delay unit 144. When the input signal X takes a binary value of “1” and “0”, each of these adders obtains an exclusive OR of two inputs. When the binarization circuit signal X takes a binary value of “1” and “−1”, the logical product of the two inputs is calculated.

  The input signal X is supplied to the first adder 134. The output of the first adder 134 is input to the second adder 136. The output of the second adder 136 is input to the third adder 138. The output of the third adder 138 is input to the frequency reduction unit 150 and the third delay unit 144.

  The output of the third delay device 144 is input to the third adder 138 and the second delay device 142. The output of the second delay unit 142 is input to the second adder 136 and the first delay unit 140. The output of the first delay device 140 is input to the first adder 134. In general, when N ways (N is an integer of 2 or more) sub-paths are provided, the interference control unit 132 may be configured by a ladder of N adders and N delay units, as in the example of FIG. Good.

The frequency reduction unit 150 corresponds to an extension of the interleave circuit 230 of FIG. 13 to 4 ways. The first sub-path 152 of the frequency reduction unit 150 does not include a delay device. The second sub path 156 includes one delay device 154. Third sub-path 160 includes two delays 158. The fourth sub path 164 includes three delay units 162. In other words, each of the plurality of sub-paths includes a different number of delay elements in a state where none of the two sub-paths is shared. In general, when N-way sub-paths are provided, the transfer function Fi (z) (i = 0, 1,..., N−1) of each sub-path is Fi (z) = z ⁻ⁱ
Can be written.

  The frequency compensation unit 172 corresponds to an extension of the second adder 226 and the second delay 224 in FIG. 13 to 4 ways. The frequency compensation unit 172 includes an adder 170 that obtains an exclusive OR of signals appearing at the ends of the first sub-path 152, the second sub-path 156, the third sub-path 160, and the fourth sub-path 164. . However, when the input signal X is “1” or “−1”, it is replaced with an arithmetic unit that calculates a logical product as before.

  As described above, according to the signal processing device 250, the frequency of signal transmission in the four sub-paths 152, 156, 160, and 164 can be reduced to ¼ of the sampling frequency fs. In general, when performing N-way interleaving, the frequency can be reduced to 1 / N.

Embodiment 3
An example of a semiconductor device test apparatus using the signal processing apparatus according to the first and second embodiments will be described. Here, an analog device is considered as the device under test. However, there is no problem even if the configuration includes any one of the first embodiment and the second embodiment.

  FIG. 15 is a configuration diagram of a semiconductor device test apparatus 300 according to the third embodiment. The semiconductor device test apparatus 300 includes a pre-processing unit 302 that generates a test signal to be supplied to the device under test 312 and a post-processing unit 314 that inspects a signal output from the device under test 312 when the test signal is applied. . The pre-processing unit 302 and the post-processing unit post-processing circuit 314 constitute the main test unit 320.

  The preprocessing unit 302 includes a pattern generator 304 that generates a test signal as a digital signal, a timing generator 310 that generates a timing signal therefor, and a digital signal generated by the pattern generator 304 that converts the digital signal into an analog signal. / A conversion unit 306 and a signal path multiplexer 308 that multiplexes a part of the transmission path of the analog signal obtained as a result of the conversion.

  The D / A conversion unit 306 includes, for example, the configuration shown in FIG. 6, specifically, a plurality of interleaved ΣΔ modulators 60, particularly a D / A converter and frequency compensation for receiving the outputs of the plurality of ΣΔ modulators 60. Unit 28. Here, due to the action of the frequency compensation unit 28, the frequency at which the signal is transmitted as the entire D / A conversion unit 306 can be set higher than the frequency at which each of the plurality of ΣΔ modulators 60 transmits the signal.

  The signal path multiplexing apparatus 308 includes, for example, the configuration shown in FIG. 14, and specifically includes an interference control unit 132, a frequency reduction unit 150 having a plurality of sub paths, a frequency compensation unit 172, and a low-pass filter 174. Here, due to the action of the frequency compensation unit 172, the frequency at which signals are transmitted as a whole of the signal path multiplexer 308 can be set higher than the frequency at which signals are transmitted in a plurality of sub-paths. With the configuration of the preprocessing unit 302 described above, an analog signal test signal is given to the device under test.

  On the other hand, the post-processing unit post-processing circuit 314 verifies the device under test by comparing the A / D converter 318 that converts the analog signal output from the device under test 312 into a digital signal, and the digital signal and the expected signal. A test result verification device 316 is included. The expected signal is given from the pattern generator 304 to the test result verification device 316.

  Note that the signal processing apparatuses according to the first and second embodiments are not necessarily limited to being in the preprocessing unit 302, and can be provided at any location on the signal transmission path.

  As described above, according to the semiconductor device test apparatus 300, the test signal can be generated first as a digital signal, and the test result can be verified by the digital signal, so that the processing becomes relatively easy. In addition, the device under test 312 can input and output a very high-speed analog signal, and can provide a semiconductor device test apparatus with high performance and high versatility.

  Although several embodiments have been described, the technical scope of the present invention is not limited to these descriptions. It will be understood by those skilled in the art that various modifications or improvements can be added to these embodiments. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

20, 70, 130, 250 Signal processor 22 First waveform shapers 24, 36, 38, 40, 42, 56, 140, 142, 144, 154, 15
8, 162, 222, 226 Delay devices 26, 32, 34, 54, 58, 134, 136, 138, 170, 220, 2
24 Adder 28, 150, 172 Frequency compensation unit 30 Modulation unit 44 Binarization circuit 52 Second waveform shaper 60, 62 ΣΔ modulator 64, 230 Interleave circuit 72, 174 Low pass filter 80, 100 First waveform sub shaper 82, 102 Second waveform sub-shaping device 84, 104 n-th waveform sub-shaping device 120, 122 Second-order ΣΔ modulator 132 Interference control unit 152, 156, 160, 164 Sub-path 182, 184, 186, 188 Flip-flop 300 Semiconductor Device test apparatus 302 Pre-processing unit 304 Pattern generator 306 D / A conversion unit 308 Signal path multiplexer 314 Post-processing unit 320 Main test unit

Claims (21)

An apparatus for processing and transmitting a signal at a predetermined reference frequency,
A modulation unit including a plurality of modulators provided in parallel on a signal transmission line, each having a function of shaping quantization noise generated when a signal is quantized;
A frequency compensation unit provided in series with the modulation unit on the transmission line,
The modulation unit performs modulation based on a second frequency that is lower than the reference frequency, while the frequency compensation unit performs frequency compensation processing so that the quantization noise is shaped based on the reference frequency. A signal processing apparatus characterized by performing the processing.   The frequency compensation unit includes a first waveform shaper and a second waveform shaper, and the transfer function of the first waveform shaper and the transfer function of the second waveform shaper are reciprocal numbers. The signal processing apparatus according to claim 1. 3. The modulation unit according to claim 2, wherein the modulation unit includes N (N = ²ⁿ , where n is a natural number) modulators, and the second frequency is 1 / N of the reference frequency. Signal processing device.   The signal processing apparatus according to claim 3, wherein each of the N modulators is an m-order (m is a natural number) ΣΔ modulator. The transfer function H1 (z) of the first waveform shaper is
H1 (z) = (1 + z ⁻¹ ) ^m (1 + z ⁻² ) ^m (1 + z ^{−N / 2} ) ^m
And the transfer function of the second waveform shaper is H2 (z)
H2 (z) = 1 / (1 + z ⁻¹ ) ^m (1 + z ⁻² ) ^m (1 + z ^{−N / 2} ) ^m
The signal processing apparatus according to claim 4, wherein:   3. The first waveform shaper is disposed on the transmission path before the modulation unit, and the second waveform shaper is disposed on the transmission path after the modulation unit. 6. The signal processing device according to any one of 5 above. A low-pass filter,
6. The device according to claim 2, wherein the second waveform shaper, the low-pass filter, and the first waveform shaper are arranged in this order after the modulation unit on the transmission line. The signal processing apparatus as described. An apparatus for processing and transmitting a signal at a predetermined reference frequency,
A frequency reduction unit including a plurality of sub-paths provided by multiplexing a part of a signal transmission path;
A frequency compensation unit provided in series with the frequency reduction unit on the transmission line,
The plurality of sub-paths transmit the signal at different timings based on a second frequency lower than the reference frequency, while the frequency compensation unit transmits the signals transmitted at the different timings. The signal processing apparatus is integrated into a form performed based on the reference frequency.   The signal processing apparatus according to claim 8, wherein the frequency reduction unit receives an output signal of a ΣΔ modulator as the signal.   The plurality of sub-paths each include a different number of delay elements in a state where none of the two sub-paths is shared, and the timing is determined according to the number of the delay elements. Item 10. The signal processing device according to any one of Items 8 and 9.   The frequency reduction unit includes N (N is an integer of 2 or more) sub-paths, and the second frequency is 1 / N of the reference frequency. A signal processing device according to 1. The signal according to claim 11, wherein the transfer function Fi (z) (i = 0, 1, ..., N-1) of each of the N sub-paths is Fi (z) = z- ^i. Processing equipment.   The signal processing apparatus according to claim 8, wherein the frequency compensation unit is an adder that analogally adds a plurality of signals appearing at the ends of the plurality of sub-paths.   The signal processing apparatus according to claim 8, wherein the frequency compensation unit is an arithmetic unit that calculates an exclusive OR of a plurality of signals appearing at the ends of the plurality of sub-paths.   The signal processing apparatus according to claim 8, wherein the frequency compensation unit is a multiplier that calculates a logical product of a plurality of signals appearing at the ends of the plurality of sub-paths.   The signal processing apparatus according to claim 8, further comprising a low-pass filter after the frequency compensation unit in the transmission path.   The signal processing apparatus according to claim 8, further comprising an interference control unit that controls interference between the plurality of sub-paths of the signal.   The signal processing apparatus according to claim 17, wherein the interference control unit is configured based on a partial response method. An apparatus for testing a semiconductor device,
A main test unit that applies a test signal to the device under test and inspects the signal output from the device under test;
In the main test unit, a part of the path for processing the test signal is multiplexed, and the frequency for processing the test signal at the multiplexed location is the same as the test signal for the main test unit as a whole. A semiconductor device test apparatus, wherein the test apparatus is set lower than a reference frequency for processing. The main test unit includes a preprocessing unit that generates a test signal to be supplied to the device under test.
The pretreatment unit is
A pattern generator for generating the test signal as a digital signal;
A D / A conversion unit for converting a digital signal generated by the pattern generator into an analog signal;
The D / A conversion unit is
With multiple interleaved modulators,
A frequency compensation unit receiving the outputs of the plurality of modulators,
20. The frequency at which a signal is transmitted as the whole D / A conversion unit is set higher than the frequency at which each of the plurality of modulators transmits a signal by the action of the frequency compensation unit. The semiconductor device test apparatus described in 1. The main test unit includes a preprocessing unit that generates a test signal to be supplied to the device under test.
The pretreatment unit is
A pattern generator for generating the test signal as a digital signal;
A D / A conversion unit for converting a digital signal generated by the pattern generator into an analog signal;
A signal path multiplexing device that multiplexes a part of the transmission path of the analog signal,
The signal path multiplexing device comprises:
A frequency reduction unit including a plurality of sub-paths;
A frequency compensation unit provided in series with the frequency reduction unit on the transmission line,
21. The frequency of transmitting a signal as a whole of the signal path multiplexing device is set higher than the frequency of transmitting a signal in the plurality of sub-paths by the action of the frequency compensation unit. The semiconductor device test apparatus according to any one of the above.

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