JP2009076555A - Multilayer resist, processing method thereof, and etching method using multilayer resist - Google Patents

Abstract

In manufacturing a semiconductor device, a processing dimension smaller than a lithography dimension is obtained.
A multilayer resist processing method includes a step (a) of sequentially forming a lower layer 4, an intermediate layer 5 and an upper layer resist 6 on a substrate 1, and a first method by patterning the upper layer resist 6 by a lithography technique. The step (b) of providing the upper layer opening 16 having the size and the intermediate layer 5 are dry-etched using the upper layer resist 6 as a mask, thereby forming the intermediate layer opening 15 having the second size below the upper layer opening 16. A step (c) and a step (d) of forming a lower layer opening 14 having a third dimension below the intermediate layer opening 15 by dry etching the lower layer 4 using the intermediate layer 5 as a mask. In the step (c), the third dimension is made smaller than the first dimension in the step (d) by forming the intermediate layer opening 15 in a shape in which the second dimension is smaller in the lower part than in the upper part.
[Selection] Figure 1

Description

  The present invention relates to a multilayer resist for processing a semiconductor, an etching method thereof, and an etching method using the multilayer resist.

  With the miniaturization and high integration of semiconductor devices, the demand for reducing the aperture size in lithography technology has become very strict. For example, with a design rule of 65 nm or less, the opening size of the lithography related to the hole size is 80 nm, which is very fine.

  For this reason, the introduction of techniques such as ArF resist, ArF immersion exposure, etc., is progressing for the exposure technique with a design rule of 65 nm or less. On the other hand, since the depth of focus decreases as the exposure wavelength becomes shorter and the aperture size decreases, the resist is made thinner than before. As described above, in a fine process with a design rule of 65 nm or less, along with CD (Critical Dimension) control and resist thinning for securing an exposure margin, an increase in dimension due to insufficient resist residual film during etching, Formation defects have become a problem.

  On the other hand, a process using a multilayer resist has been reported as a known technique as one technique for securing a resist residual film during etching (see, for example, Patent Document 1). Here, the multilayer resist process is a method of using a combination of at least two types of resist layers, ie, a thick lower layer and a sufficiently thin upper layer resist for realizing a high resolution of lithography.

  Hereinafter, an example of a processing process using a conventional multilayer resist will be described with reference to FIGS.

  First, as shown in FIG. 8A, a silicon nitride film 102 is deposited on a semiconductor substrate 101, a silicon oxide film 103 is deposited thereon, and then a lower layer 104, an intermediate layer 105, and a silicon oxide film 103 are deposited on the silicon oxide film 103. An upper resist 106 is deposited in this order. Thereafter, the upper resist 106 is patterned through a lithography process.

  Next, as shown in FIG. 8B, the intermediate layer 105 is patterned by dry etching using the patterned upper resist 106 as a mask.

  Next, as shown in FIG. 8C, the lower layer 104 is patterned by dry etching using the patterned intermediate layer 105 as a mask.

Next, as shown in FIG. 8D, a contact hole pattern is formed by etching the underlying silicon oxide film 103 using the patterned lower layer 104 as a mask.
JP-A-6-196450

  However, in the case of a conventional multilayer resist processing method, the intermediate layer 105 and the lower layer 104 are etched when forming the multilayer resist mask pattern. For this reason, etching is performed twice in total, and the etching in the lateral direction proceeds, and as shown in FIG. 8E, the upper resist 106 when exposed and patterned (shown by a broken line in FIG. 8E). The patterning dimension of the multilayer resist mask (intermediate layer 105 and lower layer 104) after etching is larger than the lithography dimension of.

  Further, in the case of a design rule of 65 nm or less, the opening size in the contact hole lithography process is as very small as 100 nm or less. For this reason, it is difficult to control a stable aperture even by using the latest lithography technology capable of realizing a high NA (numerical aperture) such as ArF exposure technology and ArF immersion exposure.

  Therefore, in further miniaturization of a semiconductor device, that is, device development based on a design rule of 65 nm or less, size reduction in the dry etching process is an essential technology.

  Here, as an example of a conventional dimension reduction technique, a dimension reduction technique for a two-layer resist will be described with reference to FIGS.

  First, as shown in FIG. 9A, a silicon nitride film 102 is deposited on a semiconductor substrate 101, a silicon oxide film 103 is deposited thereon, and then an antireflection film 107 and an upper layer are formed on the silicon oxide film 103. A resist 106 is deposited in this order. Thereafter, the upper resist 106 is patterned through a lithography process.

Next, as shown in FIG. 9B, the antireflection film 107 is dry etched using the patterned upper resist 106 as a mask. At this time, if etching is performed using a gas having a high C (carbon) / F (fluorine) ratio, such as C ₄ F ₈ or C ₅ F ₈ , the fluorocarbon polymer 108 is deposited on the pattern. The As a result, the polymer 108 reduces the resist size of the contact hole pattern.

  Next, as shown in FIG. 9C, the underlying silicon oxide film 103 is etched to form a contact pattern.

However, such a technique of reducing the size by depositing a polymer on the resist cannot be applied to the three-layer resist etching. This is because, in the case of multi-layer resist etching exceeding two layers, the lower layer is etched with an O ₂ gas, so that the polymer deposited on the resist is removed during the lower layer etching. That is, since the polymer is removed, the resist size does not decrease.

  An object of the present invention is to solve the above-mentioned problems and provide a multilayer resist for forming a fine contact smaller than the lithography dimension, an etching method thereof, and an etching method using the multilayer resist.

In order to achieve the above object, a multilayer resist processing method according to the present invention includes a step (a) of sequentially forming a lower layer, an intermediate layer and an upper layer resist on a substrate;
A step (b) of providing an upper layer opening having a first dimension by patterning the upper layer resist by a lithography technique, and dry etching the intermediate layer using the upper layer resist as a mask, so that a second dimension is formed below the upper layer opening. A step (c) of forming an intermediate layer opening having a step, and a step (d) of forming a lower layer opening having a third dimension below the intermediate layer opening by dry etching the lower layer using the intermediate layer as a mask. In the step (c), the intermediate layer opening is formed in a shape in which the second dimension is smaller in the lower part than in the upper part, so that the third dimension is made smaller than the first dimension in the step (d). To do.

  According to the multilayer resist etching method of the present invention, it is possible to provide a lower layer having a pattern dimension (third dimension) smaller than the pattern dimension (first dimension) formed in the upper resist by lithography. it can. This is realized by making the size of the intermediate layer opening formed in the intermediate layer smaller in the lower part than in the upper part (second dimension). In this way, since the lower layer can be used as a resist mask having a pattern that is smaller than the lithography dimension, a pattern that is finer than the lithography dimension can be processed.

  In the step (c), it is preferable to form the intermediate layer opening in a forward tapered shape.

  As an example of a shape in which the second dimension is smaller in the lower portion than in the upper portion, a forward tapered shape can be used.

  Further, it is preferable that the upper layer resist and the intermediate layer have a processing selection ratio, and the intermediate layer and the lower layer have a processing selection ratio.

  That is, when the upper layer resist is processed by a lithography technique, the upper layer resist can be selectively removed with respect to the intermediate layer, and the lower layer and the intermediate layer preferably have etching selectivity. If it has become like this, processing of each of three layers can be performed appropriately.

  The lower layer is preferably made of a material having an aromatic ring, and the intermediate layer is preferably made of a material containing silicon.

  In the step (c), dry etching is preferably performed using a gas containing hydrogen atoms.

  In this case, since the etching gas contains hydrogen atoms, the polymer is formed conformally (uniformly) on the side wall and bottom surface of the opening in the middle of the formation in the process of forming the opening in the intermediate layer. Etching proceeds. Since the bottom polymer removal is faster than the side polymer removal due to etching anisotropy, the interlayer opening is etched in a tapered shape. That is, an intermediate layer opening having a shape in which the second dimension decreases from top to bottom can be obtained.

  In step (c), a first step of performing dry etching without applying RF power to the lower electrode of the etching apparatus; and a second step of performing dry etching by applying RF power after the first step; Is preferably performed.

  In this way, when dry etching is performed by applying RF (Radio Frequency) power, removal of the polymer on the bottom surface is faster than removal of the polymer on the side wall by anisotropic etching. Further, when dry etching is performed without applying RF power, the etching proceeds isotropically while forming a polymer conformally on the side wall and bottom surface of the opening in the middle of formation. As a result, the intermediate layer opening is etched in a tapered shape.

  Further, it is preferable that the first step and the second step are alternately repeated in a pulse shape.

  In this way, the step of forming a uniform polymer and the step of anisotropic etching are alternately repeated, and the intermediate layer opening can be etched in a tapered shape.

  In the step (c), dry etching is preferably performed using a gas containing Ar.

  In this way, the intermediate layer opening can be etched into a tapered shape.

  Further, in the step (c), it is preferable to perform dry etching while changing from a condition in which the gas C / F ratio is large to a condition in which the C / F ratio is small.

  In this way, the intermediate layer opening can be etched into a tapered shape.

  In the step (a), it is preferable that the intermediate layer has a structure in which a plurality of films are stacked, and that the lower film of the plurality of films has a lower silicon content than the upper film. .

  In the material constituting the film, the lower the silicon content, the higher the carbon content. Therefore, when dry etching is performed using a CF-based gas, the etching rate decreases as the silicon content decreases. Therefore, when the opening is provided in the intermediate layer of the laminated structure, the progress of the etching in the lateral direction is suppressed in the lower layer film, and the dimension of the intermediate layer opening (second dimension) decreases from the top to the bottom.

  In the step (a), it is preferable to provide an intermediate layer having a silicon concentration gradient so that the silicon content increases from bottom to top.

  In this way, due to the difference in the etching rate due to the difference in the silicon content, the intermediate layer opening has a dimension from the top to the bottom (second dimension) as in the case where the intermediate layer has a laminated structure. It is formed in a tapered shape that becomes smaller.

  In addition, it is preferable to form the intermediate layer having the gradient of the silicon concentration by the CVD method.

  As a method for realizing the above-described gradient of silicon concentration in the intermediate layer, the intermediate layer may be formed by a CVD (Chemical Vapor Deposition) method.

  In the step (a), the intermediate layer has a structure in which a plurality of films are stacked, and the lower layer of the plurality of films has a lower etching rate with respect to a predetermined etching gas than the upper layer. It is preferable to do.

  In this way, when the intermediate layer opening is formed in the intermediate layer of the laminated structure, the progress of the lateral lateral etching is suppressed in the lower layer film, and the intermediate layer opening has a size from top to bottom. It is formed in a tapered shape that becomes smaller.

In order to achieve the above object, an etching method using a multilayer resist of the present invention comprises a step (a) of sequentially forming a lower layer, an intermediate layer and an upper layer resist on a substrate,
A step (b) of providing an upper layer opening having a first dimension by patterning the upper layer resist by a lithography technique, and dry etching the intermediate layer using the upper layer resist as a mask, so that a second dimension is formed below the upper layer opening. A step (c) of forming an intermediate layer opening having a step, and a step (d) of forming a lower layer opening having a third dimension below the intermediate layer opening by dry etching the lower layer using the intermediate layer as a mask. And a step (e) of forming a film opening under the lower layer opening by dry-etching the film to be processed using the lower layer as a mask. In the step (c), the second dimension is lower than the upper part. By forming the intermediate layer opening in a reduced shape, the third dimension is made smaller than the first dimension in step (d).

  According to the etching method using the multilayer resist of the present invention, the lower layer having the pattern dimension (third dimension) reduced from the pattern dimension (first dimension) formed in the upper resist by the lithography technique is provided. be able to. By performing etching using such a lower layer as a mask, an opening (a film opening to be processed) having a size smaller than the lithography dimension can be provided in the film to be processed.

  In the step (c), it is preferable to use a multilayer resist characterized by forming an intermediate layer opening in a forward tapered shape.

  As an example of a shape in which the second dimension is smaller in the lower part than in the upper part, a forward tapered shape may be used.

  In order to achieve the above object, the first multilayer resist of the present invention includes a lower layer having an aromatic ring and containing carbon, formed on a substrate, and laminated on the lower layer and containing silicon. The intermediate layer includes an upper layer resist stacked on the intermediate layer, and the intermediate layer has a structure in which a plurality of films are stacked, and the silicon content in the lower layer of the plurality of films is higher than that in the upper layer. Less is.

  In addition, the second multilayer resist of the present invention includes a lower layer having an aromatic ring and containing carbon, an intermediate layer laminated on the lower layer and containing silicon, and an intermediate layer formed on the substrate. The intermediate layer includes an upper layer resist to be stacked, and the intermediate layer has a silicon concentration gradient so that the silicon content increases from the bottom to the top.

  The third multilayer resist of the present invention comprises a lower layer having an aromatic ring and containing carbon, an intermediate layer laminated on the lower layer and containing silicon, and an intermediate layer formed on the substrate. The intermediate layer has a structure in which a plurality of films are stacked. The lower layer of the plurality of films has a lower etching rate with respect to a predetermined etching gas than the upper layer.

  According to the first to third multilayer resists of the present invention, an intermediate layer opening having a shape whose size decreases from top to bottom is obtained by dry etching the intermediate layer using the upper layer resist provided with the upper layer opening by lithography technology as a mask. Can be provided. For this reason, a lower layer opening smaller than the upper layer opening can be provided for the lower layer. By performing processing using such a lower layer as a mask, it is possible to form a pattern smaller than the lithography dimension.

  According to the multilayer resist of the present invention, the etching method thereof, and the etching method using the multilayer resist, the dimension of the interlayer opening provided in the interlayer can be reduced from the top to the bottom. For this reason, it is possible to form a lower layer having a reduced pattern as compared with an upper resist that is patterned by a lithography technique, and it is possible to process a pattern that is smaller than the lithography dimension.

(First embodiment)
Hereinafter, a multilayer resist and a processing method thereof according to a first embodiment of the present invention will be described with reference to the drawings. 1A to 1D are cross-sectional views showing the steps of forming and etching a multilayer resist. FIG. 2A shows the relationship between the CF ₄ / CHF ₃ flow rate ratio and the machining dimension, and FIGS. 2B and 2C show the relationship between the CHF ₃ flow rate and the machining shape.

  First, as shown in FIG. 1A, a silicon nitride film 2 having a thickness of about 30 nm is formed on a semiconductor substrate 1 by, eg, CVD. Subsequently, a silicon oxide film 3 having a thickness of 400 nm is formed on the silicon nitride film 2 by, eg, CVD. Further, on the silicon oxide film 3, a lower layer 4 having a thickness of 250 nm, an intermediate layer 5 having a thickness of 90 nm, and an upper resist 6 having a thickness of 150 nm are formed in this order from the bottom.

  Here, the lower layer 4 is formed of a material containing a carbon atom and having an aromatic ring (for example, a coating film of a novolac resist material). The intermediate layer 5 is formed of a resist material containing silicon (for example, a siloxane material). The upper layer resist 6 is formed using, for example, a chemically amplified resist based on an acrylic polymer.

  Thereafter, a hole pattern (upper layer opening 16) having a lithography diameter L1 of 90 nm is formed in the upper layer resist 6 using ArF excimer laser lithography.

  Next, as shown in FIG. 1B, the intermediate layer 5 is dry-etched using the upper layer resist 6 provided with the upper layer opening 16 as a mask to form the intermediate layer opening 15 below the upper layer opening 16. At this time, the hole shape of the intermediate layer opening 15 is a tapered shape having a top dimension L2 of 100 nm and a bottom dimension L3 of 70 nm. Since the sidewall of the upper layer opening 16 is also etched in the etching process of the intermediate layer 5, the top dimension L 2 of the intermediate layer opening 15 is larger than the lithography diameter L 1 of the upper layer opening 16.

  Thus, processing the intermediate layer 5 by etching and providing the tapered intermediate layer opening 15 whose size decreases from the top to the bottom is one of the features of the multilayer resist and the processing method thereof according to this embodiment. This will be described in more detail later.

  Next, as shown in FIG. 1C, the lower layer 4 is etched using the intermediate layer 5 provided with the intermediate layer opening 15 and the upper layer resist 6 remaining thereon as a mask.

An example of a dry etching method for this purpose is as follows. That is, the etching gas is set to CO / O ₂ / Ar = 100/50/500 sccm, the pressure in the etching atmosphere is set to 15 mTorr, and the substrate temperature is set to 20 ° C. In addition, using a 2-frequency RIE etching, the RF power is 1500 W for the upper electrode and 300 W for the lower electrode.

In the case of etching using such a CO / O ₂ / Ar-based gas, etching is mainly performed with oxygen radicals, so that the selectivity with respect to the intermediate layer 5 that is a resist containing Si is high. When a specific etching rate is illustrated, it is 250 nm / min for the lower layer 4, 10 nm / min for the intermediate layer 5, and the selection ratio is 25 or more.

  Therefore, the lower layer 4 can be etched without almost etching the intermediate layer 5, and the lower layer 4 can be etched without changing the bottom dimension L 3 of the intermediate layer opening 15.

  Further, the etching of the lower layer 4 is performed by optimizing the conditions so that the lower layer 4 is not laterally expanded by side etching.

  Thereby, the hole-shaped lower layer opening 14 having both the top dimension L4 and the bottom dimension L5 of 70 nm can be formed. The upper layer resist 6 is etched and disappears while the lower layer 4 is being etched.

  Subsequently, the process shown in FIG. That is, the silicon oxide film 3 is dry-etched using the intermediate layer 5 and the lower layer 4 as a mask. At this time, the intermediate layer 5 containing Si is also etched away. Moreover, about the lower layer opening 14 formed in the lower layer 4, the corner | angular part of the side wall upper part is shaved and an upper part will spread. However, by controlling the etching conditions, the film thickness of the lower layer 4 and the like so that the corner-cut portion does not reach the silicon oxide film 3, the silicon oxide film 3 is processed almost vertically to make contact. Hole 13 can be obtained. The bottom dimension L6 of the contact hole 13 is 60 nm.

  As described above, the bottom dimension L6 of the contact hole 13 is 60 nm, which is further narrower than 70 nm, which is the bottom dimension L5 of the lower layer 4. This is because, in the case of the present embodiment, contact etching is stopped by a nitride film serving as a base stopper film during oxide film etching. In this case, since the etching is performed under a condition with a large amount of polymer, the contact shape becomes a tapered shape, and the bottom dimension becomes smaller than the lithographic dimension.

  An etching step for removing the intermediate layer 5 (see FIG. 1C) remaining on the lower layer 4 may be added before etching the silicon oxide film 3.

  In this way, a contact hole having a bottom dimension L6 having a diameter of 60 nm, which is reduced by 30 nm from the lithography diameter L1 (90 nm) of the upper layer opening 16 provided in the upper layer resist 6, can be obtained.

Below, the etching method of the intermediate | middle layer 5 shown in FIG.1 (b) is further demonstrated. An example of the dry etching method of the intermediate layer 5 in the present embodiment is as follows. That is, the etching gas is set to CF ₄ / CHF ₃ = 200/40 sccm, the pressure of the etching atmosphere is set to 100 mTorr, and the substrate temperature is set to 20 ° C. A two-frequency RIE etching apparatus is used, and the RF power is 600 W for the upper electrode and 300 W for the lower electrode.

Here, the dependency of the etching gas on the CF ₄ / CHF ₃ flow rate ratio with respect to the bottom dimension L3 of the intermediate layer opening 15 and the bottom dimension L6 of the contact hole 13 is shown in FIG. As shown in FIG. 2A, when the CF ₄ / CHF ₃ flow rate ratio is low, the bottom dimension L 6 of the contact hole 13 as well as the bottom dimension L 3 of the intermediate layer opening 15 becomes small. That is, it can be seen that the bottom dimension L6 of the contact hole 13 can be reduced by reducing the bottom dimension L3 of the intermediate layer opening 15.

FIG. 2B shows cross-sectional shapes after etching the intermediate layer 5 and after etching the lower layer 4 when the CHF ₃ flow rate is 0 sccm and 40 sccm. As shown in FIG. 2B, by adding CHF ₃ , the intermediate layer opening 15 can be tapered and the bottom dimension L3 can be made smaller than the top dimension L2.

This is because H is contained in CHF ₃ added to the etching gas, so that a polymer is conformally formed on the entire surface and side surfaces of the intermediate layer opening 15 in the middle of formation. That is, since the etching in the depth direction (longitudinal direction) proceeds at a higher rate than the etching in the lateral direction because it is anisotropic etching, the polymer is left in the lateral direction due to the polymer left on the side surface as the intermediate layer opening 15 becomes deeper. The dimensions of are reduced.

In the present embodiment, the CHF ₃ gas is used to make the intermediate layer opening 15 have a tapered shape, but the present invention is not limited to this. For example, the same effect can be realized if it is a fluorohydrocarbon compound containing hydrogen such as CH ₃ F and CH ₂ F ₂ .

(Second Embodiment)
Hereinafter, a multilayer resist and a processing method thereof according to the second embodiment of the present invention will be described with reference to the drawings. FIGS. 3A to 3C are cross-sectional views showing the steps of forming and etching the multilayer resist, and FIG. 3D is a view showing application of RF power to the lower electrode during etching.

  First, as shown in FIG. 3A, a structure in which a silicon nitride film 2, a silicon oxide film 3, a lower layer 4, an intermediate layer 5 and an upper layer resist 6 are stacked in this order from the bottom on a semiconductor substrate 1 is formed. Further, a hole pattern (upper layer opening 16) having a lithography diameter of 90 nm is formed in the upper layer resist 6. The steps so far are the same as those described in the first embodiment with reference to FIG.

  Next, as shown in FIG. 3B, the intermediate layer 5 is etched using the upper layer resist 6 provided with the upper layer opening 16 as a mask. Thereby, the intermediate layer opening 15 having a hole shape with a top dimension of 100 nm and a bottom dimension of 70 nm is formed.

  The formation of the intermediate layer opening 15 having a bottom dimension smaller than the top dimension is one of the features of the multilayer resist and the processing method thereof according to the present embodiment, as in the first embodiment. This will be described in more detail later.

  Subsequently, the process of FIG. First, the lower layer opening 14 is formed in the lower layer 4 using the intermediate layer 5 in which the intermediate layer opening 15 is formed as a mask. Subsequently, the silicon oxide film 3 is dry-etched using the lower layer 4 provided with the lower layer opening 14 as a mask to form a contact hole 13 in the silicon oxide film 3. At this time, the lower opening 14 is cut off at the corner of the upper portion of the side wall and the upper portion is widened. By setting the etching conditions so that the portion to be cut does not reach the silicon oxide film 3, the contact hole 13 is formed. Can be processed vertically. An etching process for removing the intermediate layer 5 remaining on the lower layer 4 may be added before etching the silicon oxide film 3. Such steps are the same as those shown in FIGS. 1C and 1D in the first embodiment.

  In this manner, the contact hole 13 having a bottom dimension that is smaller than the lithography diameter of the upper layer opening 16 provided in the upper layer resist 6 can be obtained.

Next, an example of a method for etching the intermediate layer 5 shown in FIG. In this embodiment, C ₄ F ₈ / CF ₄ = 6/100 sccm is used as the etching gas. Unlike the etching gas used in the first embodiment, a gas containing H is not used. Further, the pressure of the etching atmosphere is set to 100 mTorr, and the substrate temperature is set to 20 ° C. In addition, the RF power of the upper electrode is set to 600 W using a two-frequency RIE etching apparatus. Further, for the lower electrode RF power, as shown in FIG. 3D, the step of applying the RF power of 300 W and the step of not applying the RF power are combined.

  During etching, when no RF power is applied to the lower electrode, no ions are attracted to the lower electrode. For this reason, the deposition reaction of the polymer becomes dominant, the etching hardly proceeds, and the polymer is deposited on the entire surface of the wafer. At this time, the polymer is also deposited on the side surface of the upper layer opening 16.

  In contrast, when RF power is applied to the lower electrode during etching, ions are attracted and the reaction proceeds as anisotropic etching. For this reason, in the intermediate layer opening 15 in the middle of formation, the etching for the bottom polymer is faster and the downward etching proceeds faster than the etching for the polymer on the wall surface.

  Accordingly, by performing etching without applying RF power in the first step, and performing etching by applying RF power as the next second step, the intermediate layer 5 has a tapered shape as shown in FIG. The intermediate layer opening 15 can be formed.

  That is, since the polymer deposited on the side surface of the upper layer opening 16 in the first step narrows the upper layer opening 16, the range etched in the vertical direction in the second step becomes gradually wider. As a result, a tapered intermediate layer opening 15 is formed.

  In the example shown in FIG. 3D, the step of not applying the RF power and the step of applying it are repeated. In this way, the intermediate layer opening 15 can be tapered more reliably.

  Further, since the deposition of the polymer occurs when the RF power is applied, the etching is terminated in the state where the RF power is applied to prevent the polymer from remaining in the intermediate layer opening 15. However, even if the polymer remains without doing in this way, it is removed when the lower layer 5 is etched.

(Third embodiment)
Hereinafter, a multilayer resist and a processing method thereof according to a third embodiment of the present invention will be described with reference to the drawings. FIGS. 4A to 4C are cross-sectional views showing the steps of forming and etching a multilayer resist, and FIG. 4D is a view showing application of RF power to the lower electrode during etching.

  First, as shown in FIG. 4A, a structure in which a silicon nitride film 2, a silicon oxide film 3, a lower layer 4, an intermediate layer 5, and an upper layer resist 6 are stacked in this order from below on a semiconductor substrate 1 is formed. Further, a hole pattern (upper layer opening 16) having a lithography diameter of 90 nm is formed in the upper layer resist 6. The steps so far are the same as those described in the first embodiment with reference to FIG.

  Next, as shown in FIG. 4B, the intermediate layer 5 is etched using the upper layer resist 6 provided with the upper layer openings 16 as a mask. Thereby, the intermediate layer opening 15 having a hole shape with a top dimension of 100 nm and a bottom dimension of 70 nm is formed.

  The formation of the intermediate layer opening 15 having a bottom dimension smaller than the top dimension is one of the features of the multilayer resist and the processing method thereof according to the present embodiment, as in the first embodiment. This will be described in more detail later.

  Then, the process of FIG.4 (c) is performed. First, the lower layer opening 14 is formed in the lower layer 4 using the intermediate layer 5 in which the intermediate layer opening 15 is formed as a mask. Subsequently, the silicon oxide film 3 is dry-etched using the lower layer 4 provided with the lower layer opening 14 as a mask to form a contact hole 13 in the silicon oxide film 3. At this time, the lower opening 14 is cut off at the corner of the upper portion of the side wall and the upper portion is widened. By setting the etching conditions so that the portion to be cut does not reach the silicon oxide film 3, the contact hole 13 is formed. Can be processed vertically. An etching process for removing the intermediate layer 5 remaining on the lower layer 4 may be added before etching the silicon oxide film 3. Such steps are the same as those shown in FIGS. 1C and 1D in the first embodiment.

  In this manner, the contact hole 13 having a bottom dimension that is smaller than the lithography diameter of the upper layer opening 16 provided in the upper layer resist 6 can be obtained.

Next, an example of a method for etching the intermediate layer 5 shown in FIG. In this embodiment, C ₄ F ₈ / CF ₄ = 6/100 sccm is used as the etching gas, the pressure of the etching atmosphere is set to 100 mTorr, and the substrate temperature is set to 20 ° C. In addition, the RF power of the upper electrode is set to 600 W using a two-frequency RIE etching apparatus. Furthermore, as for the lower electrode RF power, as shown in FIG. 4D, 300 W RF power is alternately turned on and off and applied in a pulse form.

  In this way, when no RF power is applied to the lower electrode, ions are not attracted to the lower electrode side. For this reason, the polymer is deposited on the entire wafer surface. In contrast, when RF power is applied to the lower electrode, ions are attracted and the reaction proceeds as anisotropic etching. For this reason, in the intermediate layer opening 15 in the middle of formation, the etching for the bottom polymer is faster and the downward etching proceeds faster than the etching for the polymer on the wall surface.

  Whether or not RF power is applied to the lower electrode and the progress of etching are the same as those in the second embodiment. However, in the case of the second embodiment, the RF power is controlled so that the step of applying the RF power and the step of not applying the RF power are combined. In the case of the present embodiment, the application of the RF power to the lower electrode is performed. Is controlled to turn on and off in a pulsed manner. Thereby, the same effect as the case of 2nd Embodiment is implement | achieved, and the intermediate | middle layer opening 15 whose bottom dimension is smaller than top dimension can be formed.

(Fourth embodiment)
Hereinafter, a multilayer resist and a processing method thereof according to a fourth embodiment of the present invention will be described with reference to the drawings. FIGS. 5A to 5E are cross-sectional views showing the steps of forming and etching the multilayer resist, and FIG. 5F shows the relationship between the Si content and the etching rate in the resist containing Si. Show.

  First, the process shown in FIG. 5A is performed in the same manner as described in the first embodiment. That is, the silicon nitride film 2, the silicon oxide film 3, and the lower layer 4 are stacked on the semiconductor substrate 1 in this order from the bottom.

  Subsequently, the intermediate layer 5 is formed on the lower layer 4. However, as partially enlarged in FIG. 5B, the four material layers 5a, 5b, 5c, and 5d are stacked in this order from the bottom to form the intermediate layer 5 having a stacked structure.

  Here, all of the material layers 5a to 5d are resists containing Si, and the contents of Si are different from each other. The specific Si content of each resist layer is 18% for the material layer 5a, 22% for the material layer 5b, 25% for the material layer 5c, and 28% for the material layer 5d. Is becoming smaller. Each of the material layers 5a to 5d has a film thickness of 25 nm, and the film thickness of the four intermediate layers 5 is 100 nm.

  Next, as shown in FIG. 5C, an upper layer resist 6 having a film thickness of 150 nm is deposited on the intermediate layer 5 having a four-layer structure. Further, a hole pattern (upper layer opening 16) having a lithography diameter of 90 nm is patterned on the upper resist 6 by ArF excimer laser lithography.

  Next, as shown in FIG. 5D, the intermediate layer 5 is etched using the upper layer resist 6 having the upper layer opening 16 as a mask. As a result, an intermediate layer opening 15 having a hole shape with a top dimension of 90 nm and a bottom dimension of 60 nm is formed.

  The formation of the intermediate layer opening 15 having a bottom dimension smaller than the top dimension is one of the features of the multilayer resist and the processing method thereof according to the present embodiment, as in the first embodiment. This will be described in more detail later.

  Thereafter, the step shown in FIG. First, the lower layer opening 14 is formed in the lower layer 4 using the intermediate layer 5 in which the intermediate layer opening 15 is formed as a mask. Subsequently, the silicon oxide film 3 is dry-etched using the lower layer 4 provided with the lower layer opening 14 as a mask to form a contact hole 13 in the silicon oxide film 3. At this time, the lower opening 14 is cut off at the corner of the upper portion of the side wall and the upper portion is widened. By setting the etching conditions so that the portion to be cut does not reach the silicon oxide film 3, the contact hole 13 is formed. Can be processed vertically. An etching process for removing the intermediate layer 5 remaining on the lower layer 4 may be added before etching the silicon oxide film 3. Such steps are the same as those shown in FIGS. 1C and 1D in the first embodiment.

  In this manner, the contact hole 13 having a bottom dimension that is smaller than the lithography diameter of the upper layer opening 16 provided in the upper layer resist 6 can be obtained.

Next, an example of a method for etching the intermediate layer 5 shown in FIG. In this embodiment, CF ₄ = 200 sccm is used as the etching gas, the pressure in the etching atmosphere is set to 100 mTorr, and the substrate temperature is set to 20 ° C. Also, using a two-frequency RIE etching apparatus, the RF power of the upper electrode is 600 W and the RF power of the lower electrode is 300 W.

  When etching a resist containing Si using such an etching method, the lower the Si content of the resist, the higher the relative C content in the etching material, so the etching rate with the CF-based gas decreases. To do. This is shown in FIG.

  In addition, the intermediate layer 5 of the present embodiment has a structure in which the four material layers 5a to 5d having different Si contents are stacked as described above, and the lower the layer, the lower the Si content. For this reason, when the intermediate layer 5 is etched by the above-described etching method, the etching rate decreases as the etching proceeds downward (from the material layer 5d to the material layer 5a). As a result, since the progress of lateral etching is suppressed as the lower resist layer, the intermediate layer opening 15 formed in the intermediate layer 5 made of the material layers 5a to 5d has a hole shape whose bottom dimension is smaller than the top dimension. Can be formed.

Thus, in the present embodiment, the taper shape of the intermediate layer opening 15 is realized by utilizing the relationship between the Si content of the material layers 5a to 5d constituting the intermediate layer 5 and the etching rate. For this reason, a fluorocarbon compound such as C ₄ F ₈ or C ₅ F ₈ that forms a polymer and deposits, or a fluorohydrocarbon compound that contains hydrogen such as CH ₃ F or CH ₂ F ₂ should be added. None, a hole shape having a bottom dimension smaller than the top dimension can be realized.

In the case of the first embodiment, by adding a gas of a hydrocarbon compound or a fluorocarbon compound having a high polymer deposition property to an etching gas having a low polymer deposition property (for example, CF ₄ ), the tapered shape of the intermediate layer opening 15 is formed. Is realized. In this case, if the amount of the compound added is increased in order to increase the difference between the top dimension and the bottom dimension, there is a concern that the amount of polymer to be generated increases and etch stop occurs. On the other hand, in the case of this embodiment, it is not necessary to add a hydrocarbon-based compound or a fluorocarbon-based compound, so that a process margin for increasing the difference between the top dimension and the bottom dimension is ensured while avoiding etch stop. Can do.

  In the present embodiment, the Si content is changed by laminating the four material layers 5a to 5d so that the lower the intermediate layer 5, the lower the Si content. However, instead of this, for example, by using PECVD (Plasma Enhanced CVD) method using organosilicon siloxane, the intermediate layer opening 15 having a concentration gradient in which the Si concentration increases from the bottom to the top is realized. You may do it.

(Fifth embodiment)
Hereinafter, a multilayer resist and a processing method thereof according to a sixth embodiment of the present invention will be described with reference to the drawings. FIGS. 6A to 6C are cross-sectional views showing the steps of forming and etching the multilayer resist. FIG. 6D shows the Ar flow rate in the etching gas, the bottom dimension of the intermediate layer opening 15 and the contact hole. The relationship with 13 bottom dimensions is shown.

  First, as shown in FIG. 6A, a structure in which a silicon nitride film 2, a silicon oxide film 3, a lower layer 4, an intermediate layer 5, and an upper layer resist 6 are stacked in this order from below on a semiconductor substrate 1 is formed. Further, a hole pattern (upper layer opening 16) having a lithography diameter of 90 nm is formed in the upper layer resist 6. The steps so far are the same as those described in the first embodiment with reference to FIG.

  Next, as shown in FIG. 6B, the intermediate layer 5 is etched using the upper layer resist 6 provided with the upper layer openings 16 as a mask. Thereby, the intermediate layer opening 15 having a hole shape with a top dimension of 100 nm and a bottom dimension of 70 nm is formed.

  The formation of the intermediate layer opening 15 having a bottom dimension smaller than the top dimension is one of the features of the multilayer resist and the processing method thereof according to the present embodiment, as in the first embodiment. This will be described in more detail later.

  Subsequently, the process shown in FIG. First, the lower layer opening 14 is formed in the lower layer 4 using the intermediate layer 5 in which the intermediate layer opening 15 is formed as a mask. Subsequently, the silicon oxide film 3 is dry-etched using the lower layer 4 provided with the lower layer opening 14 as a mask to form a contact hole 13 in the silicon oxide film 3. At this time, the lower opening 14 is cut at the corner of the upper portion of the side wall so that the upper portion is widened. However, by setting the etching conditions so that the portion to be cut does not reach the silicon oxide film 3, the contact hole 13 is formed. Can be processed vertically. An etching process for removing the intermediate layer 5 remaining on the lower layer 4 may be added before etching the silicon oxide film 3. Such steps are the same as those shown in FIGS. 1C and 1D in the first embodiment.

  In this manner, the contact hole 13 having a bottom dimension that is smaller than the lithography diameter of the upper layer opening 16 provided in the upper layer resist 6 can be obtained.

Next, an example of a method for etching the intermediate layer 5 shown in FIG. In this embodiment, CF ₄ / Ar = 100/400 sccm is used as the etching gas, the pressure in the etching atmosphere is set to 100 mTorr, and the substrate temperature is set to 20 ° C. In addition, a 600 W RF power is applied to the upper electrode and a 300 W RF power is applied to the lower electrode using a two-frequency RIE etching apparatus.

  FIG. 6D shows the dependence of the bottom dimension of the intermediate layer opening 15 and the bottom dimension of the contact hole 13 on the Ar flow rate in the etching gas. As shown here, the larger the Ar flow rate, the smaller the bottom dimension of the intermediate layer opening 15 and the smaller the bottom dimension of the contact hole 13. That is, the bottom dimension of the contact hole 13 can be reduced by reducing the bottom dimension of the intermediate layer opening 15 by controlling the Ar flow rate.

(Sixth embodiment)
Hereinafter, a multilayer resist and a processing method thereof according to a sixth embodiment of the present invention will be described with reference to the drawings. 7A to 7D are cross-sectional views showing the steps of forming and etching the multilayer resist.

  First, the steps shown in FIG. 7A are performed in the same manner as described in the first embodiment. That is, the silicon nitride film 2, the silicon oxide film 3, and the lower layer 4 are stacked on the semiconductor substrate 1 in this order from the bottom.

Subsequently, the intermediate layer 5 is formed on the lower layer 4. However, as shown in a partially enlarged view in FIG. 7B, after a SiO ₂ material layer 5e made of SOG (Spin on Glass) having a film thickness of 15 nm is applied on the lower layer 4, a film thickness of 90 nm is formed thereon. The intermediate layer 5 having a two-layer structure is formed by forming the Si-containing material layer 5f.

  Subsequently, as shown in FIG. 7C, an upper resist 6 having a film thickness of 150 nm is deposited on the intermediate layer 5 having a two-layer structure. Further, a hole pattern (upper layer opening 16) having a lithography diameter of 90 nm is patterned on the upper resist 6 by ArF excimer laser lithography.

Subsequently, as shown in FIG. 7D, the intermediate layer 5 (SiO ₂ -based material layer 5e and Si-containing material layer 5f) is etched using the upper layer resist 6 having the upper layer opening 16 as a mask. Thus, the intermediate layer opening 15 having a hole shape having a top dimension of 100 nm and a bottom dimension of 70 nm is formed.

  The formation of the intermediate layer opening 15 having a bottom dimension smaller than the top dimension is one of the features of the multilayer resist and the processing method thereof according to the present embodiment, as in the first embodiment. This will be described in more detail later.

  Thereafter, the step shown in FIG. First, the lower layer opening 14 is formed in the lower layer 4 using the intermediate layer 5 in which the intermediate layer opening 15 is formed as a mask. Subsequently, the silicon oxide film 3 is dry-etched using the lower layer 4 provided with the lower layer opening 14 as a mask to form a contact hole 13 in the silicon oxide film 3. At this time, the lower opening 14 is cut at the corner of the upper portion of the side wall so that the upper portion is widened. However, by setting the etching conditions so that the portion to be cut does not reach the silicon oxide film 3, the contact hole 13 is formed. Can be processed vertically. An etching process for removing the intermediate layer 5 remaining on the lower layer 4 may be added before etching the silicon oxide film 3. Such steps are the same as those shown in FIGS. 1C and 1D in the first embodiment.

  In this manner, the contact hole 13 having a bottom dimension that is smaller than the lithography diameter of the upper layer opening 16 provided in the upper layer resist 6 can be obtained.

Next, an example of an etching method for the intermediate layer 5 shown in FIG. In this embodiment, Cl ₂ / O ₂ / Ar = 60/30/200 sccm that hardly generates a polymer is used as an etching gas, the pressure in the etching atmosphere is set to 100 mTorr, and the substrate temperature is set to 20 ° C. Also, using a two-frequency RIE etching apparatus, the RF power of the upper electrode is 600 W and the RF power of the lower electrode is 300 W.

When such an etching method is used, the Si-containing material layer 5f of the two layers constituting the intermediate layer 5 can be etched by Cl ₂ , but the SiO ₂ -based material layer 5e has an etching rate by Cl _2. Low. By utilizing this difference in rate, the bottom dimension of the intermediate layer opening 15 can be processed smaller than the top dimension.

  That is, the intermediate layer opening 15 is formed in such a manner that first, vertical etching progresses in the vicinity of the center of the bottom surface to form a dent, and the dent expands in the lateral direction. Therefore, in the layer having a low etching rate, the lateral dimension increases slowly, so that the bottom dimension of the intermediate layer opening 15 is smaller than the top dimension.

(Seventh embodiment)
Hereinafter, a multilayer resist and a processing method thereof according to a seventh embodiment of the present invention will be described with reference to the drawings. FIGS. 10A to 10C are cross-sectional views showing the steps of forming and etching the multilayer resist, and FIG. 10D shows the CF ₄ / CHF ₃ flow rate and the intermediate layer when the intermediate layer 5 is etched. The relationship with the bottom dimension of the opening 15 is shown.

  First, as shown in FIG. 10A, a structure in which a silicon nitride film 2, a silicon oxide film 3, a lower layer 4, an intermediate layer 5 and an upper layer resist 6 are stacked in this order from below on a semiconductor substrate 1 is formed. Further, a hole pattern (upper layer opening 16) having a lithography diameter of 90 nm is formed in the upper layer resist 6. The steps up to here are the same as those described in the first embodiment with reference to FIG.

  Next, as shown in FIG. 10B, the intermediate layer 5 is etched using the upper layer resist 6 provided with the upper layer openings 16 as a mask. Thereby, the intermediate layer opening 15 having a hole shape with a top dimension of 100 nm and a bottom dimension of 70 nm is formed.

  The formation of the intermediate layer opening 15 having a bottom dimension smaller than the top dimension is one of the features of the multilayer resist and the processing method thereof according to the present embodiment, as in the first embodiment. This will be described in more detail later.

  Subsequently, the step shown in FIG. First, the lower layer opening 14 is formed in the lower layer 4 using the intermediate layer 5 in which the intermediate layer opening 15 is formed as a mask. Subsequently, the silicon oxide film 3 is dry-etched using the lower layer 4 provided with the lower layer opening 14 as a mask to form a contact hole 13 in the silicon oxide film 3. At this time, the lower opening 14 is cut off at the corner of the upper portion of the side wall and the upper portion is widened. By setting the etching conditions so that the portion to be cut does not reach the silicon oxide film 3, the contact hole 13 is formed. Can be processed vertically. An etching process for removing the intermediate layer 5 remaining on the lower layer 4 may be added before etching the silicon oxide film 3. Such steps are the same as those shown in FIGS. 1C and 1D in the first embodiment.

  In this manner, the contact hole 13 having a bottom dimension that is smaller than the lithography diameter of the upper layer opening 16 provided in the upper layer resist 6 can be obtained.

Next, an example of a method for etching the intermediate layer 5 shown in FIG. In this embodiment, CF ₄ / CHF ₃ gas with a fixed total flow rate of 240 sccm is used as an etching gas, the pressure of the etching atmosphere is set to 100 mTorr, and the substrate temperature is set to 20 ° C. In addition, a 600 W RF power is applied to the upper electrode and a 300 W RF power is applied to the lower electrode using a two-frequency RIE etching apparatus.

FIG. 10D shows the dependency of the bottom dimension of the intermediate layer opening 15 on the CF ₄ / CHF ₃ gas flow rate ratio of the etching gas. As shown here, at the beginning of etching, 40 sccm of CHF ₃ gas having a deposition property is added to perform etching, and the CHF ₃ addition amount is reduced in order to prevent etching stop. In this embodiment, the CHF ₃ flow rate, which was 40 sccm, is first reduced to 20 sccm, and finally the CHF ₃ flow rate is set to 0 for etching.

A gas containing H such as CHF ₃ has an effect of scavenging F to relatively increase the amount of C in the gas (increase the C / F ratio). Therefore, the C / F ratio can be gradually reduced by gradually reducing the flow rate of CHF ₃ during the etching process.

As in the first embodiment, the bottom dimension of the intermediate layer opening 15 is reduced by adding CHF ₃ gas. Therefore, in this embodiment, the bottom dimension of the intermediate layer opening 15 can be controlled by changing the CHF ₃ gas flow rate with the etching time, and etching is performed by not adding a deposition gas in the latter half of the intermediate layer etching. This has the effect of improving the detachability of the film and preventing the occurrence of etching stop.

Instead of performing etching while reducing the flow rate of a gas containing H such as CHF ₃ , a gas having a large C / F ratio such as C ₄ F ₈ , C ₅ H ₈ , C ₄ F ₆ is added. Etching may be performed while reducing the flow rate. Also in this case, the same effect as this embodiment can be obtained.

  In each of the embodiments described above (particularly, the fourth and sixth embodiments), the case where the intermediate layer opening 15 is formed in a forward tapered shape has been described. However, the present invention is not limited to this. For example, a step shape consisting of a wide vertical opening from the upper end to the center and a narrow vertical opening from the center to the lower end, or a shape in which this step shape is repeated, is formed in a shape that becomes smaller in the lower part than in the upper part. May be. Even if it is such a shape, the effect similar to the case of a forward taper shape is acquired. Since the intermediate layer 5 is hardly etched when the lower layer 4 is etched, the bottom dimension of the intermediate layer opening 15 only needs to be smaller than the top dimension.

  As described above, the multilayer resist and the processing method thereof according to the present invention can form a mask having a pattern with a size smaller than the dimension patterned in the lithography process when processing the multilayer resist. It is particularly useful when forming a fine pattern of 65 nm or less with a small lithography exposure margin.

1A to 1D are cross-sectional views showing respective steps of a multilayer resist processing method according to the first embodiment of the present invention. FIG. 2A shows the relationship between the CF ₄ / CHF ₃ flow rate ratio and the dimension of machining, and FIGS. 2B and 2C show the relationship between the flow rate of CHF ₃ and the machining shape. FIGS. 3A to 3C are cross-sectional views showing the steps of forming and etching the multilayer resist according to the second embodiment of the present invention, and FIG. It is a figure shown about application of RF power. FIGS. 4A to 4C are cross-sectional views showing the steps of forming and etching a multilayer resist according to the third embodiment of the present invention, and FIG. It is a figure shown about application of RF power. FIGS. 5A to 5E are cross-sectional views showing the steps of forming and etching a multilayer resist according to the fourth embodiment of the present invention, and FIG. 5F shows the Si in the resist containing Si. It shows about the relationship between content of and etching rate. FIGS. 6A to 6C are cross-sectional views showing the steps of forming and etching the multilayer resist according to the fifth embodiment of the present invention, and FIG. The relationship between the bottom dimension of the intermediate layer opening 15 and the bottom dimension of the contact hole 13 is shown. 7A to 7D are cross-sectional views showing the steps of forming and etching a multilayer resist according to the sixth embodiment of the present invention. 8A to 8E are cross-sectional views showing an example of a conventional multilayer resist processing method. 9A to 9E are cross-sectional views showing another example of a conventional multi-layer resist processing method. FIGS. 10A to 10C are cross-sectional views showing the steps of forming and etching the multilayer resist according to the seventh embodiment of the present invention, and FIG. 10D shows the etching gas CF ₄ / CHF. ₃ shows the dependence of the bottom dimension of the intermediate layer opening 15 on the gas flow ratio.

Explanation of symbols

1 semiconductor substrate 2 of silicon nitride film 3 a silicon oxide film 4 lower 5 intermediate layers 5a, 5b, 5c, 5d material layer 5e SiO ₂ resist layer 5f Si-containing resist layer 6 bottom dimension L
6 Upper layer resist 13 Contact hole 14 Lower layer opening 15 Intermediate layer opening 16 Upper layer opening

Claims (18)

A step (a) of sequentially forming a lower layer, an intermediate layer and an upper layer resist on the substrate;
A step (b) of patterning the upper resist by lithography to provide an upper layer opening having a first dimension;
(C) forming an intermediate layer opening having a second dimension below the upper layer opening by dry etching the intermediate layer using the upper layer resist as a mask;
And (d) forming a lower layer opening having a third dimension below the intermediate layer opening by dry etching the lower layer using the intermediate layer as a mask,
In the step (c), the intermediate layer opening is formed in a shape in which the second dimension is smaller in the lower part than in the upper part, whereby the third dimension is changed into the first dimension in the step (d). A method for processing a multi-layer resist, characterized by being made smaller. In claim 1,
In the step (c), the intermediate layer opening is formed in a forward tapered shape. In claim 1 or 2,
The upper layer resist and the intermediate layer have processing selectivity,
A method of processing a multilayer resist, wherein the intermediate layer and the lower layer have a processing selectivity. In claim 1 or 2,
The lower layer is made of a material having an aromatic ring,
The method for processing a multilayer resist, wherein the intermediate layer is made of a material containing silicon. In any one of Claims 1-4,
In the step (c), dry etching is performed using a gas containing a hydrogen atom. In any one of Claims 1-4,
A first step of performing dry etching without applying RF power to the lower electrode of the etching apparatus in the step (c); and a second step of performing dry etching by applying RF power after the first step; A method for processing a multilayer resist, characterized in that:   7. The multilayer resist processing method according to claim 6, wherein the first step and the second step are alternately repeated in a pulse shape. In any one of Claims 1-4,
In the step (c), dry etching using a gas containing Ar is performed. In any one of Claims 1-4,
In the step (c), the multi-layer resist processing method is characterized in that dry etching is performed while changing from a condition in which the gas C / F ratio is large to a condition in which the C / F ratio is small. In any one of Claims 1-4,
In the step (a), the intermediate layer has a structure in which a plurality of films are laminated, and the lower layer of the plurality of films has a lower silicon content than the upper layer. A method of processing a multilayer resist as a feature. In any one of Claims 1-4,
In the step (a), the method for processing a multilayer resist is characterized by providing the intermediate layer having a silicon concentration gradient so that the silicon content increases from bottom to top. In claim 11,
A method for processing a multi-layer resist, wherein the intermediate layer having the silicon concentration gradient is formed by a CVD method. In claim 1,
In the step (a), the intermediate layer has a structure in which a plurality of films are stacked, and the lower layer of the plurality of films has a lower etching rate with respect to a predetermined etching gas than the upper layer. A method for etching a multi-layer resist, comprising: A step (a) of sequentially forming a lower layer, an intermediate layer and an upper layer resist on the substrate;
A step (b) of patterning the upper resist by lithography to provide an upper layer opening having a first dimension;
(C) forming an intermediate layer opening having a second dimension below the upper layer opening by dry etching the intermediate layer using the upper layer resist as a mask;
(D) forming a lower layer opening having a third dimension below the intermediate layer opening by dry etching the lower layer using the intermediate layer as a mask;
And (e) providing a processed film opening below the lower layer opening by dry etching the processed film using the lower layer as a mask,
In the step (c), the intermediate layer opening is formed in a shape in which the second dimension is smaller in the lower part than in the upper part, whereby the third dimension is changed into the first dimension in the step (d). An etching method using a multilayer resist characterized by being made smaller. In claim 14,
In the step (c), the intermediate layer opening is formed in a forward tapered shape, and an etching method using a multilayer resist. A lower layer formed on a substrate and having an aromatic ring and containing carbon; an intermediate layer stacked on the lower layer and containing silicon; and an upper layer resist stacked on the intermediate layer;
The intermediate layer has a structure in which a plurality of films are laminated,
A multilayer resist characterized in that the lower film of the plurality of films has a lower silicon content than the upper film. A lower layer formed on a substrate and having an aromatic ring and containing carbon; an intermediate layer stacked on the lower layer and containing silicon; and an upper layer resist stacked on the intermediate layer;
The multi-layer resist, wherein the intermediate layer has a silicon concentration gradient so that the silicon content increases from bottom to top. A lower layer formed on a substrate and having an aromatic ring and containing carbon; an intermediate layer stacked on the lower layer and containing silicon; and an upper layer resist stacked on the intermediate layer;
The intermediate layer has a structure in which a plurality of films are laminated,
A multilayer resist, wherein a lower layer of the plurality of films has a lower etching rate with respect to a predetermined etching gas than an upper layer.