JP2009075418A - Display device, driving circuit and driving method thereof - Google Patents

Abstract

A display device capable of reducing the amplitude of an output voltage from a source driver or a gate driver while suppressing an increase in cost is provided.
In a display device, pixel forming portions A11 to Ag8, gate wirings G1 to Gg, and auxiliary capacitance wirings C1 to Cg are grouped into a plurality of groups (for example, four). In addition, the auxiliary capacity wiring included in each group is divided into a first polarity capacity wiring and a second polarity capacity wiring. The auxiliary capacitance driver 500 applies a higher potential to the auxiliary capacitance wiring corresponding to the pixel electrode in which the positive voltage is written in the selection period than in the period in which the positive voltage is written in the non-selection period. In addition, the storage capacitor wiring corresponding to the pixel electrode in which the negative voltage is written in the selection period is given a lower potential in the selection period than in the period in which the negative voltage is written.
[Selection] Figure 1

Description

  The present invention relates to a display device such as a liquid crystal display device, and more particularly to a display device that achieves low power consumption, a driving circuit and a driving method thereof.

  In recent years, liquid crystal display devices using TFTs (Thin Film Transistors) such as notebook personal computers, mobile phones, and liquid crystal televisions have become widespread. A liquid crystal display device using such TFTs can be obtained even when the magnitude of the applied voltage is the same when a positive voltage is applied to the liquid crystal and when a negative voltage is applied to the liquid crystal. There is a difference in transmittance. Therefore, in order to suppress a decrease in display quality due to a difference in transmittance due to voltage polarity, a driving method called line inversion driving and a driving method called dot inversion driving are employed. The line inversion driving is a driving method in which the polarity of the liquid crystal applied voltage is inverted every frame period and every predetermined number of scanning signal lines. On the other hand, in the dot inversion drive, the polarity of the liquid crystal applied voltage is inverted every frame period, and the polarity between adjacent pixels in the vertical (vertical) and horizontal (horizontal) directions is also inverted within one frame period. It is a drive system. By adopting the driving method in which the polarity of the liquid crystal applied voltage is inverted between adjacent dots as described above, the deterioration in display quality due to the difference in transmittance between the positive polarity and the negative polarity is suppressed.

  FIG. 38 is a block diagram showing an overall configuration of a display device that employs line inversion driving, disclosed in Japanese Patent Laid-Open No. 2006-23404. In this display device, the auxiliary capacitance lines 218 in the display panel 211 are connected to each other, and voltages having the same waveform are applied to the auxiliary capacitance lines 218 and the counter electrode. FIG. 39 is a signal waveform diagram in this display device. As shown in FIG. 39, the polarity of the voltage (Cs / Com signal) applied to the auxiliary capacitance line 218 and the counter electrode is inverted every horizontal scanning period. Here, since the pixel electrode (picture element electrode) is capacitively coupled to the auxiliary capacitance wiring and the counter electrode, the potential of the pixel electrode (picture element electrode potential) also changes every horizontal scanning period. Further, since the polarity of the pixel electrode voltage is inverted every frame period, the amplitude of the potential of the pixel electrode (pixel electrode potential) becomes relatively large as shown in FIG. Here, in order to reliably turn off the TFT in the pixel formation portion, the gate signal voltage Vgl must be made smaller than the minimum value Vdl of the potential of the pixel electrode. On the other hand, in order to surely turn on the TFT of the pixel formation portion, the gate signal voltage Vgh must be larger than the source signal voltage Vsh above the threshold voltage of the TFT. For this reason, in a display device employing line inversion driving, it is necessary to increase the amplitude Vgh−Vgl of the gate signal voltage. Accordingly, it is necessary to increase the breakdown voltage of the gate driver and the breakdown voltage of the TFT in the pixel formation portion, which causes an increase in cost.

  On the other hand, in a display device employing dot inversion driving, the voltage of the counter electrode is made constant, so that the amplitude of the potential of the pixel electrode is smaller than that of line inversion driving. However, since it is necessary to apply a positive voltage and a negative voltage around the counter electrode voltage from the source driver to the pixel electrode, it is necessary to increase the amplitude of the output voltage from the source driver. For this reason, the current flowing in the source driver increases and the power consumption increases.

Therefore, an invention for a driving method of a liquid crystal display device that can suppress an increase in amplitude of an output voltage from a source driver and also suppress an amplitude of a potential of a pixel electrode in spite of making the voltage of the counter electrode constant. It is disclosed in Japanese Patent Application Laid-Open No. 2007-128202. FIG. 40 is a diagram for explaining the operation in the pixel formation portion of this display device. According to this display device, as shown in FIG. 40A, the TFT 116 is first turned on, and the voltage Vp is applied from the source wiring 114 to the pixel electrode 118. Next, as shown in FIG. 40B, the TFT 116 is turned off, and the voltage of the auxiliary capacitance line 113 is changed by Vq. At this time, when the capacitance of the auxiliary capacitor 119 connected to the pixel electrode 118 is Cstg and the capacitance of the liquid crystal 105 is Clc, the voltage Vr of the pixel electrode 118 is expressed by the following equation (101) as shown in FIG. Indicated.
Vr = Vp + Vq × (Cstg / (Cstg + Clc)) (101)

As a result, the voltage applied to the pixel electrode 118 becomes Vq × (Cstg / (Cstg + Clc)) higher than the voltage Vp applied to the source wiring. In this way, the voltage applied to the source wiring can be made smaller than the voltage to be applied to the pixel electrode, so that the amplitude of the output voltage from the source driver can be reduced. Further, since the voltage of the counter electrode is made constant, the amplitude of the potential of the pixel electrode is suppressed and the increase in the amplitude of the gate signal voltage is suppressed as shown in FIG.
JP 2006-23404 A JP 2007-128202 A

  However, according to the display device disclosed in Japanese Unexamined Patent Application Publication No. 2007-128202, the voltage of each auxiliary capacitance line 113 must be individually controlled (for each corresponding gate line 112). Therefore, as shown in FIG. 42, a flip-flop circuit 132 and a selector circuit (storage capacitor driving circuit) 134 for generating a voltage Yci to be applied to the auxiliary capacitance line 113 based on a signal Ysi applied to the gate line 112. Are provided corresponding to each row.

  Here, in the low temperature p-Si (Polycrystalline Silicon) TFT panel and the CG silicon (Continuous Grain Silicon) TFT panel, the above-described flip-flop circuit 132 and selector circuit 134 are formed using the TFT. Can be configured. However, if these circuits are constituted by TFTs, the circuit scale increases, which may cause a decrease in yield.

  On the other hand, in an a-Si (Amorphous Silicon) TFT panel, the above-described circuit needs to be integrated into an IC. As a result, a terminal for driving the auxiliary capacitance wiring 113 must be provided corresponding to each row, so that the number of pins of the driver IC circuit increases and the cost increases.

  Therefore, an object of the present invention is to provide a display device that can reduce the amplitude of an output voltage from a source driver or a gate driver while suppressing an increase in cost. Another object of the present invention is to provide a display device capable of reducing power consumption while suppressing an increase in cost.

The first invention is provided corresponding to a plurality of video signal lines, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and an intersection of the plurality of video signal lines and the plurality of scanning signal lines. A switching element whose conduction state is controlled by a scanning signal applied to the corresponding scanning signal line, a pixel electrode electrically connected to the corresponding video signal line through the switching element, and a pixel electrode between the pixel electrode and the pixel electrode. The second predetermined capacitance is formed between the common electrode to which a predetermined capacitance of 1 is formed and a fixed potential is applied, and the pixel electrode, and corresponds to the plurality of scanning signal lines on a one-to-one basis. A display unit including a plurality of auxiliary capacitance lines, a scanning signal line driving circuit for selectively driving the plurality of scanning signal lines, and a video signal line for applying a video signal to the plurality of video signal lines A drive circuit; and A display device and a storage capacitor line drive circuit for driving the number of storage capacitor wires,
A plurality of auxiliary capacitance lines are made into one set, and one group is formed by the auxiliary capacitance lines constituting each set and the scanning signal lines, switching elements, and pixel electrodes provided corresponding to the auxiliary capacitance lines. The plurality of auxiliary capacitance lines are grouped into a plurality of sets,
When we focus on any group,
In one frame period during which display for one screen is performed, a selection period in which scanning signal lines included in the group are sequentially driven and a scanning signal line included in a group other than the group are sequentially displayed. It consists of a non-selection period that is a period to be driven,
The auxiliary capacitor lines included in the group are a first polarity capacitor line composed of two or more auxiliary capacitor lines electrically connected to each other and two or more auxiliary capacitor lines electrically connected to each other. Divided into a second polarity capacitance wiring that is an auxiliary capacitance wiring other than the auxiliary capacitance wiring included in the first polarity capacitance wiring;
The video signal line driving circuit includes a pixel electrode provided corresponding to the first polarity capacitance wiring included in the group, and a pixel electrode provided corresponding to the second polarity capacitance wiring included in the group. Then, the video signal is applied to the plurality of video signal lines so that voltages having different polarities are written in the selection period.
In the auxiliary capacitance line driving circuit, in each frame period, for the auxiliary capacitance line corresponding to the pixel electrode in which the positive voltage is written in the selection period, the positive voltage is written in the non-selection period. For the auxiliary capacitor wiring corresponding to the pixel electrode to which a higher potential than the performed period is applied and the negative voltage is written in the selection period, the negative voltage is written in the non-selection period. The polarity of the voltage applied in the non-selection period is reversed between the first polarity capacitor line and the second polarity capacitor line when a potential lower than the period is applied and the potential of the common electrode is used as a reference. As described above, a potential is applied to the first polarity capacitance wiring and the second polarity capacitance wiring.

According to a second invention, in the first invention,
When paying attention to an arbitrary group, the auxiliary capacitance wiring drive circuit is
In the Nth frame (N is a natural number), a predetermined first waveform potential consisting of one or a plurality of potentials is applied to the first and second polarity capacitance wirings included in the group during the selection period, and the non-selection is performed. In the period, a predetermined second potential is applied to the first polarity capacitor wiring included in the group and a predetermined third potential that is higher than the second potential is applied to the second polarity capacitor wiring included in the group. Give,
In the (N + 1) th frame, in the selection period, the first waveform potential is applied to the first and second polarity capacitor lines included in the group, and in the non-selection period, the third potential is applied to the group. And the second potential is applied to the second polarity capacitor wiring included in the group.

According to a third invention, in the second invention,
The first waveform potential consists of one potential,
The storage capacitor line driving circuit is characterized in that the first waveform potential is an intermediate potential between the second potential and the third potential.

According to a fourth invention, in the second invention,
The first waveform potential includes a high level first potential that is higher than the potential of the common electrode, and a low level first potential that is lower than the potential of the common electrode,
The storage capacitor line driving circuit is characterized in that the high-level first potential is set to the same potential as the third potential, and the low-level first potential is set to the same potential as the second potential.

The fifth invention is the invention of the fourth invention,
When we focus on any group,
The auxiliary capacitance line driving circuit alternately applies the high level first potential and the low level first potential to the first and second polarity capacitance lines included in the group during the selection period,
The timing at which the potential applied to the first polarity capacitor wiring first changes during the selection period is different from the timing at which the potential applied to the second polarity capacitor wiring first changes during the selection period. And

The sixth invention is the invention of the first invention,
The scanning signal line selection period in which one scanning signal line is selected includes a preceding first scanning signal line selection period and a subsequent second scanning signal line selection period.
The scanning signal line driving circuit applies a predetermined first selection voltage that turns on all the switching elements that receive scanning signals from the scanning signal line to be selected during the selection period of the first scanning signal line. Applying a predetermined second voltage lower than the first selection voltage to the scanning signal line to be selected in the second scanning signal line selection period,
In the video signal line driving circuit, all the switching elements corresponding to the pixel electrodes to which a voltage having a gradation value within a predetermined first gradation range is to be turned off during the second scanning signal line selection period. In addition, a target voltage is applied at the start of the second scanning signal line selection period among the switching elements corresponding to the pixel electrodes to which a voltage having a gradation value outside the first gradation range is to be applied. Applying the video signal to the plurality of video signal lines so that at least a switching element that is not in a conductive state,
When paying attention to an arbitrary group, the auxiliary capacitance driving circuit detects the potential of the auxiliary capacitance wiring included in the group after the end of the first scanning signal line selection period and before the start of the second scanning signal line selection period. It is characterized by changing.

The seventh invention is provided corresponding to a plurality of video signal lines, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and an intersection of the plurality of video signal lines and the plurality of scanning signal lines. A switching element whose conduction state is controlled by a scanning signal applied to the corresponding scanning signal line, a pixel electrode electrically connected to the corresponding video signal line through the switching element, and a pixel electrode between the pixel electrode and the pixel electrode. The second predetermined capacitance is formed between the common electrode to which a predetermined capacitance of 1 is formed and a fixed potential is applied, and the pixel electrode, and corresponds to the plurality of scanning signal lines on a one-to-one basis. A display device drive circuit having a display unit including a plurality of auxiliary capacitance lines provided as described above,
A scanning signal line driving circuit for selectively driving the plurality of scanning signal lines;
A video signal line driving circuit for applying a video signal to the plurality of video signal lines;
An auxiliary capacitance line driving circuit for driving the plurality of auxiliary capacitance lines,
A plurality of auxiliary capacitance lines are made into one set, and one group is formed by the auxiliary capacitance lines constituting each set and the scanning signal lines, switching elements, and pixel electrodes provided corresponding to the auxiliary capacitance lines. The plurality of auxiliary capacitance lines are grouped into a plurality of sets,
When we focus on any group,
In one frame period in which display for one screen is performed, a selection period in which scanning signal lines included in the group are sequentially driven and a scanning signal line included in a group other than the group are sequentially displayed. It consists of a non-selection period that is a period to be driven,
The auxiliary capacitor lines included in the group are a first polarity capacitor line composed of two or more auxiliary capacitor lines electrically connected to each other and two or more auxiliary capacitor lines electrically connected to each other. Divided into a second polarity capacitance wiring that is an auxiliary capacitance wiring other than the auxiliary capacitance wiring included in the first polarity capacitance wiring;
The video signal line driving circuit includes a pixel electrode provided corresponding to the first polarity capacitance wiring included in the group, and a pixel electrode provided corresponding to the second polarity capacitance wiring included in the group. Then, the video signal is applied to the plurality of video signal lines so that voltages having different polarities are written in the selection period.
In the auxiliary capacitance line driving circuit, in each frame period, for the auxiliary capacitance line corresponding to the pixel electrode in which the positive voltage is written in the selection period, the positive voltage is written in the non-selection period. For the auxiliary capacitor wiring corresponding to the pixel electrode to which a higher potential than the performed period is applied and the negative voltage is written in the selection period, the negative voltage is written in the non-selection period. The polarity of the voltage applied in the non-selection period is reversed between the first polarity capacitor line and the second polarity capacitor line when a potential lower than the period is applied and the potential of the common electrode is used as a reference. As described above, a potential is applied to the first polarity capacitance wiring and the second polarity capacitance wiring.

The eighth invention is provided corresponding to a plurality of video signal lines, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and an intersection of the plurality of video signal lines and the plurality of scanning signal lines. A switching element whose conduction state is controlled by a scanning signal applied to the corresponding scanning signal line, a pixel electrode electrically connected to the corresponding video signal line through the switching element, and a pixel electrode between the pixel electrode and the pixel electrode. The second predetermined capacitance is formed between the common electrode to which a predetermined capacitance of 1 is formed and a fixed potential is applied, and the pixel electrode, and corresponds to the plurality of scanning signal lines on a one-to-one basis. A method for driving a display device having a display unit including a plurality of auxiliary capacitance lines provided as described above,
A scanning signal line driving step of selectively driving the plurality of scanning signal lines;
A video signal line driving step of applying a video signal to the plurality of video signal lines;
A storage capacitor line driving step for driving the plurality of storage capacitor lines;
A plurality of auxiliary capacitance lines are made into one set, and one group is formed by the auxiliary capacitance lines constituting each set and the scanning signal lines, switching elements, and pixel electrodes provided corresponding to the auxiliary capacitance lines. The plurality of auxiliary capacitance lines are grouped into a plurality of sets,
When we focus on any group,
In one frame period in which display for one screen is performed, a selection period in which scanning signal lines included in the group are sequentially driven and a scanning signal line included in a group other than the group are sequentially displayed. It consists of a non-selection period that is a period to be driven,
The auxiliary capacitor lines included in the group are a first polarity capacitor line composed of two or more auxiliary capacitor lines electrically connected to each other and two or more auxiliary capacitor lines electrically connected to each other. Divided into a second polarity capacitance wiring that is an auxiliary capacitance wiring other than the auxiliary capacitance wiring included in the first polarity capacitance wiring;
In the video signal line driving step, a pixel electrode provided corresponding to the first polarity capacitance wiring included in the group and a pixel electrode provided corresponding to the second polarity capacitance wiring included in the group; The video signal is applied to the plurality of video signal lines so that voltages of different polarities are written in the selection period.
In the auxiliary capacitance line driving step, in each frame period, for the auxiliary capacitance line corresponding to the pixel electrode in which the positive voltage is written in the selection period, the positive voltage is written in the non-selection period. For the auxiliary capacitance wiring corresponding to the pixel electrode to which a potential higher than that in the selected period is applied and the negative voltage is written in the selection period, the negative voltage is written in the non-selection period. A potential lower than that of the first period is applied, and the polarity of the voltage applied in the non-selection period when the potential of the common electrode is used as a reference is reversed between the first polarity capacitor line and the second polarity capacitor line. A potential is applied to the first polarity capacitance wiring and the second polarity capacitance wiring so that

  According to the first aspect of the invention, the first polarity capacitance wiring and the second polarity capacitance wiring are constituted by two or more auxiliary capacitance wirings that are electrically connected to each other. For this reason, a plurality of storage capacitor lines are driven together. As a result, the auxiliary capacitance wiring drive circuit can be simplified. In addition, one frame period includes a selection period and a non-selection period. For the auxiliary capacitance wiring corresponding to the pixel electrode in which a positive voltage is written in the selection period, the positive voltage is applied in the non-selection period. For the auxiliary capacitance wiring corresponding to the pixel electrode to which a higher potential than the period during which writing is performed and a negative voltage is written during the selection period, the negative voltage is written during the non-selection period. A potential lower than the specified period is applied. For this reason, the amplitude of the pixel electrode voltage is larger than the amplitude of the voltage applied to the video signal line by the amount of change (pixel electrode potential) that accompanies the change of the potential of the auxiliary capacitance wiring. As a result, the amplitude of the output voltage from the video signal line driving circuit can be made smaller than before when the pixel electrode voltage is to be obtained with the same magnitude as before. Furthermore, since the potential of the common electrode is fixed, the amplitude of the pixel electrode voltage in the selection period can be made relatively small. For this reason, the amplitude of the output voltage from the scanning signal line driving circuit can be made relatively small. As described above, the amplitude of the output voltage from the video signal line driving circuit and the scanning signal line driving circuit can be made relatively small while suppressing an increase in circuit scale, and low power consumption can be achieved while suppressing an increase in cost. Can do.

  According to the second aspect, similarly to the first aspect, it is possible to reduce power consumption while suppressing an increase in cost.

  According to the third aspect, the first waveform potential is one potential, and the potential is an intermediate potential between the second potential and the third potential. For this reason, the configuration of the storage capacitor line driving circuit can be simplified.

  According to the fourth aspect of the invention, it is sufficient that the storage capacitor line driving circuit can apply a binary potential to the storage capacitor line. For this reason, the configuration of the storage capacitor line driving circuit can be simplified.

  According to the fifth aspect, the timing of changing the applied potential differs between the first polarity capacitance wiring and the second polarity capacitance wiring. If the voltage change timing for the second polarity capacitance wiring is matched with the voltage change timing for the first polarity capacitance wiring, the pixel electrode corresponding to one of the first polarity capacitance wiring or the second polarity capacitance wiring corresponds to the other. Compared with the pixel electrode to be performed, the period during which the effect of increasing the amplitude of the pixel electrode voltage is obtained is shortened. On the other hand, when the voltage change timing is different between the first polarity capacitor line and the second polarity capacitor line as in the present invention, the pixel electrode corresponding to the first polarity capacitor line and the pixel electrode corresponding to the second polarity capacitor line Thus, the period in which the effect of increasing the amplitude of the pixel electrode voltage is obtained is equal, and the same gradation display is performed in both.

  According to the sixth aspect, the period during which each scanning signal line is selected (scanning signal line selection period) includes the following first scanning signal line selection period and second scanning signal line selection period. It is. In the first scanning signal line selection period, all the switching elements included in the row corresponding to the scanning signal line to be selected (hereinafter referred to as “selection target row”) are turned on. Thus, the voltage applied to the video signal line is applied to all the pixel electrodes included in the selection target row. Further, the potential of the auxiliary capacitance line is changed during the period between the first scanning signal line selection period and the second scanning signal line selection period. As a result, the potentials of all the pixel electrodes included in the row to be selected change as the potential of the auxiliary capacitance line changes. Furthermore, in the second scanning signal line selection period, some switching elements included in the selection target row are turned on. At this time, since the switching element corresponding to the pixel electrode to which the voltage of the gradation value within the first gradation range is to be applied is turned off, the second scanning signal line selection period starts for the pixel electrode. The current voltage is maintained. In addition, since the switching element corresponding to the pixel electrode to which the target voltage is not applied at the start of the second scanning signal line selection period is turned on, the target voltage for the pixel electrode is selected during the second scanning signal line selection period. Is written. From the above, the amplitude of the pixel electrode voltage is larger than the amplitude of the voltage applied to the video signal line by the amount of change (pixel electrode potential) associated with the change of the potential of the auxiliary capacitance wiring. For this reason, a display element having a large difference between the minimum gradation voltage and the maximum gradation voltage can be employed with the amplitude of the voltage applied to the video signal line being the same as the conventional one. In addition, when a display element with the same difference between the minimum grayscale voltage and the maximum grayscale voltage is used, the amplitude of the voltage applied to the video signal line can be made smaller than before, reducing power consumption. Is done.

<1. Concept of the present invention>
Before describing the embodiment, the basic concept of the present invention will be described. Here, description will be given on the assumption of the following display device. The display unit of the display device includes a plurality of pixels provided corresponding to the intersections of the plurality of source lines, the plurality of gate lines, and the plurality of source lines and the plurality of gate lines. Forming part. In each pixel forming portion, a gate electrode is connected to a gate wiring that passes through a corresponding intersection, and a switching element in which a source electrode is connected to a source wiring that passes through the intersection, and a drain electrode of the switching element is connected A pixel electrode, an electro-optical element such as a liquid crystal, and the like are included. Note that in this description, the term “voltage” is used to mean “potential with respect to a predetermined potential (ground potential or the like)”. For example, the “pixel electrode voltage” means the potential of the pixel electrode when the predetermined potential is used as a reference. In addition, the gate wiring, auxiliary capacitance wiring, pixel formation portion, and pixel electrode that are the object of explanation are referred to as “target gate wiring”, “target auxiliary capacitance wiring”, “target pixel formation portion”, “target pixel electrode” "

  In the display device according to the present invention, the constituent elements in the display unit are grouped into N groups (N is an integer of 2 or more). Specifically, the pixel formation portion (including the pixel electrode and TFT), the gate wiring, and the auxiliary capacitance wiring are grouped into N groups. In addition, the auxiliary capacitance lines in each group are divided into a first polarity capacitance line and a second polarity capacitance line to which voltages having different polarities are applied during most of one frame period. For example, one group is constituted by the constituent elements in the first to fourth rows, the auxiliary capacitance wirings in the first row and the third row are set as the first polarity capacitance wiring, and the auxiliary capacitance wirings in the second row and the fourth row are set up. The second polarity capacitor wiring is used.

  In the configuration as described above, when attention is paid to a certain group (herein referred to as “P-th group”) from the first group to the N-th group, the selection voltage to the gate wiring included in the P-th group. In a period during which (the voltage for turning on the gate of the TFT) is applied (hereinafter referred to as “selection period”), a first waveform voltage to be described later is applied to the auxiliary capacitance wiring included in the P-th group. . On the other hand, a period during which the selection voltage is applied to the gate wiring included in a group other than the P group (hereinafter referred to as “non-selection period”) is included in the P group in a certain frame period. A second waveform voltage, which will be described later, is applied to the first polarity capacitor wiring, and a third waveform voltage, which will be described later, is applied to the second polarity capacitor wiring. In addition, in the non-selection period of the next frame period, the third waveform voltage is applied to the first polarity capacitance line among the auxiliary capacitance lines included in the P-th group, and the second waveform is applied to the second polarity capacitance line. Apply voltage. When focusing on groups other than the P-th group, the selection period and the non-selection period are different from the selection period and the non-selection period for the P-th group.

By the way, as described above, a voltage (the second waveform voltage or the third waveform voltage) different from the first waveform voltage is applied to the auxiliary capacitance wiring (target auxiliary capacitance wiring) included in the P group during the non-selection period. As a result, the pixel electrode voltage of the pixel formation portion (target pixel formation portion) included in the P-th group changes during the non-selection period. For example, when the pixel electrode voltage before the change in the target pixel formation unit is Va and the voltage of the target auxiliary capacitance line is changed from the first waveform voltage V1 to the voltage Vafter during the non-selection period, the pixel electrode voltage Vx after the change is
Vx = Va + (Vafter−V1) × Cs / (Cs + Clc) (1)
It becomes. Note that Clc indicates the capacity of the liquid crystal capacitor 22, and Cs indicates the capacity of the auxiliary capacitor 23.

  Here, if the pixel electrode voltage Va before the change is a positive voltage, a third waveform voltage V3 that satisfies “V3> V1” is applied to the target auxiliary capacitance line during the non-selection period. On the other hand, if the pixel electrode voltage Va before the change is a negative voltage, the second waveform voltage V2 satisfying “V2 <V1” is applied to the target auxiliary capacitance line during the non-selection period. As described above, by changing the voltage applied to the storage capacitor line in the non-selection period, the amplitude of the pixel electrode voltage in the non-selection period is increased in the target pixel formation portion.

  By the way, as in the example shown above, one group is constituted by the first to fourth rows, the auxiliary capacitance wirings of the first row and the third row are made the first polarity capacitance wiring, and the second row and the fourth row. When the second auxiliary capacitance line is the second polarity capacitance line, the pixel electrode in the first row and the pixel electrode in the third row are both capacitively coupled to the first polarity capacitance line through the respective auxiliary capacitance. ing. However, since the timing at which the selection voltage is applied to the corresponding gate wirings is different, the pixel electrode voltage update (rewrite) timing for the first row and the pixel electrode voltage update (rewrite) timing for the third row Is different. Therefore, focusing only on the selection period in a certain frame period, the length of the period in which the positive voltage is applied and the negative voltage are applied to the pixel electrode in the first row and the pixel electrode in the third row. The length of the period to be different is different.

  However, focusing on the total period of the selection period in the certain frame period and the selection period in the next frame period, a positive voltage is applied between the pixel electrode in the first row and the pixel electrode in the third row. The length of the period to be applied and the length of the period to which the negative polarity voltage is applied can be made equal. In order to do so, the first polarity capacitance wiring and the second polarity capacitance are set so that the same increase in amplitude is obtained for the pixel electrode voltage in the selection period in a certain frame period and in the selection period in the next frame period. A predetermined voltage is applied to the wiring. The following three methods can be considered as the method of applying the voltage.

<1.1 First Method>
First, as a first method, there is a method in which the first waveform voltage is set to an intermediate voltage between the second waveform voltage and the third waveform voltage. According to this method, the amplitude of the pixel electrode voltage increases in the selection period in both the pixel electrode to which the positive voltage is applied during the selection period and the pixel electrode to which the negative voltage is applied in the selection period. There is nothing.

<1.2 Second method>
Next, as a second method, the first waveform voltage is constituted by two or more voltages, one voltage is set equal to the second waveform voltage, and the other voltage is set equal to the third waveform voltage. There is a method of using voltage. According to this method, “the period during which the first waveform voltage is applied to the target auxiliary capacitance line”, that is, “the same magnitude as the voltage applied to the target auxiliary capacitance line when writing is performed on the target pixel electrode”. The effect of increasing the voltage amplitude for the target pixel electrode in the “period in which the voltage of the second voltage is applied” is “the period in which the second waveform voltage or the third waveform voltage is applied to the target auxiliary capacitance wiring”, that is, “in the target pixel electrode This is smaller than the effect of increasing the voltage amplitude for the target pixel electrode in the “period in which a voltage different from the voltage applied to the target auxiliary capacitance line when writing is performed”. For this reason, it is preferable to shorten the length of the period during which the first waveform voltage is applied to each auxiliary capacitance wiring. Therefore, it is preferable that the application timing of the first waveform voltage is different between the first polarity capacitance wiring and the second polarity capacitance wiring included in the same group. Further, in the same group, the application timing of the second waveform voltage (or third waveform voltage) to the first polarity capacitor wiring and the application timing of the third waveform voltage (or second waveform voltage) to the second polarity capacitor wiring Is preferably different. The reason why this is preferable will be described later (described in the description of the second embodiment).

  As described above, the effect of increasing the amplitude of the pixel electrode voltage can be enhanced by increasing the length of the period during which the second waveform voltage or the third waveform voltage is applied to each auxiliary capacitance line.

<1.3 Third method>
Further, as a third method, after the selection voltage VH is applied to the target gate wiring, before the selection voltage is applied to the gate wiring of the next row of the target gate wiring, the non-selection voltage VL and the half described later are applied to the target gate wiring. A technique for providing the selection voltage VM can be mentioned. Specifically, voltages VH, VL, and VM that satisfy “VH ≧ VM> VL” (in the case of n-type TFT) or “VL> VM ≧ VH” (in the case of p-type TFT) are sequentially applied to the target gate wiring. In addition, the first waveform voltage is changed during the period in which the voltage VL is applied to the target gate wiring.

  In this method, first, the selection voltage VH is applied to the target gate wiring, whereby the voltage applied to the source wiring is written to the target pixel electrode. Next, the non-selection voltage VL is applied to the target gate line and the voltage (first waveform voltage) of the target auxiliary capacitance line is changed, thereby changing the target pixel electrode voltage. Further, by applying the half-select voltage VM to the target gate wiring, the TFT of each pixel formation portion is selectively turned on or off according to the magnitude of the voltage applied to the source wiring, The pixel electrode voltage of some pixel formation portions changes. As described above, the effect of increasing the amplitude of the pixel electrode voltage is obtained.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

<2. First Embodiment>
<2.1 Overall configuration and operation>
FIG. 2 is a block diagram showing the overall configuration of the liquid crystal display device according to the first embodiment of the present invention. The liquid crystal display device includes a display control circuit 100, a display unit 200, a source driver (video signal line driving circuit) 300, a gate driver (scanning signal line driving circuit) 400, and an auxiliary capacitance driver (auxiliary capacitance wiring driving circuit) 500. I have. Hereinafter, the source driver 300, the gate driver 400, and the auxiliary capacitance driver 500 are collectively referred to as a driver (drive circuit). In this liquid crystal display device, 64 gradation display is performed. Further, the present embodiment realizes the first method.

  The display unit 200 includes n source wirings (video signal lines) S1 to Sn, m gate wirings (scanning signal lines) G1 to Gm, and these n source wirings and m gate wirings. A plurality of (n × m) pixel forming portions provided corresponding to the intersections are included. The display unit 200 is provided with m auxiliary capacitance lines C1 to Cm corresponding to the gate lines G1 to Gm. In the following description, it is assumed that the number of gate lines is 16 (m = 16) and the number of source lines is 8 (n = 8). That is, it is assumed that the display unit 200 includes 96 pixel forming units, and a pixel matrix of 16 rows × 8 columns is formed by these pixel forming units. Further, the pixel forming portions arranged in i rows and j columns are described with reference numerals Aij. That is, as shown in FIG. 3, each pixel forming unit in the display unit 200 will be described with reference numerals A11 to Ag8.

  FIG. 4 is a circuit diagram showing a configuration of the pixel formation portion Aij. As shown in FIG. 4, each pixel forming portion Aij has a TFT 20 in which a gate electrode 25 is connected to a gate wiring Gi passing through a corresponding intersection, and a source electrode 26 is connected to a source wiring Si passing through the intersection. The pixel electrode 21 connected to the drain electrode 27 of the TFT 20, the common electrode 24 provided in common to the plurality of pixel formation portions Aij, and the auxiliary capacitance provided so as to correspond to the gate wiring Gi. A wiring (auxiliary capacitance electrode) Ci, a liquid crystal capacitance 22 formed by the pixel electrode 21 and the common electrode 24, and an auxiliary capacitance 23 formed by the pixel electrode 14 and the auxiliary capacitance wiring Ci are included. Further, the liquid crystal capacitor 22 and the auxiliary capacitor 23 form a pixel capacitor Cp. Then, based on the video signal that the source electrode 26 of the TFT 20 receives from the source wiring Si when the gate electrode 25 of each TFT 20 receives an active scanning signal (selection signal) from the gate wiring Gi, the pixel value is stored in the pixel capacitor Cp. Is held. In the following description, the pixel electrode 21 in the pixel formation portion Aij arranged in i row and j column will be described with reference symbol Pij.

  In the present embodiment, the pixel formation portions A11 to Ag8 including the TFT 20, the pixel electrode 21, and the like, the gate wirings G1 to Gg, and the auxiliary capacitance wirings C1 to Cg are grouped into four groups. Specifically, as shown in FIG. 3, the constituent elements corresponding to the first to fourth lines are referred to as “first group”, and the constituent elements corresponding to the fifth to eighth lines are referred to as “second group”. The component corresponding to the twelfth row is a “third group”, and the component corresponding to the thirteenth to sixteenth rows is a “fourth group”.

  FIG. 1 is a block diagram showing a detailed configuration of the driver and the display unit 200 in the liquid crystal display device. The auxiliary capacitor driver 500 is connected with two wires (first polarity capacitor wire and second polarity capacitor wire) for each group for controlling the voltage applied to the auxiliary capacitor wires C1 to Cg. Since there are four groups in the present embodiment, four first polarity capacitor lines and four second polarity capacitor lines are connected to the auxiliary capacitor driver 500. For the first group auxiliary capacitance lines C1 to C4, the first row auxiliary capacitance wires C1 and the third row auxiliary capacitance wires C3 are connected to the first polarity capacitance wires, and the second row auxiliary capacitance wires C2 The auxiliary capacitance line C4 in the fourth row is connected to the second polarity capacitance line. Similarly, for the auxiliary capacitance lines in the second to fourth groups, as shown in FIG. 1, the two auxiliary capacitance lines in the odd-numbered rows are connected to the first polarity capacitance wiring, and the two auxiliary capacitance wires in the even-numbered rows are connected. The auxiliary capacity wiring is connected to the second polarity capacity wiring.

  Next, the outline of the operation of each component will be described with reference to FIG.

  The display control circuit 100 receives a data signal DAT and a timing control signal group TG sent from the outside, and controls a digital video signal Dx, a source start pulse signal SSP for controlling the timing of displaying an image on the display unit 200, a source Controls the voltage applied to the source wiring Si, the clock signal SCK, the gate start pulse signal GSP, the gate clock signal GCK, the 2-bit data signal BI, the auxiliary capacitance clock signal FCK, the latch pulse signal LP, and the gate output control signal OE Output a polarity signal PO.

  The source driver 300 receives the digital image signal Dx, the source start pulse signal SSP, the source clock signal SCK, the latch pulse signal LP, and the polarity signal PO output from the display control circuit 100, and each pixel forming unit in the display unit 200 In order to charge the pixel capacitor Cp of Aij, a driving video signal is applied to the source lines S1 to Sn (S8).

  The gate driver 400 receives the gate start pulse signal GSP, the gate clock signal GCK, and the gate output control signal OE output from the display control circuit 100, and sequentially selects selection signals (scanning signals) to the gate lines G1 to Gm (Gg). Apply.

  The auxiliary capacitance driver 500 receives the 2-bit data signal BI and the auxiliary capacitance clock signal FCK output from the display control circuit 100, and applies the auxiliary capacitance line drive signal to the auxiliary capacitance lines C1 to Cm (Cg).

  As described above, the driving video signal is applied to the source lines S1 to Sn (S8), the selection signal is applied to the gate lines G1 to Gm (Gg), and the auxiliary capacitance lines C1 to Cm (Cg). An image is displayed on the display unit 200 by applying the storage capacitor line driving signal to the display unit 200.

<2.2 Source driver configuration and operation>
As shown in FIG. 1, the source driver 300 includes a shift register 31, a register 32, and a D / A conversion circuit 33. The shift register 31 is composed of 8 bits (8 stages), and the register 32 is composed of 48 bits (8 × 6 bits). The D / A conversion circuit 33 has eight 6-bit latches.

  A source start pulse signal SSP and a source clock signal SCK are input to the shift register 31. Based on these signals SSP and SCK, the shift register 31 sequentially transfers pulses included in the source start pulse signal SSP from the input end to the output end. In response to this pulse transfer, sampling pulses corresponding to the source lines S 1 to S 8 are sequentially output from the shift register 31, and the sampling pulses are sequentially input to the register 32.

  The register 32 samples and holds 6-bit data transmitted as the digital video signal Dx from the display control circuit 100 at the timing of the sampling pulse output from the shift register 31. The D / A conversion circuit 33 takes eight 6-bit data held in the register 32 into eight 6-bit latches at the timing of the pulse of the latch pulse signal LP, and performs digital-analog conversion on the data. Further, the D / A conversion circuit 33 applies the data after digital-analog conversion to the source wirings S1 to S8 as a driving video signal.

  Here, it will be described how the digital / analog conversion is performed in the D / A conversion circuit 33 described above. FIG. 5 is a diagram for explaining digital-analog conversion in the D / A conversion circuit 33 in the present embodiment. A signal generated by this digital-analog conversion is applied to the source lines S1 to S8 as a driving video signal, and the voltage of the driving video signal (“output voltage Ax” in FIG. 5) is a digital video signal (FIG. 5). 5 "input signal Dx") and is determined as shown in FIG. 5 according to the logic level of the polarity signal PO.

  In FIG. 5, the value (“0”, “31”, etc.) of the input signal Dx indicates a gradation value. “VSH” of the output voltage Ax indicates the maximum voltage (hereinafter referred to as “source maximum voltage”) among the voltages that can be applied to the source wirings S1 to S8, and “VSL” of the output signal Ax is the source wiring. The minimum voltage (hereinafter referred to as “source minimum voltage”) among the voltages that can be applied to S1 to S8 is shown, and “VSM” of the output signal Ax is a voltage approximately halfway between the source maximum voltage and the source minimum voltage ( Hereinafter, it is referred to as “source intermediate voltage”. For example, the row indicated by the reference sign a1 indicates that if the logical level of the polarity signal PO is “low level”, the input signal Dx indicating the gradation value from “0” to “31” is the source maximum voltage VSH or less. It shows that the voltage is converted to a voltage value larger than the intermediate voltage VSM. Specifically, the input signal Dx with the gradation value “0” is converted into the source maximum voltage VSH, and the input signal Dx with the gradation value “31” is converted into a voltage slightly higher than the source intermediate voltage VSM. Thus, the smaller the gradation value of the input signal Dx, the more the input signal Dx is converted to a voltage close to the source maximum voltage VSH, and the larger the gradation value of the input signal Dx, the more the input signal Dx becomes the source intermediate voltage. It is converted to a voltage close to VSM. Further, for example, in the row indicated by the symbol a2, if the logical level of the polarity signal PO is “high level”, the input signal Dx indicating the gradation values from “32” to “63” is from the source intermediate voltage VSM. It is also shown that the voltage is converted to a voltage not higher than the source maximum voltage VSH. Specifically, the input signal Dx having the gradation value “32” is converted to a voltage slightly higher than the source intermediate voltage VSM, and the input signal Dx having the gradation value “63” is converted to the source maximum voltage VSH. Thus, the smaller the gradation value of the input signal Dx, the more the input signal Dx is converted to a voltage close to the source intermediate voltage VSM, and the larger the gradation value of the input signal Dx, the more the input signal Dx is the source maximum voltage. It is converted to a voltage close to VSH.

<2.3 Configuration and operation of gate driver>
As shown in FIG. 1, the gate driver 400 includes a shift register 41 and a gate output circuit 42. The shift register 41 is composed of 16 bits (16 stages). A gate start pulse signal GSP and a gate clock signal GCK are input to the shift register 41. Based on these signals GSP and GCK, the shift register 41 sequentially transfers pulses included in the gate start pulse signal GSP from the input end to the output end. In response to the transfer of the pulses, timing pulses GSi corresponding to the gate lines G1 to Gg are sequentially output from the shift register 41, and the timing pulses GSi are sequentially input to the gate output circuit 42.

  The gate output circuit 42 outputs selection signals G1 to Gg to the gate lines G1 to Gg based on the timing pulse GSi output from the shift register 41 and the gate output control signal OE output from the display control circuit 100 ( For convenience, the same reference numerals are assigned to the gate wiring and the selection signal). At this time, the magnitude of the voltage (“output voltage Vx” in FIG. 6) supplied to the gate lines G1 to Gg as the selection signals G1 to Gg is determined as shown in FIG.

  In FIG. 6, “L” and “H” of the timing pulse GSi and the gate output control signal OE indicate the logic levels of these signals. Further, “VH” of the output voltage Vx indicates a voltage (selection voltage) at which the gate of the TFT 20 is turned on, and “VL” of the output voltage Vx indicates a voltage (non-selection voltage) at which the gate of the TFT 20 is turned off. ing. The row indicated by the symbol a3 indicates that if the logic level of the timing pulse GSi is low, the output voltage Vx becomes “VL” regardless of the logic level of the gate output control signal OE.

<2.4 Configuration and operation of auxiliary capacitor driver>
FIG. 7 is a block diagram showing a detailed configuration of the auxiliary capacitor driver 500. As shown in FIG. 7, the auxiliary capacitor driver 500 includes a shift register 51 and a capacitor wiring output circuit 52. The shift register 51 is composed of 4 bits (4 stages). The capacitor wiring output circuit 52 includes a first group output unit 521 to a fourth group output unit 524. The first group output unit 521 to the fourth group output unit 524 are connected to the first polarity capacitor line and the second polarity capacitor line of the corresponding group.

  In the configuration as described above, the 2-bit data signal BI and the auxiliary capacitance clock signal FCK are input to the shift register 51. The shift register 51 sequentially transfers the 2-bit data signal BI from the input end to the output end based on the auxiliary capacitance clock signal FCK. In response to this transfer, the 2-bit data BCk is supplied from the shift register 51 to the capacitor wiring output circuit 52.

  Based on the 2-bit data BCk output from the shift register 51, the first group output unit 521 to the fourth group output unit 524 in the capacitance wiring output circuit 52 are respectively connected to the first polarity capacitance wiring of the corresponding group. An auxiliary capacity wiring drive signal is output to the second polarity capacity wiring. At this time, the magnitude of the voltage applied to the first and second polarity capacitor lines as the auxiliary capacitor line drive signal is determined as shown in FIG.

  In FIG. 8, “output voltage Vo” is a voltage applied to the first polarity capacitance wiring of each group, and “output voltage Ve” is a voltage applied to the second polarity capacitance wiring of each group. In addition, “VCL” of the output voltages Vo and Ve indicates a relatively low predetermined voltage (second potential), “VCH” of the output voltages Vo and Ve indicates a relatively high predetermined voltage (third potential), “VCM” of the output voltages Vo and Ve indicates a predetermined voltage (first waveform potential) that is not less than the VCL and not more than the VCH.

<2.5 Driving method>
Next, a driving method in the present embodiment will be described. 9A to 9H show a selection signal applied to the gate wiring G1 in the first row, a selection signal applied to the gate wiring G2 in the second row, and a driving video signal applied to the source wiring Sj. Auxiliary capacitance wiring drive signal applied to the first-row auxiliary capacitance wiring C1, pixel electrode voltage of the pixel formation portion A1j, auxiliary capacitance wiring drive signal applied to the second-row auxiliary capacitance wiring C2, pixel formation portion A2j The pixel electrode voltage and the waveform of the polarity signal PO are respectively shown. 10A to 10H show a selection signal applied to the third row gate wiring G3, a selection signal applied to the fourth row gate wiring G4, and a driving video signal applied to the source wiring Sj. Auxiliary capacitance wiring drive signal applied to the third row auxiliary capacitance wiring C3, a pixel electrode voltage of the pixel formation portion A3j, an auxiliary capacitance wiring drive signal applied to the fourth row auxiliary capacitance wiring C4, and a pixel formation portion A4j The pixel electrode voltage and the waveform of the polarity signal PO are respectively shown. Note that the waveforms of the drive video signal and the polarity signal PO applied to the source line Sj are shown in both FIGS. 9 and 10 for convenience of explanation. In the following, the voltage of the driving video signal is also referred to as “source voltage”.

  FIGS. 11A to 11J show an auxiliary capacitance line driving signal applied to the first auxiliary capacitance line C1, an auxiliary capacitance wiring drive signal applied to the second auxiliary capacitance line C2, and a fifth row. Storage capacitor line drive signal applied to the storage capacitor line C5, storage capacitor line drive signal applied to the storage capacitor line C6 in the sixth row, and storage capacitor line drive signal applied to the storage capacitor line C9 in the ninth row. Auxiliary capacitance line drive signal applied to the 10th auxiliary capacitance line Ca, an auxiliary capacitance line drive signal applied to the 13th auxiliary capacitance line Cd, and an auxiliary capacitance applied to the 14th auxiliary capacitance line Ce. The waveforms of the wiring drive signal, the 2-bit data signal BI, and the storage capacitor clock signal FCK are shown. The 2-bit data signal BI indicates a numerical value represented by 2 bits.

  Here, how to read FIGS. 9 to 11 and how to attach the reference numerals will be described with reference to FIGS. First, description will be made regarding how to attach reference numerals (time points) for time points. As shown in FIG. 12, the start time of application of the selection voltage to the gate lines G1, G5, G9, and Gd in the first row of each group is represented as t0, t1, t2, t3,. For example, the start time of application of the selection voltage to the gate wiring G1 in the first row is expressed as t0, t4, t8,. Further, when a selection voltage is sequentially applied to the gate wirings G1 to G4 of the first group in the period of time t0 to t1, as shown in FIG. 13, the rising time and falling time of each selection signal G1 to G4. Are represented as t0, t01, t02,..., T07. Similarly, rising and falling times of the selection signals G5 to G8 in the period from the time point t1 to the time point t2 are expressed as t1, t11, t12,. In this way, the rising time point and the falling time point of each selection signal in the period between the time point ta (a is an integer) and the time point t (a + 1) are represented as ta, ta1, ta2,.

  Focusing on the first group (FIGS. 9 and 10), the selection voltage is sequentially applied to the gate wirings G1 to G4 of the first group in the period from the time point t0 to t1. Therefore, as shown in FIGS. 12 and 13, the period from time t0 to time t1 and time t4 to t5 is called a “selection period” for the first group, and a selection voltage is applied to the gate wirings of groups other than the first group. The period to be performed, that is, the period from time t1 to t4 and time t5 to t8 is referred to as “non-selection period” for the first group. FIG. 12 shows two frame periods. For convenience of explanation, the preceding frame period is referred to as “odd frame”, and the subsequent frame period is referred to as “even frame”.

  The meaning of each line in FIG. 9C and FIG. 10C is as follows. The thick solid line shows the waveform of the source voltage Sj corresponding to the input signal Dx having a gradation value of “63”. The thick dotted line indicates the waveform of the source voltage Sj corresponding to the input signal Dx having the gradation value “31.5”. A thin solid line indicates a waveform of the source voltage Sj corresponding to the input signal Dx having a gradation value of “0”.

  In FIG. 9, for example, during the period between time t0 and time t01, the source voltage Sj is as shown in FIG. This is because an input signal Dx having a gradation value of “0” is converted to the source maximum voltage VSH, an input signal Dx having a gradation value of “31.5” is converted to the source intermediate voltage VSM, and the gradation value is “ 63 "indicates that the input signal Dx is converted to the minimum source voltage VSL. Further, in the period between the time point t02 and the time point t03, the source voltage Sj is as shown in FIG. This is because an input signal Dx having a gradation value of “63” is converted to the source maximum voltage VSH, an input signal Dx having a gradation value of “31.5” is converted to the source intermediate voltage VSM, and the gradation value is “ The “0” input signal Dx is converted into the minimum source voltage VSL.

  Next, a method for driving the auxiliary capacitance line in the two-frame period will be described with reference to FIG. In the present embodiment, as shown in FIGS. 11 (i) and 11 (j), the 2-bit data signal BI and the auxiliary capacitance clock signal FCK are supplied to the shift register 51 in the auxiliary capacitance driver 500. Based on the 2-bit data signal BI and the auxiliary capacitor clock signal FCK, 2-bit data BCk is output from the shift register 51 to the capacitor wiring output circuit 52. In the capacitive wiring output circuit 52, the output voltages Vo and Ve are generated as shown in FIG. 8 in the first group output section 521 to the fourth group output section 524 shown in FIG. For each group, the output voltage Vo is applied to the first polarity capacitance wiring, and the output voltage Ve is applied to the second polarity capacitance wiring. As a result, the auxiliary capacitance wiring ( Hereinafter, these wirings are also referred to as “first polarity capacity wiring”) and auxiliary capacity wiring connected to the second polarity capacity wiring (hereinafter, these wirings are also referred to as “second polarity capacity wiring”). The voltage waveforms are as shown in FIGS. 11 (a) to 11 (h).

  As shown in FIGS. 11A to 11H, during the selection period of each group, the voltage VCM described above is applied to the first polarity capacitor line and the second polarity capacitor line of each group. In each group, in the non-selection period following the selection period of the odd-numbered frame, the above-described voltage VCL is applied to the first polarity capacitor wiring, and the above-described voltage VCH is applied to the second polarity capacitor wiring. In each group, the voltage VCH is applied to the first polarity capacitor line and the voltage VCL is applied to the second polarity capacitor line in the non-selection period following the selection period of the even frame. In the present embodiment, a constant voltage (the above-described voltage VCM) is applied to the common electrode 24 shown in FIG.

  Next, paying attention to the rows in the first group in the pixel matrix, the driving method thereof will be described with reference to FIGS.

  In the period from time t0 to t01, the selection voltage VH is applied to the gate line G1 in the first row. As a result, the TFT 20 of the pixel formation portion A1j becomes conductive. During this period, the polarity signal PO is at a low level. Therefore, as shown in FIG. 5, if the gradation value of the input signal Dx is “0” to “31”, the voltage corresponding to each gradation value between the source maximum voltage VSH and the source intermediate voltage VSM is the source. If the gradation value of the input signal Dx applied to the wiring Sj is “31.5”, the source intermediate voltage VSM is applied to the source wiring Sj, and the gradation value of the input signal Dx is “32” to “63”. Then, a voltage corresponding to each gradation value between the source intermediate voltage VSM and the minimum source voltage VSL is applied to the source line Sj. Thereby, in the pixel formation portion A1j, the voltages VSH to VSL are applied to the pixel electrode P1j during the period of time t0 to t01.

  The selection voltage VH is applied to the gate line G1 in the first row after the period from time t0 to t01 during the period from time t4 to t41. That is, the non-selection voltage VL is applied to the gate line G1 in the first row throughout the period from the time point t01 to t4. Further, as shown in FIG. 9D, a constant voltage VCM is applied to the auxiliary capacitance line C1 in the first row throughout the period from time t0 to time t07a. Therefore, in the pixel formation portion A1j, the pixel electrode voltage at the time point t01 is held until the time point t07a. The time point t07a is a time point immediately before the first group changes from the selection period to the non-selection period.

  In the period from time t02 to t03, the selection voltage VH is applied to the gate wiring G2 in the second row. As a result, the TFT 20 of the pixel formation portion A2j becomes conductive. During this period, the polarity signal PO is at a high level. Therefore, as shown in FIG. 5, if the gradation value of the input signal Dx is “0” to “31”, the voltage corresponding to each gradation value between the source minimum voltage VSL and the source intermediate voltage VSM is the source. If the gradation value of the input signal Dx applied to the wiring Sj is “31.5”, the source intermediate voltage VSM is applied to the source wiring Sj, and the gradation value of the input signal Dx is “32” to “63”. If so, a voltage corresponding to each gradation value between the source intermediate voltage VSM and the source maximum voltage VSH is applied to the source line Sj. Thereby, in the pixel formation portion A2j, the voltages VSH to VSL are applied to the pixel electrode P2j during the period from the time point t02 to t03.

  The selection voltage VH is applied to the gate line G2 in the second row next to the period from time t2 to time t03 during the period from time t42 to time t43. That is, the non-selection voltage VL is applied to the gate line G2 in the second row throughout the period from the time point t03 to t42. In addition, as shown in FIG. 9F, a constant voltage VCM is applied to the auxiliary capacitance line C2 in the second row throughout the period from time t0 to time t07a. Therefore, in the pixel formation portion A2j, the pixel electrode voltage at the time point t03 is held until the time point t07a.

  Similarly, for the third row, voltages VSH to VSL are applied to the pixel electrode P3j during the period from time t04 to t05, and the pixel electrode voltage at time t05 is held until time t07a. For the fourth row, voltages VSH to VSL are applied to the pixel electrode P4j during a period from time t06 to t07, and the pixel electrode voltage at time t07 is held until time t07a.

  At time t07a, the voltage of the first polarity capacitance line, that is, the voltage of the auxiliary capacitance lines C1 and C3 in the first and third rows drops from VCM to VCL, and the voltage of the second polarity capacitance line, that is, the second and fourth rows. The voltage of the auxiliary capacitance lines C2 and C4 in the row rises from VCM to VCH. At this time, since the TFTs 20 in the pixel formation portions A1j to A4j are all in a non-conductive state, the pixel electrode voltages in the pixel formation portions A1j and A3j in the first row and the third row decrease, and the second and fourth rows. The pixel electrode voltage in the pixel formation portions A2j and A4j in the row rises. Then, the pixel electrode voltage after the change (decrease or rise) in the pixel formation portions A1j to A4j is maintained until time t37a immediately before the first group is in the selection period.

Here, assuming that the capacity of the liquid crystal capacitor 22 is Clc, the capacity of the auxiliary capacitor 23 is Cs, and the pixel electrode voltage before the drop in the pixel formation portions A1j and A3j in the first row and the third row is Va. The pixel electrode voltage Vx is
Vx = Va + (VCL−VCM) × Cs / (Cs + Clc) (2)
It becomes.

Further, when the pixel electrode voltage before the rise in the pixel formation portions A2j and A4j in the second row and the fourth row is Vb, the pixel electrode voltage Vy after the rise is
Vy = Vb + (VCH−VCM) × Cs / (Cs + Clc) (3)
It becomes.

  At time point t37a (a time point immediately before the first group is in the selection period), the voltages of the first polarity capacitor lines C1 and C3 rise from VCL to VCM, and the voltages of the second polarity capacitor lines C2 and C4 change from VCH to VCM. To descend. The voltage after the change (rise or fall) is maintained until time 47a. As a result, the constant voltage VCM is applied to the auxiliary capacitance lines C1 to C4 throughout the period from the time point t4 to t47a. As a result, focusing on the first row and the third row, “a voltage is applied to the auxiliary capacitance wiring C1 in the first row after the writing in the first row until the writing in the first row is performed again. The length of the period during which the VCM is applied ”and“ the voltage VCM is applied to the auxiliary capacitance line C3 in the third row after the writing in the third row and after the writing in the third row is performed again. Is equal to the length of the period. For this reason, if the gradation values of the first and third rows are equal, the average voltage (and effective value voltage) of the pixel electrode P1j of the first row and the average voltage (and effective value voltage) of the pixel electrode P3j of the third row. ) Is equal. The same applies to the second and fourth lines.

  The same driving as in the first group is performed for each row in the second to fourth groups. For example, when focusing on the third group, among the time points t0 to t8 shown in FIG. 12, the period from the time point t2 to t3 and the period from the time point t6 to t7 are the selection period, and the other period is the non-selection period.

  Incidentally, as described above, in the present embodiment, a constant voltage VCM is applied to the common electrode 24. Therefore, the liquid crystal applied voltage in the pixel formation portions A1j to A4j is the smallest when the gradation value of the input signal Dx is “31.5” in the selection period, and the gradation of the input signal Dx in the non-selection period. It becomes the smallest when the value is “0”. In the present embodiment, the length of the non-selection period is three times the length of the selection period. Thus, by making the length of the non-selection period longer than the length of the selection period, the effective value (effective value voltage) of the liquid crystal applied voltage becomes the smallest when the gradation value of the input signal Dx is “0”. Has been.

For example, “VSL = −2V”, “VSM = 0V”, “VSH = 2V”, “Cs / (Cs + Clc) = 0.5”, “VCL = −6V”, “VCM = 0V”, “VCH = 6V” '', The pixel electrode voltage Vx during the non-selection period in the pixel formation portion that becomes negative during the non-selection period is
Vx = VS + (VCL−VCM) × Cs / (Cs + Clc)
= VS-3V (4)
It becomes. Note that VS is the pixel electrode voltage in the selection period before the non-selection period.

  Here, when Vx is applied to the pixel electrode during three quarters of one frame period and VS is applied to the pixel electrode during one quarter of one frame period, the effective value voltage Vr is as shown in FIG.

Further, the pixel electrode voltage Vy during the non-selection period in the pixel formation portion that becomes positive during the non-selection period is:
Vy = VS + (VCH−VCM) × Cs / (Cs + Clc)
= VS + 3V (5)
It becomes.

  Here, when Vy is applied to the pixel electrode in three quarters of one frame period and VS is applied to the pixel electrode in one quarter of one frame period, the effective value voltage Vr is as shown in FIG.

  FIG. 17 is a diagram showing the relationship between the pixel electrode voltage VS and the effective value voltage Vr during the selection period. Note that a voltage obtained by subtracting 2 V from the supply voltage in FIG. 17 corresponds to the pixel electrode voltage VS. In FIG. 17, the gradation value “0” is associated with the supply voltage “0 V”, and the gradation value “63” is associated with the supply voltage “4 V”. Here, when a liquid crystal having voltage-transmittance characteristics (relationship between the effective value voltage Vr and the transmittance L) as shown in FIG. 18 is employed, the relationship between the gradation value and the effective value voltage Vr is as shown in FIG. It will be as shown in As described above, the relationship between the gradation value and the output voltage from the source driver 300 (supply voltage in FIG. 20) corresponds to each gradation value (from the source driver 300) so that the relationship is as shown in FIG. The output voltage may be determined.

<2.6 Effects>
According to this embodiment, a plurality of auxiliary capacitance lines included in the same group are driven together. For this reason, the auxiliary capacity driver 500 can have a simple configuration. Here, even if the pixel electrode voltage is rewritten (updated) at any timing during the selection period in the pixel formation portion Aij, if the gradation value is the same, the average of the pixel electrode voltages in the pixel formation portion Aij The value (and rms voltage) is a constant voltage. For this reason, display quality does not deteriorate due to the fact that a plurality of storage capacitor lines are driven together.

  In addition, since the auxiliary capacitance driver 500 can have a simple configuration, the circuit scale is reduced in the low-temperature polysilicon TFT panel and the CG silicon TFT panel. As a result, the yield is improved and the cost is reduced. In addition, in the amorphous silicon TFT panel, the number of pins of the auxiliary capacitor driver 500 can be reduced when the circuit is made into an IC, and the cost is reduced.

  Furthermore, since the voltage of the common electrode 24 is constant, the amplitude of the pixel electrode voltage can be made relatively small. Therefore, the amplitude of the output voltage from the gate driver 400 can be made relatively small, and cost and power consumption can be reduced. As described above, a display device that can reduce the amplitude of the output voltage from the gate driver 400 while suppressing an increase in cost and further reduce power consumption is realized.

<3. Second Embodiment>
<3.1 Configuration and operation>
FIG. 21 is a block diagram showing the configuration of the driver and the display unit 200 in the liquid crystal display device according to the second embodiment of the present invention. In the present embodiment, the configuration of the capacitor wiring output circuit 53 in the auxiliary capacitor driver 500 is different from that in the first embodiment. The configuration other than the capacitor wiring output circuit 53 is the same as that of the first embodiment. That is, the driving video signal determined as shown in FIG. 5 is output from the source driver 300 to the source lines S1 to S8, and the selection signal determined as shown in FIG. It is output to the wirings G1 to Gg. In addition, this embodiment implement | achieves the said 2nd method.

  FIG. 22 is a block diagram showing a detailed configuration of the auxiliary capacitance driver 500 in the present embodiment. In the present embodiment, the capacitor wiring output circuit 53 is supplied with the gate clock signal GCK and the polarity signal PO output from the display control circuit 100 in addition to the 2-bit data BCk output from the shift register 51. The capacitor wiring output circuit 53 includes first polarity capacitor wiring output units 5311 to 5314 connected to the first polarity capacitor wiring of each group, and a second polarity capacitor wiring connected to the second polarity capacitor wiring of each group. Output units 5321 to 5324 and delay circuits 5301 to 5304 for the respective groups are included. The waveforms of the 2-bit data signal BI and the auxiliary capacitance clock signal FCK supplied to the shift register 51 are as shown in FIGS. 11 (i) and 11 (j), as in the first embodiment. Yes.

  In the configuration as described above, the 2-bit data BCk output from the shift register 51 is supplied to the first polarity capacitance wiring output units 5311 to 5314 and the delay circuits 5301 to 5304. The gate clock signal GCK is supplied to the delay circuits 5301 to 5304, and the polarity signal PO is supplied to the first polarity capacitor wiring output units 5311 to 5314 and the second polarity capacitor wiring output units 5321 to 5324.

  The delay circuits 5301 to 5304 delay the 2-bit data BCk for each group based on the gate clock signal GCK. In the present embodiment, the 2-bit data BCk is delayed for a period corresponding to a period from when a certain row is selected until the next row is selected. The delayed 2-bit data BDk is applied to the second polarity capacitance wiring output units 5321 to 5324. Based on the 2-bit data BCk and the polarity signal PO, the first polarity capacitance wiring output units 5311 to 5314 output the auxiliary capacitance wiring drive signal to the first polarity capacitance wiring of the corresponding group. At this time, the magnitude of the voltage applied to the first polarity capacitor line as the auxiliary capacitor line drive signal is determined as shown in FIG. Based on the 2-bit data BDk and the polarity signal PO, the second polarity capacitance wiring output units 5321 to 5324 output the auxiliary capacitance wiring drive signal to the second polarity capacitance wiring of the corresponding group. At this time, the magnitude of the voltage applied to the second polarity capacitor line as the auxiliary capacitor line drive signal is determined as shown in FIG.

  In the first embodiment, the magnitude of the voltage applied to the auxiliary capacitance line is three values of VCH, VCM, and VCL. On the other hand, in the present embodiment, the magnitude of the voltage applied to the auxiliary capacitance wiring is binary of VCH and VCL.

<3.2 Driving method>
Next, the driving method in the present embodiment will be described with reference to FIGS. Here, a driving method for the rows in the first group of the pixel matrix will be described.

  As described above, in the present embodiment, the magnitude of the voltage applied to the first polarity capacitance wiring is determined as shown in FIG. 23, and the magnitude of the voltage applied to the second polarity capacitance wiring is shown in FIG. To be determined. As a result, the voltage waveforms of the auxiliary capacitance lines C1 to C4 in the first to fourth rows are as shown in FIGS. 25 (d), 25 (f), 26 (d), and 26 (f), respectively. Become.

  In the period from time t0 to t01, the selection voltage VH is applied to the gate line G1 in the first row. As a result, the TFT 20 of the pixel formation portion A1j becomes conductive. During this period, the polarity signal PO is at a low level. Therefore, as shown in FIG. 5, if the gradation value of the input signal Dx is “0” to “31”, the voltage corresponding to each gradation value between the source maximum voltage VSH and the source intermediate voltage VSM is the source. If the gradation value of the input signal Dx applied to the wiring Sj is “31.5”, the source intermediate voltage VSM is applied to the source wiring Sj, and the gradation value of the input signal Dx is “32” to “63”. Then, a voltage corresponding to each gradation value between the source intermediate voltage VSM and the minimum source voltage VSL is applied to the source line Sj. Thereby, in the pixel formation portion A1j, the voltages VSH to VSL are applied to the pixel electrode P1j during the period of time t0 to t01.

  During the period from the time t0 to the time t01, the 2-bit data BCk is “0” because the 2-bit data signal BI is “0” as shown in FIG. Therefore, based on the polarity signal PO, the voltage VCH is applied to the first polarity capacitance lines C1 and C3 as shown in FIG. During this period, the 2-bit data BDk after the delay of the 2-bit data BCk is “3”. As a result, as shown in FIG. 24, the voltage VCL is applied to the second polarity capacitance lines C2 and C4.

  In the period from time t02 to t03, the selection voltage VH is applied to the gate wiring G2 in the second row. As a result, the TFT 20 of the pixel formation portion A2j becomes conductive. During this period, the polarity signal PO is at a high level. Therefore, as shown in FIG. 5, if the gradation value of the input signal Dx is “0” to “31”, the voltage corresponding to each gradation value between the source minimum voltage VSL and the source intermediate voltage VSM is the source. If the gradation value of the input signal Dx applied to the wiring Sj is “31.5”, the source intermediate voltage VSM is applied to the source wiring Sj, and the gradation value of the input signal Dx is “32” to “63”. If so, a voltage corresponding to each gradation value between the source intermediate voltage VSM and the source maximum voltage VSH is applied to the source line Sj. Thereby, in the pixel formation portion A2j, the voltages VSH to VSL are applied to the pixel electrode P2j during the period from the time point t02 to t03.

  During the period from the time point t02 to t03, the 2-bit data signal BCk is “0” because the 2-bit data signal BI is “0” as shown in FIG. Therefore, based on the polarity signal PO, the voltage VCL is applied to the first polarity capacitance lines C1 and C3 as shown in FIG. During this period, the 2-bit data BDk after the delay of the 2-bit data BCk is also “0”. As a result, as shown in FIG. 24, the voltage VCL is also applied to the second polarity capacitance lines C2 and C4.

  During the period from time t04 to time t05, the selection voltage VH is applied to the gate wiring G3 in the third row. As a result, the TFT 20 of the pixel formation portion A3j becomes conductive. During this period, the polarity signal PO is at a low level. Therefore, as shown in FIG. 5, if the gradation value of the input signal Dx is “0” to “31”, the voltage corresponding to each gradation value between the source maximum voltage VSH and the source intermediate voltage VSM is the source. If the gradation value of the input signal Dx applied to the wiring Sj is “31.5”, the source intermediate voltage VSM is applied to the source wiring Sj, and the gradation value of the input signal Dx is “32” to “63”. Then, a voltage corresponding to each gradation value between the source intermediate voltage VSM and the minimum source voltage VSL is applied to the source line Sj. Thereby, in the pixel formation portion A3j, the voltages VSH to VSL are applied to the pixel electrode P3j during the period from the time point t04 to t05.

  In the period from the time point t04 to t05, the 2-bit data signal BCk is “0” because the 2-bit data signal BI is “0” as shown in FIG. Therefore, based on the polarity signal PO, the voltage VCH is applied to the first polarity capacitance lines C1 and C3 as shown in FIG. During this period, the 2-bit data BDk after the delay of the 2-bit data BCk is “0”. As a result, as shown in FIG. 24, the voltage VCH is also applied to the second polarity capacitance lines C2 and C4.

  In the period from time t06 to t07, the selection voltage VH is applied to the gate wiring G4 in the fourth row. As a result, the TFT 20 of the pixel formation portion A4j becomes conductive. During this period, the polarity signal PO is at a high level. Therefore, as shown in FIG. 5, if the gradation value of the input signal Dx is “0” to “31”, the voltage corresponding to each gradation value between the source minimum voltage VSL and the source intermediate voltage VSM is the source. If the gradation value of the input signal Dx applied to the wiring Sj is “31.5”, the source intermediate voltage VSM is applied to the source wiring Sj, and the gradation value of the input signal Dx is “32” to “63”. If so, a voltage corresponding to each gradation value between the source intermediate voltage VSM and the source maximum voltage VSH is applied to the source line Sj. Thereby, in the pixel formation portion A4j, the voltages VSH to VSL are applied to the pixel electrode P4j during the period from the time point t06 to t07.

  During the period from the time point t06 to t07 described above, the 2-bit data signal BIk is “0” because the 2-bit data signal BI is “0” as shown in FIG. Therefore, based on the polarity signal PO, the voltage VCL is applied to the first polarity capacitance lines C1 and C3 as shown in FIG. During this period, the 2-bit data BDk after the delay of the 2-bit data BCk is “0”. As a result, as shown in FIG. 24, the voltage VCL is also applied to the second polarity capacitance lines C2 and C4.

  During the period from time t1 to time t11, as shown in FIG. 11I, the 2-bit data signal BI is “1”, so the 2-bit data BCk is “1”. For this reason, as shown in FIG. 23, the voltage VCL is applied to the first polarity capacitor lines C1 and C3. During this period, the 2-bit data BDk after the delay of the 2-bit data BCk is “0”, and the polarity signal is at the low level. Thereby, based on the polarity signal PO, the voltage VCH is applied to the second polarity capacitance lines C2 and C4 as shown in FIG.

  Thereafter, until the next selection period of the first group, the voltage of the first polarity capacitance lines C1 and C3 is maintained at VCL, and the voltage of the second polarity capacitance lines C2 and C4 is maintained at VCH.

Here, assuming that the pixel electrode voltage of the pixel formation portions A1j and A3j at the time point t05 is Va, the pixel electrode voltage Vx during the period in which the voltage of the first polarity capacitor lines C1 and C3 is maintained at the voltage VCL described above is
Vx = Va + (VCL−VCM) × Cs / (Cs + Clc) (6)
It becomes.

Further, assuming that the pixel electrode voltage of the pixel formation portions A2j and A4j at time t07 is Vb, the pixel electrode voltage Vy during the period in which the voltage of the second polarity capacitance wirings C2 and C4 is maintained at the voltage VCH described above is
Vy = Vb + (VCH−VCM) × Cs / (Cs + Clc) (7)
It becomes.

  The application of the voltage VCL to the first polarity capacitor lines C1 and C3 continues until time t41a immediately after the application of the selection voltage to the gate line G1 in the first row is finished. As a result, focusing on the first row and the third row, “a voltage is applied to the auxiliary capacitance wiring C1 in the first row after the writing in the first row until the writing in the first row is performed again. The length of the period during which VCL is applied "and" the voltage VCL is applied to the auxiliary capacitance line C3 in the third row after the writing in the third row and after the writing in the third row is performed again. Is equal to the length of the period. For this reason, if the gradation values of the first and third rows are equal, the average voltage (and effective value voltage) of the pixel electrode P1j of the first row and the average voltage (and effective value voltage) of the pixel electrode P3j of the third row. ) Is equal. The same applies to the second and fourth lines. Further, the same driving as in the first group is performed for each row in the second to fourth groups.

  In this embodiment, as shown in FIGS. 25D and 25F, the voltage change timing for the first polarity capacitor wiring is different from the voltage change timing for the second polarity capacitor wiring. The reason why the timing of voltage change is made different will be described below. FIG. 27 is a signal waveform diagram when the voltage change timing for the second polarity capacitance wiring is matched with the voltage change timing for the first polarity capacitance wiring. Here, attention is focused on FIG. 25 (f) and FIG. 27 (f) showing changes in the pixel electrode voltage of the pixel formation portion A 2 j. If the voltage change timing for the second polarity capacitance wiring is matched with the voltage change timing for the first polarity capacitance wiring, as shown in FIG. 27 (f), the second polarity capacitance wiring also during the period from time t0 to t02. A voltage VCH is applied to C2. For this reason, in the pixel electrode P2j, compared to the pixel electrode P1j, the period during which the effect of increasing the amplitude of the pixel electrode voltage can be obtained only during this period. On the other hand, when the voltage change timing is varied as in the present embodiment, as shown in FIG. 25 (f), there is a period in which the effect of increasing the amplitude of the pixel electrode voltage is obtained between the pixel electrode P1j and the pixel electrode P2j. Will be equal. Therefore, unlike the example shown in FIG. 27F, the same gradation display is performed on the pixel electrode P1j and the pixel electrode P2j. In this way, the voltage change timing for the first polarity capacitor wiring and the voltage change timing for the second polarity capacitor wire are made different, thereby reducing the length of the period during which the first waveform voltage is applied to each auxiliary capacitor wire. It can be made uniform.

  Incidentally, a constant voltage is applied to the common electrode 24. In the present embodiment, the constant voltage is an intermediate voltage between VCH and VCL. Therefore, the liquid crystal applied voltage in the pixel formation portions A1j to A4j is the smallest when the gradation value of the input signal Dx is “31.5” in the selection period, and the gradation of the input signal Dx in the non-selection period. It becomes the smallest when the value is “0”. In the present embodiment, in all frame periods for each row, “the length of the period during which the second waveform voltage or the third waveform voltage is applied to the auxiliary capacitance line” is “the first waveform voltage is applied to the auxiliary capacitance line”. Is approximately 7 times the length of the period. For this reason, for each group, in the selection period of the odd frame, VCH as the high-level first potential is applied to the first polarity capacitor wiring, and VCL as the low-level first potential is applied to the second polarity capacitor wiring. In the non-selection period of the odd-numbered frame, VCL as the second potential is applied to the first polarity capacitor line, and VCH as the third potential is applied to the second polarity capacitor line. Further, for each group, VCL is given to the first polarity capacitor wiring and VCH is given to the second polarity capacitance wiring in the selection period of the even frame, and the first polarity capacitance is given to the non-selection period of the even frame. VCH is given to the wiring, and VCL is given to the second polarity capacitor wiring. As described above, the amplitude of the effective value voltage is effectively increased by extending the period during which the effect of increasing the amplitude of the pixel electrode voltage is obtained.

For example, “VSL = −2V”, “VSM = 0V”, “VSH = 2V”, “Cs / (Cs + Clc) = 0.5”, “VCL = −3V”, “VCH = 3V” are set. If so, the pixel electrode voltage Vx during the non-selection period in the pixel formation portion that becomes negative in the non-selection period is
Vx = VS + (VCL−VCM) × Cs / (Cs + Clc)
= VS-3V (8)
It becomes. Note that VS is a pixel electrode voltage immediately after writing to the pixel electrode of the pixel formation portion.

  Here, when Vx is applied to the pixel electrode in a period of 7/8 of one frame period and VS is applied to the pixel electrode in a period of 1/8 of one frame period, the effective value voltage Vr is as shown in FIG.

Further, the pixel electrode voltage Vy during the non-selection period in the pixel formation portion that becomes positive during the non-selection period is:
Vy = VS + (VCH−VCM) × Cs / (Cs + Clc)
= VS + 3V (9)
It becomes.

  Here, when Vy is applied to the pixel electrode in a period of 7/8 of one frame period and VS is applied to the pixel electrode in a period of 1/8 of one frame period, the effective value voltage Vr is as shown in FIG.

<3.3 Effects>
According to the present embodiment, as in the first embodiment, a plurality of storage capacitor lines included in the same group are driven together, so that the storage capacitor driver 500 can be configured simply. Thereby, the circuit scale can be reduced and the cost can be reduced.

  In the first embodiment, the output voltage from the auxiliary capacitor driver 500 is a ternary value (VCH, VCM, VCL). However, in this embodiment, the output voltage from the auxiliary capacitor driver 500 is 2. Value (VCH, VCL). For this reason, the circuit scale is further reduced as compared with the first embodiment.

  Furthermore, in the case where the maximum source voltage VSH, the minimum source voltage VSL, etc. are set in the same manner in the first embodiment and the present embodiment, in order to obtain the same voltage amplitude increase effect for the pixel electrode. The amplitude of the output voltage from the auxiliary capacitance driver 500 in this embodiment may be approximately one half of the amplitude of the output voltage from the auxiliary capacitance driver 500 in the first embodiment. For this reason, power consumption is reduced as compared with the first embodiment.

<4. Third Embodiment>
<4.1 Configuration and operation>
FIG. 30 is a block diagram showing the configuration of the driver and the display unit 200 in the liquid crystal display device according to the third embodiment of the present invention. In the present embodiment, unlike the first and second embodiments, the output voltage control signal AB is sent from the D / A conversion circuit 33 in the source driver 300, the gate output circuit 42 in the gate driver 400, This is given to the capacitor wiring output circuit 54 in the auxiliary capacitor driver 500. The configuration of the capacitive wiring output circuit 54 in the auxiliary capacitance driver 500 is substantially the same as the configuration in the second embodiment shown in FIG. 22, but in this embodiment, the output described above is used. The voltage control signal AB is supplied to the first polarity capacitor wiring output unit and the second polarity capacitor wiring output unit. The present embodiment realizes the third method.

  In the D / A conversion circuit 33 in the source driver 300, the voltage of the driving video signal (“output voltage Ax” in FIG. 31) is based on the digital video signal (“input signal Dx” in FIG. 31). 31 and the logic level of the output voltage control signal AB are determined as shown in FIG.

  In the present embodiment, when the logical level of the polarity signal PP is “low level”, that is, when the polarity of the video signal is negative, the gradation value of “0” or more and “21” or less is the first gradation range. It corresponds to the gradation value in the above. Further, when the logical level of the polarity signal PP is “high level”, that is, when the polarity of the video signal becomes positive, the gradation value of “42” or more and “63” or less becomes the gradation value within the first gradation range. Equivalent to.

  In the gate output circuit 42 in the gate driver 400, the magnitudes of the voltages (“output voltage Vx” in FIG. 32) given to the gate lines G1 to Gg as the selection signals G1 to Gg are the timing pulse GSi and the gate output control signal OE. And the output voltage control signal AB are determined as shown in FIG. As shown in FIG. 32, the magnitude of the voltage applied to the gate lines G1 to Gg is any one of VH, VM, and VL. The voltage VH indicates a voltage at which the gate of the TFT 20 is turned on (a selection voltage as “first selection voltage”), and the voltage VL indicates a voltage at which the gate of the TFT 20 is turned off (non-selection voltage). VM indicates a voltage (half selection voltage as the “second selection voltage”) at which the gates of some of the TFTs 20 are turned on.

  In the capacity wiring output circuit 54 in the auxiliary capacity driver 500, the voltage (output voltage Vo in FIG. 33) given to the first polarity capacity wiring as the auxiliary capacity wiring drive signal is the 2-bit data BCk, the polarity signal PO, and the output voltage control. Based on the signal AB, it is determined as shown in FIG. The magnitude of the voltage (output voltage Ve in FIG. 34) applied to the second polarity capacitor line as the auxiliary capacitor line drive signal is based on the 2-bit data BDk, the polarity signal PO, and the output voltage control signal AB. It is determined as shown in FIG.

<4.2 Driving method>
Next, a driving method in the present embodiment will be described with reference to FIGS. Here, a driving method for the rows in the first group of the pixel matrix will be described.

  As described above, in this embodiment, the magnitude of the voltage applied to the first polarity capacitance wiring is determined as shown in FIG. 33, and the magnitude of the voltage applied to the second polarity capacitance wiring is shown in FIG. To be determined. Here, the output voltage control signal AB has a waveform as shown in FIG. 37A, and the polarity signal PO has a waveform as shown in FIG. As a result, the voltage waveforms of the auxiliary capacitance lines C1 to C4 in the first to fourth rows are as shown in FIGS. 35 (d), 35 (f), 36 (d), and 36 (f), respectively. Become. In the present embodiment, as shown in FIGS. 35A and 35B and FIGS. 36A and 36B, each gate wiring is applied with a predetermined period after the selection voltage VH is applied. After the elapse of time, the half selection voltage VM is applied. Note that the period in which the selection voltage VH is applied to the gate wiring corresponds to the first scanning signal line selection period for the gate wiring, and the period in which the half selection voltage VM is applied to the gate wiring is related to the gate wiring. This corresponds to the second scanning signal line selection period.

  In the period from time t0 to t01, the selection voltage VH is applied to the gate line G1 in the first row. As a result, the TFT 20 of the pixel formation portion A1j becomes conductive. During this period, both the polarity signal PO and the output voltage control signal AB are at a low level. Therefore, as shown in FIG. 31, if the gradation value of the input signal Dx is “0” to “42”, the voltage corresponding to each gradation value between the source maximum voltage VSH and the source minimum voltage VSL is the source. When the gradation value of the input signal Dx is “42” to “63” applied to the wiring Sj, the minimum source voltage VSL is applied to the source wiring Sj. Thereby, in the pixel formation portion A1j, the voltages VSH to VSL are applied to the pixel electrode P1j during the period of time t0 to t01.

During the period from time t01 to t02, the non-selection voltage VL is applied to the gate line G1 in the first row. During this period, the output voltage control signal AB changes from a low level to a high level. For this reason, the voltage applied to the first polarity capacitance lines C1 and C3 rises from VCN to VCH. As a result, the pixel electrode voltage in the pixel formation portion A1j in the first row increases. Here, when the pixel electrode voltage before the rise for the pixel formation portion A1j in the first row is Va, the pixel electrode voltage Vn after the rise is
Vn = Va + (VCH−VCN) × Cs / (Cs + Clc) (10)
It becomes.
here,
ΔVp = (VCH−VCN) × Cs / (Cs + Clc) (11)
And

  In the period from the time point t02 to t03, the half selection voltage VM is applied to the gate line G1 in the first row. During this period, the polarity signal PO is at a low level, and the output voltage control signal AB is at a high level. Therefore, as shown in FIG. 31, when the gradation value of the input signal Dx is “0” to “21”, the source maximum voltage VSH is applied to the source wiring Sj, and the gradation value of the input signal Dx is If “21” to “63”, a voltage corresponding to each gradation value between the maximum source voltage VSH and the minimum source voltage VSL is applied to the source line Sj.

Incidentally, the threshold characteristics of the TFT 20 vary among the TFTs 20. Therefore, it is assumed that the threshold voltage Vth of the TFT 20 included in the display unit 200 varies within a range of minVth (minimum) to maxVth (maximum). At this time, the half selection voltage VM and the source maximum voltage VSH are set so that the following expression (12) is satisfied. In this embodiment, it is assumed that an n-type TFT 20 is employed.
VM-minVth <VSH (12)
Thus, for the pixel formation portion A1j including the pixel electrode P1j to which the voltages VSH to VSM corresponding to the gradation values of “0” to “21” are applied in the period from time t0 to t01, the period from time t02 to t03. When the source maximum voltage VSH is applied to the source line Sj, the TFT 20 is turned off. As a result, in the pixel formation portion A1j, the pixel electrode voltage after the increase in the period from the time point t01 to t02 is maintained.

Further, the half-select voltage VM and the source intermediate voltage VSM are set so that the following expression (13) is satisfied.
VM−maxVth ≧ VSM (13)
As a result, for the pixel formation portion A1j including the pixel electrode P1j to which the source minimum voltage VSL is applied as the voltage corresponding to the gradation values of “42” to “63” in the period from the time t0 to t01, the time t02 to t03 During this period, the voltages VSM to VSL corresponding to the gradation values of “42” to “63” are applied to the source line Sj, so that the TFT 20 is turned on. As a result, in the pixel formation portion A1j, the voltage applied to the source wiring Sj is applied to the pixel electrode P1j during the period from the time point t02 to t03.

  Further, regarding the pixel formation portion A1j including the pixel electrode P1j to which the voltages VSM to VSL corresponding to the gradation values of “21” to “42” are applied in the period from time t0 to t01, in the period from time t02 to t03. “VSM + ΔVP” to “VSL + ΔVP” are set to be applied to the source line Sj. As a result, regardless of whether or not the TFT 20 of the pixel formation portion A1j is in a conductive state, the pixel electrode voltage after the increase in the period from the time point t01 to t02 is maintained in the pixel formation portion A1j.

  As described above, as shown in FIG. 35E, the pixel electrode voltage of the pixel formation portion A1j in the period from the time point t02 to t03 is VSL to “VSH + ΔVP”.

  During the period from time t04 to time t05, the selection voltage VH is applied to the gate wiring G2 in the second row. As a result, the TFT 20 of the pixel formation portion A2j becomes conductive. During this period, the polarity signal PO is at a high level, and the output voltage control signal AB is at a low level. Therefore, as shown in FIG. 31, when the gradation value of the input signal Dx is “0” to “21”, the minimum source voltage VSL is applied to the source line Sj, and the gradation value of the input signal Dx is In the case of “22” to “63”, a voltage corresponding to each gradation value between the minimum source voltage VSL and the maximum source voltage VSH is applied to the source line Sj. Thereby, in the pixel formation portion A2j, the voltages VSH to VSL are applied to the pixel electrode P2j during the period from the time point t04 to t05.

In the period from time t05 to t06, the non-selection voltage VL is applied to the gate wiring G2 in the second row. During this period, the output voltage control signal AB changes from a low level to a high level. For this reason, the voltage applied to the second polarity capacitance lines C2 and C4 rises from VCL to VCM. As a result, the pixel electrode voltage in the pixel formation portion A2j in the second row increases. Here, assuming that the pixel electrode voltage Vm before the rise in the pixel formation portion A2j in the second row is Vb, the pixel electrode voltage Vm after the rise is
Vm = Vb + (VCM−VCL) × Cs / (Cs + Clc) (14)
It becomes.
here,
ΔVq = (VCM−VCL) × Cs / (Cs + Clc) (15)
And

  In the period from the time point t06 to t07, the half selection voltage VM is applied to the gate wiring G2 in the second row. During this period, both the polarity signal PO and the output voltage control signal AB are at a high level. Therefore, as shown in FIG. 31, if the gradation value of the input signal Dx is “0” to “42”, the voltage corresponding to each gradation value between the source minimum voltage VSL and the source maximum voltage VSH is the source. When the gradation value of the input signal Dx is “42” to “63” applied to the wiring Sj, the source maximum voltage VSH is applied to the source wiring Sj.

  Here, the half selection voltage VM and the source maximum voltage VSH are set so that the above equation (12) is established. As a result, for the pixel formation portion A2j including the pixel electrode P2j to which the voltages VSH to VSM corresponding to the gradation values of “63” to “42” are applied in the period from the time t04 to t05, the period from the time t06 to t07. When the source maximum voltage VSH is applied to the source line Sj, the TFT 20 is turned off. As a result, in the pixel formation portion A2j, the pixel electrode voltage after the increase in the period from the time point t05 to t06 is maintained.

  Further, the half-select voltage VM and the source intermediate voltage VSM are set so that the above expression (13) is established. As a result, for the pixel formation portion A2j including the pixel electrode P2j to which the source minimum voltage VSL is applied as the voltage corresponding to the gradation value of “21” to “0” in the period from the time t04 to t05, the time t06 to t07. During this period, the voltages VSM to VSL corresponding to the gradation values of “21” to “0” are applied to the source wiring Sj, so that the TFT 20 is turned on. As a result, in the pixel formation portion A2j, the voltage applied to the source line Sj during the period from time t06 to t07 is applied to the pixel electrode P2j.

  Further, regarding the pixel formation portion A2j including the pixel electrode P2j to which the voltages VSM to VSL corresponding to the gradation values of “42” to “21” are applied in the period from time t04 to t05, in the period from time t06 to t07. “VSM + ΔVP” to “VSL + ΔVP” are set to be applied to the source line Sj. As a result, regardless of whether or not the TFT 20 of the pixel formation portion A2j is in a conductive state, the pixel electrode voltage after the increase in the period from time t05 to t06 is maintained in the pixel formation portion A2j.

  As described above, as shown in FIG. 35G, the pixel electrode voltage of the pixel formation portion A2j in the period from the time point t06 to t07 is VSL to “VSH + ΔVP”.

  The same driving is performed for the third and fourth rows. As a result, as shown in FIG. 36E, the pixel electrode voltage of the pixel formation portion A3j in the period from the time point t0a to t0b is VSL to “VSH + ΔVP”. As shown in FIG. 36 (g), the pixel electrode voltage of the pixel formation portion A4j in the period from time t0e to t0f is VSL to “VSH + ΔVP”.

  During the period from the time point t1 to t4, a group other than the first group is selected. Through this period, the voltage VCL is applied to the first polarity capacitor lines C1 and C3, and the second polarity capacitor lines C2 and C4 are applied. The voltage VCH is applied. Thereby, as shown in FIGS. 35E and 35G and FIGS. 36E and 36G, the amplitude of the pixel electrode voltage in the non-selection period is increased. Note that the same driving as in the first group is performed for each row in the second to fourth groups.

<4.3 Effects>
According to the present embodiment, as in the first embodiment, a plurality of storage capacitor lines included in the same group are driven together, so that the storage capacitor driver 500 can be configured simply. Thereby, the circuit scale can be reduced and the cost can be reduced.

  Further, according to the present embodiment, the amplitude of the pixel electrode voltage is larger than the amplitude of the source voltage applied to the source line Sj by “a change due to the voltage change of the auxiliary capacitance line”. That is, the amplitude of the pixel electrode voltage can be made larger than the amplitude of the source voltage. For this reason, the amplitude of the source voltage remains the same as in the prior art, and the minimum gradation voltage (voltage applied to the pixel electrode when the gradation value is minimum) and the maximum gradation voltage (when the gradation value is maximum). A liquid crystal (display element) having a large difference from the voltage applied to the pixel electrode can be employed. As a result, a liquid crystal having a low viscosity and a high response speed can be adopted, so that, for example, display quality when displaying a moving image can be improved.

  Furthermore, when a liquid crystal (display element) having the same difference between the minimum grayscale voltage and the maximum grayscale voltage is used, the amplitude of the source voltage can be made smaller than in the conventional case, thereby reducing power consumption. Is done.

<5. Other>
In each of the above embodiments, the description has been made on the assumption that the liquid crystal display device is capable of displaying gradation of 64 gradations, but the present invention is not limited to this. The present invention can be applied even if the number of gradations is other than 64. The present invention can also be applied to display devices other than liquid crystal display devices.

FIG. 2 is a block diagram illustrating a detailed configuration of a driver and a display unit in the liquid crystal display device according to the first embodiment of the present invention. In the said 1st Embodiment, it is a block diagram which shows the whole structure of a liquid crystal display device. In the said 1st Embodiment, it is a figure for demonstrating how to attach the reference sign to each pixel formation part. FIG. 3 is a circuit diagram illustrating a configuration of a pixel formation unit in the first embodiment. In the said 1st Embodiment, it is a figure for demonstrating the digital analog conversion in a D / A conversion circuit. FIG. 6 is a diagram for describing determination of the magnitude of a voltage applied to a gate wiring in the first embodiment. FIG. 3 is a block diagram illustrating a detailed configuration of an auxiliary capacitance driver in the first embodiment. FIG. 6 is a diagram for describing determination of the magnitude of a voltage applied to the auxiliary capacitance line in the first embodiment. FIG. 5 is a signal waveform diagram for describing a driving method in the first embodiment. FIG. 5 is a signal waveform diagram for describing a driving method in the first embodiment. FIG. 5 is a signal waveform diagram for describing a driving method in the first embodiment. In the said 1st Embodiment, it is a figure for demonstrating regarding a time point. In the said 1st Embodiment, it is a figure for demonstrating regarding a time point. FIG. 6 is a diagram for explaining a source voltage in the first embodiment. In the said 1st Embodiment, it is a figure for demonstrating the effective value voltage in 1 frame period. In the said 1st Embodiment, it is a figure for demonstrating the effective value voltage in 1 frame period. In the said 1st Embodiment, it is a figure which shows the relationship between the pixel electrode voltage and effective value voltage during a selection period. In the said 1st Embodiment, it is a figure which shows a voltage-transmittance characteristic. In the said 1st Embodiment, it is a figure which shows the relationship between a gradation value and an effective value voltage. In the said 1st Embodiment, it is a figure which shows the relationship between a gradation value and the output voltage from a source driver. FIG. 5 is a block diagram illustrating a detailed configuration of a driver and a display unit in a liquid crystal display device according to a second embodiment of the present invention. FIG. 6 is a block diagram illustrating a detailed configuration of an auxiliary capacitance driver in the second embodiment. In the said 2nd Embodiment, it is a figure for demonstrating determination of the magnitude | size of the voltage given to a 1st polarity capacity | capacitance wiring. In the said 2nd Embodiment, it is a figure for demonstrating determination of the magnitude | size of the voltage given to a 2nd polarity capacity wiring. In the said 2nd Embodiment, it is a signal waveform diagram for demonstrating the drive method. In the said 2nd Embodiment, it is a signal waveform diagram for demonstrating the drive method. In the said 2nd Embodiment, it is a signal waveform diagram when the voltage change timing about a 2nd polarity capacity wiring is united with the voltage change timing about a 1st polarity capacity wiring. In the said 2nd Embodiment, it is a figure for demonstrating the effective value voltage in 1 frame period. In the said 2nd Embodiment, it is a figure for demonstrating the effective value voltage in 1 frame period. It is a block diagram which shows the detailed structure of a driver and a display part in the liquid crystal display device which concerns on the 3rd Embodiment of this invention. In the said 3rd Embodiment, it is a figure for demonstrating the digital analog conversion in a D / A conversion circuit. FIG. 10 is a diagram for describing determination of the magnitude of a voltage applied to a gate wiring in the third embodiment. In the said 3rd Embodiment, it is a figure for demonstrating determination of the magnitude | size of the voltage given to a 1st polarity capacity | capacitance wiring. In the said 3rd Embodiment, it is a figure for demonstrating determination of the magnitude | size of the voltage given to a 2nd polarity capacity wiring. In the said 3rd Embodiment, it is a signal waveform diagram for demonstrating the drive method. In the said 3rd Embodiment, it is a signal waveform diagram for demonstrating the drive method. In the said 3rd Embodiment, it is a signal waveform diagram for demonstrating the drive method. In a prior art example, it is a block diagram which shows the whole structure of a display apparatus. It is a signal waveform diagram in a display device according to a conventional example. FIG. 10 is a diagram for explaining an operation in a pixel formation portion of a display device in a conventional example. It is a signal waveform diagram in a display device according to a conventional example. In a prior art example, it is a block diagram which shows the whole structure of a display apparatus.

Explanation of symbols

20 ... TFT
DESCRIPTION OF SYMBOLS 21 ... Pixel electrode 22 ... Liquid crystal capacitance 23 ... Auxiliary capacitance 24 ... Common electrode 31, 41, 51 ... Shift register 32 ... Register 33 ... D / A conversion circuit 42 ... Gate output circuit 52, 53, 54 ... Capacitance wiring output circuit 100 Display control circuit 200 Display unit 300 Source driver (video signal line drive circuit)
400: Gate driver (scanning signal line driving circuit)
500 ... Auxiliary capacitance driver Aij ... Pixel formation part C1-Cg ... Auxiliary capacitance wiring, auxiliary capacitance wiring drive signal Dx ... Digital video signal G1-Gg ... Gate wiring, selection signal Pij ... Pixel electrode PO ... Polarity signal S1-S8 ... Source Wiring, drive video signal

Claims (8)

A plurality of video signal lines, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and a corresponding scanning signal line provided corresponding to an intersection of the plurality of video signal lines and the plurality of scanning signal lines A switching element whose conduction state is controlled by a scanning signal applied to the pixel, a pixel electrode electrically connected to a corresponding video signal line via the switching element, and a first predetermined capacitor formed between the pixel electrode A plurality of common electrodes to which a fixed potential is applied and a plurality of pixels provided so as to correspond to the plurality of scanning signal lines in a one-to-one correspondence with the pixel electrodes. A display unit including a plurality of storage capacitor lines, a scanning signal line driving circuit that selectively drives the plurality of scanning signal lines, a video signal line driving circuit that applies a video signal to the plurality of video signal lines, and the plurality Auxiliary capacity A display device and a storage capacitor line drive circuit for driving the line,
A plurality of auxiliary capacitance lines are made into one set, and one group is formed by the auxiliary capacitance lines constituting each set and the scanning signal lines, switching elements, and pixel electrodes provided corresponding to the auxiliary capacitance lines. The plurality of auxiliary capacitance lines are grouped into a plurality of sets,
When we focus on any group,
In one frame period in which display for one screen is performed, a selection period in which scanning signal lines included in the group are sequentially driven and a scanning signal line included in a group other than the group are sequentially displayed. It consists of a non-selection period that is a period to be driven,
The auxiliary capacitor lines included in the group are a first polarity capacitor line composed of two or more auxiliary capacitor lines electrically connected to each other and two or more auxiliary capacitor lines electrically connected to each other. Divided into a second polarity capacitance wiring that is an auxiliary capacitance wiring other than the auxiliary capacitance wiring included in the first polarity capacitance wiring;
The video signal line driving circuit includes a pixel electrode provided corresponding to the first polarity capacitance wiring included in the group, and a pixel electrode provided corresponding to the second polarity capacitance wiring included in the group. Then, the video signal is applied to the plurality of video signal lines so that voltages having different polarities are written in the selection period.
In the auxiliary capacitance line driving circuit, in each frame period, for the auxiliary capacitance line corresponding to the pixel electrode in which the positive voltage is written in the selection period, the positive voltage is written in the non-selection period. For the auxiliary capacitor wiring corresponding to the pixel electrode to which a higher potential than the performed period is applied and the negative voltage is written in the selection period, the negative voltage is written in the non-selection period. The polarity of the voltage applied in the non-selection period is reversed between the first polarity capacitor line and the second polarity capacitor line when a potential lower than the period is applied and the potential of the common electrode is used as a reference. As described above, a potential is applied to the first polarity capacitor line and the second polarity capacitor line. When paying attention to an arbitrary group, the auxiliary capacitance wiring drive circuit is
In the Nth frame (N is a natural number), a predetermined first waveform potential consisting of one or a plurality of potentials is applied to the first and second polarity capacitance wirings included in the group during the selection period, and the non-selection is performed. In the period, a predetermined second potential is applied to the first polarity capacitor wiring included in the group and a predetermined third potential that is higher than the second potential is applied to the second polarity capacitor wiring included in the group. Give,
In the (N + 1) th frame, in the selection period, the first waveform potential is applied to the first and second polarity capacitor lines included in the group, and in the non-selection period, the third potential is applied to the group. 2. The display device according to claim 1, wherein the second polarity potential is applied to the first polarity capacitance wiring included in the group and the second potential is applied to the second polarity capacitance wiring included in the group. The first waveform potential consists of one potential,
The display device according to claim 2, wherein the storage capacitor line driving circuit sets the first waveform potential to an intermediate potential between the second potential and the third potential. The first waveform potential includes a high level first potential that is higher than the potential of the common electrode, and a low level first potential that is lower than the potential of the common electrode,
The auxiliary capacitance line driving circuit is characterized in that the high-level first potential is set to the same potential as the third potential, and the low-level first potential is set to the same potential as the second potential. 2. The display device according to 2. When we focus on any group,
The auxiliary capacitance line driving circuit alternately applies the high level first potential and the low level first potential to the first and second polarity capacitance lines included in the group during the selection period,
The timing at which the potential applied to the first polarity capacitor wiring first changes during the selection period is different from the timing at which the potential applied to the second polarity capacitor wiring first changes during the selection period. The display device according to claim 4. The scanning signal line selection period in which one scanning signal line is selected includes a preceding first scanning signal line selection period and a subsequent second scanning signal line selection period.
The scanning signal line driving circuit applies a predetermined first selection voltage that turns on all the switching elements that receive scanning signals from the scanning signal line to be selected during the selection period of the first scanning signal line. Applying a predetermined second voltage lower than the first selection voltage to the scanning signal line to be selected in the second scanning signal line selection period,
In the video signal line driving circuit, all the switching elements corresponding to the pixel electrodes to which a voltage having a gradation value within a predetermined first gradation range is to be turned off during the second scanning signal line selection period. In addition, a target voltage is applied at the start of the second scanning signal line selection period among the switching elements corresponding to the pixel electrodes to which a voltage having a gradation value outside the first gradation range is to be applied. Applying the video signal to the plurality of video signal lines so that at least a switching element that is not in a conductive state,
When paying attention to an arbitrary group, the auxiliary capacitance driving circuit detects the potential of the auxiliary capacitance wiring included in the group after the end of the first scanning signal line selection period and before the start of the second scanning signal line selection period. The display device according to claim 1, wherein the display device is changed. A plurality of video signal lines, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and a corresponding scanning signal line provided corresponding to an intersection of the plurality of video signal lines and the plurality of scanning signal lines A switching element whose conduction state is controlled by a scanning signal applied to the pixel, a pixel electrode electrically connected to a corresponding video signal line via the switching element, and a first predetermined capacitor formed between the pixel electrode A plurality of common electrodes to which a fixed potential is applied and a plurality of pixels provided so as to correspond to the plurality of scanning signal lines in a one-to-one correspondence with the pixel electrodes. Drive circuit for a display device having a display unit including the auxiliary capacitance wiring,
A scanning signal line driving circuit for selectively driving the plurality of scanning signal lines;
A video signal line driving circuit for applying a video signal to the plurality of video signal lines;
An auxiliary capacitance line driving circuit for driving the plurality of auxiliary capacitance lines,
A plurality of auxiliary capacitance lines are made into one set, and one group is formed by the auxiliary capacitance lines constituting each set and the scanning signal lines, switching elements, and pixel electrodes provided corresponding to the auxiliary capacitance lines. The plurality of auxiliary capacitance lines are grouped into a plurality of sets,
When we focus on any group,
In one frame period in which display for one screen is performed, a selection period in which scanning signal lines included in the group are sequentially driven and a scanning signal line included in a group other than the group are sequentially displayed. It consists of a non-selection period that is a period to be driven,
The auxiliary capacitor lines included in the group are a first polarity capacitor line composed of two or more auxiliary capacitor lines electrically connected to each other and two or more auxiliary capacitor lines electrically connected to each other. Divided into a second polarity capacitance wiring that is an auxiliary capacitance wiring other than the auxiliary capacitance wiring included in the first polarity capacitance wiring;
The video signal line driving circuit includes a pixel electrode provided corresponding to the first polarity capacitance wiring included in the group, and a pixel electrode provided corresponding to the second polarity capacitance wiring included in the group. Then, the video signal is applied to the plurality of video signal lines so that voltages having different polarities are written in the selection period.
In the auxiliary capacitance line driving circuit, in each frame period, for the auxiliary capacitance line corresponding to the pixel electrode in which the positive voltage is written in the selection period, the positive voltage is written in the non-selection period. For the auxiliary capacitor wiring corresponding to the pixel electrode to which a higher potential than the performed period is applied and the negative voltage is written in the selection period, the negative voltage is written in the non-selection period. The polarity of the voltage applied in the non-selection period is reversed between the first polarity capacitor line and the second polarity capacitor line when a potential lower than the period is applied and the potential of the common electrode is used as a reference. As described above, the drive circuit is characterized in that a potential is applied to the first polarity capacitance wiring and the second polarity capacitance wiring. A plurality of video signal lines, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and a corresponding scanning signal line provided corresponding to an intersection of the plurality of video signal lines and the plurality of scanning signal lines A switching element whose conduction state is controlled by a scanning signal applied to the pixel, a pixel electrode electrically connected to a corresponding video signal line via the switching element, and a first predetermined capacitor formed between the pixel electrode A plurality of common electrodes to which a fixed potential is applied and a plurality of pixels provided so as to correspond to the plurality of scanning signal lines in a one-to-one correspondence with the pixel electrodes. A driving method of a display device having a display unit including the auxiliary capacitance wiring,
A scanning signal line driving step of selectively driving the plurality of scanning signal lines;
A video signal line driving step of applying a video signal to the plurality of video signal lines;
A storage capacitor line driving step for driving the plurality of storage capacitor lines;
A plurality of auxiliary capacitance lines are made into one set, and one group is formed by the auxiliary capacitance lines constituting each set and the scanning signal lines, switching elements, and pixel electrodes provided corresponding to the auxiliary capacitance lines. The plurality of auxiliary capacitance lines are grouped into a plurality of sets,
When we focus on any group,
In one frame period in which display for one screen is performed, a selection period in which scanning signal lines included in the group are sequentially driven and a scanning signal line included in a group other than the group are sequentially displayed. It consists of a non-selection period that is a period to be driven,
The auxiliary capacitor lines included in the group are a first polarity capacitor line composed of two or more auxiliary capacitor lines electrically connected to each other and two or more auxiliary capacitor lines electrically connected to each other. Divided into a second polarity capacitance wiring that is an auxiliary capacitance wiring other than the auxiliary capacitance wiring included in the first polarity capacitance wiring;
In the video signal line driving step, a pixel electrode provided corresponding to the first polarity capacitance wiring included in the group and a pixel electrode provided corresponding to the second polarity capacitance wiring included in the group; The video signal is applied to the plurality of video signal lines so that voltages of different polarities are written in the selection period.
In the auxiliary capacitance line driving step, in each frame period, for the auxiliary capacitance line corresponding to the pixel electrode in which the positive voltage is written in the selection period, the positive voltage is written in the non-selection period. For the auxiliary capacitance wiring corresponding to the pixel electrode to which a potential higher than that in the selected period is applied and the negative voltage is written in the selection period, the negative voltage is written in the non-selection period. A potential lower than that of the first period is applied, and the polarity of the voltage applied in the non-selection period when the potential of the common electrode is used as a reference is reversed between the first polarity capacitor line and the second polarity capacitor line. A driving method is characterized in that a potential is applied to the first polarity capacitance wiring and the second polarity capacitance wiring so that

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