JP2009075225A - Liquid crystal display device and driving method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device which permits low consumption power of a partial display with a simple circuit constitution, and can prevent the occurrence of defective display when performing refresh operation of a non-display area intermittently in regard to the liquid crystal display device of a holding capacity line driving system. <P>SOLUTION: By performing refresh for every two frames in the intermittent refresh operation, a polarity signal POL repeats inversion every frame in which the refresh is performed. That is, the refresh is performed at the zero'th frame, third frame, six'th frame... and the polarity signal POL is inverted so as to turn to L level at the zero'th frame, turn to H level at the third frame and turn to L level at the six'th frame. Thereby, also in the refresh of the non-display area, the polarity signal POL is inverted as in the display area, a holding capacity line drive is performed and, therefore, the defective display can be prevented. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a storage capacitor line driving type liquid crystal display device and a driving method thereof.

  Conventionally, a storage capacitor line driving method is known as a driving method of a liquid crystal display device. In this method, a storage capacitor is provided between the storage capacitor line and the pixel electrode, and after writing a display signal to the pixel electrode, the potential of the storage capacitor line is changed to change the potential of the pixel electrode in the positive or negative direction. Change. As a result, the dynamic range of the display signal can be reduced, so that driving with low power consumption is possible. A liquid crystal display device using this storage capacitor line driving method is described in Patent Document 1.

  In addition, a partial display method is known as a display method of a liquid crystal display device. In this method, a part of the pixel area is a display area where an image is displayed, and the remaining area is a non-display area (a white or black display area) where no image is displayed. This type of liquid crystal display device is described in Patent Document 2.

Further, generally, in the non-display area, a refresh operation is performed in which a signal corresponding to non-display is periodically written to the pixel electrode of the corresponding pixel.
JP 2002-196358 A JP 2007-140192 A

  In order to reduce the power consumption associated with the refresh operation, intermittent refresh (also referred to as thinning refresh) is performed in which the refresh operation is not performed for all frames but intermittently for some frames.

  However, when intermittent refresh is performed, there is a problem that a display defect occurs in a non-display area. This is because, when intermittent refresh is performed, the polarity of the polarity signal for determining the polarity of the storage capacitor line is not reversed in the non-display area, unlike the display area, depending on the selection of the frame to be refreshed. .

  The liquid crystal display device of the present invention includes a pixel region including a plurality of pixels, a plurality of source lines, a plurality of gate lines, a plurality of storage capacitor lines, and a pixel electrode connected to the pixel and the storage capacitor line. A storage capacitor, a gate selection circuit that outputs a gate selection signal to the gate line, and a switching circuit that is provided for each pixel and performs switching according to the gate selection signal, and supplies the source signal from the source line to the pixel electrode A first switching element that latches a polarity signal that alternately repeats inversion between a first level and a second level for each frame in response to the gate selection signal; And a second switching element that switches the potential of the storage capacitor line in accordance with an output signal of the first latch circuit. In the non-display area in which no image is displayed in the pixel area, 2 In the remaining frames obtained by thinning out the above frames, a refresh operation for supplying a source signal corresponding to non-display to the corresponding pixels via the first switching element is performed, and a refresh operation is performed. Control is performed so that the polarity signal is inverted between the frame and the second frame in which the next refresh operation is performed.

  The liquid crystal display device driving method according to the present invention includes a pixel region including a plurality of pixels, a plurality of source lines, a plurality of gate lines, a plurality of storage capacitor lines, a pixel electrode of the pixel, and the storage capacitor. A storage capacitor connected between the lines; a gate selection circuit that outputs a gate selection signal to the gate line; and a source signal from the source line that is provided for each pixel and switches according to the gate selection signal. And a first switching element that latches a polarity signal that repeats inversion alternately between the first level and the second level for each frame in accordance with the gate selection signal. In a driving method of a liquid crystal display device, comprising: a latch circuit; and a second switching element that switches a potential of the storage capacitor line in accordance with an output signal of the first latch circuit. In the non-display area in which no image is displayed, refresh is performed by supplying the source signal corresponding to non-display to the corresponding pixel via the first switching element in the remaining frames obtained by thinning out two or more frames. The operation is performed, and the polarity signal is controlled to be inverted in the first frame in which the refresh operation is performed and the second frame in which the next refresh operation is performed.

  According to the present invention, low power consumption of partial display can be realized with a simple circuit configuration in a storage capacitor line driving type liquid crystal display device. In addition, when intermittent refresh is performed in order to reduce the power consumption of partial display, the polarity of the polarity signal can be reversed in the non-display area as in the display area, and display defects can be prevented.

  A liquid crystal display device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a liquid crystal display device. This liquid crystal display device employs a storage capacitor line driving system and can perform partial display.

  A plurality of pixels are arranged in a matrix to form a pixel region. In FIG. 1, nine pixels of 3 rows × 3 columns are shown for simplicity. Each pixel is arranged corresponding to each intersection of the gate lines GL1 to GL3 and the source lines SL1 to SL3, and includes a pixel transistor 10 made of an N-channel thin film transistor, a pixel electrode 11 connected to the drain of the pixel transistor 10, A liquid crystal 12 is provided between the pixel electrode 11 and the common electrode CE. A common potential VCOM is supplied to the common electrode CE.

  A first storage capacitor line SC1 is provided corresponding to the pixels in the first row, and a storage capacitor 13 is provided between the pixel electrode 11 and the first storage capacitor line SC1. A second storage capacitor line SC2 is provided corresponding to the pixels in the second row, and a storage capacitor 13 is provided between the pixel electrode 11 and the second storage capacitor line SC2. A third storage capacitor line SC3 is provided corresponding to the pixels in the third row, and a storage capacitor 13 is provided between the pixel electrode 11 and the third storage capacitor line SC3.

  The source of the pixel transistor 10 of each pixel in the first column is connected to the first source line SL1, and the source of the pixel transistor 10 of each pixel in the second column is connected to the second source line SL2. The source of the pixel transistor 10 of each pixel in the third column is connected to the third source line SL3.

  The gate of the pixel transistor 10 of each pixel in the first row is connected to the first gate line GL1, and the gate of the pixel transistor 10 of each pixel in the second row is connected to the second gate line GL2. The gate of the pixel transistor 10 of each pixel in the third row is connected to the third gate line GL3.

  In addition, a source line driving circuit 20 is provided for supplying a source signal Sig (display signal) to the first to third source lines SL1 to SL3. The polarity of the source signal Sig is inverted with respect to the reference potential at a constant cycle (for example, one horizontal cycle). Further, a DSG control circuit 21 that supplies the common potential VCOM to the first to third source lines SL1 to SL3 according to the control signal DSG is provided.

  Further, a gate line driving circuit 22 that generates gate selection signals G1 to G3 is provided. The gate selection signals G1 to G3 are generated by transferring the vertical start pulse STV based on the vertical shift pulse CKV. A gate selection circuit 24 is provided for outputting the gate selection signals G1 to G3 to the first gate line GL1 to the third gate line GL3 based on the gate selection enable signal VENB. That is, the gate selection circuit 24 is formed by AND circuits 241 to 243, the gate selection signals G1 to G3 are input to the corresponding AND circuits 241 to 243, and the gate selection enable signal VENB is common to the AND circuits 241 to 243. Have been entered. Therefore, when the gate selection enable signal VENB is at the H level, the gate selection signals G1 to G3 are output to the first gate line GL1 to the third gate line GL3. When the gate selection enable signal VENB is at the L level, the output of the gate selection circuit 24 is fixed at the L level, so that the first gate line GL1 to the third gate line GL3 are not selected (the pixel transistor 10 is off). State). The gate selection enable signal VENB is controlled by the control circuit 25.

  Further, a storage capacitor line driving circuit 23 for driving the first to third storage capacitor lines SC1 to SC3 is provided. The storage capacitor line drive circuit 23 sets the potentials of the first to third storage capacitor lines SC1 to SC3 to the low potential VCOML or the high potential based on the polarity signal POL that repeats inversion between the H level and the L level every frame. Drive to potential VCOMH.

[Configuration of storage capacitor line drive circuit]
The configuration of the storage capacitor line driving circuit 23 is shown in FIG. This circuit is called a gate latch system, and latches the polarity signal POL based on the gate selection signals G1 to G3. First latch circuits LCH11, LCH21, and LCH31 are provided corresponding to the first to third storage capacitor lines SC1 to SC3, respectively. The first latch circuits LCH11, LCH21, and LCH31 latch the polarity signal POL based on the gate selection signals G1, G2, and G3. The inverted polarity signal POL is latched in the first latch circuit LCH21 corresponding to the even lines. This is because the potentials of the storage capacitor lines corresponding to the odd lines (first line, third line,...) And even lines (second line, fourth line,. This is to make it possible. For example, the potentials of the first storage capacitor line SC1 and the second storage capacitor line SC2 are opposite in polarity.

  Further, second latch circuits LCH12, LCH22, and LCH32 are provided corresponding to the first to third storage capacitor lines SC1 to SC3, respectively. The second latch circuits LCH12, LCH22, and LCH32 latch the polarity signal POL latched by the first latch circuits LCH11, LCH21, and LCH31 based on the first to third timing clocks TCLK1 to TCLK3, respectively. The first to third timing clocks TCLK1 to TCLK3 are pulse signals generated at different timings corresponding to the respective lines. Created by the timing control circuit 231 based on the timing signal TCLK.

  The first to third latch signals POL1 to POL3, which are output signals of the second latch circuits LCH12, LCH22, and LCH32, are used as signals for controlling switching of the first to third switches SW1 to SW3 in the subsequent stage.

  FIG. 3 shows the configuration of the first switch SW1. A P-channel TFT 232 and an N-channel TFT 233 are connected in series between the high potential VCOMH and the low potential VCOML, and the first latch signal POL1 from the second latch circuit LCH12 is applied to their gates. The second and third switches SW2 and SW3 are similarly configured.

  For example, when the first latch signal POL1 is at the H level, the N-channel TFT 233 is turned on, so that the low potential VCOML is applied to the first storage capacitor line SC1, and the first latch signal POL1 is at the L level. Since the P-channel TFT 232 is turned on, the high potential VCOMH is applied to the first storage capacitor line SC1.

  The potentials of the first to third storage capacitor lines SC1 to SC2 are determined by the rising timing of the first to third timing clocks TCLK1 to TCLK3. In such a storage capacitor line driving method, such timing is generally after the gate selection signals G1 to G3 fall. FIG. 4 shows the relationship between potential changes of the gate selection signals G1 to G3, the first to third timing clocks TCLK1 to TCLK3, and the first to third storage capacitor lines SC1 to SC3.

[Configuration of Source Line Driver Circuit and DSG Control Circuit]
FIG. 5 shows the configuration of the source line driver circuit 20 and the DSG control circuit 21 around the pixel region. FIG. 5 shows only the configuration related to the pixel corresponding to the first column of the pixel area. The output terminal of the source driver 14 is connected to one end of the first source line SL1 through the horizontal switch SWH. The horizontal switch SWH switches according to the horizontal scanning signal. When the horizontal switch SWH is turned on, the source signal Sig (display signal) is supplied from the source driver 14 to the first source line SL1.

  The output terminal of the common electrode driver 15 is connected to the other end of the first source line SL1 via the switch SWS. The switch SWS switches according to the control signal DSG. The output terminal of the common electrode driver 15 is connected to the common electrode CE, and the common potential VCOM is supplied to the common electrode CE. Therefore, when the switch SWS is turned on, the first source line SL1 and the common electrode CE are short-circuited, and the common potential VCOM is also supplied to the first source line SL1 for precharging.

  Next, an operation example of the liquid crystal display device will be described with reference to a timing chart of FIG. Now, assume that partial display is being performed.

(1) Refresh operation Refresh is performed on the non-display area. In this case, the gate selection enable signal VENB is periodically generated even in the non-display area, and the gate selection signals G1 to G3 are sequentially output to the first to third gate lines GL1 to GL3. Then, a source signal sig (non-display signal) corresponding to non-display is supplied to the first source lines SL1 to SL3 and is supplied to the pixels, whereby a refresh operation is performed. On the other hand, the gate selection enable signal VENB is also periodically generated in the display area, and the gate selection signals G1 to G3 are sequentially output to the first to third gate lines GL1 to GL3. Then, the source signal sig (display signal) corresponding to the display is supplied to the first source lines SL1 to SL3 to perform normal liquid crystal display.

  The storage capacitor line driving circuit 23 is also operating. Therefore, the potentials of the first to third storage capacitor lines SC1 to SC3 are repeatedly inverted in synchronization with the first to third latch signals POL1 to POL3, and the storage capacitor line drive is performed. That is, after writing a display signal (non-display signal) to the pixel electrode, the potential of the corresponding storage capacitor line is changed, and the potential of the pixel electrode 11 is changed in the positive or negative direction. As a result, the dynamic range of the display signal can be reduced, so that driving with low power consumption is possible.

(2) Non-refresh operation In intermittent refresh, there are frames that are not refreshed. That is, the non-display area is not refreshed in the non-refresh frame. In this case, the first to third gate lines GL1 to GL3 are fixed to the L level by stopping the gate selection enable signal VENB (fixed to the L level). Thereby, the non-display signal is not written to the pixel electrode.

  As described above, in intermittent refresh, refresh can be stopped by stopping the gate selection enable signal VENB. Therefore, which frame is refreshed becomes a problem. This point will be described with reference to the timing chart of FIG.

  As shown in FIG. 7A, when refreshing every other frame in the intermittent refresh, the polarity signal POL is always at the L level in the frame to be refreshed and is not inverted to the H level. For this reason, the storage capacitor line drive is stopped (the potentials of the first to third storage capacitor lines SC1 to SC3 are fixed), which causes a display defect. In general, the polarity signal POL has the same polarity in the case of even refresh, in which refresh is performed only in even-numbered frames with reference to the refreshed frame, and thus the above problem occurs.

Therefore, as shown in FIG. 7B, in the intermittent refresh, if the refresh is performed every two frames, the polarity signal POL is repeatedly inverted every frame in which the refresh is performed. That is, refresh is performed in the 0th frame, the 3rd frame, the 6th frame,..., And the polarity signal POL is L level in the 0th frame, H level in the 3rd frame, L level in the 6th frame, and so on. Invert.
Such an operation can be realized by controlling the gate selection enable signal VENB to be activated in the specific frame by the control circuit 25.

  As a result, in the refresh of the non-display area, the polarity signal POL is inverted similarly to the display area, and the storage capacitor line drive is performed, thereby preventing display defects. In general, in the case of an odd refresh in which refresh is performed only in odd-numbered frames with reference to a refreshed frame, the polarity of the polarity signal POL is repeatedly inverted, so that the above problem can be solved. .

It is a figure which shows the structure of the liquid crystal display device by embodiment of this invention. It is a figure which shows the structure of the storage capacity line drive circuit in the liquid crystal display device by embodiment of this invention. It is a figure which shows the structure of the storage capacity line drive circuit in the liquid crystal display device by embodiment of this invention. FIG. 5 is an operation timing chart of the storage capacitor line driving circuit in the liquid crystal display device according to the embodiment of the present invention. It is a figure which shows the structure of the source line drive circuit and DSG control circuit in the liquid crystal display device by embodiment of this invention. FIG. 5 is a timing diagram illustrating an operation of the liquid crystal display device according to the embodiment of the present invention. It is a timing diagram explaining operation | movement of the liquid crystal display device by a comparative example and embodiment of this invention.

Explanation of symbols

10 pixel transistor 11 pixel electrode 12 liquid crystal 13 holding capacitor 14 source driver 15 common electrode driver 20 source line driving circuit 21 DSG control circuit 22 gate line driving circuit 23 holding capacitor line driving circuit 24 gate selection circuit 25 control circuit 231 timing control circuit 232 P-channel TFT
233 N-channel TFTs 241, 242, 243 AND circuits LCH11, LCH21, LCH31 First latch circuits LCH12, LCH22, LCH32 Second latch circuits SW1-SW3 First to third switches SC1, SC2, SC3 First to third switches Third storage capacitor line

Claims (6)

A pixel region composed of a plurality of pixels;
Multiple source lines,
Multiple gate lines,
A plurality of storage capacitor lines;
A storage capacitor connected between a pixel electrode of the pixel and the storage capacitor line;
A gate selection circuit that outputs a gate selection signal to the gate line; and a first switching element that is provided for each pixel and performs switching in accordance with the gate selection signal and supplies a source signal from the source line to a pixel electrode When,
A first latch circuit that latches a polarity signal that repeats inversion alternately between a first level and a second level for each frame in accordance with the gate selection signal;
A second switching element that switches a potential of the storage capacitor line in accordance with an output signal of the first latch circuit;
In the non-display area where no image is displayed in the pixel area, in the remaining frame obtained by thinning out two or more frames, a source signal corresponding to non-display is supplied to the corresponding pixel via the first switching element. The liquid crystal display device is characterized in that a refresh operation is performed so that the polarity signal is inverted between the first frame in which the refresh operation is performed and the second frame in which the next refresh operation is performed. . In the display area where the image is displayed, the source signal is supplied to the corresponding pixel via the first switching element, and the polarity signal which is the output signal of the first latch circuit is one frame. 2. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is controlled so as to be inverted every time. The liquid crystal display device according to claim 1, wherein the gate selection circuit includes a control circuit that controls the gate selection enable signal to output the gate selection signal based on a gate selection enable signal. A second latch circuit that latches an output signal of the first latch circuit in response to a timing signal; and the second switching element is configured to output the storage capacitor line in response to the output signal of the second latch circuit. The liquid crystal display device according to claim 1, wherein the potential is switched. A pixel region composed of a plurality of pixels;
Multiple source lines,
Multiple gate lines,
A plurality of storage capacitor lines;
A storage capacitor connected between a pixel electrode of the pixel and the storage capacitor line;
A gate selection circuit for outputting a gate selection signal to the gate line;
A first switching element provided for each of the pixels, which switches according to the gate selection signal and supplies a source signal from the source line to a pixel electrode;
A first latch circuit that latches a polarity signal that repeats inversion alternately between a first level and a second level for each frame in accordance with the gate selection signal;
In a driving method of a liquid crystal display device comprising: a second switching element that switches a potential of the storage capacitor line according to an output signal of the first latch circuit.
In the non-display area in which no image is displayed in the pixel area, in the remaining frames obtained by thinning out two or more frames, the source signal corresponding to non-display is supplied to the corresponding pixel via the first switching element. The liquid crystal display device is characterized in that a refresh operation is performed so that the polarity signal is inverted between the first frame in which the refresh operation is performed and the second frame in which the next refresh operation is performed. Driving method. A pixel region composed of a plurality of pixels;
Multiple source lines,
A plurality of storage capacitor lines;
A storage capacitor connected between a pixel electrode of the pixel and the storage capacitor line;
A gate selection circuit that outputs a gate selection signal based on a gate selection enable signal;
A first switching element provided for each of the pixels, switching according to a gate selection signal from the gate selection circuit, and supplying a source signal from the source line to a pixel electrode;
A first latch circuit that latches a polarity signal that repeats inversion alternately between a first level and a second level for each frame in accordance with a gate selection signal from the gate selection circuit;
In a driving method of a liquid crystal display device comprising: a second switching element that switches a potential of the storage capacitor line according to an output signal of the first latch circuit.
In the non-display area in which no image is displayed in the pixel area, in the remaining frames obtained by thinning out two or more frames, the source signal corresponding to non-display is supplied to the corresponding pixel via the first switching element. The gate selection enable signal is controlled so that the polarity signal is inverted in the first frame in which the refresh operation is performed and the second frame in which the next refresh operation is performed. A driving method of a liquid crystal display device.

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