JP2009071228A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device improved in current driving force by improving stress applied from a stress liner film to a channel by devising a structure. <P>SOLUTION: The semiconductor device includes a semiconductor substrate 1, an element isolation insulating film 2 formed on the semiconductor substrate 1, and a gate electrode 4 formed from the upper part of the semiconductor substrate 1 toward the upper part of the element isolation insulating film 2. The element isolation insulating film 2 has a multi-stage structure of an upper stage and a lower stage by digging down the upper part of the element isolation insulating film 2 other than a part under the gate electrode 4. The semiconductor device 1 further includes a semiconductor region which becomes a source or a drain formed on the semiconductor substrate 1 at both sides of the gate electrode 4, and the stress liner film 3 formed by covering the semiconductor region, the lower stage of the element isolation insulating film 2, and the gate electrode 4. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a stress liner film and a method for manufacturing the semiconductor device.

  In recent years, with the demand for higher integration and higher functionality of MOS transistors, scaling has been performed to improve the performance of MOS transistors. However, in current semiconductor integrated circuits in which performance improvement due to scaling is approaching the limit, attempts have been made to improve the performance of MOS transistors by techniques other than scaling. One of them is the application of local strain using a stress liner film, which is a technique for improving the mobility of electrons and holes by mechanically applying stress to a silicon substrate. Non-Patent Documents 1 and 2 below disclose semiconductor devices to which local strain is applied using this stress liner film. Hereinafter, a MOS transistor having a stress liner film will be described.

  FIG. 8A is a diagram showing a MOS transistor formed by using a stress liner film adding method in the prior art. FIG. 8B is a cross-sectional view of the MOS transistor of FIG. FIG. 8C is a cross-sectional view taken along line E-F of the MOS transistor of FIG. The MOS transistor includes a silicon substrate 1, a shallow trench isolation (STI) 2 formed on the silicon substrate 1, a gate electrode 4 formed on the silicon substrate 1 and the STI 2, and a side surface of the gate electrode 4. And a stress liner film 3 formed on the sidewall 5 formed on the STI 2, the silicon substrate 1, the STI 2, and the gate electrode 4. Here, the dimension L is the gate length, and the dimension W is the channel width.

  9 and 10 are process flows showing a method for manufacturing the MOS transistor. FIG. 9 shows a cross section taken along the line CD in FIG. 8A, and FIG. 10 shows a cross section taken along the line E-F in FIG. A method for manufacturing the MOS transistor will be described with reference to the drawings. First, an STI 2 is formed using a general MOS transistor manufacturing method, a well electrode is formed through well channel implantation, gate oxidation and polysilicon deposition, and a gate electrode 4 is formed by a photolithography process and anisotropic etching (FIG. 9). (A), FIG. 10 (a)). Next, extension implantation and halo implantation are performed using the gate electrode 4 as a mask (FIGS. 9B and 10B). Next, sidewalls 5 are formed on the side surfaces of the gate electrode 4 and on the silicon substrate 1 and the STI 2 (FIGS. 9C and 10C). Next, ion implantation is performed using the silicon substrate 1 and the sidewalls 5 as a mask, and annealing for impurity activation is performed to form a source or drain in the region of the silicon substrate 1 located under both sides of the gate electrode 4. A semiconductor region is formed (FIGS. 9D and 10D). Next, the stress liner film 3 is deposited (FIGS. 9E and 10E).

  FIG. 11 is a diagram showing the results of calculating the steps shown in FIGS. 9 and 10 using process simulation. FIG. 11 corresponds to the portion surrounded by the dotted line in FIG. 8, and the gate length L is 0.06 μm and the channel width W is 0.25 μm. FIG. 11A shows a shape after the gate electrode 4 is formed by anisotropic etching. FIG. 11B shows a shape after the stress liner film 3 is deposited. In FIG. 11A, the upper end surface of the STI 2 is slightly lower than the upper end surface of the silicon substrate 1 for the sake of convenience in order to simulate the actual STI 2 shape. The actual shape of STI2 is as shown in FIG. As a result of repeated sacrificial oxidation after the formation of STI2, removal of the oxide film by etching, gate oxidation, and removal of the oxide film by etching, a dent is formed at the end of STI2, as shown in FIG. In order to simulate this depression, the upper end surface of the STI 2 is made slightly lower than the upper end of the silicon substrate 1 for convenience in FIG.

  When the MOS transistor formed through such a process is an NMOS, the film formation conditions are adjusted so that the stress liner film 3 has an intrinsic stress of tension (it tries to shrink itself). At this time, a tensile stress is applied to the channel of the MOSFET in the channel direction, and a compressive stress is applied in the vertical direction of the wafer. Therefore, the mobility of electrons is improved by the stress applied to the MOS channel, and the current driving capability of the MOSFET can be improved. In the case of a PMOS, by adjusting the film formation conditions so that the stress liner film 3 has a compressive intrinsic stress, a compressive stress is applied to the MOS channel and a tensile stress is applied to the vertical direction of the wafer. , Current driving capability can be improved.

Shinichi Takagi, "Si-based high mobility MOS transistor technology", Applied Physics, July 4, 2005, 74, 9 F. Ootsuka, “A Highly Dense, High-Performance 130nm node CMOS Technology for Large Scale System-on-a-Chip Applications”, IEDM 2000, Tech. Digest, p575 S. T. Ahn, H, W. Kennel, J.A. D. Plummer, W. A. Tiller, “Film stress-related vacancy supersaturation in silicon under low-pressure chemical vapor deposited silicon nitride films” November 15, 1988, Volume 64, Issue 10, p 4914-4919.

  The current driving force of the MOS transistor using the stress liner film in the conventional technique increases as the intrinsic stress in the stress liner film increases. The intrinsic stress in the stress liner film can be increased by adjusting film forming conditions such as a flow rate ratio (see Non-Patent Document 3).

  However, increasing the intrinsic stress by adjusting the film forming conditions such as the flow rate ratio has a problem that the current technology has almost reached its limit.

  Accordingly, the present invention has been made to solve such a problem. By devising the structure of the MOS transistor, the stress applied to the channel by the stress liner film is increased, and a semiconductor device with improved current driving capability is obtained. With the goal.

  A semiconductor device according to an embodiment of the present invention includes a semiconductor substrate, an element isolation insulating film formed on the semiconductor substrate, and a gate electrode formed from the semiconductor substrate to the element isolation insulating film. The element isolation insulating film has a step structure of an upper stage and a lower stage by digging up the upper part of the element isolation insulating film except under the gate electrode. This semiconductor device includes a semiconductor region which is a source or drain formed on a semiconductor substrate on both sides of a gate electrode, and a stress liner film formed so as to cover the semiconductor region, the lower part of the element isolation insulating film, and the gate electrode. It has more.

  In the method for manufacturing a semiconductor device according to an embodiment of the present invention, an element isolation insulating film is formed on a semiconductor substrate, and a gate electrode is formed on the semiconductor substrate and the element isolation insulating film. Next, anisotropic etching is performed to etch the upper portion of the element isolation insulating film except under the gate electrode, thereby forming a step structure of the upper and lower steps. Next, a semiconductor region to be a source or a drain is formed in a region of the semiconductor substrate located under both sides of the gate electrode. Thereafter, a stress liner film is formed on the semiconductor substrate, the lower part of the element isolation insulating film, and the gate electrode.

  In the semiconductor device according to an embodiment of the present invention, the element isolation insulating film is formed by digging up the upper portion to form a step structure having an upper stage and a lower stage. Can be placed in position. Therefore, it is possible to apply a higher stress to the MOS channel than before, and a higher current driving force can be obtained.

  According to the method of manufacturing a semiconductor device in one embodiment of the present invention, the stress liner film deposited on the portion where the upper portion of the element isolation insulating film is etched also contributes to the stress on the MOS channel. Therefore, it is possible to apply a higher stress to the MOS channel than before, and a higher current driving force can be obtained.

<Embodiment 1>
FIG. 1A is a diagram showing a configuration of a MOS transistor formed by using the stress liner film adding method according to the first embodiment of the present invention. FIG. 1B is a cross-sectional view of the MOS transistor of FIG. FIG. 1C is a cross-sectional view taken along line E-F of the MOS transistor of FIG. This MOS transistor includes a semiconductor substrate (hereinafter referred to as a silicon substrate 1), an element isolation insulating film (hereinafter referred to as STI (Shallow Trench Isolation) 2) formed on the silicon substrate 1, and from the top of the silicon substrate 1 to the top of STI2. Stress liner film 3 formed to cover gate electrode 4 formed, sidewall 5 formed on side surfaces of gate electrode 4 and on silicon substrate 1 and STI 2, silicon substrate 1, STI 2, and gate electrode 4. It has.

  Here, the feature of the structure of the MOS transistor in the first embodiment of the present invention is a structure in which the STI 2 has a step between the upper and lower steps by digging up the upper portion other than under the gate electrode 4, The stress liner film 3 deposited on the STI 2 is a structure that is deposited on the lower part of the STI 2. Here, the dimension L is the gate length, and the dimension W is the channel width.

  2 and 3 are process flows showing the manufacturing method of this MOS transistor. 2 represents a cross section taken along the line CD in FIG. 1A, and FIG. 3 represents a cross section taken along the line E-F in FIG. A method for manufacturing the MOS transistor will be described with reference to the drawings. First, the STI 2 is formed by using a general MOS transistor manufacturing method, and the gate electrode 4 is formed by photolithography and anisotropic etching through well channel implantation, gate oxidation, and polysilicon deposition (FIG. 2). (A), FIG. 3 (a)). Next, using the gate electrode 4 as a mask, the upper part of the STI 2 except under the gate electrode 4 is partially etched and removed (FIGS. 2B and 3B). Next, extension implantation and halo implantation are performed using the gate electrode 4 as a mask (FIGS. 2C and 3C). Next, sidewalls 5 are formed on the side surfaces of the gate electrode 4 and on the silicon substrate 1 and the STI 2 (FIGS. 2D and 3D). Next, ion implantation is performed using the gate electrode 4 and the sidewalls 5 as a mask, and annealing for impurity activation is performed to form a source or drain in the region of the silicon substrate 1 located under both sides of the gate electrode 4. A semiconductor region is formed (FIGS. 2 (e) and 3 (e)). Next, the stress liner film 3 is deposited (FIGS. 2 (f) and 3 (f)).

  FIG. 4 is a diagram showing the results of calculating the steps shown in FIGS. 2 and 3 using process simulation. FIG. 4 corresponds to the portion surrounded by the dotted line in FIG. 1, and the gate length L is 0.06 μm and the channel width W is 0.25 μm. In FIG. 4, the side wall 5 attached to the side wall of the STI 2 is not shown for simplicity. FIG. 4A shows a shape after the gate electrode 4 is formed by anisotropic etching. FIG. 4B shows a shape obtained by removing the upper part of the STI 2 by etching. FIG. 4C shows the shape after the stress liner film 3 is deposited. By manufacturing the MOS transistor through the above-described process, the STI 2 has a structure having a step between an upper stage and a lower stage where the upper part other than the area under the gate electrode 4 is dug down. In addition, the stress liner film 3 deposited on the STI 2 has a structure deposited on the lower part of the STI 2.

  FIG. 5 is a diagram showing the MOS channel 6 distribution of the MOS transistor. FIG. 5 corresponds to a diagonal position with respect to the gate electrode surrounded by the dotted line in FIG. 1, and is a view seen from the gate electrode side. The MOS transistor formed by the manufacturing method of the present embodiment has a structure in which the stress liner film 3 is embedded in the lower portion of the STI 2 by etching the oxide film above the STI 2. Therefore, since the stress liner film 3 deposited on the dug-down lower portion also contributes to the stress on the MOS channel, the stress applied to the MOS channel 6 increases.

  FIG. 6 is a diagram showing the stress distribution in the MOS channel 6 calculated by the process simulation. The stress distribution along A-B in FIG. 6A is shown in FIGS. 6B and 6C. FIG. 6B shows the stress component in the channel direction, and FIG. 6C shows the stress component in the wafer vertical direction. A positive stress value represents tensile stress, and a negative stress value represents compressive stress. As can be seen from these calculation results, the stress of each component is greater in the method of adding the stress liner film 3 in the method of the present invention than in the method of adding the stress liner film 3 in the prior art. I understand.

  FIG. 7 is a diagram showing a result of calculating a change in MOS current due to an increase in stress by device simulation. It can be seen that the MOS drive current is increased by about 3% by using the method of adding the stress liner film 3 in the method of the present invention.

  As described above, according to the MOS transistor manufacturing method of the present invention, the stress liner film 3 deposited on the portion where the upper portion of the STI 2 is etched (lower portion) also contributes to the stress on the MOS channel 6. Therefore, it is possible to apply a larger stress to the MOS channel 6 than in the conventional case, and a higher current driving force can be obtained.

<Embodiment 2>
In the first embodiment, the stress liner film 3 is added directly on the silicon of the source / drain, but silicide may be formed on the silicon surface. That is, after the steps of FIGS. 2E and 3E, a silicide layer is formed on the surface of the source / drain region. Further, a thin oxide film may be formed by thermal oxidation instead of the silicide layer. Further, a thin oxide film may be deposited. Even with such a structure, as in the first embodiment, the stress liner film 3 deposited on the etched portion (lower portion) of the STI 2 also contributes to the stress on the MOS channel 6. Accordingly, it is possible to apply a larger stress to the MOS channel 6 than in the prior art, and a higher current driving force can be obtained.

  In the first embodiment, the stress liner film 3 having a tensile stress is deposited on the assumption of NMOS, but in the case of the PMOS, the stress liner film 3 having a compressive stress is deposited.

  In the process flow shown in FIGS. 2 and 3, the order of the etching of the upper part of STI 2 in step (b) and the extension / halo implantation in step (c) may be reversed.

  The present invention can be applied to all semiconductor integrated circuits in which element isolation is performed using STI and MOS current driving capability is improved using a stress liner film.

It is the figure which showed the structure of the MOS transistor in Embodiment 1 of this invention. It is the figure which showed the manufacturing method of the MOS transistor in Embodiment 1 of this invention. It is the figure which showed the manufacturing method of the MOS transistor in Embodiment 1 of this invention. It is the figure which showed the addition method of the stress liner film | membrane of the MOS transistor in Embodiment 1 of this invention. It is the figure which showed the channel distribution of the MOS transistor in Embodiment 1 of this invention. It is the figure which compared the stress distribution of the channel surface of the MOS transistor in Embodiment 1 of this invention, and the MOS transistor in a prior art. It is the figure which compared the drive current of the MOS transistor in Embodiment 1 of this invention, and the MOS transistor in a prior art. It is the figure which showed the structure of the MOS transistor in a prior art. It is the figure which showed the manufacturing method of the MOS transistor in a prior art. It is the figure which showed the manufacturing method of the MOS transistor in a prior art. It is the figure which showed the addition method of the stress liner film | membrane of the MOS transistor in a prior art. It is sectional drawing which showed the shape of an actual silicon substrate and STI.

Explanation of symbols

  1 Silicon substrate, 2 STI, 3 Stress liner film, 4 Gate electrode, 5 Side wall, 6 MOS channel.

Claims (8)

A semiconductor substrate;
An element isolation insulating film formed on the semiconductor substrate;
A gate electrode formed on the element isolation insulating film from the semiconductor substrate,
The element isolation insulating film has a step structure of an upper stage part and a lower stage part by digging up the upper part of the element isolation insulating film except under the gate electrode,
A semiconductor region to be a source or drain formed on the semiconductor substrate on both sides of the gate electrode;
A semiconductor device further comprising: a stress liner film formed to cover the semiconductor region, a lower part of the element isolation insulating film, and the gate electrode.   The semiconductor device according to claim 1, further comprising a sidewall formed on a side surface of the gate electrode and on the semiconductor substrate and the element isolation insulating film.   The semiconductor device according to claim 1, further comprising a silicide layer formed on an upper portion of the semiconductor region.   The semiconductor device according to claim 1, further comprising an insulating film formed on the semiconductor region. (A) forming an element isolation insulating film on a semiconductor substrate;
(B) forming a gate electrode on the semiconductor substrate and the element isolation insulating film;
(C) performing an anisotropic etching to etch the upper portion of the element isolation insulating film other than under the gate electrode to form a step structure of an upper step portion and a lower step portion;
(D) forming a semiconductor region serving as a source or drain in a region of the semiconductor substrate located under both sides of the gate electrode;
(E) forming a stress liner film on the semiconductor substrate, the lower part of the element isolation insulating film, and the gate electrode; and a method of manufacturing a semiconductor device.   The semiconductor device according to claim 5, further comprising a step of forming a sidewall on the side surface of the gate electrode on the semiconductor substrate and on the element isolation insulating film after the step (c). Production method.   (G) After the said process (d), the manufacturing method of the semiconductor device of Claim 5 or 6 further equipped with the process of forming a silicide layer on the said semiconductor region.   (H) The method for manufacturing a semiconductor device according to claim 5, further comprising a step of forming an insulating film on the semiconductor region after the step (d).

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