JP2009070918A - Semiconductor memory device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device capable of speedup, and its manufacturing method. <P>SOLUTION: A control gate electrode 5a is formed on a surface of a well region 3, with a control gate insulating film 4 interposed. A memory gate electrode 7a is formed on one of side faces of the control gate electrode 5a with an ONO film 6 interposed. A lightly-doped region 10a and a heavily-doped region 12a as the drain region D, and a lightly-doped region 10b and a heavily-doped region 12b as a source region S are formed on the well region. A silicon nitride film 14 is formed, as a film with relative intense tension stress, is formed to cover the control gate electrode 5a and the memory gate electrode 7a. An interlayer insulating film 20 is further formed so as to cover the silicon nitride film 14. Thus, electron mobility can be improved with the tensile stress applied to a channel region, and thereby transistor current is increased. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly to a nonvolatile semiconductor memory device having a control gate electrode and a memory gate electrode and a manufacturing method thereof.

  One type of semiconductor memory device is a nonvolatile semiconductor memory device in which information is not lost even when the power is turned off. As one of such nonvolatile semiconductor memory devices, Patent Document 1 proposes a nonvolatile semiconductor memory device that includes a control transistor including a control gate electrode in a memory cell and a memory transistor including a memory gate electrode. ing.

  In this semiconductor memory device, the control gate electrode is formed on the surface of the semiconductor substrate with a gate insulating film interposed. The memory gate electrode is formed in a sidewall shape on the side surface of the control gate electrode with an ONO (Oxide Nitride Oxide) film interposed on the surface of the semiconductor substrate. The ONO film extends from the surface of the semiconductor substrate to the side surface of the control gate electrode and is interposed between the side surface of the control gate electrode and the memory gate electrode.

A source region is formed in a region of the semiconductor substrate located on one side of the control gate electrode and the memory gate electrode, and a drain region is formed in a region of the semiconductor substrate located on the other side. Each of writing, reading and erasing operations of the memory cell is performed by applying predetermined voltages to the control gate electrode, the memory gate electrode, the source region, the drain region and the semiconductor substrate.
JP 2004-186252 A

  In recent years, miniaturization of semiconductor memory devices has been demanded along with miniaturization of electronic devices and the like. However, when the semiconductor memory device is miniaturized, there is a restriction that the current cannot be simply increased in relation to the power consumption. For this reason, there is a problem that the speed of the semiconductor memory device cannot be increased.

  The present invention has been made to solve the above-described problems, and one object is to provide a semiconductor memory device capable of increasing the speed, and another object is to provide such a semiconductor memory device. It is to provide a method for manufacturing a device.

  A semiconductor memory device according to the present invention includes a first electrode, a pair of impurity regions, a second electrode, a stress film, and a third insulating film. The first electrode is formed on the surface of the semiconductor substrate with a first insulating film interposed, and has a first side surface and a second side surface facing each other. The pair of impurity regions are formed in a region of the semiconductor substrate portion located on the first side surface and a region of the semiconductor substrate portion located on the second side surface with the first electrode interposed therebetween. The second electrode is formed on the first side surface with a second insulating film interposed on the surface of the semiconductor substrate and on the surface of the first side surface. The stress film is formed on the semiconductor substrate so as to cover the first electrode and the second electrode, and has a predetermined tensile stress for generating a tensile stress in the semiconductor substrate. The third insulating film is formed on the semiconductor substrate so as to cover the stress film.

  One method of manufacturing a semiconductor memory device according to the present invention includes the following steps. A first electrode having a first side surface and a second side surface facing each other is formed with a first insulating film interposed on the surface of the semiconductor substrate. A pair of impurity regions are formed in a region of the semiconductor substrate portion located on the first side surface and a region of the semiconductor substrate portion located on the second side surface with the first electrode interposed therebetween. A second electrode is formed on the first side surface with a second insulating film interposed on the surface of the semiconductor substrate and on the surface of the first side surface. A stress film having a predetermined tensile stress for generating a tensile stress is formed on the semiconductor substrate so as to cover the first electrode and the second electrode. A third insulating film is formed so as to cover the stress film.

  Another method of manufacturing a semiconductor memory device according to the present invention includes the following steps. A plurality of element isolation insulating films, which are spaced from each other, are formed in predetermined regions of the semiconductor substrate to partition the cell formation region. A first wiring portion including a first electrode having a first side surface and a second side surface facing each other with a first insulating film interposed on the surface of the semiconductor substrate so as to cross the plurality of element isolation insulating films and the cell formation region Form. Using the first wiring portion as a mask, the position of the upper surface of the element isolation insulating film is made lower than the position of the surface of the cell formation region. A pair of impurity regions are formed in a region of the cell formation region located on the first side surface and a region of the cell formation region located on the second side surface across the first electrode. A second wiring portion including a second electrode is formed on the first side surface with a second insulating film interposed on the surface of the cell formation region and on the surface of the first side surface. A stress film having a predetermined tensile stress for generating a tensile stress on the semiconductor substrate so as to cover the surface of the cell formation region where the first wiring part and the second wiring part are formed and the surface of the element isolation insulating film. Form. A third insulating film is formed on the stress film.

  Still another method of manufacturing a semiconductor memory device according to the present invention includes the following steps. A first wiring portion including a first electrode having a first side surface and a second side surface facing each other is formed with a first insulating film interposed on the surface of the semiconductor substrate. A stress film having a predetermined tensile stress is formed on the semiconductor substrate so as to cover the first wiring part. A predetermined heat treatment for applying a tensile stress to the base of the stress film is performed. The stress film subjected to the heat treatment is removed. A pair of impurity regions are formed in a region of the semiconductor substrate portion located on the first side surface and a region of the semiconductor substrate portion located on the second side surface with the first electrode interposed therebetween. A second wiring part including a second electrode is formed on the first side surface with a second insulating film interposed on the surface of the semiconductor substrate and on the surface of the first side surface. A third insulating film is formed on the semiconductor substrate so as to cover the first wiring portion and the second wiring portion.

  According to the semiconductor memory device of the present invention, a stress film having a predetermined tensile stress for generating a tensile stress on the semiconductor substrate is formed on the semiconductor substrate so as to cover the first electrode and the second electrode. As a result, tensile stress acts on the channel region under the first electrode to increase the mobility of electrons. As a result, the current of the transistor can be increased, and the speed of the semiconductor memory device can be increased.

  According to one method of manufacturing a semiconductor memory device of the present invention, a stress having a predetermined tensile stress for generating a tensile stress on the semiconductor substrate on the semiconductor substrate so as to cover the first electrode and the second electrode. A film is formed. As a result, tensile stress acts on the channel region under the first electrode to increase the mobility of electrons and increase the current of the transistor. As a result, the speed of the semiconductor memory device can be increased.

  According to another method of manufacturing a semiconductor memory device according to the present invention, the position of the upper surface of the element isolation insulating film is made lower than the position of the surface of the cell formation region, so that the element isolation insulating film and the element isolation insulating film It is considered that a compressive stress acts on the sandwiched cell formation region in a direction from the element isolation insulating film toward the cell formation region, and a tensile stress acts on a portion of the cell formation region where the first electrode is located. As a result, tensile stress acts on the channel region immediately below the first electrode to increase the mobility of electrons and increase the current of the transistor. As a result, the speed of the semiconductor memory device can be increased.

  According to still another method of manufacturing a semiconductor memory device according to the present invention, the semiconductor substrate is subjected to a predetermined heat treatment for applying a tensile stress to the base of the stress film formed on the semiconductor substrate. In this case, tensile stress remains as residual stress. As a result, tensile stress acts on the channel region, the electron mobility increases, and the current of the transistor can be increased. As a result, the speed of the semiconductor memory device can be increased.

Embodiment 1
Here, an example of a semiconductor memory device will be described. In a semiconductor memory device, a plurality of memory cells are formed in a matrix in a memory cell region. First, a circuit of the memory cell region is shown in FIG. As shown in FIG. 1, in the memory cell region, each of the memory gate electrodes 7 a of the memory transistors MT arranged in the column direction (vertical direction) is electrically connected to the memory gate wiring 7. In addition, each of the control gate electrodes 5 a of the control transistor CT is electrically connected to the control gate wiring 5. Each of the source regions of the memory cells arranged in the column direction is connected to the source line SL, and each of the drain regions of the memory cells arranged in the row direction (lateral direction) is connected to the bit line BL.

  Next, the structure of the memory cell region will be described. As shown in FIG. 2, a plurality of memory cells are formed in the memory cell region MC of the semiconductor substrate 1. A control gate electrode 5a and a memory gate electrode 7a are formed in one memory cell. A control gate line 5 that electrically connects the control gate electrodes 5a to each other is formed across the semiconductor substrate region of the memory cell region MC, and a memory gate line 7 that electrically connects the memory gate electrodes 7a to each other. The memory cell region is formed so as to cross the region of the semiconductor substrate.

  As shown in FIG. 3, in one memory cell, a well region 3 is formed on the surface of a semiconductor substrate 1. A control gate electrode 5a is formed on the surface of well region 3 with control gate insulating film 4 interposed. A side wall-like memory gate electrode 7a is formed on one of the side surfaces of the control gate electrode 5a. The memory gate electrode 7a is formed on the surface of the semiconductor substrate 1 with the ONO film 6 interposed. The ONO film 6 extends from the surface of the semiconductor substrate 1 to one side surface of the control gate electrode 5a and is interposed between the side surface of the control gate electrode 5a and the memory gate electrode 7a.

  A low-concentration impurity region 10a and a high-concentration impurity region 12a are formed as a drain region D in a region of the portion of the semiconductor substrate 1 located on the opposite side to the side where the memory gate electrode 7a is located across the control gate electrode 5a. Has been. On the other hand, a low concentration impurity region 10b and a high concentration impurity region 12b are provided as source regions S in a region of the semiconductor substrate 1 located on the opposite side to the side where the control gate electrode 5a is located across the memory gate electrode 7a. Is formed. Thus, the control transistor CT including the control gate electrode and the memory transistor MT including the memory gate electrode 7a are configured (see FIG. 1).

  Metal silicide films 13 are formed on the surface of the control gate electrode 5a, the surface of the memory gate electrode 7a, and the surfaces of the high-concentration impurity regions 12a and 12b, respectively. A sidewall insulating film 11 is formed on the other side surface of the control gate electrode 5a. A sidewall insulating film 11 is also formed on one side surface of the memory gate electrode 7a. A silicon nitride film 14 is formed on the semiconductor substrate 1 so as to cover the control gate electrode 5a and the memory gate electrode 7a. As will be described later, in the semiconductor memory device, the silicon nitride film 14 is formed as a film having a relatively strong tensile stress.

  Further, an interlayer insulating film 20 is formed so as to cover the silicon nitride film 14. A contact hole 20 a that exposes the surface of the drain region D is formed in the interlayer insulating film 20. A plug 21 is formed in the contact hole 20a. A wiring 22 electrically connected to the plug 21 is formed on the interlayer insulating film 20.

  Next, the operation of the memory cell will be described. In order to write, read, or erase the memory cell, a predetermined voltage is applied to each of the control gate electrode 5a, the memory gate electrode 7a, the source region S, and the drain region D. Therefore, as shown in FIG. 4, the voltage applied to the control gate electrode 5a is the voltage Vcg, the voltage applied to the memory gate electrode 7a is the voltage Vmg, the voltage applied to the source region S is applied to the voltage Vs, and the drain region D. The voltage is a voltage Vd, and the voltage applied to the semiconductor substrate is a voltage Vsub. First, as shown in FIG. 5, the write operation is performed by setting, for example, voltage Vcg = 1.5V, voltage Vmg = 12V, voltage Vs = 5V, voltage Vd = 1V, and Vsub = 0V.

  At this time, hot electrons are generated in a region (channel region) of the semiconductor substrate located immediately below the memory gate electrode 7a and the select gate electrode 5a, and the generated hot electrons are generated between the memory gate electrode 7a and the semiconductor substrate 1. It is locally injected into the select gate electrode 5a side of the silicon nitride film of the ONO film 6 interposed between the two. The injected hot electrons are trapped in the silicon nitride film. As a result, the threshold voltage of the memory transistor MT increases.

  Next, as shown in FIG. 5, the erase operation is performed by setting, for example, voltage Vcg = 0V, voltage Vmg = −5V, voltage Vs = 7V, voltage Vd = open, and Vsub = 0V. At this time, holes (holes) are generated by the band-to-band tunnel phenomenon, and the generated holes are accelerated by the electric field and injected into the silicon nitride film of the ONO film 6. As a result, the threshold voltage of the memory transistor MT is lowered.

  Then, as shown in FIG. 5, the read operation is performed by setting, for example, voltage Vcg = 1.5V, voltage Vmg = 1.5V, voltage Vs = 0V, voltage Vd = 1V, and Vsub = 0V. At this time, the voltage Vmg applied to the memory gate electrode 7a in the read operation is set to a voltage between the threshold voltage of the memory transistor in the write state and the threshold voltage of the memory transistor in the erase state. Thus, it is determined whether or not information is written in the memory transistor MT.

  In the semiconductor memory device described above, the silicon nitride film 14 is formed on the semiconductor substrate 1 so as to cover the control gate electrode 5a and the memory gate electrode 7a. As shown in FIG. 6, the silicon nitride film 14 is formed as a film having a strong force (arrow 80) for spreading outward, that is, a film having a strong tensile stress. By forming the silicon nitride film 14 having a strong tensile stress so as to cover the control gate electrode 5a and the like, the region (well region 3) of the semiconductor substrate 1 where the channel region is formed immediately below the control gate electrode 5a is formed. As indicated by an arrow 81, a tensile stress is generated. When tensile stress acts on the channel region, electrons having a relatively small effective mass increase and the mobility of the electrons increases. Thus, as a result of the increase in electron mobility, the transistor current can be increased, and the speed of the semiconductor memory device can be increased.

  Next, a method for manufacturing the semiconductor memory device described above will be described. First, as shown in FIG. 7, a well region 3 is formed in a predetermined region of the semiconductor substrate 1. Next, as shown in FIG. 8, a control gate is formed on the surface of the semiconductor substrate 1 including the well region 3. An insulating film 44 to be an insulating film is formed. A polysilicon film 55 serving as a control gate wiring is formed on the insulating film 44. Next, as shown in FIG. 9, the control gate wiring 5 is formed by subjecting the polysilicon film 55 to predetermined photolithography and etching.

  Next, by implanting predetermined impurity ions using the control gate wiring 5 as a mask, low-concentration impurity regions 10a and 10b to be part of the source region and the drain region are formed (see FIG. 10). Next, as shown in FIG. 10, an ONO (Oxide Nitride Oxide) film 6 made of a laminated film of a silicon oxide film and a silicon nitride film is formed so as to cover the control gate wiring 5. A polysilicon film 77 such as a memory gate wiring is formed on the ONO film 6.

  Next, anisotropic etching is performed on the entire surface of the polysilicon film 77 to leave the portions 77a and 77b of the polysilicon film 77 located on the side surface of the control gate wiring 5 as shown in FIG. The portion of the polysilicon film 77 is removed. Next, as shown in FIG. 12, a predetermined resist pattern 31 for forming the memory gate wiring is formed. Using the resist pattern 31 as a mask, the exposed portion 77b of the polysilicon film is etched to remove the portion 77b of the polysilicon film. Thereafter, as shown in FIG. 13, the resist pattern 31 is removed, and the remaining portion 77 a of the polysilicon film becomes the memory gate wiring 7.

  Next, an insulating film (not shown) such as a silicon oxide film is formed so as to cover the memory gate wiring 7 and the control gate wiring 5. By performing anisotropic etching on the entire surface of the insulating film, sidewall insulating films 11 are formed on one side surface of the memory gate wiring 7 and one side surface of the control gate wiring 5, respectively, as shown in FIG. It is formed.

  Next, as shown in FIG. 15, by using the memory gate wiring 7, the control gate wiring 5, the sidewall insulating film 11 and the like as a mask, predetermined impurity ions are implanted to become part of the source region and the drain region. High concentration impurity regions 12a and 12b are formed. The drain region D is formed by the low concentration impurity region 10a and the high concentration impurity region 12a, and the source region S is formed by the low concentration impurity region 10b and the high concentration impurity region 12b. The portion of the control gate wiring 5 located immediately above the region sandwiched between the drain region D and the source region S becomes the control gate electrode 5a, and the portion of the memory gate wiring 7 located immediately above the region is the memory gate electrode 7a. It becomes.

  Next, as shown in FIG. 16, a metal silicide film 13 is formed on the surfaces of the memory gate wiring 7, the control gate wiring 5, the source region S, and the drain region D by a salicide process. Next, as shown in FIG. 17, a silicon nitride film 14 is formed so as to cover the memory gate wiring 7, the control gate wiring 5, and the like, for example, by plasma CVD (Chemical Vapor Deposition). As conditions for plasma CVD, conditions are set such that the density of the silicon nitride film 14 is higher. By increasing the density, tensile stress is generated in the silicon nitride film 14. Thereafter, an interlayer insulating film 20 (see FIG. 3) is formed so as to cover the silicon nitride film 14, and a predetermined plug and wiring are formed, thereby forming the semiconductor memory device shown in FIG.

  In the semiconductor memory device formed as described above, a silicon nitride film 14 having a high tensile stress is formed as a silicon nitride film, and the silicon nitride film 14 is formed so as to cover the control gate electrode 5a and the like. The tensile stress acts on the channel region, and the mobility of electrons increases. As a result, the current of the transistor can be increased, and the speed of the semiconductor memory device can be increased.

Embodiment 2
Here, as another example of the semiconductor memory device, a semiconductor memory device will be described in which an element isolation insulating film that electrically insulates a plurality of memory cells from each other is over-etched. As shown in FIG. 18, in the memory cell region, individual memory cells are electrically insulated by the element isolation insulating film 2. 19, 20, and 21, the element isolation insulating film 2 is filled in the trench 1 a, and the portion of the element isolation insulating film 2 is removed by overetching except for the portion where the control gate wiring 5 is located. The surface is at a lower position than the surface of the cell formation region (the surface of the well region 3).

  Further, as shown in FIG. 22, in the portion of the cell region where the control gate line 5, the control gate electrode 5a, the memory gate line 7, and the memory gate electrode 7a are not located, the surface of the element isolation insulating film 2 is the well region 3. Therefore, the silicon nitride film 14 is formed so as to cover the depression and the plateau-shaped well region 3. Since other structures are the same as those of the semiconductor memory device described above, the same members are denoted by the same reference numerals, and the description thereof is omitted.

  Next, a method for manufacturing the semiconductor memory device described above will be described. First, as shown in FIG. 23, a well region 3 is formed in a predetermined region of the semiconductor substrate 1. Next, as shown in FIG. 24, a trench 1 a having a predetermined depth is formed in the well region 3. An element isolation insulating film 2 is formed so as to fill the trench 1a. Next, an insulating film 44 serving as a control gate insulating film is formed on the surface of the semiconductor substrate 1. A polysilicon film 55 serving as a control gate wiring is formed on the insulating film 44.

  Next, predetermined photoengraving processing and etching processing for forming a control gate wiring in the polysilicon film 55 are performed. As shown in FIGS. 25 and 26, by performing over-etching during the etching process, in a region other than the region where the control gate wiring 5 is formed, the portion of the element isolation insulating film 2 located in that region The position of the surface of is lower than the position of the surface of the well region 3 (depth L).

  On the other hand, as shown in FIGS. 25 and 27, the surface of the element isolation insulating film 2 and the well region 3 are not etched in the element isolation insulating film 2 located immediately below the control gate wiring 5. It is almost in the same position as the surface. Thereafter, the semiconductor memory device shown in FIGS. 19 to 22 is formed through steps similar to those shown in FIGS.

  In the semiconductor memory device formed as described above, the surface of the element isolation insulating film 2 is the surface of the well region 3 in the element formation region (well region 3) where the control gate electrode 5a and the memory gate electrode 7a are not located. Therefore, the silicon nitride film 14 is formed so as to cover the depression and the plate-like well region 3. As shown in FIGS. 28 and 29, when a tensile stress (arrow 80) is generated in the silicon nitride film 14, in particular, a plate-like well region sandwiched between the element isolation insulating film 2 and the element isolation insulating film 2 3, it is considered that compressive stress acts in the direction from the element isolation insulating film 2 to the well region 3 as indicated by an arrow 82.

  It is considered that the tensile stress 81 acts more reliably on the well region 3 where the control gate electrode 5a is located by generating such a compressive stress (arrow 82) in the region immediately below the control gate electrode 5a. Thus, tensile stress acts on the well region 3 (channel region) to increase the mobility of electrons. As a result, the current of the transistor can be increased and the speed of the semiconductor memory device can be increased.

  With regard to this overetching, in the case of a normal MOS transistor, although the effective gate width can be increased to increase the current, variation occurs when patterning the gate electrode, and the vicinity of the edge of the gate electrode Due to the fringe electric field, dose loss, etc., the channel width dependency is deteriorated. Therefore, the substantial performance as a MOS transistor tends to be deteriorated.

  In contrast, in this semiconductor memory device, the portion of the element isolation insulating film 2 located immediately below the control gate wiring 5 is not etched, and the portion of the element isolation insulating film 2 immediately below the memory gate wiring 7 is not etched. Etching is performed. In addition, since the memory gate wiring 7 is formed in a self-aligned manner, there is no pattern variation.

Embodiment 3
Here, an example of a semiconductor memory device in which stress remains in a semiconductor substrate by forming a highly stressed film will be described.

  First, the manufacturing method will be described. After the steps shown in FIGS. 7 to 9, the silicon nitride film 15 having a relatively high density and high tensile stress is formed so as to cover the control gate wiring 5 by plasma CVD as shown in FIG. Is done. Next, as shown in FIG. 31, for example, the semiconductor substrate 1 including the silicon nitride film 15 is annealed at a temperature of about 1000 ° C. Next, as shown in FIG. 32, the silicon nitride film 15 is removed. Thereafter, through the same steps as those shown in FIGS. 10 to 17 described above, a semiconductor memory device is formed as shown in FIG.

  In the semiconductor memory device described above, the silicon nitride film 15 having a relatively high tensile stress is formed so as to cover the control gate wiring 5, and the silicon nitride film 15 is subjected to an annealing process and removed. As a result, the grain size, density, and the like of the polysilicon film forming the control gate wiring located under the silicon nitride film 15 change, and tensile stress remains as residual stress (arrow 81) on the semiconductor substrate 1. Become. As a result, tensile stress acts on the channel region to increase the mobility of electrons. As a result, the current of the transistor can be increased, and the speed of the semiconductor memory device can be increased.

Embodiment 4
Here, another example of a semiconductor memory device in which stress remains in a semiconductor substrate by forming a highly stressed film will be described.

  First, the manufacturing method will be described. After the steps shown in FIGS. 7 to 11 described above, as shown in FIG. 34, the density is relatively high and tensile stress is applied so as to cover the control gate wiring 5 and the polysilicon films 77a and 77b by plasma CVD. A high silicon nitride film 16 is formed. Next, as shown in FIG. 35, the semiconductor substrate 1 including the silicon nitride film 16 is annealed at a temperature of about 1000 ° C., for example. Next, as shown in FIG. 36, the silicon nitride film 16 is removed. Thereafter, through the same steps as those shown in FIGS. 12 to 17, the semiconductor memory device is formed as shown in FIG.

  In the semiconductor memory device described above, the silicon nitride film 16 having a relatively high tensile stress is formed so as to cover the control gate wiring 5 and the polysilicon films 77a and 77b, and the silicon nitride film 16 is subjected to an annealing process and removed. Is done. As a result, the grain size, density, etc., of the polysilicon film forming the control gate wiring located under the silicon nitride film 16 or the polysilicon film serving as the memory gate wiring change, and the semiconductor substrate 1 is subjected to tensile stress. It remains as a residual stress (arrow 81). As a result, tensile stress acts on the channel region to increase the mobility of electrons. As a result, the current of the transistor can be increased, and the speed of the semiconductor memory device can be increased.

  In the semiconductor memory device manufacturing method described above, a case where the silicon nitride film 16 having a high tensile stress is formed with the polysilicon films 77a and 77b left on both side surfaces of the control gate wiring 5 is taken as an example. Although described, a silicon nitride film may be further formed after the memory gate wiring is formed on one side surface of the control gate wiring 5 as described below.

  That is, after the step shown in FIG. 13, as shown in FIG. 38, the silicon nitride film 17 having a relatively high tensile stress is formed so as to cover the control gate line 5 and the memory gate line 7. Next, as shown in FIG. 39, the silicon nitride film 17 is annealed. Next, as shown in FIG. 40, the silicon nitride film 17 is removed.

  By adding such a step, tensile stress further acts on the channel region, electron mobility increases, the transistor current can be increased, and the speed of the semiconductor memory device can be increased. it can.

  In each of the above-described embodiments, a silicon nitride film is taken as an example as a film having a relatively high tensile stress. Such a stress film is not limited to the silicon nitride film as long as it can apply a tensile stress to the semiconductor substrate, and may be another film.

  The embodiment disclosed this time is an example, and the present invention is not limited to this. The present invention is defined by the terms of the claims, rather than the scope described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a diagram showing a circuit of a memory cell of a semiconductor memory device according to a first embodiment of the present invention. 4 is a partial plan view showing a layout of a memory cell region of the semiconductor memory device in the embodiment. FIG. FIG. 3 is a cross-sectional view taken along a cross-sectional line III-III shown in FIG. 2 in the same embodiment. 4 is a schematic cross-sectional view of a memory cell for explaining an operation of the semiconductor memory device in the embodiment. FIG. FIG. 4 is a diagram showing an example of voltages applied to each part of the memory cell for explaining the operation of the semiconductor memory device in the embodiment. 4 is a partial cross-sectional view of a memory cell for illustrating the operation and effect of the semiconductor memory device in the embodiment. FIG. FIG. 28 is a cross-sectional view showing a step of the method of manufacturing the semiconductor memory device in the embodiment. FIG. 8 is a cross-sectional view showing a step performed after the step shown in FIG. 7 in the same embodiment. FIG. 9 is a cross-sectional view showing a step performed after the step shown in FIG. 8 in the same embodiment. FIG. 10 is a cross-sectional view showing a step performed after the step shown in FIG. 9 in the same embodiment. FIG. 11 is a cross-sectional view showing a step performed after the step shown in FIG. 10 in the same embodiment. FIG. 12 is a cross-sectional view showing a step performed after the step shown in FIG. 11 in the same embodiment. FIG. 13 is a cross-sectional view showing a step performed after the step shown in FIG. 12 in the same embodiment. FIG. 14 is a cross-sectional view showing a step performed after the step shown in FIG. 13 in the same embodiment. FIG. 15 is a cross-sectional view showing a step performed after the step shown in FIG. 14 in the same embodiment. FIG. 16 is a cross-sectional view showing a step performed after the step shown in FIG. 15 in the same embodiment. FIG. 17 is a cross-sectional view showing a step performed after the step shown in FIG. 16 in the same embodiment. FIG. 6 is a partial plan view showing a layout of a memory cell region of a semiconductor memory device according to a second embodiment of the present invention. FIG. 19 is a cross-sectional view taken along a cross-sectional line XIX-XIX shown in FIG. 18 in the same embodiment. FIG. 19 is a cross-sectional view taken along a cross-sectional line XX-XX shown in FIG. 18 in the same embodiment. FIG. 19 is a cross-sectional view taken along a cross-sectional line XXI-XXI shown in FIG. 18 in the same embodiment. FIG. 19 is a cross sectional view taken along a cross sectional line XXII-XXII shown in FIG. 18 in the same embodiment. FIG. 28 is a cross-sectional view showing a step of the method of manufacturing the semiconductor memory device in the embodiment. FIG. 24 is a cross sectional view corresponding to a cross sectional line XIX-XIX shown in FIG. 18 and showing a step performed after the step shown in FIG. 23 in the embodiment. FIG. 25 is a cross-sectional view showing a step performed after the step shown in FIG. 24 in the same embodiment. FIG. 26 is a cross sectional view corresponding to a cross sectional line XX-XX shown in FIG. 18 in the step shown in FIG. 25 in the embodiment. FIG. 26 is a cross sectional view corresponding to a cross sectional line XXII-XXII shown in FIG. 18 in the step shown in FIG. 25 in the embodiment. FIG. 30 is a cross sectional view taken along a cross sectional line XXVIII-XXVIII shown in FIG. 29 for describing the operation and effect of the semiconductor memory device in the embodiment. 4 is a partial plan view of a memory cell region for illustrating the operation and effect of the semiconductor memory device in the embodiment. FIG. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor memory device concerning Embodiment 3 of this invention. FIG. 31 is a cross-sectional view showing a step performed after the step shown in FIG. 30 in the same embodiment. FIG. 32 is a cross-sectional view showing a step performed after the step shown in FIG. 31 in the same embodiment. 4 is a partial cross-sectional view of a memory cell for illustrating the operation and effect of the semiconductor memory device in the embodiment. FIG. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor memory device concerning Embodiment 4 of this invention. FIG. 35 is a cross-sectional view showing a step performed after the step shown in FIG. 34 in the same embodiment. FIG. 36 is a cross-sectional view showing a step performed after the step shown in FIG. 35 in the same embodiment. 4 is a partial cross-sectional view of a memory cell for illustrating the operation and effect of the semiconductor memory device in the embodiment. FIG. FIG. 37 is a cross-sectional view showing an additional step performed after the step shown in FIG. 36 in the embodiment. FIG. 39 is a cross-sectional view showing a step performed after the step shown in FIG. 38 in the same embodiment. FIG. 40 is a cross-sectional view showing a step performed after the step shown in FIG. 39 in the same embodiment.

Explanation of symbols

  1 semiconductor substrate, 2 element isolation insulating film, 3 well region, 4 control gate insulating film, 5 control gate wiring, 5a control gate electrode, 6,6a ONO film, 7 memory gate wiring, 7a memory gate electrode, 10a, 10b low Concentration impurity region, 11 Side wall insulating film, 12a, 12b High concentration impurity region, 13 Metal silicide film, 14, 15, 16 Silicon nitride film, 20 Interlayer insulation film, 20a Contact hole, 21 Plug, 22 Wiring, 31 Resist pattern 55, 77, 77a, 77b Polysilicon film.

Claims (8)

A first electrode formed on a surface of a semiconductor substrate with a first insulating film interposed therebetween and having a first side surface and a second side surface facing each other;
A pair of impurities formed in a region of the semiconductor substrate portion located on the first side surface and a portion of the semiconductor substrate portion located on the second side surface across the first electrode Area,
A second electrode formed on the first side surface with a second insulating film interposed on the surface of the semiconductor substrate and on the surface of the first side surface;
A stress film formed on the semiconductor substrate so as to cover the first electrode and the second electrode, and having a predetermined tensile stress for generating a tensile stress in the semiconductor substrate;
A semiconductor memory device comprising: a third insulating film formed on the semiconductor substrate so as to cover the stress film. Each of the first electrode, the second electrode, and the pair of impurity regions is formed over a predetermined depth from the surface of the semiconductor substrate for partitioning a plurality of cell formation regions in which the memory cells are formed. A plurality of element isolation insulating films;
A first wiring portion formed on the surface of the semiconductor substrate and extending to include the first electrode;
A second wiring portion formed on the surface of the semiconductor substrate and extending to include the second electrode;
Of the plurality of element isolation insulating films, the first element isolation insulating film and the second element isolation insulating film are spaced apart from each other so as to sandwich one cell formation region of the plurality of cell formation regions. Arranged,
The first wiring portion and the second wiring portion are formed so as to cross the first element isolation insulating film, the one cell formation region, and the second element isolation insulating film, respectively.
In the first element isolation insulating film and the second element isolation insulating film, the positions of the upper surfaces of the first element isolation insulating film and the second element isolation insulating film, except for the region where the first electrode is positioned. Is lower than the position of the surface of the semiconductor substrate,
The stress film is formed to cover the upper surfaces of the first element isolation insulating film and the second element isolation insulating film, which are lower than the position of the surface of the semiconductor substrate, and the cell formation region. The semiconductor memory device according to claim 1.   The semiconductor memory device according to claim 1, wherein the stress film includes a silicon nitride film. Forming a first electrode having a first side surface and a second side surface facing each other with a first insulating film interposed on the surface of the semiconductor substrate;
A pair of impurity regions are formed in the region of the semiconductor substrate portion located on the first side surface and the region of the semiconductor substrate portion located on the second side surface with the first electrode interposed therebetween. And a process of
Forming a second electrode on the first side surface by interposing a second insulating film on the surface of the semiconductor substrate and on the surface of the first side surface;
Forming a stress film having a predetermined tensile stress for generating a tensile stress on the semiconductor substrate so as to cover the first electrode and the second electrode;
Forming a third insulating film so as to cover the stress film;
A method for manufacturing a semiconductor memory device, comprising: Forming a plurality of element isolation insulating films spaced apart from each other for partitioning a cell formation region in a predetermined region of a semiconductor substrate;
A first electrode including a first electrode having a first side surface and a second side surface facing each other with a first insulating film interposed on a surface of the semiconductor substrate so as to cross the plurality of element isolation insulating films and the cell formation region. Forming a wiring portion;
Using the first wiring portion as a mask, making the position of the upper surface of the element isolation insulating film lower than the position of the surface of the cell formation region;
A pair of impurity regions in the region of the cell formation region located on the first side surface and the region of the cell formation region located on the second side surface across the first electrode Forming a step;
Forming a second wiring part including a second electrode on the first side surface by interposing a second insulating film on the surface of the cell formation region and on the surface of the first side surface;
A predetermined tensile stress for generating a tensile stress on the semiconductor substrate so as to cover the surface of the cell formation region where the first wiring portion and the second wiring portion are formed and the surface of the element isolation insulating film. Forming a stress film having
Forming a third insulating film on the stress film;
A method for manufacturing a semiconductor memory device, comprising: Forming a first wiring portion including a first electrode having a first side surface and a second side surface facing each other with a first insulating film interposed on a surface of the semiconductor substrate;
Forming a stress film having a predetermined tensile stress on the semiconductor substrate so as to cover the first wiring portion;
Applying a predetermined heat treatment to exert a tensile stress on the base of the stress film;
Removing the stress film subjected to heat treatment;
A pair of impurity regions are formed in the region of the semiconductor substrate portion located on the first side surface and the region of the semiconductor substrate portion located on the second side surface with the first electrode interposed therebetween. And a process of
Forming a second wiring portion including a second electrode on the first side surface by interposing a second insulating film on the surface of the semiconductor substrate and on the surface of the first side surface;
And a step of forming a third insulating film on the semiconductor substrate so as to cover the first wiring portion and the second wiring portion. Between the step of forming the second wiring portion and the step of forming the third insulating film,
Forming another stress film having a predetermined tensile stress on the semiconductor substrate so as to cover the first wiring part and the second wiring part;
Applying a predetermined heat treatment to exert a tensile stress on the base of the other stress film;
The method of manufacturing a semiconductor memory device according to claim 6, further comprising a step of removing the other stress film subjected to heat treatment.   The method of manufacturing a semiconductor memory device according to claim 4, wherein the stress film includes a silicon nitride film.

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