JP2009070947A - Solid-state imaging device and manufacturing method thereof - Google Patents

Abstract

An FD portion having a small capacitance can be easily manufactured.
A first conductive film 52 made of non-doped conductive silicon is formed on a gate insulating film 40 formed on a silicon substrate 40 (FIG. 5A). A resist mask R2 having an opening immediately above the formation region of the FD portion is formed on the first conductive film 52, and etching is performed to remove the first conductive film 52 and the gate insulating film 40 below the opening. Thus, an opening 46 is formed (FIG. 5B). The resist mask R1 is removed, and n-type impurity ions (As ⁺ ) are implanted from above the first conductive film 52, thereby forming the FD portion 16 on the surface layer of the silicon substrate 40 (FIG. 5C). Thereafter, the first conductive film 52 is patterned, and further, a second conductive film made of non-doped conductive silicon is formed on the entire surface so as to cover the first conductive film 52, and the second conductive film is patterned. As a result, the gate electrode of the driving transistor in contact with the FD portion 16 is formed.
[Selection] Figure 5

Description

  The present invention relates to a solid-state imaging device and a manufacturing method thereof, and more particularly to a solid-state imaging device including a floating diffusion (FD) amplifier for converting a signal charge generated by photoelectric conversion into a voltage signal and outputting the voltage signal, and a manufacturing method thereof. About.

  An electronic camera such as a digital camera incorporates a CCD (charge coupled device) type or CMOS (complementary metal oxide semiconductor) type solid-state imaging device. These solid-state imaging devices receive light by a plurality of light receiving portions (light receiving elements) arranged two-dimensionally. The light receiving unit generates and accumulates signal charges corresponding to the amount of incident light by photoelectric conversion. The signal charge accumulated in the light receiving unit is transferred to the output amplifier, converted into a voltage signal by the output amplifier, and output externally. For example, in the case of a CCD type solid-state imaging device that performs charge transfer using a vertical CCD and a horizontal CCD, an output amplifier is disposed at the output end of the horizontal CCD, and sequentially converts signal charges transferred from the horizontal CCD into voltage signals. Output.

  As this output amplifier, an FD amplifier is widely used. The FD amplifier includes an FD portion composed of a diffusion layer having a high impurity concentration for accumulating signal charges, and a source follower type output circuit including a drive transistor having a gate electrode electrically connected to the FD portion. The circuit buffers and amplifies the potential of the FD section (impedance conversion) and outputs the result.

  As a method for connecting the FD portion and the gate electrode, for example, as disclosed in Patent Document 1, a contact hole is formed in an interlayer insulating film immediately above the FD portion, and a sputtering method is formed in the contact hole. A general method is to connect the FD portion and the gate electrode extending to the vicinity of the FD portion by forming a metal film such as aluminum. However, in this method, the surface area of the metal film increases, The wiring capacity resulting from the electrostatic capacity is increased. When the capacitance of the FD portion increases, the potential of the FD portion decreases due to the relationship of V = Q / C (V: potential of the FD portion, Q: accumulated charge amount of signal charge, C: capacitance), and charge There arises a problem that the voltage conversion efficiency and the SN ratio of the output signal are lowered.

  Therefore, a connection structure has been proposed in which the gate electrode of the drive transistor is in direct contact with the FD portion without using a metal film (see, for example, Patent Documents 2 and 3). Since the capacitance of the FD portion is also caused by the junction capacitance with the substrate and the parasitic capacitance between the adjacent output gate electrode and reset gate electrode, the size of the FD portion is made as small as possible, and the entire FD portion It is desired to reduce the electrostatic capacity as

  FIG. 9 shows a manufacturing method around the FD part described in Patent Document 2. First, the p-well layer 101 is formed on the surface layer of the n-type silicon substrate 100, and the FD amplifier formation region 102 and the channel region formation region 103 including the FD portion are electrically separated on the surface layer of the p-well layer 101. A field oxide film 104 is formed (FIG. 9A). Next, a channel region 105 made of an n-type diffusion layer is formed on the surface layer of the p-well layer 101 by ion implantation using a resist mask, and an ONO (Oxide-Nitride-Oxide) film or the like is formed on the n-type silicon substrate 100. A gate insulating film 106 is formed (FIG. 9B).

Next, part of the gate insulating film 106 over the channel region 105 is removed by etching using a resist mask, so that an opening 106a is formed (FIG. 9C). Then, a polysilicon (doped polysilicon) film 107 to which n-type impurity ions are added is deposited on the gate insulating film 106 by a CVD (chemical vapor deposition) method, whereby the channel region 105 under the opening 106a is deposited. Then, the FD portion 108 made of a high concentration n ⁺ -type diffusion layer is formed (FIG. 9D). The FD portion 108 is formed by n-type impurity ions contained in the doped polysilicon film 107 moving into the channel region 105 and diffusing. Thereafter, the doped polysilicon film 107 is patterned by etching using a resist mask to form a gate electrode (FIG. 9E). In this manufacturing method, the number of steps is small, and the FD portion can be easily formed.
JP 2007-208143 A US Pat. No. 6,740,915 Japanese Patent Laid-Open No. 2005-236013

  However, in the manufacturing method described above, since the FD portion is formed by impurity diffusion, the FD portion is wider than the opening width of the gate insulating film, and not only the junction capacitance but also the parasitic capacitance increases. Ideally, the width of the FD portion should be substantially the same as the opening width of the gate insulating film (that is, the contact width of the gate electrode) because of the above-described capacitance problem. Have difficulty.

  The present invention has been made in view of the above problems, and an object of the present invention is to enable easy manufacture of an FD portion having a small capacitance.

  In order to achieve the above object, a method of manufacturing a solid-state imaging device according to the present invention includes a floating diffusion part that accumulates signal charges and a transistor having a gate electrode connected to the floating diffusion part. In a manufacturing method of a solid-state imaging device including an output circuit that outputs a signal according to a potential, a gate insulating film forming step of forming a gate insulating film on a semiconductor substrate, and conductive silicon on the gate insulating film A first conductive film forming step for forming the first conductive film; and a resist mask having an opening at a position immediately above the formation region of the floating diffusion portion is formed on the first conductive film, and etching is performed. Removing the first conductive film and the gate insulating film under the opening to form an opening Forming an opening, and removing the resist mask and implanting impurity ions from above the first conductive film, thereby forming the floating diffusion portion in a surface layer of the semiconductor substrate, and the first A second conductive film forming step of forming a second conductive film made of conductive silicon on the entire surface so as to cover the conductive film; patterning the first and second conductive films; And a patterning step to be formed. Thereby, the floating diffusion part is formed in a self-aligned manner with the openings formed in the first conductive film and the gate insulating film.

  The first conductive film is preferably made of non-doped conductive silicon. The second conductive film is preferably made of non-doped conductive silicon.

  The impurity ions implanted in the ion implantation step are preferably arsenic ions. Thus, by using arsenic ions having a large mass number, diffusion is small and the degree of self-alignment is increased.

  Preferably, the method further includes a step of implanting impurity ions on the first conductive film after the first conductive film forming step. By this ion implantation, the resistance of the first conductive film can be adjusted.

  Preferably, the method further includes a step of implanting impurity ions on the second conductive film after the second conductive film forming step. By this ion implantation, the resistance of the second conductive film can be adjusted.

  The conductive silicon is preferably polysilicon or amorphous silicon.

  In addition, the solid-state imaging device of the present invention is manufactured by any one of the above manufacturing methods, and the floating diffusion portion is self-aligned with the openings formed in the first conductive film and the gate insulating film. And

  According to the method for manufacturing a solid-state imaging device of the present invention, the floating diffusion (FD) portion is formed by self-aligning with high accuracy with respect to the openings formed in the first conductive film and the gate insulating film. The width of the portion is almost the same as the width of the contact portion of the gate electrode and is minimized. As a result, the junction capacitance and the parasitic capacitance of the FD portion can be reduced, and the overall capacitance of the FD portion is reduced, so that the charge-voltage conversion efficiency is improved and the SN ratio of the output signal is increased. can get.

  In FIG. 1, a solid-state imaging device 10 according to the present invention is arranged in a two-dimensional matrix, and a plurality of light receiving units (photoelectric conversion elements) 11 that generate and store signal charges by photoelectric conversion, and a vertical direction of the light receiving unit 11. A plurality of vertical CCDs 12 that are provided for each column and transfer signal charges in the vertical direction, are connected in common to the output terminals of the vertical CCDs 12, and are connected to the output terminals of the horizontal CCDs 13 and 13. The output unit 14 is connected and converts the signal charge into a voltage signal and outputs the voltage signal to the outside. The vertical CCD 12 receives four-phase drive signals (φV1 to φV4) so that four-phase charge transfer can be performed. In addition, two-phase drive signals (φH1, φH2) are input to the horizontal CCD 13 so that two-phase charge transfer can be performed.

  The output unit 14 includes an output gate 15 provided adjacent to the output end of the horizontal CCD 13, an FD unit 16 provided adjacent to the output gate 15, and a source follower type output circuit connected to the FD unit 16. 17, a reset gate 18 provided adjacent to the FD portion 16, and a reset drain 19 provided adjacent to the reset gate 18. The output gate 15 sequentially transfers the signal charges at the end of the horizontal CCD 13 to the FD unit 16 according to the output gate signal (OG). The FD unit 16 generates a potential corresponding to the amount of accumulated signal charge. The output circuit 17 buffers and amplifies the potential generated in the FD unit 16 and outputs it as a voltage signal (Vout). The reset gate 18 discharges the signal charge in the FD unit 16 to the reset drain 19 in accordance with the reset gate signal (φRG) input every time the voltage signal (Vout) is output. A reset drain voltage (RD) is applied to the reset drain 19.

  The FD amplifier 16 is configured by the FD unit 16 and the output circuit 17. The output circuit 17 is configured as a two-stage source follower circuit including MOS type drive transistors 20a and 20b and MOS type load transistors 21a and 21b. The drain electrodes of the drive transistors 20a and 20b are connected in common, and a reset drain voltage (RD) is applied. The source electrodes of the drive transistors 20a and 20b are connected to the drain electrodes of the load transistors 21a and 21b, respectively. The source electrodes of the load transistors 21a and 21b are commonly connected and grounded. Further, the gate electrodes of the load transistors 21a and 21b are connected in common and a predetermined voltage Vg is applied.

  The gate electrode of the first-stage driving transistor 20a is connected to the FD unit 16, and the potential of the FD unit 16 is input. The source electrode of the first-stage drive transistor 20a is connected to the gate electrode of the subsequent-stage drive transistor 20b, and the output voltage of the first-stage source follower is input to the subsequent-stage source follower. The output voltage of the subsequent source follower is output as a voltage signal (Vout) from the source electrode of the subsequent driving transistor 20b.

  FIG. 2 shows a planar structure around the FD portion 16. In FIG. 2, a channel region 30 made of an n-type diffusion layer extends from the horizontal CCD 13 under the gate electrode 31 of the output gate 15 and the gate electrode 32 of the reset gate 18 to form a reset drain 19. The FD portion 16 is formed in the surface layer of the channel region 30 between the output gate 15 and the reset gate 18, and the gate electrode 33 of the drive transistor 20 a described above is connected to the FD portion 16.

  The horizontal CCD 18 includes a transfer electrode 34 formed of a first polysilicon layer and a transfer electrode 35 formed of a second polysilicon layer. The transfer electrodes 34 and 35 are provided on the channel region 30 via a gate insulating film, and are alternately arranged in the horizontal transfer direction. Note that the gate electrode 32 of the reset gate 18 is formed of a first polysilicon layer, and the gate electrode 31 of the output gate 15 is formed of a second polysilicon layer. Further, the gate electrode 33 of the driving transistor 20a is formed in a composite manner by the first and second polysilicon layers.

FIG. 3 shows a cross-sectional structure taken along line II in FIG. In FIG. 3, a p-well layer 41 is formed on the surface layer of an n-type silicon substrate (semiconductor substrate) 40. On the surface layer of the p-well layer 41, an FD amplifier formation region 50 and a channel region including an FD portion are formed. A field oxide film 42 that electrically isolates the region 51 is formed. A channel region 30 made of an n-type diffusion layer is formed on the surface layer of the p-well layer 41, and the FD portion 16 made of an n ⁺ -type diffusion layer is formed on the surface layer of the channel region 30. Yes.

  A gate insulating film 43 made of an ONO film or the like is formed on the n-type silicon substrate 40, and the gate electrode 33 of the driving transistor 20a is formed on the gate insulating film 43. The gate electrode 33 extends from the FD amplifier formation region 50 over the field oxide film 42 to the channel region formation region 51. The gate electrode 33 is formed by laminating a first electrode layer 44 made of a first polysilicon layer and a second electrode layer 45 made of a second polysilicon layer. Furthermore, an opening 46 is formed in the first electrode layer 44 and the gate insulating film 43 immediately above the FD portion 16, and the second electrode layer 45 is in contact with the surface of the FD portion 16 through the opening 46. Yes.

  The first and second electrode layers 44 and 45 are made of doped polysilicon into which n-type impurity ions are implanted. Further, the FD portion 16 is formed in self-alignment (self-alignment) with the opening 46. Further, although an interlayer insulating film, a light shielding film, and the like are formed on the gate electrode 33 and the gate insulating film 43, the illustration is omitted for simplification.

Next, the manufacturing method of the solid-state imaging device 10 is demonstrated along each process drawing shown in FIGS. 4 to 6 show a manufacturing process in a cross section taken along the line II in FIG. First, p-type impurity ions (for example, boron B ⁺ ) are implanted into the surface layer of the n-type silicon substrate 40 to form a p-well layer 41, and the surface layer of the p-well layer 41 is formed by a LOCOS (local oxidation of silicon) method. Then, a field oxide film 42 for electrically separating the FD amplifier formation region 50 and the channel region formation region 51 including the FD portion is formed (FIG. 4A). At this time, a thermal oxide film is formed on the surface of the n-type silicon substrate 40, but the illustration is omitted. The field oxide film 42 may be formed by STI (shallow trench isolation) method.

Next, a resist mask R1 having an opening in the channel region formation region 51 is formed by photolithography, and n-type impurity ions (for example, phosphorus P ⁺ ) are implanted based on the resist mask R1, thereby forming the p-well layer 41. A channel region 30 made of an n-type diffusion layer is formed on the surface layer (FIG. 4B). Next, ashing (ashing) and cleaning are performed to remove the resist mask R1 and the thermal oxide film, and a gate insulating film 43 made of an ONO film is formed by thermal oxidation and CVD (FIG. 4C). .

Next, a first conductive film 52 made of non-doped polysilicon to which no impurity ions are added is formed on the gate insulating film 43 by CVD, and n-type impurity ions (for example, for example) are formed on the first conductive film 52. , Arsenic As ⁺ ) is implanted to form the first conductive film 52 as doped polysilicon (FIG. 5A). Next, a resist mask R2 having an opening in the formation region of the FD portion is formed by photolithography, and anisotropic etching (reactive ion etching (RIE)) is performed on the basis of the resist mask R2. The film 52 and the gate insulating film 43 are partially removed to form an opening 46 (FIG. 5B). Note that the etching for forming the opening 46 is not limited to anisotropic etching, and isotropic etching can also be used.

Next, the resist mask R2 is removed by ashing, and n-type impurity ions (for example, arsenic As ⁺ ) are implanted from above the first conductive film 52, whereby the FD portion 16 made of the n ⁺ -type diffusion layer is removed from the first conductive film 52. A self-alignment (self-alignment) is formed under the openings 46 of the conductive film 52 and the gate insulating film 43 (FIG. 5C). Next, the formation region of the electrodes (the first electrode layer 44 of the gate electrode 33 of the driving transistor 20a, the gate electrode 32 of the reset gate 18, the transfer electrode 34, etc.) formed by the first polysilicon layer is covered by photolithography. A resist mask R3 is formed as described above, and anisotropic etching (reactive ion etching (RIE)) is performed based on the resist mask R3, thereby patterning the first conductive film 52, and the first electrode layer 44 described above. Etc. are formed (FIG. 6A).

Next, the resist mask R3 is removed by ashing, and a second conductive film 53 is formed by laminating non-doped polysilicon to which no impurity ions are added over the entire surface so as to cover the first electrode layer 44. By implanting n-type impurity ions (for example, arsenic As ⁺ ) onto the two conductive film 53, the second conductive film 53 is made doped polysilicon (FIG. 6B). Note that a silicon oxide film may be formed on the second conductive film 53 in order to adjust the depth of ion implantation after the second conductive film 53 is formed and before ion implantation is performed.

  Next, the formation region of the electrodes (second electrode layer 45 of gate electrode 33 of drive transistor 20a, gate electrode 31 of output gate 15, transfer electrode 35, etc.) formed by the second polysilicon layer is covered by photolithography. The resist mask R4 is formed as described above, and anisotropic etching (reactive ion etching (RIE)) is performed based on the resist mask R4 to pattern the second conductive film 53, and the second electrode layer 45 described above. Etc. are formed (FIG. 6C).

  Then, the structure shown in FIG. 3 is formed by removing the resist mask R4 by ashing. Thereafter, the solid-state imaging device 10 is completed by forming an interlayer insulating film, a light shielding film, and the like.

  As described above, according to the manufacturing method described above, the FD portion 16 is formed by self-aligning with high accuracy with respect to the opening 46 formed in the first conductive film 52 and the gate insulating film 43. The width of 16 is almost the same as the width of the contact portion of the gate electrode 33 and is minimized. As a result, the junction capacitance and parasitic capacitance of the FD unit 16 are reduced, and the overall capacitance of the FD unit 16 is reduced, so that the charge-voltage conversion efficiency is improved and the SN ratio of the output signal (Vout) is increased. An effect is obtained.

In the manufacturing method described above, arsenic As ⁺ is exemplified as the n-type impurity ion when forming the FD portion 16. Arsenic As ⁺ has a large mass number, which suppresses diffusion in the silicon substrate 40 and is therefore suitable for forming the FD portion 16 small.

  In the above embodiment, the first and second conductive films 52 and 53 formed of non-doped polysilicon are modified to doped polysilicon by implantation of n-type impurity ions. This is performed to control the contact resistance value and the wiring resistance. Depending on the characteristics of the target gate electrode 33, the ion implantation step shown in FIG. 5C and the ion implantation step shown in FIG. 6B may be omitted.

  Further, since the first conductive film 52 is formed on the gate insulating film 43, the impurity ions are not diffused into the silicon substrate 40 even if the first conductive film 52 contains impurity ions at the time of film formation. Therefore, the first conductive film 52 is not necessarily non-doped at the time of film formation.

  Since the second conductive film 53 is in contact with the surface of the silicon substrate 40 through the opening 46, in order to prevent diffusion of impurity ions into the silicon substrate 40, the second conductive film 53 is preferably non-doped at the time of film formation. The film may contain a slight amount of impurity ions. For example, when the second conductive film 53 includes impurity ions having a mass number larger than that of the impurity ions implanted into the FD portion 16, diffusion is unlikely to occur and the shape (self-aligned shape) of the FD portion 16 is changed. I will not let you.

  In the above embodiment, polysilicon (polycrystalline silicon) is used as a material for forming the first and second conductive films 52 and 53. However, amorphous silicon (amorphous silicon) is used instead of polysilicon. It may be used. In this case, non-doped amorphous silicon is used when forming the first and second conductive films 52 and 53 in the manufacturing process. Polysilicon and amorphous silicon are conductive silicon.

  Next, a solid-state imaging device according to the second embodiment of the present invention will be described. The overall configuration of the solid-state imaging device according to the present embodiment and the planar structure around the FD unit are the same as those shown in FIGS. FIG. 7 shows a cross-sectional structure taken along line II of FIG. 2 in the present embodiment.

In FIG. 7, a p-well layer 41 is formed on the surface layer of an n-type silicon substrate 40, and an FD amplifier formation region 50 and a channel region formation region 51 including the FD portion are formed on the surface layer of the p-well layer 41. An electrically isolated field oxide film 60 is formed by the STI method. Thus, the upper surface of the field oxide film 60 is substantially flush with the surface of the silicon substrate 40. Similarly to the above embodiment, a channel region 30 made of an n-type diffusion layer is formed in the surface layer of the p-well layer 41, and the surface layer of the channel region 30 is made of the n ⁺ -type diffusion layer. An FD portion 16 is formed.

  A gate insulating film 61 made of an ONO film or the like is formed on the n-type silicon substrate 40, and the gate electrode 33 of the driving transistor 20a is formed on the gate insulating film 61. The gate electrode 33 extends from the FD amplifier formation region 50 over the field oxide film 60 and onto the channel region formation region 51.

  The gate electrode 33 includes a first electrode layer 62 made of a first polysilicon layer and a second electrode layer 63 made of a second polysilicon layer, and is made into a single layer so that the height of the upper surface is equal. ing. An opening 64 is formed in the first electrode layer 62 and the gate insulating film 61 at a position immediately above the FD portion 16, and the second electrode layer 63 is embedded in the opening 64 and contacts the surface of the FD portion 16. ing.

  The first and second electrode layers 62 and 63 are made of doped polysilicon into which n-type impurity ions are implanted. Further, the FD portion 16 is formed in self-alignment (self-alignment) with the opening 64. Further, although an interlayer insulating film, a light shielding film, and the like are formed on the gate electrode 33 and the gate insulating film 61, the illustration is omitted for simplification.

Next, a method for manufacturing a solid-state imaging device according to the second embodiment of the present invention will be described with reference to each step diagram shown in FIG. First, p-type impurity ions (for example, boron B ⁺ ) are implanted into the surface layer of the n-type silicon substrate 40 to form the p-well layer 41. In this embodiment, the surface layer of the p-well layer 41 is formed by the STI method. A field oxide film 60 is formed (FIG. 8A).

Next, the structure shown in FIG. 8B is formed through the same steps as those in FIGS. 4B to 6B described in the above embodiment. The first conductive film 65 is formed after implanting n-type impurity ions (for example, arsenic As ⁺ ) on non-doped polysilicon formed on the gate insulating film 61 to form the opening 64 to form the FD portion 16. The first electrode layer 62 is formed by patterning. The second conductive film 66 is obtained by implanting n-type impurity ions (for example, arsenic As ⁺ ) on non-doped polysilicon deposited on the entire surface so as to cover the first electrode layer 62.

  Next, the surface of the second conductive film 66 is polished by CMP (chemical mechanical polish), and the surface is flattened so as to be almost the same height as the upper surface of the first electrode layer 62 (FIG. 8C). This planarization may be performed by an etch back method.

  Similarly to the above embodiment, an electrode formed by the second polysilicon layer (second electrode layer 63 of the gate electrode 33 of the drive transistor 20a, gate electrode 31 of the output gate 15, transfer electrode 35, etc.) is formed by photolithography. ) To form a resist mask R5 so as to cover the formation region, and anisotropic etching (reactive ion etching (RIE)) is performed on the resist mask R4 to pattern the second conductive film 66. An electrode pattern such as the second electrode layer 63 is formed (FIG. 8D). Thereafter, the resist mask R5 is removed by ashing to form the structure shown in FIG.

  Similarly, in the present embodiment, the first and second conductive films 65 and 66 may be amorphous silicon, and may not necessarily be non-doped at the time of film formation.

  In the first and second embodiments, the CCD type solid-state imaging device is illustrated. However, the present invention is not limited to this, and any other type such as a CMOS type may be used as long as it includes an FD amplifier. It is also applicable to the solid-state imaging device.

  Moreover, in the said embodiment, although the conductivity type in a silicon substrate is set so that an electron may be handled as a signal charge among the electron-hole pairs produced | generated by the photoelectric conversion of a photoelectric conversion element, this invention is this. However, the conductivity type may be changed so that holes are handled as signal charges.

1 is a schematic plan view illustrating a configuration of a solid-state imaging device according to a first embodiment of the present invention. It is a schematic plan view which shows the structure of the periphery of FD part. It is a schematic sectional drawing in alignment with II of FIG. It is process drawing (the 1) which shows the manufacturing method of the solid-state imaging device concerning the 1st Embodiment of this invention. It is process drawing (the 2) which shows the manufacturing method of the solid-state imaging device concerning the 1st Embodiment of this invention. It is process drawing (the 3) which shows the manufacturing method of the solid-state imaging device concerning the 1st Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the solid-state imaging device concerning the 2nd Embodiment of this invention. It is process drawing which shows the manufacturing method of the solid-state imaging device concerning the 2nd Embodiment of this invention. It is process drawing which illustrates the conventional manufacturing method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Solid-state imaging device 11 Light receiving part 12 Vertical CCD
13 Horizontal CCD
DESCRIPTION OF SYMBOLS 14 Output part 15 Output gate 16 Floating diffusion (FD) part 17 Output circuit 18 Reset gate 19 Reset drain 20a, 20b Drive transistor 21a, 21b Load transistor 30 Channel area 31, 32, 33 Gate electrode 34, 35 Transfer electrode 40 n-type Silicon substrate 41 P well layer 42, 60 Field oxide film 43, 61 Gate insulating film 44, 62 First electrode layer 45, 63 Second electrode layer 46, 64 Opening 50 FD amplifier formation region 51 Channel region including FD portion Formation region 52, 65 First conductive film 53, 66 Second conductive film

Claims (8)

Production of a solid-state imaging device comprising: a floating diffusion part that accumulates signal charges; and an output circuit that has a transistor having a gate electrode connected to the floating diffusion part and outputs a signal corresponding to the potential of the floating diffusion part In the method
A gate insulating film forming step of forming a gate insulating film on the semiconductor substrate;
A first conductive film forming step of forming a first conductive film made of conductive silicon on the gate insulating film;
A resist mask having an opening at a position immediately above the formation region of the floating diffusion portion is formed on the first conductive film, and etching is performed, whereby the first conductive film and the gate insulating film below the opening are formed. An opening forming step of removing and forming an opening;
Removing the resist mask and implanting impurity ions from above the first conductive film to form the floating diffusion portion in the surface layer of the semiconductor substrate;
A second conductive film forming step of forming a second conductive film made of conductive silicon over the entire surface so as to cover the first conductive film;
Patterning each of the first and second conductive films to form the gate electrode; and
The manufacturing method of the solid-state imaging device characterized by including this.   The method for manufacturing a solid-state imaging device according to claim 1, wherein the first conductive film is made of non-doped conductive silicon.   The method for manufacturing a solid-state imaging device according to claim 1, wherein the second conductive film is made of non-doped conductive silicon.   4. The method of manufacturing a solid-state imaging device according to claim 1, wherein the impurity ions implanted in the ion implantation step are arsenic ions. 5.   5. The method of manufacturing a solid-state imaging device according to claim 1, further comprising a step of implanting impurity ions on the first conductive film after the first conductive film forming step. .   6. The method of manufacturing a solid-state imaging device according to claim 1, further comprising a step of implanting impurity ions on the second conductive film after the second conductive film forming step. .   The method for manufacturing a solid-state imaging device according to claim 1, wherein the conductive silicon is polysilicon or amorphous silicon.   8. A solid manufactured by the manufacturing method according to claim 1, wherein the floating diffusion portion is self-aligned with an opening formed in the first conductive film and the gate insulating film. Imaging device.

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