JP2009060702A - Charge pump booster circuit - Google Patents

Abstract

In a charge pump booster circuit, when generating an output voltage _VOUT that is a non-integer multiple of an input voltage _VIN , it is necessary to configure a regulator that generates a non-integer multiple voltage from an integer multiple voltage with a high withstand voltage. is there.
A boosted output voltage _VOUT is _divided by resistors R1 and R2. The operational amplifier A controls the amplitude of the drive clocks of the capacitor drive circuits 30 and 32 with the output voltage V _A so that the _divided voltage V _B becomes V _REF . As a result, V _OUT is feedback-controlled, and a non-integer multiple V _OUT set according to V _REF and the resistance ratio (R1 / R2) is taken out from the output terminal N _OUT .
[Selection] Figure 1

Description

  The present invention relates to a charge pump booster circuit, and more particularly to a circuit that generates an output voltage that is a non-integer multiple of an input voltage.

FIG. 2 is a circuit diagram of a conventional charge pump booster circuit. This charge pump type booster circuit 2 has a charge pump unit 4 that boosts the input voltage _VIN three times, and steps down the output voltage _VIN of the charge pump unit 4 to give a desired output voltage V _OUT to the output terminal N _OUT. And a regulator unit 6 to be generated.

The charge pump unit 4 includes three switching elements SW1, SW2, and SW3 connected in series between the input terminal _NIN and the regulator unit 6. SW1 and to the connection point _{N 1} and SW2 is connected to one terminal of the first capacitor C1, to the connection point _{N 2} between the SW2 and SW3 is connected to one terminal of the second capacitor C2. The input terminal N _IN is connected to the driving power supply of the circuit, and the power supply voltage is set as the input voltage _VIN .

A switching element SW4 is connected to the other terminal of the capacitor C1 between the power supply voltage (= input voltage V _IN ) and a switching element SW5 is connected to the ground voltage GND (= 0V). Similarly, the switching element SW6 is connected to _VIN on the other terminal of the capacitor C2, and the switching element SW7 is connected to GND.

  SW1 and SW3 are switched by a control clock CLK1, and SW2 is switched by a control clock CLK2 having a phase opposite to that of CLK1. SW4 and SW5 are complementarily switched according to the control clock CLK1. SW6 and SW7 are complementarily switched according to the control clock CLK2. For example, SW1, SW3, SW5, and SW6 are selectively turned on when CLK1 is at H level (CLK2 is at L level at this time), and SW2, SW4, and SW7 are when CLK2 is at H level (at this time CLK1 Is at the L level) and is selectively turned on.

A capacitor Cout that smoothes the output voltage of the charge pump unit 4 is connected to a connection point N _R between the charge pump unit 4 and the regulator unit 6.

In the steady state, C1 when CLK1 is at H level is charged in a state where the inter-terminal voltage is _{V IN,} the potential of the _{N 1} becomes _{V IN.} When CLK2 becomes an H level, the potential of the other end of C1 is raised from GND by turning on the SW4 to _{V IN,} the potential of the _{N 1} becomes _{2V IN.} At this time, when SW2 and SW7 are on, C2 is charged to a state where the voltage between terminals is 2V _IN . When CLK1 is at H level, Cout is also charged in parallel with the above-described charging of C1. Specifically, the potential at the other end of C2 charged to the inter-terminal voltage 2V _IN rises from GND to _VIN by turning on SW6, and the potential of N ₂ becomes 3V _IN . At this time, Cout is charged by the SW3 being in the on state, and the voltage 3V _IN is obtained at _NR .

Although the above-described charge pump unit 4 is a two-stage charge pump, generally, the charge pump is set to (n−1) stages, and an n-fold boosted voltage of nV _IN can be obtained in N _R.

The regulator unit 6 includes a p-channel MOS transistor Tr and an operational amplifier A. Tr has a source connected to N _R and a drain connected to N _OUT . The operational amplifier A constitutes a non-inverting amplifier circuit, and its output voltage is applied to the gate of the Tr to control the channel current of the Tr. A reference voltage V _REF is applied to the non-inverting input terminal (+), R1 serving as a feedback resistor is connected between the inverting input terminal (−) and N _OUT, and the inverting input terminal is connected via a resistor R2. Connected to GND. MOS transistor Tr of the operational amplifier A and a p-channel feedback controls the drain current _{I D} of Tr to the potential of the connection point _{N D} between R1 and R2 and _{V REF.} As a result, an output voltage V _OUT represented by the following equation is obtained as N _OUT .
V _OUT = (1 + R1 / R2) V _REF (1)

Regulator unit 6 is a voltage _{nV IN} following range is applied to the drain of the Tr, in accordance with the resistance ratio R1 / _R2, it is possible to produce a non-integer multiple of _{V OUT} of _{V IN.}
JP 2006-280160 A

The regulator unit 6 is applied with the high voltage generated by the charge pump unit 4. That is, there is a problem that the regulator unit 6 needs to be configured with a high breakdown voltage. For example, if the size of the MOS transistor Tr is increased in order to increase the breakdown voltage, there is a problem that the chip size increases when the charge pump booster circuit 2 is configured as an integrated circuit. Further, in order to suppress the fluctuation of _VOUT due to the discharge of Cout, the regulator unit 6 is generally configured to reduce _ID . In this case, Tr is operated in a state that is almost close to OFF, and the gate voltage of Tr can be a high voltage corresponding to the voltage applied from _NR to the source. For this reason, the operational amplifier A that generates the gate voltage is also required to have a high breakdown voltage, and there is a problem that the size increases.

The present invention has been made to solve the above problems, and provides a charge pump booster circuit capable of generating an output voltage _VOUT that is a non-integer multiple of the input voltage _VIN without using a high-breakdown-voltage regulator section. The purpose is to do.

  A charge pump booster circuit according to the present invention boosts an input voltage applied to an input terminal and outputs a boosted output voltage from an output terminal, and is connected in series between the input terminal and the output terminal A plurality of switching elements in which adjacent ones are alternately rendered conductive, a capacitor having one end connected to an interconnection point of a pair of adjacent switching elements, and a clock pulse at the other end of the capacitor In synchronization with the conduction state of the switching element located on the input terminal side connected to one end of the capacitor, the other end is set to a first potential, and connected to one end of the capacitor A capacitor driving circuit having the other end as a second potential in synchronization with the conduction state of the switching element located on the output terminal side; A feedback control circuit that monitors the voltage and performs feedback control to adjust the first potential or the second potential of the clock pulse so that the boosted output voltage becomes a value according to a predetermined reference voltage; Have

  According to the present invention, the feedback control circuit monitors fluctuations in the boosted output voltage in order to control the boosted output voltage to a value corresponding to a predetermined reference voltage. The monitoring voltage is sufficient if the increase / decrease in the boosted output voltage can be grasped for feedback control, and need not be the boosted output voltage itself, but can be a relatively low voltage such as a divided voltage, for example. . That is, in the present invention, first, a high voltage regulator to which the boosted output voltage is applied is unnecessary. Further, the feedback control circuit for generating a voltage that is a non-integer multiple of the input voltage does not directly apply the boosted output voltage and does not need to be configured to have a high breakdown voltage. Therefore, according to the present invention, it is possible to reduce the number of parts to be configured with a high breakdown voltage, and it is possible to reduce the size of the circuit.

  Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.

FIG. 1 is a schematic circuit diagram of a charge pump booster circuit 20 according to an embodiment of the present invention. The charge pump booster circuit 20 can be formed as an integrated circuit on a single semiconductor chip, for example, and includes a charge pump unit 22 and a feedback control circuit 24. Here, the charge pump unit 22 is configured to boost two stages. The charge pump unit 22 includes MOS transistors SW1 to SW7 that function as switching elements, boost capacitors C1 and C2, and an output capacitor Cout. On the other hand, the feedback control circuit 24 includes resistance elements R1 and R2, an operational amplifier A, and a reference voltage source _VREF .

SW1 to SW3 are composed of, for example, n-channel MOS transistors, and are connected in series between the input terminal _NIN and the output terminal _NOUT . In SW1 to SW3, a clock signal CLK1 or CLK2 is applied to each gate from a switching control circuit (not shown). CLK1 and CLK2 are switched and H-level voltage _{V H,} and L level voltage _{V L} (the voltage _V L _{<V H)} at a constant period, and a relationship whose phases are mutually inverted. SW1 and SW3 are applied with CLK1, and SW2 is applied with CLK2. As a result, a pair of SW1 to SW3 operate in a complementary manner, and when one is applied with an H level and is in an on state (conducting state), the other is applied with an L level and is in an off state (blocking state).

C1 is connected to one end to the connection point _{N 1} between SW1 and SW2, it is connected to a capacitor drive circuit 30 comprising the other end from the SW4 and SW5. Moreover, C2 is connected to one end to the connection point _{N 2} of SW2 and SW3, is connected to a capacitor drive circuit 32 comprising the other end from the SW6 and SW7.

  SW4 and SW6 constituting the capacitor driving circuits 30 and 32 are constituted by, for example, p-channel MOS transistors, while SW5 and SW7 are constituted by, for example, n-channel MOS transistors. The sources of SW4 and SW6 are respectively connected to the output terminal of the operational amplifier A, and the sources of SW5 and SW7 are respectively connected to GND. The drains of SW4 and SW5 are connected to the other end of C1. In SW4 and SW5, CLK1 is applied to each gate in common. Here, the p-channel MOS transistor is turned on when an L level is applied to the gate, and is turned on when an H level is applied, as opposed to an n-channel transistor. Therefore, SW4 and SW5 are complementarily switched according to CLK1. On the other hand, the drains of SW6 and SW7 are connected to the other end of C2. In SW6 and SW7, CLK2 is commonly applied to the respective gates, and they are complementarily switched according to CLK2.

Cout is on the one hand is connected to an end to the output terminal _{N OUT,} is connected to the other end to GND. Cout is charged and discharged in response to the switching of SW3, the charge voltage is outputted from the _{N OUT} as the output voltage _{V OUT} of the charge pump type booster circuit 20. Cout can be set to a relatively large capacitance in order to smooth the variation in _VOUT due to switching.

R1 and R2 are connected in series between _NOUT and GND. R1, R2 functions as voltage divider which divides the _{V OUT,} produces a divided voltage _{V B} represented by the following formula to a connection point _{N B} of R1, R2.
V _B = V _OUT · R2 / (R1 + R2) (2)

Operational amplifier A has an inverting input terminal (-) is connected to the _{N B,} is connected to the non-inverting input terminal (+) to the reference voltage source _{V REF.} The output voltage V _A of the operational amplifier A is applied to the sources of SW4 and SW6. The operational amplifier A monitors the voltage V _B corresponding to V _OUT and controls the operation state of the charge pump unit 22 to adjust V _OUT .

Here, the operational amplifier A will constitute a non-inverting amplifier circuit of a kind, which controls the charge pump unit 22 so as to maintain the voltage V _B of the N _B to the inverting input terminal is connected to the reference voltage V _REF. The feedback control circuit 24 performs feedback control to make V _OUT a value corresponding to the reference voltage V _REF by the operation of the operational amplifier A. Incidentally, V _OUT obtained by the control of keeping V _B at V _REF is obtained from the equation (2).
V _OUT = V _REF (1 + R1 / R2) (3)
It becomes.

  Next, the operation of the charge pump booster circuit 20 will be described. As described above, when CLK1 is H level (CLK1 = H), CLK2 is L level (CLK2 = L), while when CLK1 is L level (CLK1 = L), CLK2 is H level (CLK2 = H). )

When CLK1 = H, one end of C1, is applied to the connected _{V IN} to _{N IN} through SW1, the other end is applied to GND by capacitor drive circuit 30, thereby C1 is charged. The charging voltage of C1 when reaching a steady state is _VIN .

When CLK2 = H, SW2 is turned on, one end of C2 are connected to _{N 1,} is applied to the potential of the _{N 1,} the other end is applied to GND by capacitor driving circuit 32. At this time, occurs charge transfer between the C1 to balance the potential and the potential of N ₂ N ₁ C2, amount that C1 is discharged, C2 is charged. Since the other end of C1 is applied the output voltage _V A of the operational amplifier A (> 0) by a capacitor drive circuit 30, at the time that the CLK2 = H, the potential of the _{N 1} and _(V IN + _{V A)} Become. The potential of the N ₁ is applied to one end of C2. When the steady state is reached, the charging voltage of C2 is (V _IN + V _A ).

When CLK1 = H, not only SW1 but also SW3 is turned on, and Cout is charged in parallel with the above-described charging of C1. By SW3 is turned on, one end of Cout is connected to the N _2, it is applied a potential of N _2. At this time, occurs charge transfer between the C2 and Cout to balance the potentials of the potential and N _OUT N _2, correspondingly to C2 is discharged, Cout is charged. Here, since the output voltage V _A (> 0) of the operational amplifier A is applied to the other end of C2 by the capacitor driving circuit 32, the potential of N ₂ is (V _IN + 2V _A ) when CLK1 = H. Become. The potential of the N ₂ is applied to one end of the Cout. When the steady state is reached, the charging voltage of Cout is (V _IN + 2V _A ), which is output as V _OUT . That is,
V _OUT = V _IN + 2V _A (4)
It is.

Here, V _A is obtained from the equations (3) and (4).
V _A = {V _REF (1 + R1 / R2) −V _IN } / 2 (5)
Is obtained. The operational amplifier A performs non-inverting amplification operation with _VA represented by the equation (5) as an operating point. For example, when V _OUT is (3) the input voltage V _B to the inverting input terminal by raising the value given by equation increases, the potential V ₊ and the inverting input terminal of the non-inverting input terminal (+) potential V _- Corresponding to the difference (V ₊ −V ₋ ) with respect to V _A becomes lower than the operating point of the equation (5). As a result, _VOUT expressed by the equation (4) also decreases. Conversely, when V _OUT drops below the value given by equation (3), the operational amplifier A operates to raise V _OUT . As described above, the feedback control circuit 24 performs feedback control so that V _OUT becomes a value corresponding to the reference voltage V _REF represented by the expression (3).

The charge pump booster circuit 20 can obtain V _OUT that is a non-integer multiple of _VIN according to V _REF and the ratio of R 1 and R 2 (R 1 / R 2), as shown in Equation (3). Is possible. In particular, if (R1 / R2) is set large, it is possible to generate a high voltage V _OUT without setting V _REF to a high voltage. That is, the input terminal voltages V ₊ and V ₋ of the operational amplifier A need not be high voltages.

Further, in the charge pump type booster circuit 2 performs conventional boosted, if (n-1) configured to perform boosting stages, _{nV IN} following _{V OUT} is obtained. The number of boosting stages of the charge pump booster circuit 20 is not limited to the above-described two stages, and can be an arbitrary number of stages. For comparison under the same conditions, let us consider a case where the charge pump type booster circuit 20 is set to the number of boosting stages (n−1) and V _OUT less than nV _IN is obtained. V _{A in} this case is the following equation corresponding to equation (4):
V _OUT = V _IN + (n−1) V _A (6)
From
V _A = {V _OUT −V _IN } / (n−1) (7)
It is. The upper limit _{V A} of the V _A (max) _is the value at which a V OUT = _{nV IN,} its value is given by the following equation (7).
V _A (max) = V _IN (8)

That is, the output voltage V _A of the operational amplifier A is also not necessary to basically a high voltage. In other words, the operational amplifier A does not need to have a high voltage at both the input terminal and the output terminal, and does not need to be configured to have a high breakdown voltage.

Incidentally, in the charge pump type booster circuit 20, since V _A may be set to voltages above V _IN, within the scope of the breakdown voltage of the operational amplifier A, and sets the boost voltage per stage to a value greater than V _IN It is also possible to obtain a higher _VOUT than before with a small number of boosting stages.

As is clear from the above description, the boosted voltage per stage is determined by the amplitude of the capacitor drive clock applied to the other ends of the boost capacitors C1 and C2 by the capacitor drive circuits 30 and 32. Therefore, the voltage V _CL at the time of falling of the capacitor driving clock is fixed to GND, and the voltage V _CH at the time of rising is controlled by the output voltage V _A of the operational amplifier A, contrary to the above-described configuration, V _CH is fixed. A configuration in which _VCL is feedback controlled by a circuit including the operational amplifier A is also possible. In this case, for example, when V _OUT increases, the feedback control circuit is configured to increase V _A and reduce the amplitude of the capacitor drive clock, contrary to the above configuration. For example, in this case, the operational amplifier A is used to configure an inverting amplifier circuit instead of the non-inverting amplifier circuit configured as described above.

In the above-described embodiment, the positive voltage booster circuit boosts the voltage in the positive direction. However, the negative voltage booster circuit increases the absolute value of the voltage in the negative direction. For example, the negative voltage booster circuit is configured to apply CLK2 to the gates of SW4 and SW5 of the capacitor driving circuit 30 and apply CLK1 to the gates of SW6 and SW7 of the capacitor driving circuit 32 in the circuit shown in FIG. Can be realized. In this configuration, the charging voltage V _{OUT of} Cout is (V _IN −2V _A ) instead of the voltage expressed by the equation (4). When V _IN is a negative voltage, it is apparent that V _OUT is a voltage having an absolute value increased in the negative direction as compared with V _IN , and a boosted negative voltage can be obtained. If the number of boosting stages is (n−1), V _OUT is V _IN − (n−1) _VA instead of the expression (6).

  According to the present invention, a high withstand voltage regulator is not required, and the operational amplifier A that constitutes the feedback control circuit 24 is not required to have a high withstand voltage, and the portion requiring a high withstand voltage in the circuit can be reduced. . Therefore, it is easy to reduce the chip size in that the increase in the size of the transistor for ensuring the breakdown voltage is suppressed.

  The switching control circuit for supplying CLK1 and CLK2 may be formed outside the semiconductor chip on which the charge pump booster circuit 20 is formed, or may be formed on the same chip.

1 is a schematic circuit diagram of a charge pump booster circuit according to an embodiment of the present invention. It is a circuit diagram of a conventional charge pump booster circuit.

Explanation of symbols

  20 charge pump type booster circuit, 22 charge pump unit, 24 feedback control circuit, 30, 32 capacitor drive circuit, SW1 to SW7 MOS transistor, C1, C2 boost capacitor, Cout output capacitor, A operational amplifier, R1, R2 resistor.

Claims (2)

In the charge pump booster circuit that boosts the input voltage applied to the input terminal and outputs the boosted output voltage from the output terminal,
A plurality of switching elements connected in series between the input terminal and the output terminal, wherein adjacent ones are alternately made conductive;
A capacitor having one end connected to an interconnection point of a pair of the switching elements adjacent to each other;
A clock pulse is supplied to the other end of the capacitor, and the other end is set to a first potential in synchronization with the conduction state of the switching element connected to one end of the capacitor and located on the input terminal side, A capacitor driving circuit that is connected to one end of a capacitor and has the other end as a second potential in synchronization with the conduction state of the switching element located on the output terminal side;
Feedback control for monitoring the boosted output voltage and performing feedback control for adjusting the first potential or the second potential of the clock pulse so that the boosted output voltage becomes a value corresponding to a predetermined reference voltage. Circuit,
A charge pump type booster circuit. The charge pump booster circuit according to claim 1,
The feedback control circuit includes:
A voltage dividing circuit for dividing the boosted output voltage;
A reference voltage source for generating the reference voltage;
An amplifier that generates an output corresponding to a difference between the divided voltage output from the voltage dividing circuit and the reference voltage;
Have
The capacitor driving circuit uses the output of the amplifier as a supply source of either the first potential or the second potential;
A charge pump booster circuit.

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