JP2009060144A - Electronic component built-in multilayer board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic component having a highly reliable connection structure that does not cause a crack starting from a contact point between an edge of a transition layer and a passivation layer and that does not allow a processing solution to enter the interface between a die pad and a resin layer through a wall surface of a bump. A built-in multilayer substrate is provided.
A recess 24 formed in a core substrate 23, a resin layer 26 filled in the recess, an electronic component 25 embedded in the resin layer, a transition layer 29 formed on a pad 27 of the electronic component, and a pad are covered. A passivation film 28, a via hole 31 formed on the transition layer, and a wiring layer 32 connected to the transition layer via the via hole. The diameter (Dd) of the transition layer is set to be smaller than the diameter (De) of the pad and larger than the opening diameter (Df) of the passivation film covering the pad, and the roughened portion is formed only on the contact surface with the resin layer. The height of the boundary surface between the transition layer and the via hole is made lower than the opening surface of the recess.
[Selection] Figure 1

Description

  The present invention relates to a multilayer substrate with a built-in electronic component, and more particularly, to a multilayer substrate with a built-in electronic component that incorporates an electronic component in which a transition layer having an arbitrary height dimension is formed on a die pad.

  An electronic component built-in type multi-layer substrate is an “embedded” electronic component such as a semiconductor integrated circuit (hereinafter abbreviated as “IC”) chip in a multilayer printed wiring board (in this specification, “built-in” for convenience). Expresses)) and is composed. Since the electronic component and the printed wiring board are directly connected by a via hole or the like, for example, a connecting member (wire, lead or bump) in a mounting method such as wire bonding, TAB (Tape Automated Bonding) or flip chip Etc.) is not required. Therefore, various problems (disconnection, contact failure, corrosion, etc.) related to those connecting members do not occur, and high reliability is obtained.

<First Conventional Example: For example, see Patent Document 1>
FIG. 7 is a cross-sectional view (a) of the first conventional example and an enlarged cross-sectional view (b) thereof. In these figures, the electronic component built-in multilayer substrate 1 has a multilayer structure of one or more layers, for example, a three-layer structure, and an arbitrary layer (first layer in the figure) is a heat sink using aluminum or the like. A core substrate 3 having a predetermined thickness dimension Ha is laminated on the plate 2, and an electronic component 5 is placed in a recess (also simply referred to as a depression or a cavity) 4 formed in the core substrate 3. After fixing the bottom surface of the component 5 and the heat sink plate 2 with an adhesive, the gap between the recesses 4 is filled with an insulating resin 6 and sealed.

  Here, the electronic component 5 has an arbitrary number (for convenience, three in the figure) of electrodes (hereinafter referred to as “die pads”) 7 formed on the upper surface 5a and covers the upper surface 5a. A hole 8a is formed in the passivation film 8 so as to expose a part of each surface of the die pad 7 and has a predetermined height that is electrically connected to the die pad 7 through the hole 8a. A transition layer 9 having a dimension Hb is provided. More specifically, the transition layer 9 includes a small width portion 9a having a width dimension substantially equal to the opening dimension Da of the hole 8a formed in the passivation film 8, and the die pad 7 continuous to the upper portion of the small width portion 9a. It consists of a large part 9b having a width dimension Dc larger than the width dimension Db, and the total height dimension of the small width part 9a and the large part 9b is Hb. The surface of the transition layer 9 is roughened to increase the bonding strength with the insulating resin 6. In the example shown in the drawing, the processed surface subjected to the roughening treatment is indicated by sawtooth wavy lines. .

  The transition layer 9 is made of a highly conductive material such as copper, and the diameter dimension of the transition layer 9 (however, the width dimension when facing the drawing: Dc) is a hole 8a formed on the die pad 7. Larger than the opening diameter (Da) of (Dc> Da). This is because the description of the drawing (especially FIG. 6) of the cited reference 1 and the paragraph [0037] of the cited cited reference 1 (especially “a larger diameter transition layer is interposed on the pad of the IC chip”). ).

  In the illustrated electronic component built-in multilayer substrate 1, an insulating layer 10 having a predetermined thickness is stacked on the first layer having such a structure, and a required number of via holes 11 and a predetermined number of via holes 11 are formed in the insulating layer 10. A conductor circuit 12 having a required shape is formed to form a second layer, and an insulating layer 13 having a predetermined thickness is further laminated on the second layer, and a required number of via holes are formed in the insulating layer 13. 14 and a conductor circuit 15 of a required shape are formed to form a third layer, and solder bumps 16 for connecting to an external substrate such as a daughter board are formed on the uppermost conductor circuit 15, The entire surface of the uppermost layer except the solder bump 16 formation portion is coated with an insulating film 17.

<Second Conventional Example: For example, see Patent Document 2>
As a second conventional example, one in which the diameter dimension (Dc) of the transition layer 9 is “more than” the opening diameter (Da) of the hole 8 a formed on the die pad 7 is known. Specifically, as described in “Claim 2” of Patent Document 2, it is defined that “the width of the transition layer is 1.0 to 30 times the width of the pad”. If attention is paid to “1.0”, which is the numerical value limitation as defined above, “the width of the transition layer = 1.0 times the width of the pad”, this means that the transition layer 9 in the first conventional example described above. This means that the diameter dimension (Dc) is equal to the opening diameter (Da) of the hole 8a formed on the die pad 7 (Dc = Da).

<Third Conventional Example: For example, see Patent Document 3>
In the third conventional example, a stud bump is formed on a bonding pad formed on a semiconductor chip, the semiconductor chip is mounted in a concave portion of a printed circuit board, and then the semiconductor chip is embedded by filling the concave portion with an insulating resin. For example, a technique is disclosed in which the head of the stud bump is exposed from the resin layer by drilling with the method described above.
JP 2001-339165 A ([0017]-[0019], [0037], FIG. 6) JP 2001-352174 A ([Claim 2]) Japanese Patent No. 2842378 ([0016]-[0020], FIGS. 1 and 3)

However, the above first to third conventional examples have the following problems.
(1) In the first conventional example, since the transition layer (diameter Dc)> pat (diameter Da), a crack is likely to occur at the contact point between the edge of the transition layer and the passivation layer. There is a problem that damage to the die occurs when the semiconductor substrate is passed through.
(2) In the second conventional example, the transition layer (diameter Dc) ≧ pat (diameter Da), and particularly when Dc = Da, no damage to the die occurs, but the transition layer and the pad are the same. It is very difficult to form with a width, and there is a problem that it is not practical.
(3) In the third conventional example, since the die pad portion (die pad portion having a high flatness) other than the bump mounting area is in contact with the resin layer, the treatment liquid passes through the bump wall surface during plating or desmear treatment. There is a problem that it easily penetrates into the interface of the layer and peeling occurs.

  Accordingly, the object of the present invention is to cause die damage from cracks starting from the contact points between the edge of the transition layer and the passivation layer among the above-mentioned problems, and the treatment liquid passes through the wall surface of the bump. Both of the fact that penetration and separation at the interface between the die pad and the resin layer are new findings and are not described in any prior art, so that these problems can be solved simultaneously and are highly reliable. An object of the present invention is to provide an electronic component built-in multilayer substrate having a connection structure.

In order to achieve the above object, the present invention provides a recess formed in a core substrate, a resin layer filled in the recess, an electronic component embedded in the resin layer, and a pad of the electronic component. A built-in electronic component comprising: a transition layer formed; a passivation film covering the pad; a via hole formed on the transition layer; and a wiring layer connected to the transition layer via the via hole. In the substrate, a diameter (Dd) of the transition layer is set smaller than a diameter (De) of the pad and larger than an opening diameter (Df) of a passivation film covering the pad, and the transition layer is formed of the resin A roughened portion only on the contact surface with the layer, and the height of the boundary surface between the transition layer and the via hole is It is characterized in that less than the mouth surface.
In the present invention, since the diameter of the transition layer is set smaller than the diameter of the pad and larger than the opening diameter of the passivation film covering the periphery of the pad, the corner of the transition layer is not located on the pad. For this reason, even if there is a passivation film below the transition layer, cracks in the passivation film and the structural member (Si, etc.) below the passivation film, regardless of the stress from the top (force generated during resin pressing, etc.) Occurrence is avoided.

  According to the present invention, since the diameter of the transition layer is set smaller than the diameter of the pad and larger than the opening diameter of the passivation film covering the periphery of the pad, the corner of the transition layer is not located on the pad. For this reason, even if there is a passivation film under the transition layer, cracks in the passivation film and the structural member (Si, etc.) below the passivation film, regardless of the stress from the top (force generated during resin pressing, etc.) Occurrence can be avoided. Further, by roughening the surface of the transition layer, the bond with the insulating resin can be strengthened to avoid peeling and the like.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a cross-sectional view (a) and an enlarged cross-sectional view (b) of a main part of a multilayer substrate with a built-in electronic component according to an embodiment.
In these drawings, the electronic component built-in multilayer substrate 21 has a multilayer structure of one or more layers. Hereinafter, although not particularly limited, a three-layer structure is used for convenience of explanation. The first layer (corresponding to an arbitrary layer described in the gist of the invention) is obtained by laminating a core substrate 23 made of copper or the like having a predetermined height dimension Ha on a heat sink plate 22 using aluminum or the like, and the core. Arbitrary electronic components 25 are put into the recesses (or depressions or cavities) 24 formed on the substrate 23, and the space between the bottom surface of the electronic components 25 and the heat sink plate 22 is fixed with an adhesive, and then the gaps in the recesses 24 are insulated. The resin 26 is filled and sealed.

  The electronic component 25 in the present embodiment has an arbitrary number (for convenience, three in the drawing) of die pads (or electrodes or terminals) 27 formed on the upper surface 25a and is formed so as to cover the upper surface 25a. A hole 28a is formed in the passivation film 28 so as to expose a part of the surface of each die pad 27, and a predetermined height is electrically connected to the die pad 27 through the hole 28a. It has a transition layer 29 made of a highly conductive material such as copper having a dimension Hb.

  The transition layer 29 has a shape with substantially the same width dimension over its entire height, for example, a shape similar to the letter “I” of the alphabet. Specifically, for example, the transition layer 29 The width dimension Dd is smaller than the diameter De of the die pad 27 over the entire height dimension Hb (De> Dd), and the hole 28a formed in the passivation film 28 has a height dimension Hd. They are arranged so as to be larger than the opening dimension Df (Df <Dd). In short, they have a cross-sectional shape of a cylindrical body having a relationship of De> Dd and Df <Dd. Further, the surface of the transition layer 29 in the present embodiment is roughened in order to increase the bonding strength with the insulating resin 26. In the example shown in the drawing, the processed surface subjected to the roughening treatment has a sawtooth shape. It is shown with a wavy line.

  In the illustrated electronic component built-in multilayer substrate 21, an insulating layer 30 having a predetermined thickness is laminated on the first layer having such a structure, and a required number of via holes 31 and a required shape are formed in the insulating layer 30. The conductive circuit 32 is formed as a second layer, and an insulating layer 33 having a predetermined thickness is further laminated on the second layer, and a predetermined number of via holes 34 are formed in the insulating layer 33. A conductor circuit 35 having a required shape is formed to form a third layer, and a solder bump 36 for connecting to an external substrate such as a daughter board is formed on the uppermost conductor circuit 35, and these solder bumps are formed. The entire surface of the uppermost layer except the portion where 36 is formed is coated with an insulating film 37.

Said electronic component 25 is manufactured by the following processes. Here, an IC chip manufacturing process is taken as an example, but the present invention is not limited to this. For example, a passive component such as a resistor, a capacitor, or a coil, or a component including them may be used.
<Fig. 2 (a)>
First, the die pad 27 is formed on the silicon wafer 41 by a known method. The size of the die pad 27 is De.
<Fig. 2 (b)>
Next, a passivation film 28 having a predetermined thickness is formed so as to cover the die pad 27, and a hole 28 a is formed in the passivation film 28 to expose all the die pads 27. The opening size of the hole 28a is Df smaller than the size (De) of the die pad 27.

<FIGS. 3A to 3C>
Next, a resist layer 42 is formed so as to cover the entire passivation film 28. Then, an exposure mask 43 having a predetermined size (Dd) opening 43 a is placed on the resist layer 42, and exposure and development are performed to form an opening 42 a in the resist layer 42.
<Fig. 3 (d)>
Next, the transition layer 29 is formed in the opening 42a of the resist layer 42 and the hole 28a of the passivation film 28 by bonder or plating. The material of the transition layer 29 can be arbitrarily selected from copper, nickel, gold, silver, zinc, iron, etc., but the material of the conductor layer (via hole 31) formed in the upper layer in the subsequent process is copper. Then, it is preferable that the material of the transition layer 29 is the same (copper) in terms of affinity. Also, in the following roughening treatment, it is preferable that the material of the transition layer 29 is copper even when considering that the roughness peak Rz of the roughening treatment is about 0.5 to 2 μm.

  Here, the size (Dd) of the opening 43a of the exposure mask 43 is larger than the opening size Df of the hole 28a formed in the passivation film 28 (Df <Dd) and smaller than the diameter De of the die pad 27 (De>). Dd).

<FIGS. 4A to 4C>
Next, the remaining resist layer 42 is removed to expose the transition layer 29, and the exposed surface 29a is roughened by, for example, spraying a roughening liquid such as Meltex CZ8100. . In addition, when the peak to peak of the roughness (unevenness) of the roughening treatment of the exposed surface 29a is Rz, Rz is about 0.1 to 4 μm (preferably, Rz = 0.5 to 2 μm). desirable.
<FIGS. 5A and 5B>
Finally, the silicon wafer 41 is cut into a desired size, and each piece is made into an electronic component 25, which is embedded in an arbitrary layer (first layer for convenience in this embodiment), and the electronic component shown in FIG. The built-in multilayer substrate 21 is manufactured.

  As described above, in the electronic component built-in multilayer substrate 21 of the present embodiment, the diameter (Dd) of the transition layer 29 is smaller than the diameter (De) of the pad 27 and the opening diameter (Df) of the passivation film 28. Even when the pressure (see the white arrow in FIG. 1B) when the upper layer is stacked is applied to the transition layer 29 because it is larger, that is, the relationship of “De> Dd> Df”. Since a uniform force is applied in the width direction of the transition layer 29, no stress concentration occurs. Therefore, it is possible to avoid a crack in the passivation film 28 and to obtain a specific effect that the reliability of the electronic component 25 can be improved.

  In the above embodiment, the height dimension of the transition layer 29 is Hb, but the present invention is not limited to this. For example, it may be a thin film-like transition layer 29b having a height dimension Hb ′ much smaller than Hb (see FIG. 6A). In this case, for example, a via hole 45 is formed in the insulating resin layer 44 laminated on the transition layer 29b, and the via in the upper layer is formed via the via hole 45 and the thin film transition layer 29b. What is necessary is just to connect between the hole 31 (refer Fig.1 (a)) and the die pad 27 of the electronic component 25. FIG.

  In the above example, the transition layer 29 (or 29b) is formed directly on the die pad 27 of the electronic component 25, but it may be formed indirectly with a conductive film interposed therebetween. That is, a structure of die pad 27 / conductive film / transition layer 29 (or 29b) may be used. In this case, the conductive film can be selected from copper, gold, silver, tin, chromium, titanium, nickel, zinc, cobalt, and the like. The conductive film can be formed by sputtering or plating, and the thickness of the conductive film can be 0.01 to 1.0 μm.

It is sectional drawing (a) of the electronic component built-in type multilayer substrate in embodiment, and its principal part expanded sectional view (b). It is a manufacturing process figure (the 1) of the electronic component in an embodiment. It is a manufacturing process figure (the 2) of the electronic component in embodiment. It is a manufacturing process figure (the 3) of the electronic component in embodiment. FIG. 6 is a fourth manufacturing process diagram of an electronic component in the embodiment. It is the principal part expanded sectional view which shows the modification of the electronic component built-in type multilayer substrate in embodiment. It is the sectional view (a) which shows an example of the conventional multilayer board | substrate with a built-in electronic component, and the principal part expanded sectional view (b).

Explanation of symbols

21 Multi-layer substrate with built-in electronic components 24 Cavity 25 Electronic components 27 Die pad (pad)
28 Passivation film 29 Transition layer 31 Via hole 32 Conductor circuit (wiring layer)

Claims (4)

A recess formed in the core substrate, a resin layer filled in the recess, an electronic component embedded in the resin layer, a transition layer formed on the pad of the electronic component, and a passivation covering the pad In an electronic component-embedded substrate comprising a film, a via hole formed on the transition layer, and a wiring layer connected to the transition layer through the via hole,
Setting the diameter (Dd) of the transition layer to be smaller than the diameter (De) of the pad and larger than the opening diameter (Df) of the passivation film covering the pad;
The transition layer has a roughened portion only on a contact surface with the resin layer, and a height of a boundary surface between the transition layer and the via hole is lower than an opening surface of a recess of the core substrate. Electronic component built-in multilayer board. A recess formed in the core substrate, a resin layer filled in the recess, an electronic component embedded in the resin layer, a transition layer formed on the pad of the electronic component, and a passivation covering the pad In an electronic component-embedded substrate comprising a film, a via hole formed on the transition layer, and a wiring layer connected to the transition layer through the via hole,
Setting the diameter (Dd) of the transition layer to be smaller than the diameter (De) of the pad and larger than the opening diameter (Df) of the passivation film covering the pad;
The transition layer has a roughened portion only on the contact surface with the resin layer, the material of the transition layer is copper, and the roughness peak Rz of the roughening treatment of the roughened portion is A multilayer board with a built-in electronic component, characterized by having a thickness of 0.5 μm to 2 μm.   2. The electronic component built-in type according to claim 1, wherein the material of the transition layer is copper, and the roughness peak Rz of the roughening portion is 0.5 μm to 2 μm. Multilayer board.   4. The electronic component built-in multilayer substrate according to claim 1, wherein a material of the transition layer and a material of a via hole formed on the transition layer are both copper.

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