JP2009060082A - Semiconductor device and driving method thereof - Google Patents

Abstract

A semiconductor device which can be driven with a low power supply and which can obtain a high gain and a driving method thereof are provided.
A first semiconductor region 11 and a second semiconductor region 10 are adjacent to each other at junction surfaces 30a and 30b, a pn junction forming a potential barrier, and an insulator in the first semiconductor region 11 in the vicinity of the junction surface. 12, a second electrode 21 connected to the first semiconductor region 11, and a third electrode 20 connected to the second semiconductor region. When a forward bias is applied between the second electrode 21 and the third electrode 20, the potential barrier is lowered corresponding to the bonding surface. The potential barrier is changed by applying a potential difference between the first electrode 22 and the second electrode 21, and the first semiconductor region 11 is a surface vicinity region on the surface layer of the boundary with the insulator 13. Is formed as a channel 31 through which a drive current flows. As a result, the semiconductor device can be driven as a transistor.
[Selection] Figure 1

Description

  The present invention is named as a semiconductor device (Field Effect Bipolar Transistor) having a part of the structure of a semiconductor device and its driving method, in particular, a MOS FET (Metal-Oxide-Semiconductor Field Effect Transistor) and a bipolar transistor. ) And its driving method.

    In recent years, with the progress of miniaturization technology in integrated circuit manufacturing, the power supply voltage that can be used on the integrated circuit is decreasing due to the thinning of the gate oxide film and the thinning of the diffusion region. When using a normal bipolar transistor on an integrated circuit, it is difficult to operate with a low voltage and low power consumption because a bias voltage to the base region is required. It is an obstacle to use above.

    Another disadvantage of bipolar transistors is the low input resistance. On the other hand, the field effect transistor has a feature that the input resistance is large, and does not require a steady bias current, so that it is widely used in current integrated circuits as a highly convenient element.

    The exponential function characteristic of a bipolar transistor has an advantage that a large gain can be easily realized as compared with the square characteristic of a field effect transistor. At present, however, a field effect transistor is used instead of a bipolar transistor. An amplifier using a field effect transistor is inferior to a bipolar transistor in terms of gain, output resistance, operation speed, and the like. Therefore, an element that replaces a field effect transistor is required in next-generation high-speed communication technology.

  Incidentally, Non-Patent Document 1 is a semiconductor device in which an electrode is directly attached to a semiconductor substrate. Non-Patent Document 1 shows a MOS FET in which an electrode is embedded in a pn junction using a source / drain layer as a metal layer.

Toshiba Review Vol.56No.4 (2001)

  However, there is no semiconductor device that can be driven at a low voltage and can obtain a high gain, and a driving method thereof.

    Therefore, an object of the present invention is to provide a semiconductor device that can be driven at a low voltage and can obtain a high gain.

      (1) The first configuration of the present invention has a first impurity concentration region having a first impurity concentration and a hole density higher than a conduction electron density and a second impurity concentration, and the conduction electron density is the hole density. A joined body having a higher second impurity concentration region joined at a joining surface; a first electrode connected to the first impurity concentration region in the vicinity of the joining surface through an insulator; and the first impurity concentration A second electrode directly connected to the region and a third electrode directly connected to the second impurity concentration region, and constitutes a potential barrier from the junction surface corresponding to the first impurity concentration region. By applying a forward bias between the first electrode and the third electrode, the potential barrier is lowered, and the first impurity concentration region is formed on the surface layer at the boundary with the insulator. 1 near-surface region where the impurity concentration is insufficient Results that are formed as a channel to flow a driving current between the electrode and the third electrode is a semiconductor device which is characterized in that can be driven as a transistor.

(2) A second configuration of the present invention has a first impurity concentration region having a first impurity concentration and a hole density higher than a conduction electron density and a second impurity concentration, and the conduction electron density is the hole density. A step of forming a bonded body in which the higher second impurity concentration region is bonded at the bonding surface, and a first electrode connected to the first impurity concentration region through the insulator in the vicinity of the bonding surface A step of forming a second electrode directly connected to the first impurity concentration region, and a step of forming a third electrode directly connected to the second impurity concentration region, from the bonding surface Forming a potential barrier corresponding to the first impurity concentration region, and further applying a forward bias between the first electrode and the third electrode, the potential barrier being lowered, 1 impurity concentration region is the boundary with the insulator The semiconductor is characterized in that in the surface layer, the region near the surface where the first impurity concentration is insufficient is formed as a channel through which a driving current flows between the first electrode and the third electrode, and can be driven as a transistor. It is a drive method of an apparatus.

    According to the first or second configuration of the present invention, the first electrode connected to the joined body including the first impurity concentration region and the second impurity concentration region via the insulator, and directly to the second impurity concentration region. A forward bias is applied between the third electrode to be connected. In this case, the potential barrier is lowered. The first impurity concentration region is formed in a surface layer at a boundary with the insulator as a channel through which a driving current flows between the first electrode and the third electrode in a region near the surface where the first impurity concentration is insufficient. Is done. As a result, the semiconductor device of the present invention can be driven as a transistor.

  (3) According to a third configuration of the present invention, a joined body in which a first semiconductor region containing minority carriers as conduction electrons and a second semiconductor region containing majority carriers as conduction electrons are joined at a joining surface; A first electrode provided in the vicinity of the first semiconductor region via an insulator; a second electrode directly connected to the first semiconductor region; and a third electrode directly connected to the second semiconductor region; And a potential barrier is formed corresponding to the first semiconductor region from the junction surface, and the potential barrier is reduced by forward biasing between the first electrode and the third electrode. In the first semiconductor region, a region near the surface is formed as a channel for flowing a driving current as a diffusion current dependent on the minority carriers at the boundary with the insulator, and can thereby be driven as a transistor. That It is a semiconductor device according to symptoms.

  (4) The fourth configuration of the present invention is a step of forming a joined body in which a first semiconductor region containing minority carriers as conduction electrons and a second semiconductor region containing majority carriers as conduction electrons are joined at a joining surface; Forming a first electrode provided in the first semiconductor region via an insulator in the vicinity of the bonding surface; forming a second electrode directly connected to the first semiconductor region; Forming a third electrode directly connected to the semiconductor region, and forming a potential barrier corresponding to the first semiconductor region from the junction surface, and forming the first electrode and the third electrode; Further comprising a step of forward-biasing the potential barrier, the potential barrier is lowered, the first semiconductor region is a boundary with the insulator, and the surface vicinity region is a diffusion dependent on the minority carriers. Drive current as current Is formed as Yaneru, thereby, a driving method of a semiconductor device, characterized in that can be driven as a transistor.

      According to the third or fourth configuration of the present invention, the first electrode connected to the joined body composed of the first semiconductor region and the second semiconductor region via the insulator and directly connected to the second semiconductor region. A forward bias is applied between the third electrode. In this case, the potential barrier is lowered. The first semiconductor region has a surface vicinity region where the conduction electrons of minority carriers in the first semiconductor region become excessive between the first electrode and the third electrode on a surface layer at a boundary with the insulator. It is formed as a channel through which a drive current flows. As a result, the semiconductor device of the present invention can be driven as a transistor.

  According to a fifth configuration of the present invention, a p-type semiconductor region joined at a pn junction surface and a pn junction constituting the n-type semiconductor region are connected to the pn junction near the pn junction surface via an insulator. A first electrode connected to the p-type semiconductor region, and a third electrode connected directly to the n-type semiconductor region. Correspondingly, a potential barrier is formed, and a forward voltage is applied in an operation region between the first electrode and the third electrode. In the n-type semiconductor region, conduction electrons of majority carriers pass through the potential barrier. Is diffused to the p-type semiconductor region, the operating region is shifted in the negative direction, a reverse voltage is applied, and the holes of the majority carriers in the p-type semiconductor region are accumulated, and the conduction electrons of the minority carriers While reducing the diffusion current, The carriers flowing in the pn junction can be controlled by an electric field by eliminating minority carrier holes in the n-type semiconductor region and increasing the diffusion current of conduction electrons of majority carriers. It is a semiconductor device.

  A sixth configuration of the present invention includes a step of forming a p-type semiconductor region and a pn junction constituting the n-type semiconductor region that are joined at a pn junction surface, and an insulator in the pn junction near the pn junction surface. Forming a first electrode connected via the first electrode; forming a second electrode directly connected to the p-type semiconductor region; and forming a third electrode directly connected to the n-type semiconductor region. And a step of forming a potential barrier corresponding to the first semiconductor region from the junction surface and applying a forward voltage in an operation region between the first electrode and the third electrode; The n-type semiconductor region includes a step of diffusing majority-carrier conduction electrons across the potential barrier to the p-type semiconductor region, moving the operating region in a negative direction, and applying a reverse voltage; The p-type semiconductor region further includes In addition to reducing the diffusion current of minority carrier conduction electrons by setting the majority carrier holes in the accumulation state, the minority carrier holes in the n-type semiconductor region are rejected and increasing the diffusion current of majority carrier conduction electrons. By doing so, the carrier flowing in the pn junction can be controlled by an electric field.

  According to the fifth and sixth configurations of the present invention, the potential barrier is configured corresponding to the first semiconductor region from the junction surface, and the forward voltage is applied in the operation region between the first electrode and the third electrode. Is applied. At this time, in the n-type semiconductor region, conduction electrons of majority carriers diffuse over the potential barrier and diffuse into the p-type semiconductor region. When the operating region is shifted in the negative direction and a reverse voltage is applied, the holes of majority carriers in the p-type semiconductor region are accumulated, the diffusion current of conduction electrons of the minority carriers decreases, and the n-type Minority carrier holes in the semiconductor region are eliminated, and the diffusion current of conduction electrons of majority carriers increases. Thereby, the carriers flowing in the pn junction can be controlled by the electric field.

A seventh configuration of the present invention includes a first semiconductor region having a first impurity concentration,
A first electrode connected to the first semiconductor region via an insulator; one and other embedded regions configured in the first semiconductor region at a position sandwiching the first electrode; and the one embedded region The second electrode directly connected, the third electrode directly connected to the other buried region, and the one buried region are filled with a first impurity plus semiconductor having a concentration higher than the first impurity concentration. In the other buried region, a high-concentration second impurity plus semiconductor of a second impurity semiconductor having a second impurity concentration different from the first impurity concentration is buried, and the first electrode, the third electrode, A forward voltage is applied in the operation region between the first semiconductor region, carriers in the first semiconductor region are accumulated, a reverse voltage is applied by moving the operation region in a negative direction, and the second impurity plus region is applied. The semiconductor device is characterized in that the carriers flowing from the second impurity plus region to the first impurity plus region can be controlled by an electric field by setting the carriers to the excluded state.

    According to an eighth aspect of the present invention, there is provided a step of forming a first semiconductor region having a first impurity concentration, a step of forming a first electrode connected to the first semiconductor region via an insulator, Forming one and the other buried regions configured in the first semiconductor region at a position sandwiching one electrode, forming a second electrode directly connected to the one buried region, and the other buried Forming a third electrode directly connected to the region; and filling the one buried region with a first impurity plus semiconductor having a concentration higher than the first impurity concentration, and filling the other buried region with A high concentration second impurity plus semiconductor of a second impurity semiconductor having a second impurity concentration different from the first impurity concentration is embedded, and a forward voltage is applied in an operation region between the first electrode and the third electrode. The process of applying And further comprising a step of putting carriers in the first semiconductor region into an accumulation state, moving the operation region in a negative direction and applying a reverse voltage, and putting carriers in the second impurity plus region into a rejection state. Thus, the method for driving a semiconductor device is characterized in that the carriers flowing from the second impurity plus region to the first impurity plus region can be controlled by an electric field.

  According to the seventh and eighth configurations of the present invention, the second electrode is connected in one buried region, and the first impurity plus semiconductor having a higher concentration than the first impurity concentration is buried. The third electrode is connected in the other buried region, and a second impurity semiconductor having a high concentration of a second impurity semiconductor having a second impurity concentration different from the first impurity concentration is buried. When a forward voltage is applied in the operation region between the first electrode and the third electrode, carriers in the first semiconductor region are in an accumulation state, and the operation region is shifted in the negative direction to cause a reverse voltage. Applied. Carriers in the second impurity plus region are rejected, and carriers flowing from the second impurity plus region to the first impurity plus region can be controlled by an electric field.

  According to the semiconductor device and the driving method thereof of the present invention, the diffusion current in the pn junction can be directly controlled by the electric field. Since the collector current has an exponential characteristic with respect to the gate voltage and the forward bias voltage of the emitter-side pn junction, a high gain amplifier can be easily realized.

  In addition, since the bias input terminal for injecting carriers into the base region and the gate terminal for signal input are independent, the signal input terminal does not require a bias current or a large bias voltage and operates with a low power supply voltage. There is an effect that a transistor can be realized.

    A semiconductor device and a driving method thereof according to an embodiment of the present invention will be described. The present invention has created a structure and a control system for applying electric field control to a pn junction, and has the advantages of both a conventional field effect transistor and a bipolar transistor, and is a semiconductor device that can operate under a low power supply voltage. A field effect bipolar transistor (FEBT).

  More specifically, by attaching an insulated electrode to the joined body, the energy band on the joined body surface is bent according to the relationship between the work function of the electrode material and the Fermi level determined by the impurity concentration on the joined body surface.

Emitter - If only biasing Vf the pn junction in the forward direction between the base, the base region conduction electrons are majority carriers in the emitter region is beyond the potential barrier V _s corresponding to the potential obtained by subtracting the bias voltage V _f from the diffusion potential Vd The holes which are majority carriers in the base region also diffuse into the emitter region. The conduction electrons diffused in the base region are taken into the collector disposed at a distance shorter than the diffusion length of the conduction electrons.

In this process, when a slight negative voltage V _gn is applied to the gate electrode and an electric field is applied to the bipolar transistor region, the p-type semiconductor in the base region is in an accumulation state, so that the surface concentration of holes becomes the gate voltage V _gn . On the other hand, the Fermi level approaches the valence band while increasing approximately exponentially, and the potential difference in the surface layer region between both regions of the pn junction increases by approximately V _gn . Due to this effect, there is little change in the diffusion current of holes from the base region, and the diffusion current of conduction electrons from the emitter region is reduced.

On the other hand, since the n-type semiconductor in the emitter region is rejected by applying a negative gate voltage V _gn , the surface concentration of conduction electrons decreases almost exponentially with respect to the gate voltage V _gn and the Fermi level is reduced. As the Fermi level of the intrinsic semiconductor is approached, the potential barrier difference between the two regions of the pn junction decreases by approximately V _gn . Due to this effect, there is little change in the diffusion current of conduction electrons from the emitter region, and the diffusion current of holes from the base region increases.

Due to these two effects, when the impurity concentration of the semiconductor constituting the emitter region is higher than that of the base region and the diffusion current of the pn junction is determined by the conduction electron concentration of the emitter, the emitter- The current of the base pn junction decreases exponentially with respect to the negative gate voltage V _gn .

When a slight positive voltage V _gp is applied to the gate electrode, the p-type semiconductor in the base region is in an excluded state, so that the surface concentration of holes decreases almost exponentially with respect to the gate voltage V _gp . The Fermi level approaches the Fermi level of the intrinsic semiconductor, and the potential difference between the two regions of the pn junction is reduced by approximately V _gp . Due to this effect, the change in the diffusion current of holes from the base region is small, and the diffusion current of conduction electrons from the emitter region increases.

On the other hand, since the n-type semiconductor in the emitter region becomes an accumulation state by applying a positive gate voltage V _gp , the surface concentration of conduction electrons increases almost exponentially with respect to the gate voltage V _gp , and the Fermi level is When approaching the conduction band, the potential difference between the two regions of the pn junction increases by approximately V _gp . Due to this effect, there is little change in the diffusion current of conduction electrons from the emitter region, and the diffusion current of holes from the base region is reduced.

Due to these two effects, when the impurity concentration of the semiconductor constituting the emitter region is higher than that of the base region and the diffusion current of the pn junction is determined by the conduction electron density of the emitter, the emitter- The current of the base pn junction increases exponentially with respect to the positive gate voltage V _gp .

  When the collector-base pn junction is reverse-biased, the diffusion current from the collector-base pn junction is negligibly small compared to the diffusion current from the emitter-base pn junction, and the emitter region A diffusion current of conduction electrons injected from the emitter through the emitter-base pn junction is observed as a collector current.

  When the collector-base pn junction is biased in the forward direction, the same effect as the emitter-base pn junction occurs in the collector-base pn junction by applying the gate voltage. The combined current is observed as the collector current.

When the forward bias voltage V _f of the emitter-base pn junction is changed, the magnitude of the current of the emitter-base pn junction can be changed exponentially with respect to V _f , and the collector current Will change accordingly. The forward bias voltage V _f and gate voltage V _g of the pn junction between the emitter and the base can be controlled independently, and the bias input circuit and the signal input circuit can be separated. Further, when the forward bias voltage V _f and the gate voltage V _g of the pn junction between the emitter and the base are controlled at the same time, the effects of both can be superimposed and function as a high gain amplifying device.

    BRIEF DESCRIPTION OF THE DRAWINGS FIG. The figure is not according to the dimensions, and for the sake of convenience, the layer thickness direction is shown enlarged.

FIG. 1A is a structural cross-sectional view of a field effect bipolar transistor of the present invention, which is insulated by an insulating film 12 on a pn junction p-type semiconductor region 11 composed of an n-type semiconductor region 10 and a p-type semiconductor region 11. The field control electrode 13 is arranged to constitute a field effect bipolar transistor. Regarding the connection of the electrodes to the field effect bipolar transistor, the emitter electrode 20 is applied to the n-type semiconductor region 10, the collector electrode 21 is applied to the p-type semiconductor region 11, and the gate electrode is applied to the electric field control electrode 13. 22 is joined to make an electrical connection. The emitter electrode 20, the collector electrode 21, and the gate electrode 22 are insulated by an insulating layer 23. The device of the present invention can be manufactured using a semiconductor manufacturing method, can be easily realized on a state-of-the-art integrated circuit without introducing special manufacturing technology, and has high industrial utility value It is.

    The operation of the semiconductor device of the present invention, that is, the field effect bipolar transistor will be described. In the field effect bipolar transistor of the present invention, a diffusion current generated by applying a voltage to the pn junctions 30 a and 30 b formed by the n-type semiconductor region 10 and the p-type semiconductor region 11 is generated by the potential applied to the electric field control electrode 13. By controlling the surface level in the near-surface region 31 of the p-type semiconductor region by the generated electric field, a transistor capable of operating at a high gain and under a low power supply voltage is realized. It has the feature that input resistance is high.

First, the current density of the pn junctions 30a and 30b composed of only the n-type semiconductor region 10 and the p-type semiconductor region 11, that is, the current density J _bulk when not affected by the gate electrode 13 will be considered. The current due to the generation of electron-hole pairs is assumed to be negligibly small, and the pn junction current can be determined mainly by the carrier diffusion current. The conduction electron density n _p injected from the n-type semiconductor region 10 into the p-type semiconductor region 11 is:

n _p = n _p0 × exp (−qV _ec / kT), (1)

It becomes. Here, n _p0 is the density of conduction electrons which are minority carriers in the p-type semiconductor region 11, q is the elementary charge, k is the Boltzmann constant, T is the absolute temperature, and V _ec is the n-type with the n-type semiconductor region 10 being positive. The emitter-collector voltage applied to the pn junction between the semiconductor region 10 and the p-type semiconductor region 11 is shown. The current density J _n due to the conduction electrons of the pn junctions 30a and 30b is determined by the diffusion of the conduction electrons obtained by the equation (1) in the p-type semiconductor region 11,

_{J n = qD n n p0 /} L n × (exp (-qV ec / kT) - 1), (2)

It is known that Here, D _n represents a conduction electron diffusion constant, and L _n represents a conduction electron diffusion length. hole density p _n injected from p-type semiconductor region 11 to the n-type semiconductor region 10,

p _n = p _n0 × exp (−qV _ec / kT), (3)

It becomes. Here, pn ₀ represents the density of holes that are minority carriers in the n-type semiconductor region 10. The current density J _p due to the holes in the pn junctions 30a and 30b is determined by diffusing the holes obtained by the formula (3) through the n-type semiconductor region 10,

_{J p = qD p p n0 /} L p × (exp (-qV ec / kT) - 1), (4)

It becomes. Here, D _p represents the hole diffusion constant, and L _p represents the hole diffusion length. The current density J _bulk of the pn junctions 30a and 30b is determined by the sum of the current density J _n due to conduction electrons and the current density J _p due to holes, which are obtained by the equations (2) and (4).

_{J bulk = (qD n n p0} / L n + qD p p n0 / L p) × (exp (-qV ec / kT) - 1), (5)

It becomes. 1B to 1G are energy band diagrams of a field effect bipolar transistor. In FIG. 1B, E _cn is the energy level of the conduction band of the n-type semiconductor region 10, E _vn is the energy level of the valence band of the n-type semiconductor region 10, E _fn is the Fermi level of the n-type semiconductor region 10, E _cpb represents the energy level of the conduction band of the p-type semiconductor region 11, E _vpb represents the energy level of the valence band of the p-type semiconductor region 11, and E _fp represents the Fermi level of the p-type semiconductor region 11. . The pn junctions 30a and 30b are arranged such that the Fermi levels E _fn and E _{fp of} the n-type semiconductor region 10 and the p-type semiconductor region 11 have the same energy level when the applied voltage _Vec between the emitter and the collector is zero. Join. energy level of the energy level and the valence band of the conduction band of the n-type semiconductor region 10 and the p-type semiconductor region 11, respectively, with a step qV _d energy level determined by the diffusion potential V _d. FIG. 1C shows an energy band diagram when an applied voltage _Vec is applied between the emitter and collector of the pn junctions 30a and 30b. pn junction 30a, the emitter of 30b - The application of the applied voltage V _ec between the collector, the energy band of the p-type semiconductor region 11 is joined shifted downward energy level component of qV _ec. Due to this shift, the step E _cpb −E _cn of the conduction electron energy barrier _viewed from the n-type semiconductor region 10 and the step E _vpb −E _vn of the hole energy barrier viewed from the p-type semiconductor region 11 are qV _ec minutes. The current density J _bulk of the pn junctions 30a and 30b increases exponentially as shown in the equation (5) corresponding to the decrease of each energy barrier.

Next, the current density of the pn junctions 30a and 30b when the electric field control electrode 13 is arranged on the p-type semiconductor region 11 of the field effect bipolar transistor, that is, the current density when the influence of the electric field control electrode 13 is taken into consideration will be considered. . If the region of the pn junction 30a is sufficiently away from the electric field control electrode 13 and is not affected by the electric field by the electric field control electrode 13, the current density in the region of the pn junction 30a is not affected by the electric field control electrode 13. Therefore, it becomes the same as the equation (5). On the other hand, the current density J _sur in the region of the pn junction 30b changes greatly by joining the electric field control electrode 13. The surface energy level φ _s0 of the p-type semiconductor near-surface region 31 is the difference φ _ms (= φ _m between the work function φ _{m of the} material constituting the electric field control electrode 13 and the Fermi level φ _s of the p-type semiconductor region 11. −φ _s ) changes by q (φ _ms −V _i ). Here, V _i is a potential difference generated between both interfaces of the insulating film 12 immediately below the electric field control electrode due to the bonding of the electric field control electrode 13. The potential difference φ _ms generated by the bonding of the electric field control electrode 13 is divided into the potential difference V _i between the interfaces of the insulating film 12 and the surface potential φ _s0 of the near-surface region 31 of the p-type semiconductor. Here, for the sake of convenience, it is assumed that the influence of the electric charge or the like existing in the insulating coating 12 or at the interface is small, and the current density in the region of the pn junction 30b is mainly determined by the characteristics in the vicinity of the surface. FIG. 1D shows an energy band diagram when the electric field control electrode 13 is disposed on the p-type semiconductor region 11 of the field effect bipolar transistor. In the energy band diagram of FIG. 1D, the energy levels E _cps and E _vps are respectively determined by the conduction band energy level E _cpb and the valence band energy level E _{vpb of} the p-type semiconductor region 11 from the electric field control electrode 13. It shows a state in which reduced by Qfai _s0 by bonding the effect. state of near-surface region 31 of the p-type semiconductor region 11, the size of Qfai _s0, accumulation state, reject condition, the weak inversion state, it becomes a strong inversion state. The energy band diagram of FIG. 1D illustrates an example in which the state of the near-surface region 31 of the p-type semiconductor is in the rejected state when φ _s0 is about 0.15V. The conduction electron density n _p1 in the surface vicinity region 31 of the p-type semiconductor when the electric field control electrode 13 is joined is

n _p1 = n _p × exp (qφ _s0 / kT) (6)

It becomes. It can be seen that when φ _s0 is 0.15 V at room temperature, the density of conduction electrons in the near-surface region 31 of the p-type semiconductor increases about 400 times. On the other hand, in this embodiment in which the electric field control electrode 13 is not joined to the upper part of the n-type semiconductor region 10, the hole density _pn1 in the n-type semiconductor region 10 remains _pn . In the examples described later, an example in which the n-type semiconductor region 10 is provided with an electric field control electrode is also referred to. The current density J _sur in the region of the pn junction 30b is obtained from the equations (2), (4), and (6).

_{J sur = qD n n p0 /} L n × (exp (q (-V ec + φ s0) / kT) -exp (qφ s0 / kT)) + qD p p n0 / L p × (exp (-qV ec / kT -1), (7)

It becomes. Here, when the impurity concentration of the n-type semiconductor region 10 is sufficiently higher than the impurity concentration of the p-type semiconductor region 11, the current due to holes becomes sufficiently smaller than the current due to conduction electrons, and the equation (7) Is

_{J sur = qD n n p0 /} L n × (exp (q (-V ec + φ s0) / kT) -exp (qφ s0 / kT)), (8)

Is approximated. The current density J _sur in the region of the pn junction 30b is determined only by the diffusion current of conduction electrons in the near-surface region 31 of the p-type semiconductor. Comparing equations (5) and (8), it can be seen that J _sur passes a much larger current to J _bulk . When φ _s0 is 0.15 V at room temperature, J _sur has a current about 400 times that of J _bulk . Therefore, by choosing the material of the field-control electrode 13 and the p-type semiconductor region 11 as Qfai _s0 it becomes appropriate size, pn junction 30a, 30b of the current, the current passing through the near-surface region of the pn junction 30b It can be determined by the density J _sur . Further, when comparing the energy band diagrams of FIG. 1C and FIG. 1D, the conduction band energy level E _cps of the near-surface region 31 of the p-type semiconductor affected by the junction of the electric field control electrode 13 depends on the junction of the electric field control electrode 13. It is lower than the conduction band energy level E _{cpb of the unaffected} p-type semiconductor region 11 by qφ _s0 . The conduction electrons diffuse into the surface vicinity region 31 of the p-type semiconductor having a lower energy level than the surroundings. Although not shown in the cross-sectional view of FIG. 1A, there is a region near the surface of the p-type semiconductor that is not affected by the electric field control electrode 13, that is, a p-type semiconductor region where the electric field control electrode 13 is not applied to the surface. There is a case. Since the conduction band energy level E _cps1 of the p-type semiconductor region where the electric field control electrode 13 is not applied to the surface is the same as the energy level E _spb of the conduction band of the p-type semiconductor region 11, the electric field control electrode 13 is It becomes difficult for current to flow even in the p-type semiconductor region that is not applied to. That is, by joining the electric field control electrode 13 in the vicinity of the pn junction, a current path (channel) for selectively flowing a current generated in the pn junction is realized.

Next, consider that the gate voltage _Vg is applied to the electric field control electrode 13 of the field effect bipolar transistor to control the current density J _sur of the pn junction 30b. The gate voltage V _g is determined by the inter-interface potential difference V _gi between the electric field control electrode 13-insulating film 12 interface and the insulating film 12-p-type semiconductor region 11 interface in the insulating film 12 immediately below the electric field control electrode 13, and the surface vicinity region of the p-type semiconductor. 31 is _divided into a surface potential φ _{gs of} 31. Therefore, the application of the gate voltage V _g changes the surface level of the near-surface region 31 of the p-type semiconductor by φ _gs . The ratio of the partial pressure between the interfacial potential difference V _gi and the surface potential φ _gs of the near-surface region 31 of the p-type semiconductor can be accurately obtained by solving Poisson's equation from the charge distribution in the near-surface region 31 of the p-type semiconductor. it can. FIG. 1E shows an energy band diagram when a positive gate voltage _Vg is applied to the electric field control electrode 13, that is, when the near-surface region 31 of the p-type semiconductor is in the rejected state. When a positive gate voltage V _g is applied to the electric field control electrode 13, the energy level E _cps of the conduction band and the energy level E _vps of the valence band in the near-surface region 31 of the p-type semiconductor are compared with FIG. 1D. It decreases by qφ _{gs in} the direction of the plus sign in the figure. FIG. 1F shows an energy band diagram when a higher positive gate voltage _Vg is applied to the electric field control electrode 13, that is, when the near-surface region 31 of the p-type semiconductor is in an inverted state. When a higher positive gate voltage V _g is applied to the electric field control electrode 13, the energy level E _cps of the conduction band and the energy level E _vps of the valence band in the near-surface region 31 of the p-type semiconductor are as shown in FIG. Compared to the direction of the sign ++ in the figure, it decreases by qφ _gs , and in the near-surface region 31 of the p-type semiconductor, the Fermi level E _fpn exceeds the intrinsic Fermi level and becomes n-type to form an inversion layer, Furthermore, since the Fermi level in the region of the p-type semiconductor near-surface region 31 is inclined, a drift current flows in addition to the diffusion current. FIG. 1G shows an energy band diagram when a negative gate voltage V _g is applied to the electric field control electrode 13, that is, when the vicinity of the surface region 31 of the p-type semiconductor is in an accumulation state. When a negative gate voltage V _g is applied to the electric field control electrode 13, the energy level E _cps of the conduction band and the energy level E _vps of the valence band in the near-surface region 31 of the p-type semiconductor are compared with FIG. 1D. In the figure, it increases by qφ _{gs in} the direction of the sign of −. At this time, the current density J _sur in the region of the pn junction 30b is obtained from the equation (8):

_{J sur = qD n n p0 /} L n × (exp (q (-V ec + φ gs + φ s0) / kT) -exp (q (φ gs + φ s0) / kT)), (9)

Is required. When a negative gate voltage is applied, the current density J _sur of the pn junction 30b decreases exponentially as φ _gs decreases. When the gate voltage decreases until the fluctuation amount φ _gs of the surface state due to application of the gate voltage and the fluctuation amount φ _s0 of the surface state due to joining of the electric field control electrode 13 become equal, the region near the surface of the p-type semiconductor The energy band 31 is a flat band, which is equivalent to a state where the electric field control electrode 13 is not joined. At this time, the current density J _sur in the region of the pn junction 30b is equal to the current density J _bulk in the region of the pn junction 30a. The energy band diagram of FIG. 1G shows this state and is consistent with FIG. 1C. This condition gives the minimum value of the gate voltage V _g which controls the diffusion current of the pn junction by the electric field. The gate voltage V _gf when the energy band of the near-surface region 31 of the p-type semiconductor is a flat band is V _gf = φ _ms . When a positive gate voltage is applied, the current density J _sur of the pn junction 30b increases exponentially with increasing φ _gs as shown in the equation (9). When the gate voltage is further increased, a strong inversion layer of the n-type semiconductor is formed in the near-surface region 31 of the p-type semiconductor, and a drift current flows in addition to the diffusion current, and the exponential characteristic is lost. . Therefore, in the field effect bipolar transistor of the present invention, the gate voltage V _g applied to the electric field control electrode 13 has an exponential current characteristic with respect to the input voltage in a voltage range from φ _ms to a strong inversion layer. . Further, by adjusting the emitter-collector voltage V _ec corresponding to the forward bias voltage of the pn junction, it is possible to set the current bias level exponentially with respect to V _ec .

Next, consider the emitter current of a field effect bipolar transistor. The current density J _sur of the pn junction 30b shown in Expression (9) is the current density when the collector electrode 21 that captures the conduction electrons does not exist within the range of the diffusion length L _n of the conduction electrons from the junction surface of the pn junction 30b. Show. When the length L of the electric field control electrode 13 on the near-surface region 31 of the p-type semiconductor is shorter than the diffusion length L _{n of the} conduction electrons, the current density J _sur of the pn junction 30b is obtained from the equation (9):

_{J sur = qD n n p0 /} L × (exp (q (-V ec + φ gs + φ s0) / kT) -exp (q (φ gs + φ s0) / kT)), (10)

Thus, the current density J _sur in the region of the pn junction 30b increases to L _n / L times. In order to smoothly diffuse conduction electrons in the surface vicinity region 31 of the p-type semiconductor, the energy band in the vicinity of the collector electrode that captures the conduction electrons is as shown in the energy band diagrams of FIGS. In contrast, it is necessary that the energy level be bonded so as to decrease toward the collector electrode 21. FIG. 2A shows a configuration example when this condition is satisfied. The collector electrode 21 is joined to the p-type semiconductor region 11 through the high-concentration p-type semiconductor region 28. The emitter current _Ie of the field effect bipolar transistor is obtained by multiplying the cross-sectional area A of the near-surface region 31 of the p-type semiconductor cut along a cross section perpendicular to the direction in which J _sur flows by the equation (10):

_{I e = AqD n n p0 /} L × (exp (q (-V ec + φ gs + φ s0) / kT) -exp (q (φ gs + φ s0) / kT)), (11)

Is required. Furthermore, if the average thickness of the near-surface region 31 of the p-type semiconductor through which the emitter current I _e flows is d, the cross-sectional area A of the near-surface region 31 of the p-type semiconductor is the depth direction of the electric field control electrode 13 in FIG. A = dW, and the emitter current Ie of the field effect bipolar transistor is

_{I e = qD n n p0 dW} / L × (exp (q (-V ec + φ gs + φ s0) / kT) -exp (q (φ gs + φ s0) / kT)), (12a)

It becomes. The emitter current I _e is a current proportional to the shape ratio W / L of the electric field control electrode 13. In equations (11) and (12a), the current distribution in the depth direction is simplified for convenience, but the emitter current I _e is expressed by the equation (10) of the current density J _sur of the pn junction 30b in the depth direction. It is possible to obtain more accurately by integrating into.

FIG. 3B shows the measurement results when measuring the emitter current of the field effect bipolar transistor shown in FIG. 2A of Example 1 using the measurement circuit of FIG. 3A. The gate voltage V _g is measured by changing from −0.70 V to 0.70 V in increments of 0.01 V. Emitter - collector voltage V _ec as a parameter, are measured by changing from 0.00V to increments -0.10V to -0.80V. The emitter current of the field effect bipolar transistor was measured as a current flowing through a voltage source connected to the emitter electrode 20. The voltage at which a strong inversion layer is formed in the near-surface region 31 of the p-type semiconductor of the field effect bipolar transistor is about 0.6V, and the flat band voltage is about −0.2V. The shape of the electric field control electrode of the field effect bipolar transistor is W = 10 μm and L = 2 μm. In the measurement result of FIG. 3B, the exponential function characteristic of the formula (10) is obtained in the range of the gate voltage V _g from the flat band voltage −0.2 V to the voltage 0.6 V at which a strong inversion layer is formed. The field effect bipolar transistor operates even when the gate voltage V _g is near 0V. Since the field effect bipolar transistor does not require a bias voltage for operating the transistor for an input signal, it is possible to ensure a large signal amplitude in an integrated circuit that is required to have a low power supply voltage in recent years. Φ _gs fluctuates by about 0.12 V with respect to 0.2 _g fluctuation of the gate voltage V _g , and as a result, a current fluctuation of about 100 times is measured. In today's integrated circuits that require low power consumption, a high gain amplifier equivalent to a bipolar transistor can be realized when configuring an integrated circuit that operates with a low output bias current. At this time, the current flowing into the gate electrode is 50 fA or less, and the field effect bipolar transistor has a high input resistance. Emitter - for variations 0.10V of collector voltage V _ec, about 50 times the current variation is measured. The output bias current can be set in a wide current range by the emitter-collector voltage _Vec . Variation 0.2V and the emitter of the gate voltage V _g - if the fluctuations 0.10V of collector voltage V _ec gave simultaneously, about 5000 times the current variation is measured. These actual measurement results accurately correspond to the operation principle of the above-described field effect bipolar transistor and confirm that the operation principle is correct. In the first embodiment, an example in which the impurity concentration of the n-type semiconductor region 10 is sufficiently higher than that of the p-type semiconductor region 11 is shown. However, when the concentration relationship is reversed, the carrier that determines the current is positively transferred from the conduction electrons. It can be handled in the same way by replacing it with a hole.
As a modification of the first embodiment, as shown in FIG. 2B, the electric field control bipolar transistor is surrounded by insulating layers 27 and 25, and the collector electrode 21 is bonded to the p-type semiconductor region 11 through the high-concentration p-type semiconductor region 28. An example is shown. In this configuration, it is possible to reduce the current density J _bulk of the deep layer portion at 30a and to expand the surface layer current density at 30b to a lower current range. A circuit with low leakage and low noise can be realized. Furthermore, by preparing another electric field control electrode under the insulating layer 25, a multi-electrode field effect bipolar transistor can be configured in place of the surface type field effect bipolar transistor of FIG. 2A.
As a modification of the first embodiment, as shown in FIG. 2C, the n-type semiconductor region 10 in FIG. 1A is replaced with the p-type semiconductor region 15 in FIG. 2C, and the p-type semiconductor region 11 in FIG. 1A is replaced with the n-type semiconductor region 16 in FIG. It is possible to configure a field effect bipolar transistor having a relative structure by replacing each of the above. In this case, the emitter current I _e is similar to the equation (12a):
I _e = qD _{pp n0} dW / L × (exp (q (V _ec −φ _s1 −φ _gsn ) / kT) _−exp (q (−φ _s1 −φ _gsn ) / kT)), (12b)
It becomes. Here, p _n0 is the density of holes which are minority carriers in the n-type semiconductor region 16, φ _s1 is the surface level in the region near the surface of the n-type semiconductor when the electric field control electrode 17 is joined, and φ _gsn is the electric field control. The amount of change in the surface level in the region near the surface of the n-type semiconductor when the voltage V _g is applied to the electrode 17 is shown. In the modification of the first embodiment, as shown in Expression (12b), the emitter current decreases exponentially when a positive gate voltage is applied, and the emitter current exponentially decreases when a negative gate voltage is applied. It is possible to construct a relative field effect bipolar transistor having an increasing characteristic and a change in the emitter current with respect to the gate voltage having a characteristic opposite to that of the first embodiment. FIG. 2D shows an example in which the collector electrode 21 is joined to the n-type semiconductor region 16 via the high-concentration n-type semiconductor region 29 as a modification of the first embodiment shown in FIG. 2C.
FIG. 4B shows the measurement results when measuring the emitter current for the field effect bipolar transistor shown in FIG. 2D of Example 1 using the measurement circuit of FIG. 4A. The gate voltage V _g is measured by changing from −0.70 V to 0.70 V in increments of 0.01 V. Emitter - collector voltage V _ec as a parameter, are measured by changing from 0.00V to increments 0.10V to 0.80 V. The emitter current of the field effect bipolar transistor was measured as a current flowing through a voltage source connected to the emitter electrode 20. The voltage at which a strong inversion layer is formed in the near-surface region 31 of the p-type semiconductor of the field effect bipolar transistor is about −0.7V, and the flat band voltage is about 0.1V. The shape of the electric field control electrode of the field effect bipolar transistor is W = 10 μm and L = 2 μm. In the measurement results of FIG. 4B, the gate voltage V _g is the characteristic of the exponential function of equation (12b) in the range of the voltage -0.7V strong inversion layer is formed from a flat band voltage 0.1V is obtained. The field effect bipolar transistor operates even when the gate voltage V _g is near 0V. Since the field effect bipolar transistor does not require a bias voltage for operating the transistor for an input signal, it is possible to ensure a large signal amplitude in an integrated circuit that is required to have a low power supply voltage in recent years. Φ _gs fluctuates by about 0.12 V with respect to 0.2 _g fluctuation of the gate voltage V _g , and as a result, a current fluctuation of about 100 times is actually measured. In today's integrated circuits that require low power consumption, a high gain amplifier equivalent to a bipolar transistor can be realized when configuring an integrated circuit that operates with a low output bias current. At this time, the current flowing into the gate electrode is 50 fA or less, and the field effect bipolar transistor has a high input resistance. Emitter - for variations 0.10V of collector voltage V _ec, about 50 times the current variation is measured. The output bias current can be set in a wide current range by the emitter-collector voltage _Vec . Variation 0.2V and the emitter of the gate voltage V _g - if the fluctuations 0.10V of collector voltage V _ec gave simultaneously, about 5000 times the current variation is measured. These actual measurement results accurately correspond to the operation principle of the above-mentioned field effect bipolar transistor, and confirm that the operation principle is correct. In the first embodiment, an example in which the impurity concentration of the n-type semiconductor region 10 is sufficiently higher than that of the p-type semiconductor region 11 is shown. However, when the concentration relationship is reversed, the carrier that determines the current is positively transferred from the conduction electrons. It can be handled in the same way by replacing it with a hole. As a modification of the first embodiment shown in FIG. 2C, as shown in FIG. 2E, the electric field control bipolar transistor is surrounded by insulating layers 27 and 25, and the collector electrode 21 is n-typed via a high-concentration n-type semiconductor region 29. An example of bonding to the shaped semiconductor region 16 is shown. In this configuration, it is possible to reduce the current density J _bulk of the deep layer portion at 30a and to expand the surface layer current density at 30b to a lower current range. A circuit with leakage and low noise can be realized. Furthermore, by preparing another electric field control electrode under the insulating layer 25, a multi-electrode field effect bipolar transistor can be configured in place of the surface type field effect bipolar transistor of FIG. 2E.

FIG. 5A is a structural cross-sectional view of Example 2 in the field effect bipolar transistor of the present invention. In the second embodiment, a field effect bipolar transistor in which an electric field control electrode 13 insulated by an insulating film 12 is disposed on a pn junction p-type semiconductor region 11 composed of an n-type semiconductor region 10 and a p-type semiconductor region 11. And a field effect bipolar transistor in which the electric field control electrode 13 is arranged on the p-type semiconductor region 11 of the pn junction constituted by the n-type semiconductor region 14 and the p-type semiconductor region 11, and the p-type semiconductor region 11 in common The field effect bipolar transistor is configured by arranging. Regarding the connection of the electrodes to the field effect bipolar transistor, the emitter electrode 20 is applied to the n-type semiconductor region 10, the base electrode 24 is applied to the p-type semiconductor region 11, and the collector is applied to the n-type semiconductor region 14. The electrode 21 is electrically connected to the electric field control electrode 13 by bonding the gate electrode 22. In order to give the potential of the p-type semiconductor region 11 that is commonly used by two field effect bipolar transistors, a base electrode 24 is disposed to constitute a four-terminal transistor. The base electrode 24 is connected to the back surface of the element for convenience, but electrical connection can be established from the surface of the p-type semiconductor region 11 that is not covered by the electric field control electrode 13. When the junction between the p-type semiconductor region 11 and the base electrode 24 is not a resistive junction, the p-type semiconductor region 11 and the base electrode 24 are joined via the high-concentration p-type semiconductor region. The emitter electrode 20, the collector electrode 21, and the gate electrode 22 are insulated by an insulating layer 23. The device according to the second embodiment of the present invention can be manufactured by using a semiconductor manufacturing method as in the first embodiment, and can be easily realized on a state-of-the-art integrated circuit without introducing a special manufacturing technique. There is a high industrial utility value.

  The operation of the field effect bipolar transistor will be described. In the field effect bipolar transistor of the present invention, a diffusion current generated by applying a voltage to the pn junctions 30 a and 30 b formed by the n-type semiconductor region 10 and the p-type semiconductor region 11 is generated by the potential applied to the electric field control electrode 13. By controlling the surface level of the near-surface region 31 of the p-type semiconductor region by the generated electric field, a high-gain transistor that operates under a low power supply voltage is realized. It is characterized by high resistance.

First, the current density of the pn junctions 30a and 30b composed of only the n-type semiconductor region 10 and the p-type semiconductor region 11, that is, the current density J _bulk when not affected by the gate electrode 13 will be considered. The current due to the generation of electron-hole pairs is assumed to be negligibly small, and the pn junction current can be determined mainly by the carrier diffusion current. The conduction electron density n _p injected from the n-type semiconductor region 10 into the p-type semiconductor region 11 is:

n _p = n _p0 × exp (−qV _eb / kT), (13)

It becomes. Here, n _p0 is the density of conduction electrons that are minority carriers in the p-type semiconductor region 11, q is the elementary charge, k is the Boltzmann constant, T is the absolute temperature, and V _eb is the n-type with the n-type semiconductor region 10 being positive. The emitter-base voltage applied to the pn junction between the semiconductor region 10 and the p-type semiconductor region 11 is shown. The current density J _n due to the conduction electrons of the pn junctions 30a and 30b is determined by the diffusion of the conduction electrons obtained by the equation (13) in the p-type semiconductor region 11,

_{J n = qD n n p0 /} L n × (exp (-qV eb / kT) - 1), (14)

It becomes. Here, D _n represents a conduction electron diffusion constant, and L _n represents a conduction electron diffusion length. hole density p _n injected from p-type semiconductor region 11 to the n-type semiconductor region 10,

p _n = p _n0 × exp (−qV _eb / kT), (15)

It becomes. Here, pn ₀ represents the density of holes that are minority carriers in the n-type semiconductor region 10. The current density J _p due to the holes of the pn junctions 30a and 30b is determined by the diffusion of the holes obtained by the equation (15) through the n-type semiconductor region 10,

_{J p = qD p p n0 /} L p × (exp (-qV eb / kT) - 1), (16)

It becomes. Here, D _p represents the hole diffusion constant, and L _p represents the hole diffusion length. The current density J _bulk of the pn junctions 30a and 30b is determined by the sum of the current density J _n due to conduction electrons and the current density J _p due to holes determined by the equations (14) and (16),

_{J bulk = (qD n n p0} / L n + qD p p n0 / L p) × (exp (-qV eb / kT) - 1), (17)

It becomes. FIG. 5B is an energy band diagram of a field effect bipolar transistor. E _cn is the energy level of the conduction band of the n-type semiconductor region 10, E _vn is the energy level of the valence band of the n-type semiconductor region 10, E _fn is the Fermi level of the n-type semiconductor region 10, and E _cpb is p The energy level of the conduction band of the p-type semiconductor region 11, E _vpb represents the energy level of the valence band of the p-type semiconductor region 11, and E _fp represents the Fermi level of the p-type semiconductor region 11. The pn junctions 30a and 30b are arranged so that the Fermi levels E _fn and E _{fp of} the n-type semiconductor region 10 and the p-type semiconductor region 11 have the same energy level when the applied voltage V _eb between the emitter and the base is zero. Join. energy level of the energy level and the valence band of the conduction band of the n-type semiconductor region 10 and the p-type semiconductor region 11, respectively, with a step qV _d energy level determined by the diffusion potential V _d. FIG. 5C shows an energy band diagram when an applied voltage V _eb is applied between the emitter and base of the pn junctions 30a and 30b. When an applied voltage V _eb is applied between the emitter and base of the pn junctions 30a and 30b, the energy band of the p-type semiconductor region 11 is shifted downward by the energy level of qV _eb and joined. As a result of this shift, the step E _cpb −E _cn of the conduction electron energy barrier _viewed from the n-type semiconductor region 10 and the step E _vpb −E _vn of the hole energy barrier viewed from the p-type semiconductor region 11 are equal to qV _eb . The current density J _bulk of the pn junctions 30a and 30b increases exponentially as shown in the equation (17) corresponding to the reduction of the respective energy barriers.

Next, the current density of the pn junctions 30a and 30b when the electric field control electrode 13 is arranged on the p-type semiconductor region 11 of the field effect bipolar transistor, that is, the current density when the influence of the electric field control electrode 13 is taken into consideration will be considered. . If the region of the pn junction 30a is sufficiently away from the electric field control electrode 13 and is not affected by the electric field by the electric field control electrode 13, the current density in the region of the pn junction 30a is not affected by the electric field control electrode 13. Therefore, it becomes the same as Expression (17). On the other hand, the current density J _sur in the region of the pn junction 30b changes greatly when the electric field control electrode 13 is joined. The surface energy level φ _s0 of the p-type semiconductor near-surface region 31 is the difference φ _ms (= φ _m between the work function φ _{m of the} material constituting the electric field control electrode 13 and the Fermi level φ _s of the p-type semiconductor region 11. −φ _s ) changes by q (φ _ms −V _i ). Here, V _i is a potential difference generated between both interfaces of the insulating film 12 immediately below the electric field control electrode due to the bonding of the electric field control electrode 13. The potential difference φ _ms generated by the bonding of the electric field control electrode 13 is divided into the potential difference V _i between the interfaces of the insulating film 12 and the surface potential φ _s0 of the near-surface region 31 of the p-type semiconductor. Here, for the sake of convenience, it is assumed that the influence of the electric charge or the like existing in the insulating coating 12 or at the interface is small, and the current density in the region of the pn junction 30b is mainly determined by the characteristics in the vicinity of the surface. FIG. 5D shows an energy band diagram when the electric field control electrode 13 is disposed on the p-type semiconductor region 11 of the field effect bipolar transistor. In the energy band diagram of FIG. 5D, the energy level E _cps and E _vps, respectively, the energy level E _vpb energy level E _cpb the valence band of the conduction band of the p-type semiconductor region 11 is a field control electrode 13 It shows a state where qφ _s0 has been lowered due to the effect of joining. The state of the surface vicinity region 31 of the p-type semiconductor region 11 becomes an accumulation state, a rejection state, a weak inversion state, and a strong inversion state depending on the magnitude of qφ _s0 . The energy band diagram of FIG. 5D illustrates an example in which the state of the near-surface region 31 of the p-type semiconductor is in the rejected state when φ _s0 is about 0.15V. The conduction electron density n _p1 in the surface vicinity region 31 of the p-type semiconductor when the electric field control electrode 13 is joined is

n _p1 = n _p × exp (qφ _s0 / kT) (18)

It becomes. It can be seen that when φ _s0 is 0.15 V at room temperature, the density of conduction electrons in the near-surface region 31 of the p-type semiconductor increases about 400 times. On the other hand, in this embodiment in which the electric field control electrode 13 is not joined to the upper part of the n-type semiconductor region 10, the hole density _pn1 in the n-type semiconductor region 10 remains _pn . In the examples described later, an example in which the n-type semiconductor region 10 is provided with an electric field control electrode is also referred to. The current density J _sur in the region of the pn junction 30b is obtained from the equations (14), (16), and (18).

_{J sur = qD n n p0 /} L n × (exp (q (-V eb + φ s0) / kT) -exp (qφ s0 / kT)) + qD p p n0 / L p × (exp (-qV eb / kT -1), (19)

It becomes. Here, when the impurity concentration of the n-type semiconductor region 10 is sufficiently higher than the impurity concentration of the p-type semiconductor region 11, the current density due to holes becomes sufficiently smaller than the current density due to conduction electrons. )

_{J sur = qD n n p0 /} L n × (exp (q (-V eb + φ s0) / kT) -exp (qφ s0 / kT)), (20)

Is approximated by The current density J _sur in the region of the pn junction 30b is determined only by the diffusion current of conduction electrons in the near-surface region 31 of the p-type semiconductor. Comparing equation (17) and equation (20) shows that J _sur passes a much larger current to J _bulk . When φ _s0 is 0.15 V at room temperature, J _sur has a current about 400 times that of J _bulk . Therefore, by choosing the material of the field-control electrode 13 and the p-type semiconductor region 11 as Qfai _s0 it becomes appropriate size, pn junction 30a, 30b of the current, the current passing through the near-surface region of the pn junction 30b It can be determined by the density J _sur . 5C and FIG. 5D are compared, the conduction band energy level E _cps of the near-surface region 31 of the p-type semiconductor affected by the junction of the electric field control electrode 13 is determined by the junction of the electric field control electrode 13. only qφ _s0 lower than the conduction band energy level E _cpb of the p-type semiconductor region 11 which is not affected. The conduction electrons diffuse into the surface vicinity region 31 of the p-type semiconductor having a lower energy level than the surroundings. Although not shown in the cross-sectional view of FIG. 5A, there is a region near the surface of the p-type semiconductor that is not affected by the electric field control electrode 13, that is, a p-type semiconductor region where the electric field control electrode 13 is not applied to the surface. There is a case. Since the conduction band energy level E _cps1 of the p-type semiconductor region where the electric field control electrode 13 is not applied to the surface is the same as the energy level E _spb of the conduction band of the p-type semiconductor region 11, It becomes difficult for current to flow even in the p-type semiconductor region that is not applied to. That is, by joining the electric field control electrode 13 in the vicinity of the pn junction, a current path (channel) for selectively flowing a current generated in the pn junction is realized.

Next, consider that the gate voltage _Vg is applied to the electric field control electrode 13 of the field effect bipolar transistor to control the current density J _sur of the pn junction 30b. The gate voltage V _g is determined by the inter-interface potential difference V _gi between the electric field control electrode 13-insulating film 12 interface and the insulating film 12-p-type semiconductor region 11 interface in the insulating film 12 immediately below the electric field control electrode 13, and the surface vicinity region of the p-type semiconductor. 31 is _divided into a surface potential φ _{gs of} 31. Therefore, application of the gate voltage V _g changes the surface level of the near-surface region 31 of the p-type semiconductor by qφ _gs . The ratio of the partial pressure between the interfacial potential difference V _gi and the surface potential φ _gs of the near-surface region 31 of the p-type semiconductor can be accurately obtained by solving Poisson's equation from the charge distribution in the near-surface region 31 of the p-type semiconductor. it can. FIG. 5E shows an energy band diagram when a positive gate voltage _Vg is applied to the electric field control electrode 13, that is, when the near-surface region 31 of the p-type semiconductor is in the rejected state. When a positive gate voltage V _g is applied to the electric field control electrode 13, the energy level E _cps of the conduction band and the energy level E _vps of the valence band in the near-surface region 31 of the p-type semiconductor are compared with FIG. 5D. It decreases by qφ _{gs in} the direction of the plus sign in the figure. FIG. 5F shows an energy band diagram when a higher positive gate voltage _Vg is applied to the electric field control electrode 13, that is, when the near-surface region 31 of the p-type semiconductor is in an inverted state. When a higher positive gate voltage V _g is applied to the electric field control electrode 13, the energy level E _cps of the conduction band and the energy level E _vps of the valence band in the near-surface region 31 of the p-type semiconductor are shown in FIG. 5D. Compared to the direction of the sign of ++ in the figure, it decreases by qφ _gs , and in the near-surface region 31 of the p-type semiconductor, the Fermi level E _fpn exceeds the intrinsic Fermi level and becomes n-type to form an inversion layer, Furthermore, since the Fermi level in the region of the p-type semiconductor near-surface region 31 is inclined, a drift current flows in addition to the diffusion current. When applying a negative gate voltage V _g to the field control electrode 13, i.e., an energy band diagram in the case where the near-surface region 31 of the p-type semiconductor and the storage state in FIG 5G. When a negative gate voltage V _g is applied to the electric field control electrode 13, the energy level E _cps of the conduction band and the energy level E _vps of the valence band in the near-surface region 31 of the p-type semiconductor are compared with FIG. 5D. In the figure, it rises by qφ _{gs in} the direction of the sign of −. At this time, the current density J _sur in the region of the pn junction 30b is obtained from the equation (20).

_{J sur = qD n n p0 /} L n × (exp (q (-V eb + φ gs + φ s0) / kT) -exp (q (φ gs + φ s0) / kT)), (21)
Is required. When a negative gate voltage is applied, the current density J _sur of the pn junction 30b decreases exponentially as φ _gs decreases. When the gate voltage decreases until the fluctuation amount φ _gs of the surface state due to application of the gate voltage and the fluctuation amount φ _s0 of the surface state due to joining of the electric field control electrode 13 become equal, the region near the surface of the p-type semiconductor The energy band 31 is a flat band, which is equivalent to a state where the electric field control electrode 13 is not joined. At this time, the current density J _sur in the region of the pn junction 30b is equal to the current density J _bulk in the region of the pn junction 30a. Figure 5G illustrates this state, this state gives a lower limit value of the gate voltage V _g which controls the diffusion current of the pn junction by the electric field. The gate voltage V _gf when the energy band of the near-surface region 31 of the p-type semiconductor is a flat band is V _gf = φ _ms . When a positive gate voltage is applied, the current density J _sur of the pn junction 30b increases exponentially as φ _gs increases as shown in the equation (21). When the gate voltage is further increased, a strong inversion layer of the n-type semiconductor is formed in the near-surface region 31 of the p-type semiconductor, and a drift current flows in addition to the diffusion current, and the exponential characteristic is lost. . Therefore, in the field effect bipolar transistor of the present invention, the gate voltage V _g applied to the electric field control electrode 13 has an exponential current characteristic with respect to the input voltage in a voltage range from φ _ms to a strong inversion layer. . Further, by adjusting the emitter-base voltage V _eb corresponding to the forward bias voltage of the pn junction, it is possible to set the current bias level exponentially with respect to V _eb .

Next, consider the collector current of a field effect bipolar transistor. The current density J _sur of the pn junction 30b shown in the equation (21) is the current density when the collector electrode 21 that captures conduction electrons does not exist within the range of the diffusion length L _n of conduction electrons from the junction surface of the pn junction 30b. Show. When the length L of the electric field control electrode 13 on the surface vicinity region 31 of the p-type semiconductor is shorter than the diffusion length L _{n of the} conduction electrons, the current density J _sur of the pn junction 30b is

_{J sur = qD n n p0 /} L × (exp (q (-V eb + φ gs + φ s0) / kT) -exp (q (φ gs + φ s0) / kT)), (22)

Thus, the current density J _sur in the region of the pn junction 30b increases to L _n / L times. In the configuration of Embodiment 2 of the present invention, FIG. 5A, the p-type semiconductor region 11 is shared, and the n-type semiconductor region 10 connected to the emitter electrode 20 and the n-type semiconductor region 14 connected to the collector electrode 21 are symmetrical. It has a simple structure. Therefore, the current density in the pn junctions 30a and 30b and the pn junctions 32a and 32b can be considered in the same manner by replacing the emitter-base voltage in the equation (21) with the collector-base voltage _Vcb . The current density J _surc in the pn junctions 32a and 32b is _obtained from the equation (21):

_{J surc = -qD n n p0 /} L × (exp (q (-V cb + φ gs + φ s0) / kT) -exp (q (φ gs + φ s0) / kT)), (23)

Is required. Here, V _cb represents a collector-base voltage applied to the pn junction between the n-type semiconductor region 14 and the p-type semiconductor region 11 with the n-type semiconductor region 14 being positive. In addition, in consideration of the direction of the current, a minus sign is attached. In order for the current obtained by the equation (22) to flow, it is necessary that there exists a concentration distribution in which the conduction electrons can diffuse from the emitter electrode toward the collector electrode in the near-surface region 31 of the p-type semiconductor. This concentration distribution is determined by setting the current density J _surc of the pn junction 32b to be sufficiently smaller than the current density J _sur of the pn junction 30b, that is, by applying the collector-base voltage V _cb negatively, This is achieved by operating 32a and 32b in the reverse bias state. 5A to 5G, E _cnc is the energy level of the conduction band of the n-type semiconductor region 14, E _vnc is the energy level of the valence band of the n-type semiconductor region 14, and E _fnc is the n-type semiconductor region. It represents 14 Fermi levels. When an applied voltage V _{cb in} which the p-type semiconductor region 11 is negative is applied between the collector and base of the pn junctions 32a and 32b, the energy band of the n-type semiconductor region 14 is shifted downward by the energy level of qV _cb. Join. Due to this shift, the energy barrier step E _cpb −E _cnc of the conduction electron seen from the n-type semiconductor region 14 and the step E _vpb −E _vnc of the hole energy barrier seen from the p-type semiconductor region are equal to qV _cb . It has increased. The conduction electrons injected from the n-type semiconductor region 10 into the p-type semiconductor region 11 diffuse in the p-type semiconductor region 11 and reach the collector electrode 21 connected to the n-type semiconductor region 14 down the energy barrier step qV _cb. To do. The collector current I _c of the field effect bipolar transistor is obtained from the equation (22):

I _c = AqD _n n _p0 / L × (exp (q (−V _eb + φ _gs + φ _s0 ) / kT) −exp (q (φ _gs + φ _s0 ) / kT)), (24)

Is required. Furthermore, if the average thickness of the near-surface region 31 of the p-type semiconductor through which the collector current I _c flows is d, the cross-sectional area A of the near-surface region 31 of the p-type semiconductor is the depth direction of the electric field control electrode 13 in FIG. A = dW, and the collector current I _c of the field effect bipolar transistor is

I _c = qD _n n _p0 dW / L × (exp (q (−V _eb + φ _gs + φ _s0 ) / kT) −exp (q (φ _gs + φ _s0 ) / kT)), (25a)

It becomes. The collector current I _c is a current proportional to the shape ratio W / L of the electric field control electrode 13. In formula (24) and formula (25a), the current distribution in the depth direction is simplified for the sake of convenience, but the collector current I _c is the formula (22) of the current density J _sur of the pn junction 30b in the depth direction. It is possible to obtain more accurately by integrating into. In addition, the field effect bipolar transistor of Example 2 gives the direction of the diffusion current of conduction electrons by switching the collector-base voltage V _cb and the emitter-base voltage V _eb , due to the symmetry of the structure. It is also possible to control so as to go from the collector electrode to the emitter electrode.

FIG. 7B shows the measurement results when the collector current I _c is measured for the field effect bipolar transistor shown in FIG. 6A of Example 2 using the measurement circuit of FIG. 7A. FIG. 6A shows a configuration in which a p-type semiconductor region 28 for bringing the base electrode 24 into resistance contact is disposed under the base electrode 24 as a modification of the second embodiment. The gate voltage V _g is measured by changing from −0.60 V to 1.00 V in increments of 0.01 V. The emitter-base voltage V _eb is measured by changing the parameter from 0.00 V to −0.80 V in steps of −0.10 V. The collector-base voltage V _cb is fixed at −1.0V. The collector current I _c of the field effect bipolar transistor was measured as the current flowing through the voltage source connected to the collector electrode 21. The voltage at which a strong inversion layer is formed in the near-surface region 31 of the p-type semiconductor of the field effect bipolar transistor is about 0.6V, and the flat band voltage is about −0.2V. The shape of the electric field control electrode of the field effect bipolar transistor is W = 10 μm and L = 2 μm. In the drawing, a curve with V _eb of 0 V represents a part of the characteristics of the field effect transistor. In the measurement result of FIG. 7B, the exponential function characteristic of the formula (25a) is obtained in the range of the gate voltage V _g from the flat band voltage −0.2 V to the voltage 0.6 V at which a strong inversion layer is formed. The field effect bipolar transistor operates even when the gate voltage V _g is near 0V. Since the field effect bipolar transistor does not require a bias voltage for operating the transistor for an input signal, it is possible to ensure a large signal amplitude in an integrated circuit that is required to have a low power supply voltage in recent years. Φ _gs fluctuates by about 0.12 V with respect to 0.2 _g fluctuation of the gate voltage V _g , and as a result, a current fluctuation of about 100 times is measured. In today's integrated circuits that require low power consumption, a high gain amplifier equivalent to a bipolar transistor can be realized when configuring an integrated circuit that operates with a low output bias current. At this time, the current flowing into the gate electrode is 50 fA or less, and the field effect bipolar transistor has a high input resistance. About 50 times the current fluctuation is measured with respect to the fluctuation 0.10 V of the emitter-base voltage V _eb . The output bias current can be set in a wide current range by the emitter-base voltage V _eb . Variation 0.2V and the emitter of the gate voltage V _g - if given simultaneously change 0.10V of base voltage V _eb, about 5000 times the current variation is measured.

Finally, FIG. 8B shows the measurement results when the static characteristics of the field effect bipolar transistor are measured using the measurement circuit of FIG. 8A. This is a result of measurement by changing the collector-base voltage V _cb from −0.6 V to 1.0 V in increments of 0.01 V. The emitter-base voltage V _eb is fixed at −0.50 V, and V _g is measured as a parameter by changing from −0.1 V to 0.7 V in increments of 0.10 V. In Figure 8B, the near-surface region 31 of the p-type semiconductor in the characteristic curve of the gate voltage V _g is 0.7V is inverted state, the weak inversion state gate voltage V _g is the characteristic curve of 0.6V～0.3V, the gate voltage The characteristic curve with V _g of 0.2V to -0.2V shows the operation in the rejected state, and the characteristic curve with gate voltage V _g of -0.3V to -0.5V shows the operation in the accumulation state. When the collector-base voltage V _cb is in the range of 0.0 V or more, a saturation characteristic is obtained in which the collector current I _c does not change with respect to the change of the collector-base voltage V _cb . In the case where the gate voltage is V _g = 0.0V, V _cb - output resistor R _o obtained from the slope in the saturation to that region of the I _c characteristics are 7.2Emuomega, transfer conductance obtained from the change of the gate voltage g _m is 32 μS. Therefore, specific gain of the field-control bipolar transistor obtained from the product of g _m and R _o is 230 takes an intermediate value between the bipolar transistor and the MOSFET, 2 to 3 with respect to MOSFET having an equivalent current value It has about twice the intrinsic gain.

For the electric field control bipolar transistor in the present invention, g _m obtained from the slope of the V _g -I _c characteristic in FIG. 7B, R _o obtained from the slope of the V _cb -I _c characteristic in FIG. 8B, corresponding I _c , V _g, V _eb, measurement conditions V _cb, g _m and R values of intrinsic gain obtained from the product of _o g _m R _o, the V _g -I _c characteristics when changing the V _eb of Figure 7B g _mm obtained from the slope, and show the g _mm and the value of intrinsic gain obtained from the product of R _o g _mm R _o in Table 1 of FIG. 22. The intrinsic gain values g _{m Ro} and g _{mm Ro} are also entered in FIG. 7B corresponding to the measurement points. The intrinsic gain is obtained in the range of 70 to 486 when the emitter-base voltage V _eb is -0.5V. Further, when the collector current I _c is 50 μA, it is obtained in the range of 84 to 117. Further, the transfer conductance g _mm obtained from changes in both the gate voltage and the emitter-base voltage is 210 μS. specific gain of the field-control bipolar transistor obtained from the product of g _mm and R _o is 1500. The intrinsic gain value g _{mm Ro} is also entered in FIG. 7B corresponding to the measurement point.

A comparison result of typical characteristics of the electric field control bipolar transistor, MOSFET, and bipolar transistor of Example 2 is shown in Table 3 of FIG. In FIG. 8B, the polarity of the collector current Ic is switched at the point where the collector-base voltage V _cb = −0.5V. With this point as a boundary, the magnitude relationship between the current J _sur of the pn junction 30b expressed by the equation (22) and the current J _surc of the pn junction 32b expressed by the equation (23) is switched, so that the emitter electrode and the collector electrode are switched. Bi-directional transistor operation. The field effect bipolar transistor of the present invention also has an advantage that bidirectional operation is possible.
FIG. 6A shows an example in which a high-concentration p-type semiconductor region 28 connected to the base electrode is disposed in the vicinity of the n-type semiconductor region 14 connected to the collector electrode for convenience, but is connected to the base electrode. The high-concentration p-type semiconductor region 28 is preferably disposed at an equal distance from the n-type semiconductor region 14 connected to the collector electrode and the n-type semiconductor region 11 connected to the emitter electrode.
These actual measurement results accurately correspond to the operation principle of the above-described field effect bipolar transistor and confirm that the operation principle is correct. In the second embodiment, an example in which the impurity concentration of the n-type semiconductor region 10 and the n-type semiconductor region 14 is sufficiently higher than that of the p-type semiconductor region 11 is shown. However, when the concentration relationship is reversed, the current is determined. It can be handled in the same way by replacing the carrier from conduction electrons to holes. Even when the impurity concentration of the n-type semiconductor region 10 is different from the impurity concentration of the n-type semiconductor region 14, it can be handled in the same manner.
As a modification of the second embodiment, as shown in FIG. 6B, the electric field control bipolar transistor is surrounded by insulating layers 27 and 25, and the base electrode 24 is joined to the p-type semiconductor region 11 through the p-type semiconductor region 28. An example is shown. FIG. 6C shows a partial view from the top surface of the field effect bipolar transistor shown in FIG. 6B made by another manufacturing method. In this configuration, it is possible to reduce the current density J _bulk of the deep layer portion at 30a and to expand the surface layer current density at 30b to a lower current range. A circuit with leakage and low noise can be realized. Furthermore, by preparing another field control electrode under the insulating layer 25, a multi-electrode field effect bipolar transistor can be configured in place of the surface field effect bipolar transistor of FIG. 6A.
As a modification of the second embodiment, as shown in FIG. 6D, the n-type semiconductor region 10 in FIG. 5A is replaced by the p-type semiconductor region 15 in FIG. 6D, and the p-type semiconductor region 11 in FIG. Further, by replacing the n-type semiconductor region 14 in FIG. 5A with the p-type semiconductor region 18 in FIG. 6D, a field effect bipolar transistor having a relative structure can be formed. In this case, the collector current I _c is equal to the expression (25a),
I _c = qD _{pp n0} dW / L × (exp (q (V _eb −φ _s1 −φ _gsn ) / kT) _−exp (q (−φ _s1 −φ _gsn ) / kT)), (25b)
It becomes. Here, p _n0 is the density of holes which are minority carriers in the n-type semiconductor region 16, φ _s1 is the surface level in the region near the surface of the n-type semiconductor when the electric field control electrode 17 is joined, and φ _gsn is the electric field control. The amount of change in the surface level in the region near the surface of the n-type semiconductor when the voltage V _g is applied to the electrode 17 is shown. In the modification of the second embodiment, the collector current decreases exponentially when a positive gate voltage is applied, and the collector current exponentially decreases when a negative gate voltage is applied, as shown in Expression (25b). It is possible to construct a relative field effect bipolar transistor having an increasing characteristic and a change in the collector current with respect to the gate voltage having a characteristic opposite to that of the second embodiment. FIG. 6E shows an example in which the base electrode 24 is joined to the n-type semiconductor region 16 via the n-type semiconductor region 29 as a modification of the second embodiment shown in FIG. 6D.
FIG. 9B shows a measurement result when the collector current I _c is measured for the field effect bipolar transistor shown in FIG. 6E of Example 2 using the measurement circuit of FIG. 9A. The gate voltage V _g is measured by changing from −1.0 V to 0.6 V in increments of 0.01 V. The emitter-base voltage V _eb is measured by changing the parameter from 0.00V to 0.80V in increments of 0.10V. The collector-base voltage V _cb is fixed at 1.0V. The collector current I _c of the field effect bipolar transistor was measured as the current flowing through the voltage source connected to the collector electrode 21. The voltage at which a strong inversion layer is formed in the n-type semiconductor region 16 of the field effect bipolar transistor is about −0.7V, and the flat band voltage is about 0.1V. The shape of the electric field control electrode of the field effect bipolar transistor is W = 10 μm and L = 2 μm. In the drawing, a curve with V _eb of 0 V represents a part of the characteristics of the field effect transistor. In the measurement result of FIG. 9B, the characteristic of the exponential function of the formula (25a) is obtained in the range of the gate voltage V _g from the flat band voltage 0.1 V to the voltage −0.7 V at which a strong inversion layer is formed. The field effect bipolar transistor operates even when the gate voltage V _g is near 0V. Since the field effect bipolar transistor does not require a bias voltage for operating the transistor for an input signal, it is possible to ensure a large signal amplitude in an integrated circuit that is required to have a low power supply voltage in recent years. Φ _gs fluctuates by about 0.12 V with respect to 0.2 _g fluctuation of the gate voltage V _g , and as a result, a current fluctuation of about 100 times is measured. In today's integrated circuits that require low power consumption, a high gain amplifier equivalent to a bipolar transistor can be realized when configuring an integrated circuit that operates with a low output bias current. At this time, the current flowing into the gate electrode is 50 fA or less, and the field effect bipolar transistor has a high input resistance. About 50 times the current fluctuation is measured with respect to the fluctuation 0.10 V of the emitter-base voltage V _eb . The output bias current can be set in a wide current range by the emitter-base voltage V _eb . Variation 0.2V and the emitter of the gate voltage V _g - if given simultaneously change 0.10V of base voltage V _eb, about 5000 times the current variation is measured.
FIG. 10B shows the measurement results when the static characteristics of the field effect bipolar transistor are measured using the measurement circuit of FIG. 10A. This is a result of measurement by changing the collector-base voltage V _cb from −1.0 V to 0.6 V in increments of 0.01 V. The emitter-base voltage V _eb is fixed to 0.50 V, and V _g is measured as a parameter by changing from −0.9 V to 0.5 V in steps of 0.10 V. In FIG. 10B, the surface of the n-type semiconductor region 16 is inverted in the characteristic curve with the gate voltage V _g of −0.9V to −0.7V, and the characteristic curve with the gate voltage V _g of −0.6V to −0.3V. in weak inversion state indicates the gate voltage V _g is repelled state at characteristic curve of -0.2V～0.1V, the gate voltage V _g is the operation when the storage state in the characteristic curve of 0.2V~0.5V respectively ing. When the collector-base voltage V _cb is 0.0 V or less, a saturation characteristic is obtained in which the collector current I _c does not change with respect to the change of the collector-base voltage V _cb . For the electric field control bipolar transistor in the present invention, g _m obtained from the slope of the V _g -I _c characteristic of FIG. 9B, R _o obtained from the slope of the V _cb -I _c characteristic of FIG. 10B, the corresponding I _c , V _g, V _eb, measurement conditions V _cb, g _m and R values of intrinsic gain obtained from the product of _o g _m R _o, the V _g -I _c characteristics when changing the V _eb in Figure 9B g _mm obtained from the slope, and show the g _mm and the value of intrinsic gain obtained from the product of R _o g _mm R _o in Table 2 of FIG. 23. Further, the intrinsic gain values g _{m Ro} and g _{mm Ro} are also entered in FIG. 9B corresponding to the measurement points. The intrinsic gain is obtained in the range of 22 to 102 when the emitter-base voltage V _eb is 0.5V. Further, when the collector current I _c is 20 μA, it is obtained in the range of 33 to 42. The intrinsic gain value g _{mm Ro} is also entered in FIG. 9B corresponding to the measurement point.

A comparison result of typical characteristics of the electric field control bipolar transistor, MOSFET, and bipolar transistor of Example 2 is shown in Table 3 of FIG. In FIG. 10B, the polarity of the collector current Ic is switched at the point where the collector-base voltage V _cb = 0.5V. The field effect bipolar transistor of the present invention is capable of bidirectional operation.
FIG. 6E shows an example in which the n-type semiconductor region 29 connected to the base electrode is disposed in the vicinity of the p-type semiconductor region 18 connected to the collector electrode for convenience, but the n-type semiconductor connected to the base electrode is shown. The region 29 is preferably arranged at an equal distance from the p-type semiconductor region 18 connected to the collector electrode and the p-type semiconductor region 15 connected to the emitter electrode.
These actual measurement results accurately correspond to the operation principle of the above-described field effect bipolar transistor and confirm that the operation principle is correct. In the modification of the second embodiment, an example in which the impurity concentration of the p-type semiconductor region 15 and the p-type semiconductor region 18 is sufficiently higher than that of the n-type semiconductor region 16 is shown. It can be handled in the same manner by replacing the carrier to be determined from holes to conduction electrons. Even when the impurity concentration of the p-type semiconductor region 15 is different from the impurity concentration of the p-type semiconductor region 18, it can be handled in the same manner.
As a modification of the second embodiment, as shown in FIG. 6F, the electric field control bipolar transistor is surrounded by insulating layers 27 and 25, and the base electrode 24 is joined to the n-type semiconductor region 16 via the n-type semiconductor region 29. An example is shown. FIG. 6G shows a partial view from the top surface of the field effect bipolar transistor shown in FIG. 6F made by another manufacturing method. In this configuration, the current density J _bulk in the deep layer can be reduced, and the current density in the surface layer can be extended to a lower current range for use, resulting in low consumption, low leakage, and low noise. A simple circuit can be realized. Furthermore, by preparing another electric field control electrode under the insulating layer 25, a multi-electrode field effect bipolar transistor can be configured in place of the surface type field effect bipolar transistor of FIG. 6E.

As shown in FIG. 11, the third embodiment has a configuration in which the field control electrode is provided only on the upper surface of the n-type semiconductor region in the field effect bipolar transistor of the first embodiment. The current density J _bulk of the pn junction when not affected by the electric field control electrode is obtained in the same manner as the equation (5). Unlike the first embodiment, the conduction electron density n _p1 of the _p- type semiconductor region due to the arrangement of the electric field control electrode does not change as in the formula (6) but remains n _p , and instead of the n-type semiconductor region. The hole density p _n1 is

_{p n1 = p n × exp (} -qφ s1 / kT) (26)

It changes as follows. Here, φ _s1 is the surface energy level of the near-surface region of the n-type semiconductor. The surface energy level φ _{s1 in the} region near the surface of the n-type semiconductor is the difference φ _ms (= φ _m −φ _sn) between the work function φ _{m of the} material constituting the electric field control electrode and the Fermi level φ _{sn in} the n-type semiconductor region. ) Changes by q (φ _ms −V _i ). Here, Vi is a potential difference generated between both interfaces of the insulating film immediately below the electric field control electrode due to bonding of the electric field control electrode. The potential difference φ _ms generated by the bonding of the electric field control electrode is divided into the potential difference V _i between the interfaces of the insulating film and the surface level φ _s1 in the region near the surface of the n-type semiconductor. Due to the change of these surface states, the current density J _{sur in the} vicinity of the pn junction surface is obtained from the equations (2), (4) and (26).

_{J sur = qD n n p0 /} L n × (exp (-qV ec / kT) -1) + qD p p n0 / L p × (exp (q (-V ec -φ s1) / kT) -exp (- qφ _s1 / kT)), (27)

It becomes. When applying a gate voltage V _g to the field control electrode, the gate voltage V _g in the same manner as in Example 1, minute surface level phi _gsn interfacial potential difference V _gin and the n-type semiconductor region near the surface of the insulating film Pressed. The current density J _sur in the pn junction is _calculated using the equation (27) and the surface state φ _gsn ,

_{J sur = qD n n p0 /} L n × (exp (-qV ec / kT) -1) + qD p p n0 / L p × (exp (q (-V ec -φ s1 -φ gsn) / kT) - exp (q (−φ _s1 −φ _gsn ) / kT)), (28)

Can be expressed as When the impurity concentration of the p-type semiconductor region is sufficiently larger than the impurity concentration of the n-type semiconductor region, the current density due to conduction electrons is sufficiently smaller than the current density due to holes, and Equation (28) is

_{J sur = qD p p n0 /} L p × (exp (q (-V ec -φ s1 -φ gsn) / kT) -exp (q (-φ s1 -φ gsn) / kT)), (29)

Is approximated. The hole diffusion current equation of equation (29) is the same as the conduction electron diffusion current equation of equation (9) when the polarity of the surface state is reversed. That is, contrary to the conduction electron behavior in equation (9), the hole current density J _sur decreases with respect to the positive gate voltage and increases with respect to the negative gate voltage. Except for this difference in polarity, the field-effect bipolar transistor of Example 3 exhibits the same characteristics as Example 1. Similar to the first embodiment, the collector electrode may be bonded to the p-type semiconductor region via the high-concentration p-type semiconductor region. The present embodiment realizes two types of field effect bipolar transistors having different polarity of changes in the emitter current with respect to the gate voltage, so that the complementary field effect required for constructing a current digital integrated circuit with low power consumption. A bipolar transistor is provided.

As shown in FIG. 12, the fourth embodiment has a configuration in which the field control electrode is also provided on a part of the upper surface of the n-type semiconductor region in the field effect bipolar transistor of the first embodiment. When not affected by the electric field control electrode, the current density J _bulk of the pn junction is obtained in the same manner as in the equation (5). Due to the arrangement of the electric field control electrode, the conduction electron density n _{p1 in the} region near the surface of the p-type semiconductor changes in the same manner as the equation (6) in Example 1, and the hole density p _n1 in the n-type semiconductor region is implemented. It changes similarly to the expression (26) of Example 3. The current density J _{sur in the} vicinity of the pn junction surface is obtained from the equations (2), (4), (6), and (26).

_{J sur = qD n n p0 /} L n × (exp (q (-V ec + φ s0) / kT) -exp (qφ s0 / kT)) + qD p p n0 / L p × (exp (q (-V ec −φ _s1 ) / kT) −exp (−qφ _s1 / kT)), (30)

It becomes. When applying a gate voltage V _g to the field control electrode, the gate voltage V _g in the same manner as in Example 1, minute surface level phi _gsn interfacial potential difference V _gin and the n-type semiconductor region near the surface of the insulating film Pressed. The current density J _{sur at the} pn junction is obtained by using the surface _states φ _gs and φ _gsn by applying the equation (30) and the gate voltage V _g ,

_{J sur = qD n n p0 /} L n × (exp (q (-V ec + φ gs + φ s0) / kT) -exp (q (φ gs + φ s0) / kT)) + qD p p n0 / L p × ( exp (q (−V _ec −φ _s1 −φ _gsn ) / kT) _−exp (q (−φ _s1 −φ _gsn ) / kT)), (31)

Desired. This result is a current density equation that is a combination of the equation (9) of the diffusion current density of conduction electrons in Example 1 and the equation (29) of the diffusion current density of holes in Example 3. Can be considered in the same manner as in Example 1 and Example 3. Similar to the first embodiment, the collector electrode may be bonded to the p-type semiconductor region via the high-concentration p-type semiconductor region.

Current density J _sur of the pn junction in Example 4, the diffusion current of the conduction electrons which increases exponentially with respect to the gate voltage V _g, the hole diffusion current decreases exponentially with respect to the gate voltage V _g is , The characteristics are added by the ratio of the density of both minority carriers. This example shows that when the electric field control electrode protrudes above the semiconductor region on the high concentration side of the semiconductor region constituting the pn junction, the influence of the protrusion on the characteristics is small. This shows that the manufacturing cost can be reduced by reducing the burden on the matching technique when manufacturing the polar transistor.

As shown in FIG. 13, the fifth embodiment has a configuration in which the field control electrode on the n-type semiconductor region and the field control electrode on the p-type semiconductor region are separated into two in the field effect bipolar transistor of the fourth embodiment. . The two gate electrodes Gn and Gp, the conduction electron density n _p1 of hole density p _n1 and p-type semiconductor region of the n-type semiconductor area can be controlled individually. The change of the surface level in the region near the n-type semiconductor surface due to the gate voltage V _gn applied to the gate electrode Gn is φ _gsn , and the change in the surface level in the region near the p-type semiconductor surface due to the gate voltage V _gp applied to the gate electrode Gp Is φ _gs , the current density J _{sur at the} pn junction is the same as that in the equation (31), and the following operation can be considered as in the fourth embodiment. As in the fourth embodiment, the collector electrode may be joined to the p-type semiconductor region via the high-concentration p-type semiconductor region. The current density J _sur of the pn junction in Example 5 is determined by the diffusion current of conduction electrons that increases exponentially with respect to the gate voltage V _gn and the diffusion current of holes that decreases exponentially with respect to the gate voltage V _gp . , The characteristics are added by the ratio of the density of both minority carriers. The field effect bipolar transistor of this embodiment constitutes a two-input differential field effect bipolar transistor in which the gate electrode Gn has a reverse phase input and the gate electrode Gp has a positive phase input.

As shown in FIG. 14, the sixth embodiment has a configuration in which two field effect transistors of the first embodiment and a semiconductor region connected to the collector electrode are arranged in common. The operation of each field effect bipolar transistor is the same as in the first embodiment. Similar to the first embodiment, the collector electrode may be bonded to the p-type semiconductor region via the high-concentration p-type semiconductor region. When field effect bipolar transistors are integrated and used for signal processing or the like, a basic circuit is configured by using a plurality of field effect bipolar transistors with close characteristics created in close proximity. This embodiment has the advantage that the area of the collector region can be saved when the basic circuit for signal processing is integrated. The present invention provides a high-gain differential amplifier circuit that is indispensable when constructing high-speed communication equipment in recent years.
As a modification of the sixth embodiment, instead of having a common p-type semiconductor region connected to the collector electrode, the sixth embodiment can be configured with a common n-type semiconductor region connected to the emitter electrode. The characteristics can be considered similarly. As a modification of the sixth embodiment, the n-type semiconductor region connected to the emitter electrode and the p-type semiconductor region connected to the collector electrode are commonly used, and two field effect bipolar transistors are connected in parallel. And their characteristics can be considered similarly. Further, as a modification of the sixth embodiment, instead of the two field effect bipolar transistors of the first embodiment, two field effect bipolar transistors having the structures of the third, fourth, and fifth embodiments are used. These characteristics can be considered similarly.

As shown in FIG. 15, the seventh embodiment has a configuration in which the field control electrode is provided only on the upper surface of the n-type semiconductor region connected to the emitter electrode in the field effect bipolar transistor of the second embodiment. The current density J _bulk of the pn junction when not affected by the electric field control electrode is obtained in the same manner as in the equation (17). Unlike the second embodiment, the conduction electron density n _p1 of the _p- type semiconductor region due to the arrangement of the electric field control electrode does not change as in the equation (18) but remains n _p and is connected to the emitter electrode instead. The hole density p _n1 of the n-type semiconductor region is

_{p n1 = p n × exp (} -qφ s1 / kT) (32)

It changes as follows. Here, φ _s1 is the surface energy level of the near-surface region of the n-type semiconductor connected to the emitter electrode. The surface energy level φ _s1 of the region near the surface of the n-type semiconductor connected to the emitter electrode is expressed by the work function φ _{m of the} material constituting the electric field control electrode and the Fermi level φ of the n-type semiconductor region connected to the emitter electrode. the difference in _{sn φ ms (= φ m -φ} sn), changes by q (φ _ms -V _i). Here V _i by joining the field control electrode, a potential difference generated between both the interface between the insulating film immediately under the field control electrode. The potential difference φ _ms generated by the bonding of the electric field control electrode is divided into the potential difference V _i between the interfaces of the insulating film and the surface level φ _s1 in the region near the surface of the n-type semiconductor. Due to the change of these surface states, the current density J _{sur in the} vicinity of the pn junction surface is obtained from the equations (14), (16), and (32).

_{J sur = qD n n p0 /} L n × (exp (-qV eb / kT) -1) + qD p p n0 / L p × (exp (q (-V eb -φ s1) / kT) -exp (- qφ _s1 / kT)), (33)

It becomes. When applying a gate voltage V _g to the field control electrode, the gate voltage V _g in the same manner as in Example 2, the interface between the electric potential difference V _gin and the n-type surface of the semiconductor near the surface region connected to the emitter electrode of the insulation coating The _voltage is _divided to the level φ _gsn . The current density J _{sur at the} pn junction is _calculated using the equation (33) and the surface state φ _gsn .

_{J sur = qD n n p0 /} L n × (exp (-qV eb / kT) -1) + qD p p n0 / L p × (exp (q (-V eb -φ s1 -φ gsn) / kT) - exp (q (−φ _s1 −φ _gsn ) / kT)), (34)

Can be expressed as When the impurity concentration of the p-type semiconductor region is sufficiently higher than the impurity concentration of the n-type semiconductor region connected to the emitter electrode, the current density due to conduction electrons is sufficiently smaller than the current density due to holes, Equation (34) is

J _sur = qD _p p _n0 / L _p × (exp (q (−V _eb −φ _s1 −φ _gsn ) / kT) _−exp (q (−φ _s1 −φ _gsn ) / kT)), (35)

Is approximated. The hole diffusion current equation of Equation (35) is the same as the conduction electron diffusion current equation of Equation (21) when the polarity of the surface state is reversed. That is, contrary to the behavior of conduction electrons in equation (21), the hole current density J _sur decreases with respect to the positive gate voltage, and increases with respect to the negative gate voltage. Except for this difference in polarity, the field effect bipolar transistor of Example 7 exhibits the same characteristics as Example 2. Further, in the seventh embodiment, the configuration in which the electric field control electrode is provided only on the upper surface of the n-type semiconductor region connected to the emitter electrode is shown as an example. However, the n-type semiconductor connected to the emitter electrode due to the symmetry of the structure. The same can be considered when the electric field control electrode is provided only on the upper surface of the n-type semiconductor region connected to the collector electrode instead of the upper surface of the region. This embodiment realizes two types of field effect bipolar transistors having different polarities of changes in the collector current with respect to the gate voltage, so that the complementary field effect required for constructing today's digital integrated circuit with low power consumption. A bipolar transistor is provided.

As shown in FIG. 16, the eighth embodiment has a configuration in which the field control electrode is also provided on a part of the upper surface of the n-type semiconductor region connected to the emitter electrode in the field effect bipolar transistor of the second embodiment. When not affected by the electric field control electrode, the current density J _bulk of the pn junction is obtained in the same manner as in the equation (17). The conduction electron density n _{p1 in the} region near the surface of the p-type semiconductor due to the arrangement of the electric field control electrode changes in the same manner as in the equation (18) of Example 2, and the positive polarity of the n-type semiconductor region connected to the emitter electrode The hole density p _n1 changes in the same manner as the expression (32) in the seventh embodiment. The current density J _{sur in the} vicinity of the pn junction surface composed of the n-type semiconductor region and the p-type semiconductor region connected to the emitter electrode is obtained from the equations (14), (16), (18), and (32).

_{J sur = qD n n p0 /} L n × (exp (q (-V eb + φ s0) / kT) -exp (qφ s0 / kT)) + qD p p n0 / L p × (exp (q (-V eb −φ _s1 ) / kT) −exp (−qφ _s1 / kT)), (36)

It becomes. When applying a gate voltage V _g to the field control electrode, the gate voltage V _g in the same manner as in Example 2, the interface between the electric potential difference V _gin and the n-type surface of the semiconductor near the surface region connected to the emitter electrode of the insulation coating The _voltage is _divided to the level φ _gsn . The current density J _{sur at the} pn junction is obtained by using the surface _states φ _gs and φ _gsn by applying the equation (36) and the gate voltage V _g ,

_{J sur = qD n n p0 /} L n × (exp (q (-V eb + φ gs + φ s0) / kT) -exp (q (φ gs + φ s0) / kT)) + qD p p n0 / L p × ( exp (q (−V _eb −φ _s1 −φ _gsn ) / kT) _−exp (q (−φ _s1 −φ _gsn ) / kT)), (37a)

Is required. This result is a current density equation obtained by combining the equation (21) of the diffusion current density of conduction electrons in Example 2 and the equation (35) of the diffusion current density of holes in Example 7. The current density J _{surc in the} vicinity of the pn junction surface composed of the n-type semiconductor region and the p-type semiconductor region connected to the collector electrode is

_{J surc = -qD n n p0 /} L n × (exp (q (-V cb + φ gs + φ s0) / kT) -exp (q (φ gs + φ s0) / kT)) - qD p p n0 / L p × (exp (−qV _cb / kT) −1), (37b)

Is required. In consideration of the direction of current, the symbol-is attached. The eighth embodiment can be considered as a characteristic combining the equations (37a) and (37b), and the following operations can be considered in the same manner as the second and seventh embodiments. The current density J _sur + J _surc of the pn junction in Example 8 is the diffusion current of the conduction electrons from the emitter electrode and the gate voltage V that increase exponentially with respect to the gate voltage V _g under the emitter-base voltage V _eb. and diffusion current of holes toward the emitter decreases exponentially with respect to _g, the collector - under the base voltage V _cb, conduction electrons diffusion current from the collector electrode increases exponentially with respect to the gate voltage V _g and diffusion current of holes toward the collector does not depend on the gate voltage V _g becomes the ratio are added in consideration of the orientation by the characteristics of the density of minority carriers. Further, in Example 8, a configuration in which the electric field control electrode is also provided on a part of the upper surface of the n-type semiconductor region connected to the emitter electrode is shown as an example. However, due to the symmetry of the structure, it is connected to the emitter electrode. The same can be considered when an electric field control electrode is provided on a part of the upper surface of the n-type semiconductor region connected to the collector electrode instead of a part of the upper surface of the n-type semiconductor region. This example shows that when the electric field control electrode protrudes above the semiconductor region on the high-concentration side among the semiconductor regions constituting the emitter-base pn junction, the influence of the protrusion on the characteristics is small. This shows that the manufacturing cost can be reduced by reducing the burden on the mask matching technique when manufacturing the field effect bipolar transistor.

As shown in FIG. 17, the ninth embodiment has two field control electrodes on the n-type semiconductor region and two p-type semiconductor regions connected to the emitter electrode in the field effect bipolar transistor of the eighth embodiment. It is the structure separated into. The two gate electrodes Gn and Gp, it is possible to individually control the conduction electron density n _p1 of hole density p _n1 and p-type semiconductor region of the n-type semiconductor region connected to the emitter electrode. The change in the surface level of the region near the n-type semiconductor surface connected to the emitter electrode due to the gate voltage V _gn applied to the gate electrode Gn is φ _gsn , and the region near the p-type semiconductor surface due to the gate voltage V _gp applied to the gate electrode Gp _Where φ _gs is the change in the surface level of the pn junction, the current density J _sur + J _{surc at} the pn junction can be obtained by the sum of the expressions (37a) and (37b). The following operation can be considered in the same manner as in the eighth embodiment. The current density J _sur + J _surc of the pn junction in Example 9 is the diffusion current of conduction electrons that increases exponentially with respect to the gate voltage V _gn and the holes that decrease exponentially under the emitter-base voltage V _eb. And the diffusion current of the conduction electrons exponentially increasing with respect to the gate voltage V _gp and the diffusion current of the holes toward the collector independent of the gate voltage V _g under the collector-base voltage V _cb , It becomes the characteristic added in consideration of the direction by the ratio of the density of minority carriers in each region. Therefore, the field effect bipolar transistor of Example 9 constitutes a differential input field effect bipolar transistor in which the gate electrode Gn is a reverse phase input and the gate electrode Gp is a positive phase input. Further, in the ninth embodiment, a configuration in which the electric field control electrode is also provided on a part of the upper surface of the n-type semiconductor region connected to the emitter electrode is shown as an example, but it is connected to the emitter electrode due to the symmetry of the structure. The same can be considered when the electric field control electrode is applied to a part of the upper surface of the n-type semiconductor region connected to the collector electrode instead of a part of the upper surface of the n-type semiconductor region.

Example 10 is an n-type semiconductor region connected to an emitter electrode, a p-type semiconductor region, and an n-type semiconductor region connected to a collector electrode in the field effect bipolar transistor shown in Example 2 as shown in FIG. In this configuration, the electric field control electrode is disposed over the upper part of the electrode. The current density J _{sur at the} pn junction composed of the n-type semiconductor region and the p-type semiconductor region connected to the emitter electrode is the same as that in Expression (37a). The current density J _surc in a pn junction composed of an n-type semiconductor region and a p-type semiconductor region connected to the collector electrode is

_{J surc = -qD n n p0 /} L n × (exp (q (-V cb + φ gs + φ s0) / kT) -exp (q (φ gs + φ s0) / kT)) - qD p p n0 / L p × (exp (q (−V _cb −φ _s1 −φ _gsn ) / kT) _−exp (q (−φ _s1 −φ _gsn ) / kT)), (38)

It becomes. In consideration of the direction of current, the symbol-is attached. Since Expression (38) is the same as Expression (37a) except that the direction of the current is different, Example 10 is considered in the same manner as Example 8 as the combined characteristic of Expression (37a) and Expression (38). be able to. The current density J _sur + J _surc of the pn junction in Example 10 is the diffusion current of the conduction electrons from the emitter electrode and the gate voltage V that increase exponentially with respect to the gate voltage V _g under the emitter-base voltage V _eb. and diffusion current of holes toward the emitter decreases exponentially with respect to _g, the collector - under the base voltage V _cb, conduction electrons diffusion current from the collector electrode increases exponentially with respect to the gate voltage V _g and hole diffusion current toward collector decreases exponentially with respect to the gate voltage V _g becomes the ratio are added in consideration of the orientation by the characteristics of the density of minority carriers.

In Example 11, as shown in FIG. 19, in the field effect bipolar transistor shown in Example 2, the electric field control electrode on the p-type semiconductor region is divided into two electrodes. The current density J _sur in a pn junction composed of an n-type semiconductor region and a p-type semiconductor region connected to the emitter electrode is

_{J sur = qD n n p0 /} L n × (exp (q (-V eb + φ gs + φ s0) / kT) -exp (q (φ gs + φ s0) / kT)) + qD p p n0 / L p × ( exp (−qV _eb / kT) −1), (39)

It is obtained. On the other hand, the current density J _surc in a pn junction composed of an n-type semiconductor region and a p-type semiconductor region connected to the collector electrode is

_{J surc = -qD n n p0 /} L n × (exp (q (-V cb + φ gs + φ s0) / kT) -exp (q (φ gs + φ s0) / kT)) - qD p p n0 / L p × (exp (−qV _cb / kT) −1), (40)

Is required. In consideration of the direction of current, the symbol-is attached. Since Expression (40) is the same as Expression (39) except that the direction of the current is different, Example 11 is considered in the same manner as Example 2 as a characteristic combining Expression (39) and Expression (40). be able to. The current density J _sur + J _surc of the pn junction in Example 11 is the diffusion current of the conduction electrons from the emitter electrode and the gate voltage V that increase exponentially with respect to the gate voltage V _g under the emitter-base voltage V _eb. The diffusion current of holes toward the emitter independent of _g , and the diffusion current of the conduction electrons from the collector electrode and the gate voltage V _g that increase exponentially with respect to the gate voltage V _g under the collector-base voltage V _cb. The diffusion current of the holes toward the collector, which does not depend on, becomes a characteristic obtained by adding the density considerations of the minority carriers in consideration of the direction. Therefore, the field effect bipolar transistor of Example 11 constitutes a differential input field effect bipolar transistor in which the gate electrode G1 has a negative phase input and the gate electrode G2 has a positive phase input.
As a modification of the eleventh embodiment, when the electric field control electrode is applied to a part of the upper surface of the n-type semiconductor region connected to the emitter electrode, that is, two field effect bipolar transistors having the structure of the eighth embodiment are provided. The same applies to the case where Example 11 is configured using a p-type semiconductor region connected to the base electrode in common. Further, as a modification of the eleventh embodiment, when the electric field control electrode is applied only to the n-type semiconductor region connected to the emitter electrode and the n-type semiconductor region connected to the collector electrode, that is, 2 having the structure of the seventh embodiment. The same applies to the case where the eleventh embodiment is configured using a common p-type semiconductor region in which two field effect bipolar transistors are connected to the base electrode.

In Example 12, as shown in FIG. 20, two field effect bipolar transistors of Example 2 are arranged with a common n-type semiconductor region connected to the collector electrode. The operation of each field effect bipolar transistor is the same as that of the second embodiment. When the forward bias voltages applied to the emitter-base pn junctions of the two field effect bipolar transistors are equal, the p-type semiconductor region connected to the base electrode is commonly used. When field effect bipolar transistors are integrated and used for signal processing or the like, a basic circuit is configured by using a plurality of field effect bipolar transistors with close characteristics created in close proximity. The twelfth embodiment has an advantage that the area of the collector region can be saved when the signal processing basic circuit is integrated. The present invention provides a high-gain differential amplifier circuit that is indispensable when constructing high-speed communication equipment in recent years.
As a modification of Example 12, instead of having a common n-type semiconductor region connected to the collector electrode, Example 12 can be configured with a common n-type semiconductor region connected to the emitter electrode. The characteristics can be considered similarly. Further, as a modification of the twelfth embodiment, the n-type semiconductor region connected to the emitter electrode and the n-type semiconductor region connected to the collector electrode are shared, and two field effect bipolar transistors are connected in parallel. And their characteristics can be considered in the same way. Further, as a modification of the twelfth embodiment, two field effect bipolar transistors having the structures of the seventh, eighth, ninth, tenth, and eleventh embodiments are used instead of the two field effect bipolar transistors of the second embodiment. Field effect bipolar transistors can be constructed and their characteristics can be considered as well.

In Example 13, as shown in FIG. 21, in the field effect bipolar transistor of Example 2, the current density J _{bulk represented} by the equation (17) in the region where the electric field control electrode is not disposed on the pn junction is reduced. Thus, an example is shown in which the current control range by the gate voltage is secured by the structure of the electric field control electrode. The n-type semiconductor region connected to the emitter electrode is surrounded by a p-type semiconductor region connected to the gate electrode, and the entire surface of the p-type semiconductor region is covered with an annular electric field control electrode. The n-type semiconductor region connected to the collector electrode has a structure surrounding the p-type semiconductor region connected to the gate electrode. The high-concentration implantation region for connecting the base electrode surrounds the n-type semiconductor region connected to the collector electrode in an annular shape to constitute a device. By surrounding the periphery with an electric field control electrode so as to surround the n-type semiconductor region connected to the emitter electrode, the current density of the pn junction composed of the n-type semiconductor region connected to the emitter electrode and the p-type semiconductor region is pn All can be treated as the current density J _sur shown in the equation (20) except for the deep part of the junction. In this embodiment, minority carriers leaking out from the n-type semiconductor region connected to the emitter electrode can be reduced, and parasitic elements generated when an integrated circuit is configured using a field effect bipolar transistor are used. Can solve various problems.
As a modification of the thirteenth embodiment, the same effect can be obtained by providing a structure surrounding the periphery with a buried insulating layer instead of surrounding the periphery with an electric field control electrode so as to surround the n-type semiconductor region connected to the emitter electrode. Can do. As a modification of the thirteenth embodiment, instead of the second embodiment, the field effect bipolar transistors of the first embodiment and the third to twelfth embodiments can be used to configure the device of the thirteenth embodiment. Can be considered similarly.

As described above, according to the present invention, the diffusion current in the pn junction can be directly controlled by the electric field effect, and a transistor with a new operation principle that controls the diffusion current by electric field control can be configured. The field effect bipolar transistor can be applied to a high gain amplifier because the collector current has an exponential characteristic with respect to the gate voltage and the forward bias voltage of the emitter side pn junction. From the static characteristics of the field effect bipolar transistor in the case of utilizing the gate electrode as an input, it can be seen that a high order of several MΩ output resistor R _o. The intrinsic gain g _m × R _o is about 230 times, and a high gain amplifier close to a bipolar transistor can be realized. A field effect bipolar transistor is independent of a bias input terminal for injecting carriers into the base region and a gate terminal for signal input. Therefore, the signal input terminal does not require a bias current or a large bias voltage, and has a low power supply voltage. Works below. The field effect bipolar transistor has a high input resistance because the gate electrode has an insulating structure. When both the gate electrode and the emitter electrode are used as inputs, the intrinsic gain g _mm × _Ro is about 1500 times, and the device functions as a high gain amplification device in which the effect of the electric field and the characteristics of the bipolar transistor are superimposed. In a field effect bipolar transistor, the surface density of minority carriers in each region can be individually controlled by controlling each semiconductor region constituting the pn junction with an individual electric field control electrode. A highly functional transistor having a function can be configured. In a field effect bipolar transistor, a transistor having a relative structure and a relative characteristic can be configured by switching the types of semiconductors constituting the pn junction.

  The present invention has a high input resistance with a high gain, does not require a large bias voltage at the signal input terminal, and is capable of low power supply voltage operation that solves the problems that are a problem in today's large-scale integrated circuits. It can be used as a functional field effect bipolar transistor. In addition, since the field effect bipolar transistor does not require special technology in manufacturing, it has the advantage that it can be used in combination with existing integrated circuit technology, and can be used as an extremely effective device.

FIG. 1A is a longitudinal sectional view showing the principle of a semiconductor device (field effect bipolar transistor) according to a first embodiment of the present invention. FIG. 1B is an energy band diagram of a deep pn junction layer corresponding to the longitudinal sectional view of the semiconductor device (field effect bipolar transistor) of FIG. 1A (when no voltage is applied to the pn junction). FIG. 1C is an energy band diagram of a pn junction deep layer corresponding to a longitudinal sectional view of the semiconductor device (field effect bipolar transistor) of FIG. 1A (when the pn junction is forward-biased). FIG. 1D is an energy band diagram (V _g = 0 V) of the pn junction surface layer corresponding to the longitudinal sectional view of the semiconductor device (field effect bipolar transistor) of FIG. 1A. FIG. 1E is an energy band diagram (exhausted state) of the pn junction surface layer corresponding to the longitudinal sectional view of the semiconductor device (field effect bipolar transistor) of FIG. 1A. FIG. 1F is an energy band diagram (inverted state) of the pn junction surface layer corresponding to the longitudinal sectional view of the semiconductor device (field effect bipolar transistor) of FIG. 1A. FIG. 1G is an energy band diagram (accumulation state) of a pn junction surface layer corresponding to a longitudinal sectional view of the semiconductor device (field effect bipolar transistor) of FIG. 1A. FIG. 2A is a vertical cross-sectional view of a field effect bipolar transistor having a buried structure used for measurement, which is a modification of the semiconductor device (field effect bipolar transistor) of FIG. 1A. FIG. 2B is a modification of the semiconductor device (field effect bipolar transistor) of FIG. 1A, and is a longitudinal section of a field effect bipolar transistor having a structure in which leakage current to areas other than the electric field control region is reduced by covering the periphery and bottom with an insulating layer. FIG. 2C is a vertical cross-sectional view of a field effect bipolar transistor in which an n-type semiconductor region and a p-type semiconductor region are interchanged, as a modification of the semiconductor device (field effect bipolar transistor) of FIG. 1A. 2D is a vertical cross-sectional view of a field effect bipolar transistor having a buried structure corresponding to FIG. 2C, which is a modification of the semiconductor device (field effect bipolar transistor) of FIG. 1A. FIG. 2E is a modification of the semiconductor device (field effect bipolar transistor) of FIG. 1A. The field effect has a structure in which leakage current to areas other than the electric field control region is reduced by covering the periphery and bottom corresponding to FIG. 2C with an insulating layer. It is a longitudinal cross-sectional view of a bipolar transistor. FIG. 3A is a measurement circuit for the semiconductor device (field effect bipolar transistor) of the first embodiment of the present invention corresponding to FIG. 2A. FIG. 3B shows a measurement result of the emitter current Ie with respect to the gate voltage Vg when the emitter-collector voltage is used as a parameter in the semiconductor device (field effect bipolar transistor) of the first embodiment of the present invention corresponding to FIG. 2A. It is an Ie characteristic view. FIG. 4A is a measurement circuit for the semiconductor device (field effect bipolar transistor) of the first embodiment of the present invention corresponding to FIG. 2D. 4B shows a measurement result of the emitter current Ie with respect to the gate voltage Vg when the emitter-collector voltage is used as a parameter in the semiconductor device (field effect bipolar transistor) of the first embodiment of the present invention corresponding to FIG. 2D. It is an Ie characteristic view. FIG. 5A is a sectional view of a semiconductor device (field effect bipolar transistor) according to a second embodiment of the present invention. FIG. 5B is an energy band diagram (when no voltage is applied to the pn junction) of the pn junction deep layer corresponding to the cross-sectional view of the semiconductor device (field effect bipolar transistor) of FIG. 5A. FIG. 5C is an energy band diagram of the pn junction deep layer corresponding to the cross-sectional view of the semiconductor device (field effect bipolar transistor) of FIG. It is. FIG. 5D is an energy band diagram (V _g = 0 V) of the pn junction surface layer corresponding to the cross-sectional view of the semiconductor device (field effect bipolar transistor) of FIG. 5A. FIG. 5E is an energy band diagram (exhausted state) of the pn junction surface layer corresponding to the cross-sectional view of the semiconductor device (field effect bipolar transistor) of FIG. 5A. FIG. 5F is an energy band diagram (inverted state) of the pn junction surface layer corresponding to the cross-sectional view of the semiconductor device (field effect bipolar transistor) of FIG. 5A. FIG. 5G is an energy band diagram (accumulation state) of the pn junction surface layer corresponding to the cross-sectional view of the semiconductor device (field effect bipolar transistor) of FIG. 5A. FIG. 6A is a vertical cross-sectional view of a field effect bipolar transistor having a buried structure used for measurement in a modification of the semiconductor device (field effect bipolar transistor) of FIG. 5A. FIG. 6B is a modification of the semiconductor device (field effect bipolar transistor) of FIG. 5A, and is a longitudinal section of a field effect bipolar transistor having a structure in which leakage current to areas other than the electric field control region is reduced by covering the periphery and bottom with an insulating layer. FIG. 6C is a top view of FIG. 6B. FIG. 6D is a vertical cross-sectional view of a field effect bipolar transistor in which an n-type semiconductor region and a p-type semiconductor region are interchanged in a modification of the semiconductor device (field effect bipolar transistor) of FIG. 5A. 6E is a vertical cross-sectional view of a field effect bipolar transistor having a buried structure corresponding to FIG. 6D, which is a modification of the semiconductor device (field effect bipolar transistor) of FIG. 5A. FIG. 6F is a modified example of the semiconductor device (field effect bipolar transistor) of FIG. 5A, and has a structure in which leakage current to a region other than the electric field control region is reduced by covering the periphery and bottom corresponding to FIG. 6D with an insulating layer. It is a longitudinal cross-sectional view of a bipolar transistor. 6G is a top view of FIG. 6F. FIG. 7A is a measurement circuit for measuring the collector current characteristic with respect to the gate voltage when the emitter-base voltage is used as a parameter for the field effect bipolar transistor having the structure of FIG. 6A in the second embodiment of the present invention. FIG. 7B is a diagram showing a measurement result of the collector current with respect to the gate voltage when the emitter-base voltage is used as a parameter for the field effect bipolar transistor having the structure of FIG. 6A in the second embodiment of the present invention. FIG. 8A is a measurement circuit for measuring the collector current characteristic with respect to the collector-base voltage when the gate voltage is used as a parameter for the field effect bipolar transistor having the structure of FIG. 6A in the second embodiment of the present invention. FIG. 8B is a diagram showing a measurement result of the collector current with respect to the collector-base voltage when the gate voltage is used as a parameter for the field effect bipolar transistor having the structure of FIG. 6A in the second embodiment of the present invention. FIG. 9A is a measurement circuit for measuring the collector current characteristics with respect to the gate voltage when the emitter-base voltage is used as a parameter for the field effect bipolar transistor having the structure of FIG. 6E in the second embodiment of the present invention. FIG. 9B is a diagram showing a measurement result of the collector current with respect to the gate voltage when the emitter-base voltage is used as a parameter for the field effect bipolar transistor having the structure of FIG. 6E in the second embodiment of the present invention. FIG. 10A is a measurement circuit for measuring the collector current characteristics with respect to the collector-base voltage when the gate voltage is used as a parameter for the field effect bipolar transistor having the structure of FIG. 6E in the second embodiment of the present invention. FIG. 10B is a diagram showing a measurement result of the collector current with respect to the collector-base voltage when the gate voltage is used as a parameter for the field effect bipolar transistor having the structure of FIG. 6E in the second embodiment of the present invention. It is a partial cross-sectional view of the field effect bipolar transistor embodiment 3 of the present invention. It is a partial sectional view of a field effect bipolar transistor embodiment 4 of the present invention. 6 is a partial cross-sectional view of a field effect bipolar transistor embodiment 5 of the present invention. FIG. 7 is a partial sectional view of a field effect bipolar transistor embodiment 6 of the present invention. FIG. It is a partial cross-sectional view of the field effect bipolar transistor embodiment 7 of the present invention. 10 is a partial cross-sectional view of a field effect bipolar transistor embodiment 8 of the present invention. FIG. 10 is a partial cross-sectional view of a field effect bipolar transistor embodiment 9 of the present invention. FIG. It is a partial cross-sectional view of the field effect bipolar transistor embodiment 10 of the present invention. It is a partial sectional view of the field effect bipolar transistor embodiment 11 of the present invention. It is a partial cross section figure of this invention field effect bipolar transistor Example 12. FIG. It is a partial surface view of the field effect bipolar transistor Example 13 of the present invention. Table 1 Table 2 Table 3

Explanation of symbols

10 ... n-type semiconductor region,
11 ... p-type semiconductor region,
12 ... Insulating coating,
13 ... Electric field control electrode,
14 ... n-type semiconductor region,
15 ... p-type semiconductor region,
16 ... n-type semiconductor region,
17 ... Electric field control electrode,
18 ... p-type semiconductor region,
20 ... Emitter electrode,
21 ... Collector electrode,
22 ... Gate electrode,
23 ... Insulating layer,
24 ... Base electrode,
25 ... Insulating layer deep in substrate,
26 ... substrate,
27 ... Insulating layer on the side surface,
28 ... p-type semiconductor region,
29... N-type semiconductor region,
30a, 32a ... deep pn junctions 30b, 32b ... surface layer pn junctions,
31 ... Surface layer of p-type semiconductor region

Claims (10)

A first semiconductor region in which the density of the first carrier is higher than the density of the second carrier and a second semiconductor region in which the density of the second carrier is higher than the density of the first carrier are adjacent to each other. Comprising a joined body comprising
A semiconductor device, characterized in that it can be driven as a transistor by means for interposing an insulator at least in the first semiconductor region and for applying a charge to the second semiconductor region. A first semiconductor region in which the density of the first carrier is higher than the density of the second carrier and a second semiconductor region in which the density of the second carrier is higher than the density of the first carrier are adjacent to each other. Forming a joined body comprising:
Providing an electric charge between the second semiconductor region by interposing an insulator at least in the first semiconductor region;
A method for driving a semiconductor device, characterized in that it can be driven as a transistor. The first semiconductor region has a first impurity concentration,
The second semiconductor region has a second impurity concentration;
The bonded body is a semiconductor device in which the first and second semiconductor regions are adjacent to each other at a bonding surface,
A first electrode bonded to at least the first semiconductor region via an insulator in the vicinity of the bonding surface;
A second electrode connected to the first semiconductor region;
A third electrode connected to the second semiconductor region;
With
A forward bias is applied between the second and third electrodes to lower the potential barrier corresponding to the bonding surface,
By applying a potential difference between the first electrode and the second electrode, the potential barrier changes, and the first semiconductor region changes in the second carrier density on the surface layer at the boundary with the insulator. 2. The semiconductor device according to claim 1, wherein the surface vicinity region to be formed can be driven as a transistor as a result of being formed as a channel through which a drive current flows between the second electrode and the third electrode. The first semiconductor region has a first impurity concentration,
The second semiconductor region has a second impurity concentration;
The joined body is a method for driving a semiconductor device in which the first and second semiconductor regions are adjacent to each other at a joining surface,
Forming a first electrode bonded to at least the first semiconductor region via an insulator in the vicinity of the bonding surface;
Forming a second electrode connected to the first semiconductor region;
Forming a third electrode connected to the second semiconductor region;
A forward bias is applied between the second and third electrodes to lower the potential barrier corresponding to the junction surface,
By applying a potential difference between the first electrode and the second electrode, the potential barrier changes, and the first semiconductor region changes in the second carrier density on the surface layer at the boundary with the insulator. 3. The method of driving a semiconductor device according to claim 2, wherein the surface vicinity region to be formed can be driven as a transistor as a result of being formed as a channel through which a drive current flows between the second electrode and the third electrode. . Second and third semiconductors having a density of the second carrier higher than the density of the first carrier are adjacent to each other at a position sandwiching the first semiconductor region where the density of the first carrier is higher than the density of the second carrier. A joined body constituting the first and second potential barriers;
The first semiconductor region has one surface and the other surface, and is joined to the one surface via an insulator;
A second electrode connected to the second semiconductor region;
A third electrode connected to the third semiconductor region;
A fourth electrode connected to any one of both surfaces of the first semiconductor region;
A semiconductor comprising:
At least one of the first and second potential barriers is changed by means for applying a potential difference between the first electrode and the fourth electrode, and the first semiconductor region is connected to the insulator. A semiconductor device characterized in that a surface vicinity region is formed at a boundary as a channel through which a driving current flows, and thereby can be driven as a transistor. The second and third semiconductors having a density of the second carrier higher than the density of the first carrier are adjacent to each other at a position sandwiching the first semiconductor region where the density of the first carrier is higher than the density of the second carrier. Forming a joined body constituting the first and second potential barriers;
The first semiconductor region has one and other surfaces, and a step of forming a first electrode bonded to the one surface via an insulator;
Forming a second electrode connected to the second semiconductor region;
Forming a third electrode connected to the third semiconductor region;
Forming a fourth electrode connected to any one of both surfaces of the first semiconductor region;
A semiconductor driving method comprising:
Providing a potential difference between the first electrode and the fourth electrode, whereby at least one of the first and second potential barriers changes, and the first semiconductor region includes:
A method for driving a semiconductor device, characterized in that a region near the surface is formed as a channel through which a driving current flows at a boundary with the insulator, and thereby can be driven as a transistor. A p-type substrate having a first impurity concentration having one and the other surfaces and having the first electrode bonded to the one surface via an insulator and embedded in the one surface sandwiching the first electrode First and second n plus semiconductor regions having a concentration higher than the first impurity concentration;
A p plus semiconductor region having a higher concentration than the first impurity concentration embedded in the one surface;
A second electrode connected directly to the first n-plus semiconductor region;
A third electrode directly connected to the second n-plus semiconductor region;
A fourth electrode directly connected to the p plus semiconductor region,
A semiconductor to which a forward bias is applied between the second electrode and the fourth electrode,
In the operation region between the first electrode and the fourth electrode, by means for applying a positive potential to the first electrode, the majority carrier holes in the p-type substrate are eliminated, and minority carrier conduction electrons While increasing the diffusion current of
By applying a potential for moving the operating region in a negative direction, the holes of the majority carriers in the p-type substrate are brought close to the accumulation state, and the diffusion current of conduction electrons of the minority carriers is reduced, so that the surface layer of the p-type substrate A semiconductor device characterized in that conduction electrons in the first n-plus semiconductor region are moved to the p-type substrate and can be controlled by an electric field. Forming a p-type substrate having a first impurity concentration having one and the other surface and having the first electrode joined to the one surface via an insulator; and the one surface sandwiching the first electrode Forming first and second n plus semiconductor regions having a higher concentration than the first impurity concentration embedded in a surface;
Forming a p plus semiconductor region having a higher concentration than the first impurity concentration embedded in the one surface;
Forming a second electrode directly connected to the first n-plus semiconductor region;
Forming a third electrode directly connected to the second n-plus semiconductor region, and forming a fourth electrode directly connected to the p-plus semiconductor region,
A semiconductor driving method in which a forward bias is applied between the second electrode and the fourth electrode,
A step of applying a positive potential to the first electrode in an operation region between the first electrode and the fourth electrode, wherein the majority carrier holes in the p-type substrate are rejected to conduct minority carriers. While increasing the electron diffusion current,
A step of applying a potential for moving the operating region in the negative direction, and bringing the holes of majority carriers in the p-type substrate closer to the accumulation state to reduce the diffusion current of conduction electrons of minority carriers, thereby reducing the p-type A driving method of a semiconductor device, wherein conduction electrons in the first n-plus semiconductor region are moved to the p-type substrate on the surface layer of the substrate and can be controlled by an electric field. An n-type substrate having a first impurity concentration, having one and the other surfaces and having the first electrode joined to the one surface via an insulator, and embedded in the one surface sandwiching the first electrode First and second p plus semiconductor regions having a concentration higher than the first impurity concentration;
An n-plus semiconductor region having a higher concentration than the first impurity concentration embedded in the one surface;
A second electrode connected directly to the first p-plus semiconductor region;
A third electrode directly connected to the second p-plus semiconductor region;
A fourth electrode connected directly to the n-plus semiconductor region,
A semiconductor to which a forward bias is applied between the second electrode and the fourth electrode,
In the operation region between the first electrode and the fourth electrode, by means of applying a negative potential to the first electrode, the conduction electrons of the majority carrier in the n-type substrate are rejected, and the holes of the minority carrier While increasing the diffusion current of
By applying a potential for moving the operating region in the positive direction and bringing the conduction electrons of majority carriers in the n-type substrate closer to the accumulation state and reducing the diffusion current of the holes of minority carriers, the surface layer of the n-type substrate A semiconductor device, wherein holes in the first p-plus semiconductor region are moved to the n-type substrate and can be controlled by an electric field. Forming an n-type substrate having a first impurity concentration having one and the other surface and having the first electrode joined to the one surface via an insulator; and the one surface sandwiching the first electrode Forming first and second p plus semiconductor regions having a higher concentration than the first impurity concentration embedded in a surface;
Forming an n plus semiconductor region having a higher concentration than the first impurity concentration embedded in the one surface;
Forming a second electrode directly connected to the first p-plus semiconductor region;
Forming a third electrode directly connected to the second p-plus semiconductor region;
Forming a fourth electrode connected directly to the n-plus semiconductor region,
A semiconductor driving method in which a forward bias is applied between the second electrode and the fourth electrode,
A step of applying a negative potential to the first electrode in an operation region between the first electrode and the fourth electrode, wherein conduction electrons of the majority carriers in the n-type substrate are rejected, and While increasing the diffusion current of the holes,
A step of applying a potential to shift the operating region in a positive direction, and bringing the conduction electrons of majority carriers in the n-type substrate closer to the accumulation state and reducing the diffusion current of the holes of minority carriers, thereby A method for driving a semiconductor device, wherein holes in the first p-plus semiconductor region are moved to the n-type substrate on a surface layer of the substrate and can be controlled by an electric field.

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