JP2009059940A - THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THIN FILM TRANSISTOR, AND ELECTRONIC DEVICE - Google Patents

Abstract

Provided is a thin film transistor capable of obtaining a good gettering effect for suppressing generation of leakage current.
A thin film transistor including a semiconductor layer having a source region and a drain region with a channel region interposed therebetween, wherein at least one of the source region and the drain region has a region thinner than the channel region. It is a thin film transistor, and preferably, at least one of the source region and the drain region is a thin film transistor having a thick region and a thin region in the region.
[Selection] Figure 1

Description

The present invention relates to a thin film transistor, a method for manufacturing the thin film transistor, and an electronic device. More specifically, the present invention relates to a thin film transistor suitable for forming continuous grain boundary silicon, a method for manufacturing such a thin film transistor, and an electronic device including such a thin film transistor.

A thin film transistor (TFT) is provided as a semiconductor element in an electronic device such as an active matrix liquid crystal display device, and is used in a wide range of fields such as a switching element and a control circuit. In recent years, there has been a strong demand for higher performance of TFTs due to the rapid progress in the enlargement and high definition of liquid crystal display devices. For example, a plurality of silicon layers in a TFT are actually required. Various devices have been tried (see, for example, Patent Document 1).

A continuous grain boundary silicon (CGS) is a preferable example of a silicon layer used in a semiconductor element. CGS is particularly excellent in mobility and can be formed at a relatively low temperature because the arrangement of atoms between silicon crystal particles (grain boundaries) is continuous. In order to perform CGS, a large amount of catalyst element is usually added to the silicon layer. However, if a metal catalyst or the like is present in the channel region of the silicon layer, a leak current may be generated via the metal catalyst or the like.

An example of a device for suppressing the occurrence of leakage current is gettering. Gettering is a technique for diffusing a metal catalyst or the like existing in a semiconductor layer into a defect site using a crystal defect generated in the semiconductor layer in the TFT and in the vicinity of the semiconductor layer as a trap. Specifically, for example, the gettering effect can be obtained by performing thermal annealing under certain conditions on the TFT. By performing gettering and removing the metal catalyst or the like in the channel region, a high-performance TFT with a low leakage current generation rate can be obtained.

However, the gettering method that has been used in the past may not provide a sufficient gettering effect. Therefore, there is still room for improvement in order to obtain the gettering effect more reliably.
JP 2000-114542 A

The present invention has been made in view of the above situation, and provides a thin film transistor, a thin film transistor manufacturing method, and an electronic device capable of obtaining a good gettering effect for suppressing the occurrence of leakage current. It is intended.

The inventor conducted various studies on TFTs capable of obtaining a good gettering effect, and focused on the shape of the semiconductor layer in the TFTs. When the thickness of the semiconductor layer is the same for the entire semiconductor layer, even if gettering is performed, the metal element is located near the boundary portion (junction portion) between the channel region and the source / drain region of the semiconductor layer. It has been found that this may cause a leakage failure such as generation of an off-leakage current between the source region and the drain region and a breakdown voltage of the gate insulating film. In addition, in order to enhance the gettering effect, if measures such as increasing the amount of impurities implanted into the semiconductor layer, such as increasing the number of crystal defects in the semiconductor layer, are taken, excessive crystal breakdown of the semiconductor layer occurs. It was found that it was difficult to obtain a good TFT.

FIG. 26 is a schematic cross-sectional view showing the positional relationship of the metal elements in the semiconductor layer after ion implantation into the source / drain regions and after the thermal activation / gettering step in a normal method. (A) shows after ion implantation, and (b) shows after thermal activation / gettering step. As shown in FIG. 26A, in this embodiment, the gate insulating film 3 and the gate electrode 4 are laminated on the semiconductor layer 2, and the entire channel region 2a and source / drain region 2b of the semiconductor layer 2 are formed. The film thicknesses are almost the same. When impurities are implanted into the source / drain region 2b, the crystal defect density increases in order from the bottom surface (substrate surface) side. In FIG. 26A, the difference in density in the source / drain region 2b of the semiconductor layer 2 indicates a difference in the density of crystal defects, and the darker the color, the more defects. At this time, it is assumed that the metal element 10 exists uniformly in the semiconductor layer 2.

When the thermal activation / gettering process is performed on such a semiconductor layer 2, the metal element 10 present in the channel region 2a moves to the source / drain region (gettering site) 2b, and the source / drain region 2b Will exist uniformly. However, when the thickness of the semiconductor layer 2 is the same as in the present embodiment, the metal element 10 remains in the channel region 2a in the thermal activation / gettering process as shown in FIG. This may cause a leak failure.

Therefore, the present inventor has intensively studied (1) that a good gettering site can be formed by increasing the density of crystal defects in a part of the semiconductor layer, and (2) the semiconductor layer. By providing such a gettering site in the source / drain region, it is found that leakage defects can be avoided, and (3) the density of crystal defects increases as the semiconductor layer thickness decreases. The present inventors have arrived at the present invention by conceiving that it can be solved on a case-by-case basis.

That is, the present invention is a thin film transistor including a semiconductor layer in which a source region and a drain region are formed with a channel region interposed therebetween, and at least one of the source region and the drain region has a thickness greater than that of the channel region. A thin film transistor having a thin region.
The present invention is described in detail below.

The thin film transistor of the present invention includes a semiconductor layer in which a source region and a drain region are formed with a channel region interposed therebetween. By applying a voltage to the gate electrode of the TFT, the semiconductor layer provided through the gate insulating film has conductivity, so that the TFT is used as a switching element or the like using this. The semiconductor layer is usually made of silicon (Si), and impurities such as phosphorus (P), boron (B), and arsenic (As) are implanted to adjust the semiconductor characteristics. The semiconductor layer is composed of a channel region having a low impurity concentration and a source / drain region having a high impurity concentration. The channel region is a region disposed between the source region and the drain region, and current flows through the source region and the drain region through the channel region. The channel region preferably has a lower metal element content from the viewpoint of avoiding leakage defects, and preferably has a lower density of crystal defects in order to obtain a good gettering effect. In the semiconductor layer, a channel region is usually formed in a region overlapping with the gate electrode, and a source region and a drain region are formed in a region not overlapping with the gate electrode. Note that in this specification, the source / drain region means a source region and / or a drain region.

At least one of the source region and the drain region has a region thinner than the channel region. Impurity implantation causes crystal defects in the semiconductor layer. Such crystal defects serve as gettering sites for trapping metal elements. The crystal defects formed by the impurity implantation disappear due to the recovery of crystallinity by the annealing process for impurity activation, but the recovery of crystallinity of the semiconductor layer is often caused by crystal defects. Since it occurs from a region having a low degree, that is, a region having a low density of crystal defects, generally, the lower surface of the semiconductor layer (substrate surface side) having the smallest implantation damage in the semiconductor layer is a starting point for crystallinity recovery. Therefore, by making the source / drain region into which the impurity is implanted at a high concentration, the thickness of the defect in the source / drain region can be increased by reducing the thickness of the source / drain region compared to the conventional case, and gettering characteristics are improved as compared with the conventional case. An excellent region can be formed. This makes it difficult for metal elements and the like to remain in the channel region, so that a TFT with improved leakage failure can be obtained. “Metal element” refers to a substance that corresponds to a metal when the substance is divided into a metal and a non-metal. Specific examples of the generation of the leakage current include a leak between the source region and the drain region, a leak between the gate electrode and the semiconductor layer, and the like.

In the present specification, the “region having a thickness smaller than that of the channel region” refers to a region having a thickness difference that can provide the effects of the present invention. The effect of the present invention can be obtained satisfactorily by setting the film thickness to not more than%, more preferably not more than 70%. Generally, the larger the difference in film thickness, the greater the effect of gettering. In view of the effect of the present invention, the semiconductor layer in the present invention can be formed so that the entire source / drain region is substantially thinner than the channel region in terms of the gettering effect. Is preferred. In addition, both the source region and the drain region are preferably in the form of the present invention. Other conditions such as the ratio between the channel region and the source / drain regions may be those of a semiconductor layer that is normally used.

As long as such a component is formed as an essential component of the TFT of the present invention, it may or may not include other components, and is usually on the source region of the semiconductor layer. Are provided with a source electrode and a drain electrode on the drain region of the semiconductor layer. Further, a base coat layer or the like that prevents a metal element from entering the semiconductor layer may be provided between the semiconductor layer and the substrate.

In the semiconductor layer, a step is preferably provided at the boundary between the channel region and at least one of the source region and the drain region. Thus, by providing a clear step between the channel region and the source / drain regions, the gettering effect can be obtained more reliably. In addition, since a step is provided between the channel region and the source / drain region, a thin region can be maximized in the source / drain region. The angle of the step is not particularly limited, but a sufficient effect can be obtained at 60 to 120 °.

At least one of the source region and the drain region preferably has a thick region and a thin region in the region. That is, in the same region of the source region or the drain region, a relatively thick region and a thin region are formed. For example, when considering the thickness of the source region, It is not necessary to consider the thickness of the drain region.

If the film thickness of the semiconductor layer is made different in the source region or the drain region, the impurity implantation damage on the lower surface of the semiconductor layer becomes larger in the thin film region than in the thick film region in the region. The crystallinity is hardly recovered and the defect density after the crystallinity recovery is increased. Therefore, when gettering is performed, a region having a higher defect density and a smaller film thickness can be used as a region dedicated to gettering in the semiconductor layer. If the density of crystal defects in the source / drain region becomes too large, the resistance may increase due to this, which may affect the semiconductor characteristics. According to this embodiment, the source / drain region It is not necessary to cause excessive crystal defects in all of them, and the characteristics of the source / drain regions are not significantly changed. In addition, it is more preferable that both the source region and the drain region have such a form.

In this embodiment, since regions having different film thicknesses are formed in the source / drain regions, the crystal defect density can inevitably be varied in the regions by the normal impurity implantation process. The process is not complicated as a method for enhancing the ring effect.

In this embodiment, the “thick film region” and the “thin film region” need to have a film thickness difference that can achieve the effects of the present invention. The effect of this embodiment can be obtained satisfactorily by setting the thickness to 80% or less of the thickness of the thicker region. Generally, the larger the film thickness difference, the more the gettering effect. Can get big. Moreover, it is preferable that the area of these “thin regions” is one tenth or more of the “thick region”. Further, as the degree of crystal defects in these regions, the “thin region” preferably has a crystal defect density that is twice or more that of the “thick region”. Such relativity can be detected by an electron spin resonance (ESR) or the like.

The thin film region is preferably located at the end opposite to the channel region side. As a result, a dedicated gettering site is formed at an end portion away from the channel region, so that a region closer to the channel region among the source / drain regions can function as the source / drain region. . Specifically, by connecting the source / drain electrode to a region closer to the channel region of the source / drain region, it is not necessary to connect the source / drain electrode to a region whose resistance is increased by crystal defects. As a result, it is possible to obtain a TFT that has the same characteristics as the conventional one but can suppress the generation of leakage current by stronger gettering.

It is preferable that at least one of the source region and the drain region is provided with a step at a boundary between a thick region and a thin region in the region. Thus, by providing a clear step in the source / drain region, the gettering effect can be obtained more reliably. The angle of the step is not particularly limited, but a sufficient effect can be obtained at 60 to 120 °.

The semiconductor layer preferably has a trapezoidal cross-sectional shape. In this specification, the trapezoid means a trapezoid as a whole, and is not particularly limited as long as it has an upper base and a lower base and a line connecting the upper base and the lower base is a hypotenuse. That is, the upper base and the lower base are not necessarily parallel to each other, and some steps may be provided on the hypotenuse, and the angles of the steps may be different from each other. Furthermore, the hypotenuse may have a shape in which one side is vertically cut. In this way, the gettering effect can be obtained in a well-balanced manner by making the thickness of the source / drain region gradually thinner in the direction opposite to that of the channel region. Further, such a shape is a shape that can be easily patterned by light irradiation such as a photolithography method. Note that this embodiment can also be referred to as a shape in which the cross-sectional shape of the semiconductor layer tapers as it goes to the end of the semiconductor layer.

In this embodiment, the starting point of the trapezoidal hypotenuse may be any of the channel region, the source region, and the drain region, but the effect differs depending on the starting point. For example, when the starting point of the hypotenuse starts in the source region and / or drain region, regions having different film thicknesses are formed in the source / drain region. Crystal defects do not need to be generated, and the characteristics of the source / drain regions are not greatly changed.

Preferred forms of the trapezoid include (1) an angle formed by the hypotenuse and the base is 20 ° or less, and (2) a point projected on the base of the hypotenuse and a lower end of the hypotenuse. A form in which the distance to the point located at is at least twice as high as the height. By adopting such a form, gettering proceeds more effectively and the characteristics as the source / drain region are improved.

The semiconductor layer is preferably made of polysilicon. By being made of polysilicon, a semiconductor layer having excellent conductivity can be obtained. The present invention can be said to be particularly effective for a form in which polysilicon is formed in this way, because a metal element mixed during the TFT manufacturing process can be excluded from the channel region of the semiconductor layer by a later gettering process.

The semiconductor layer preferably contains a metal catalyst. For example, by including a metal catalyst in the silicon layer, a solid phase crystal growth method for performing CGS can be performed, and the characteristics of the silicon layer can be improved. Examples of the metal catalyst include nickel (Ni), iron (Fe), cobalt (Co), germanium (Ge), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir). ), Platinum (Pt), copper (Cu), gold (Au) and the like, and nickel (Ni) is particularly preferable. According to the embodiment of the present invention, the metal catalyst is contained in the semiconductor layer in this way because the metal catalyst can be moved from the channel region by a subsequent gettering step even when the metal catalyst is included. It can be said that it is particularly effective for the form.

The present invention is also a method for manufacturing a thin film transistor having a semiconductor layer in which a source region and a drain region are formed with a channel region interposed therebetween, and in the manufacturing method, at least one of the source region and the drain region is etched. It is also a method of manufacturing a thin film transistor including a thinning step and a step of performing gettering on the semiconductor layer.

Crystal defects can also be generated by performing an etching process. This is not simply because the film thickness is reduced, but is caused by etching damage. By performing an etching process on the source / drain regions of the semiconductor layer, the etched region has a higher density of crystal defects than the unetched region. Therefore, according to the manufacturing method of the present invention, the density of crystal defects is made different by ion implantation after thinning the source / drain regions, and also due to crystal defects caused by etching, compared to a channel region that is not etched. Since a crystal defect region can be formed, a stronger gettering site can be formed as compared with a case where only the thickness of the source / drain region is reduced. The type of etching is not limited and may be either dry etching or wet etching, but dry etching is more preferable from the viewpoint of patterning accuracy. The region to be etched is not particularly limited as long as it is within the source / drain region, and may be the entire source / drain region or a part of the source / drain region. A method for etching a part of the source / drain region will be described in detail below.

In this specification, “gettering” refers to a technique for diffusing a metal catalyst or the like existing in a semiconductor layer to the defect site by using a crystal defect generated in the semiconductor layer in the TFT as a trap, and heating the semiconductor layer. The method is not particularly limited, and examples of the gettering method include a thermal annealing method such as a furnace annealing method and a lamp annealing method. Since the impurity activation step is also performed by thermal annealing or the like, according to the manufacturing method of the present invention, the gettering step and the impurity activation step may be performed at a time. According to the manufacturing method of the present invention, by performing gettering, a metal element or the like in the channel region can be effectively moved out of the channel region, and the thin film transistor thus obtained has an off-leakage current. This suppresses leakage defects such as generation and gate insulating film breakdown voltage defects.

The thinning process is preferably a process in which selective etching is performed in at least a part of at least one of the source region and the drain region. By selectively etching a part of the source / drain region, a “thick film region” and a “thin film region” can be formed in the source region or the drain region. Within this, regions having different crystal defect densities can be formed. According to this embodiment, when gettering is performed, a region having a higher defect density and a smaller film thickness can be used as a region dedicated to gettering in the semiconductor layer. If the density of crystal defects in the source / drain region becomes too large, the resistance may increase due to this, which may affect the semiconductor characteristics. According to this embodiment, the source / drain region It is not necessary to cause excessive crystal defects in all of them, and the characteristics of the source / drain regions are not significantly changed. Note that the selective etching is more preferably performed on both the source region and the drain region.

Examples of the selective etching method include a method of selectively exposing a resist using a mask to select an etching region, and more specifically, exposing, developing and stripping the resist, Examples of the method include a method of performing a plurality of times by changing, a method of using a halftone mask at the time of exposure, and the like.

The selective etching is preferably performed using a halftone mask. As a method of performing selective etching, there is a method of performing selective exposure to a resist using a mask to select an etching region and performing an etching process. At this time, by using a halftone mask, In the exposure, development, and peeling processes, it is possible to vary the film thickness of the etched region. This also makes it possible to easily pattern the shape of the semiconductor layer into a shape that gradually decreases in thickness toward the opposite side of the channel region, such as a trapezoid, and to perform subsequent gettering in a balanced manner. Is possible. In this specification, the “halftone mask” refers to a mask having a portion where the light transmittance is smaller than the light transmitting portion of the mask and the light transmittance is larger than the light shielding portion of the mask. Such a mask can be manufactured by providing a fine opening pattern or making the film thickness thinner than the light shielding region. In addition, the degree of angle of the formed silicon step and the hypotenuse can be adjusted by adjusting the light transmittance with the halftone mask.

The manufacturing method preferably includes a step of implanting impurities into the source region and the drain region after the thinning step. In this specification, “impurities” refer to elements such as phosphorus (P), boron (B), and arsenic (As) that are doped for adjusting semiconductor characteristics. It is possible to cause crystal defects in the semiconductor layer also by the impurity implantation step, and the crystallinity recovery of the crystal defects formed by the impurity implantation is less likely to occur as the semiconductor layer is thinner. By performing the impurity implantation step after the regions having different film thicknesses are selectively etched, the density of crystal defects in the semiconductor layer can be varied from region to region. In addition, a combination of crystal defects caused by selective etching and crystal defects caused by impurity implantation increases the defect difference between the thinned region and the non-thinned region. A gettering site is formed.

Such an impurity implantation step is particularly suitable when a method of selectively etching at least one part of the source region and the drain region is used, and is selectively etched in this manner in the source / drain region. A region having a high crystal defect density can be formed in a part of the source / drain region only by performing a normal impurity implantation step after regions having different thicknesses are formed. Therefore, according to the manufacturing method of this embodiment, a stronger gettering site can be formed in a part of the source / drain region without particularly increasing the number of manufacturing steps.

The thinning step is preferably a step of thinning the end opposite to the channel region side. As a result, a dedicated gettering site is formed at an end portion away from the channel region, so that a region closer to the channel region among the source / drain regions can function as the source / drain region. . Specifically, by connecting the source / drain electrode to a region closer to the channel region of the source / drain region, it is not necessary to connect the source / drain electrode to a region whose resistance is increased by crystal defects. As a result, it is possible to obtain a TFT that has the same characteristics as the conventional one but can suppress the generation of leakage current by stronger gettering.

The manufacturing method preferably includes a polysilicon crystallization step of the semiconductor layer. The polysilicon crystallization process is a method of crystallizing amorphous silicon into polysilicon by melting and cooling by laser irradiation or the like, and a semiconductor layer having excellent conductivity can be obtained. The present invention can be said to be particularly effective for the method of forming polysilicon in this way, because the metal element mixed during the TFT manufacturing process can be excluded from the channel region of the semiconductor layer by a later gettering process.

The manufacturing method preferably includes a step of adding a metal catalyst to the semiconductor layer. According to the method of the present invention, for example, even when a metal catalyst is added for CGS treatment of silicon, the metal catalyst can be moved from the channel region by a subsequent gettering step. In particular, it can be said to be particularly effective for a method of incorporating a metal catalyst into the semiconductor layer.

The present invention is also an electronic device including the thin film transistor or the thin film transistor manufactured by the manufacturing method. Since the electronic device of the present invention includes the thin film transistor or the thin film transistor manufactured by the manufacturing method, an electronic device in which leakage defects such as generation of off-leak current and defective breakdown voltage of the gate insulating film are suppressed is obtained. Examples of the electronic device include a liquid crystal display device, an organic electroluminescence display device, a car navigation system, a mobile phone, a personal computer, and an electronic dictionary.

According to the TFT of the present invention, since the region thinner than the channel region is formed outside the channel region, many crystal defects are generated in the region thinner than the channel region. This can be used as a gettering site, thereby obtaining a good gettering effect.

Embodiments will be described below, and the present invention will be described in more detail with reference to the drawings. However, the present invention is not limited only to these embodiments.

(Embodiment 1)
FIG. 1 is a schematic sectional view of a TFT according to the first embodiment. As shown in FIG. 1, the TFT according to the first embodiment has a configuration in which a silicon layer (semiconductor layer) 12, a gate insulating film 13, and a gate electrode 14 are stacked in this order on a substrate 11. As the substrate 11, a glass substrate, a flexible substrate such as plastic, or the like can be used. The silicon layer 12 can be made of amorphous silicon, polysilicon, or the like, but is preferably polysilicon from the viewpoint of conductivity. More preferably, it is continuous grain boundary silicon (CGS), and since the arrangement of atoms between the silicon crystal particles (grain boundaries) is continuous, the mobility is particularly excellent and the temperature is relatively low. Can be formed. Of the silicon layer 12, the channel region 12a has a lower impurity concentration than the source / drain region 12b. The impurity contained in the silicon layer 12 is generally phosphorus (P) or boron (B). Further, the silicon layer 12 contains a large amount of the catalyst element (Ni) used for performing CGS.

In the first embodiment, the silicon layer 12 has a step at the boundary between the channel region 12a and the source / drain region 12b, and the film thickness is thinner in the source / drain region 12b than in the channel region 12a. In the first embodiment, the source / drain region 12b is set to have a smaller film thickness than the conventional one, and therefore includes more crystal defects than the conventional source / drain region. Therefore, according to the TFT of Embodiment 1, the gettering effect of removing the catalytic element from the channel region 12a can be obtained satisfactorily.

Note that the density of silicon crystal defects can be detected by an electron spin resonance apparatus (ESR), and the channel region 12a is preferably at least twice as large as the source / drain region 12b.

FIG. 2 is a schematic plan view of the TFT according to the first embodiment. As shown in FIG. 2, the silicon layer 12 formed on the substrate 11 in the TFT of Embodiment 1 has a channel region 12a located under the gate electrode 14 and a source / drain region 12b other than the region under the gate electrode 14. It is located in the shape of a rectangle as a whole.

The principle that the TFT of the present invention can obtain the gettering effect will be described below with reference to the drawings. 3A and 3B are schematic cross-sectional views of a silicon layer showing a distribution of generation of crystal defects due to impurity implantation. FIG. 3A shows a conventional configuration, and FIG. 3B shows a first embodiment. FIG. 5 is a schematic cross-sectional view of a silicon layer showing the distribution of generation of crystal defects by etching.

As shown in FIG. 3B, the thickness of the silicon layer 12 is made thinner in the source / drain region 12b located in a region other than the region under the gate electrode 14 than in the channel region 12a located in the region under the gate electrode 14. In this case, the density of crystal defects in the source / drain regions 12b caused by the subsequent impurity implantation through the gate insulating film 13 (arrows in the figure) is as shown in FIG. The thickness of the layer 2 is the same for the channel region 2 a located in the region under the gate electrode 4 and the source / drain region 2 b located in the region other than under the gate electrode 4, and impurity implantation is performed through the gate insulating film 3. Will be larger than if done. The curve shown by the broken line in FIG. 3 is a projection of the curve of FIG. 4 described later. 3 indicates crystal defects formed in the semiconductor layer 2. In FIG. After the impurity implantation, an activation process such as thermal annealing is performed in order to bond the impurity and silicon. At this time, generally, crystal recovery occurs from the point where the crystallinity is not broken most. . According to the TFT of Embodiment 1, since many impurities are present at the lower end (substrate side) of the silicon layer 12 in the source / drain region b, the crystal recovery rate by the activation process is lowered, and crystal defects Many remain.

FIG. 4 is a graph showing the relationship between the depth of impurity implantation and the concentration of implanted impurities. As shown in FIG. 4, as the depth of the impurity implantation becomes deeper, the impurity concentration suddenly increases once, and after the peak point (Rp value) is exceeded, the impurity concentration gradually decreases. Therefore, the impurity concentration reaching the lower part (substrate side) of the silicon layer can be changed by changing the film thicknesses of the gate insulating film and the silicon layer.

As shown in FIG. 5, as a method of forming the silicon layer 12 to be thinner in the source / drain region 12b than in the channel region 12a, a resist 15 is provided on the region where the channel region 12a is to be formed. There is a method of performing etching in the direction. By reducing the thickness of the source / drain region 12b, the density of crystal defects becomes larger than when the film thickness is the same as that of the channel region 12a. As shown by x in FIG. 5, many crystal defects are formed in the source / drain region 12b by the action of etching. Thus, even if there is no difference in the film thickness of the silicon layer, crystal defects can be created by exposure to plasma or chemicals as in etching, so the effect of reducing the film thickness of the source / drain region 12b. In addition, more crystal defects can be generated in the source / drain regions 12b of the silicon layer 12 by the effect of etching, and the gettering ability can be improved. As indicated by a mark x in FIG. 5, many crystal defects of the silicon layer 12 due to etching are formed in the upper part of the silicon layer 12 (gate insulating film side), and as the silicon layer 12 goes to the lower part (substrate side), the crystal defect Will be less.

Thus, by forming the film thickness of the source / drain region 12b of the silicon layer 12 to be thinner than that of the channel region 12a by etching, the source / drain region 12b can be a good gettering site, and subsequent gettering is performed. Through the process, the catalyst element and the like can be effectively removed from the channel region 12a, and the impurity can be activated simultaneously.

FIG. 6 is a schematic cross-sectional view showing the positional relationship of metal elements in the semiconductor layer after ion implantation into the source / drain regions and after thermal activation / gettering in the first embodiment. (A) shows after ion implantation, and (b) shows after thermal activation and gettering. As shown in FIG. 6A, in the first embodiment, a gate insulating film 13 and a gate electrode 14 are stacked on the semiconductor layer 12, and the channel region 12a and source / drain regions of the semiconductor layer 12 are formed. A step is provided at the boundary with 12b. In FIG. 6A, the difference in density in the source / drain region 12b indicates the difference in the degree of crystal defects, and the darker the color, the more defects. That is, when impurities are implanted into the semiconductor layer 12 of the first embodiment, the crystal defect density increases in order from the bottom surface (substrate surface) side. At this time, it is assumed that the metal element 10 exists uniformly in the semiconductor layer 12.

When the thermal activation / gettering process is performed on such a semiconductor layer 12, the metal element 10 existing in the channel region 12a is favorably moved to the source / drain region (gettering site) 12b. As shown in FIG. 6B, the metal element is less likely to stay in the channel region 12a in the semiconductor layer 12 after the thermal activation / gettering process, and the leakage defect is improved.

FIG. 7 is a graph showing the relationship between the magnitude of the sheet resistance in the source / drain regions and the film thickness of the silicon layer. Note that the sheet resistance in FIG. 7 is the resistance in the source / drain region after injecting phosphorus (P), which is actually an impurity, into the source / drain region and performing an activation process such as thermal annealing. Value (Ω / □). As shown in FIG. 7, as the thickness of the silicon layer is reduced, the density of crystal defects in the silicon layer tends to increase, so the sheet resistance also increases.

FIG. 8 is a graph showing the relationship between the defect rate due to insufficient gettering of the TFT such as a leak defect and the film thickness of the silicon layer. As shown in FIG. 8, as the film thickness of the silicon layer decreases and the number of crystal defects after activation increases, the number of gettering sites increases, so the defect rate due to insufficient gettering decreases.

Below, the manufacturing method of TFT of Embodiment 1 is explained in full detail. FIGS. 9-1 to 9-10 and FIGS. 10-1 to 10-4 are schematic views showing a manufacturing flow of the TFT of the first embodiment. Each drawing is a schematic cross-sectional view at each manufacturing stage of the TFT. is there.

First, a silicon layer is formed on the substrate 11. In the first embodiment, after forming the silicon layer 12 made of amorphous silicon, the silicon layer 12 is subjected to a low temperature poly silicon (LPS) process including a solid phase crystal growth method for forming a CGS, and continuously. A silicon layer 12 made of grain boundary polysilicon is formed.

Specifically, first, as shown in FIG. 9A, silicon made of amorphous silicon on a substrate 11 by a CVD (Chemical Vapor Deposition) method, a plasma CVD method, a low pressure CVD method, an atmospheric pressure CVD method, a remote CVD method, or the like. The layer 12 is formed over the entire surface with a thickness of 50 nm.

Next, as shown in FIG. 9-2, nickel (Ni) as a catalytic element is added to the silicon layer 12 from the direction of the arrow in the figure, and the substrate 11 and the silicon layer 12 are about 600 in a nitrogen atmosphere in a furnace. Heat treatment is performed at about 0 ° C. for about 1 hour to cause solid phase crystal growth. Next, the silicon layer 12 grown by solid-phase crystal is irradiated with a laser beam to be melted and recrystallized to form a silicon layer 12 made of continuous grain boundary polysilicon. Examples of the laser light include a XeCl excimer laser. As for crystallization of amorphous silicon, only solid phase crystal growth may be performed and laser light irradiation may not be performed.

Next, as shown in FIG. 9-3, a resist 15a is formed on the silicon layer 12, and a light shielding portion is provided in a region where the silicon layer of the first embodiment is patterned, and an opening is provided in other regions. A mask 16a is arranged, exposure and development are performed from the direction of the arrow in the drawing, dry etching using carbon tetrafluoride (CF ₄ ) is further performed, the resist 15a is removed, and the silicon layer 12 is formed into an island shape. To pattern.

Next, as shown in FIG. 9-4, a resist 15b is formed on the silicon layer 12, and a mask 16b having a light-shielding portion in a region for forming a channel region and an opening in another region is disposed. Then, exposure and development are performed from the direction of the arrow in the figure, and further dry etching using carbon tetrafluoride (CF ₄ ) is performed to remove the resist 15b, and the film thickness as shown in FIG. 9-5 is obtained. A silicon layer 12 having a part of the thin region is formed. In this step, it is necessary to adjust conditions such as etching time so that the thin region is not completely etched away.

As an exposure method, in addition to the method described above, a method using a halftone mask may be used. In this case, as shown in FIG. 10A, first, a resist 15c is formed on the silicon layer 12 formed on the substrate 11, and then a light shielding portion is provided on a region where the channel region 12a is formed. A halftone mask 16c having a halftone portion in the region where the source / drain region 12b is formed and having an opening in the other region is disposed, and exposure and development are performed from the direction of the arrow in the figure. Then, dry etching using carbon tetrafluoride (CF ₄ ) is performed.

At this time, as one method of dry etching, as shown in FIG. 10-2, there is a method of performing collective etching and removing the regions where the resist 15c and the source / drain regions 12b of the silicon layer 12 are formed. Then, the remaining resist 15d is peeled off to obtain the shape of the silicon layer 12 as shown in FIG. 9-5.

As another method of dry etching at this time, as shown in FIG. 10-3, the island-shaped silicon layer 12 is once formed, and then the resist 15e is receded by ashing or the like. As shown in the figure, after forming the resist 15f in which the resist thin film portion has disappeared, etching for forming a step is further performed, and the remaining resist 15f is peeled off to obtain the shape of the silicon layer 12 as shown in FIG. 9-5. A method is mentioned.

According to the etching process of the present embodiment as described above, a part of the silicon layer can be thinned and a crystal defect can be generated in the region, and the crystal defect can function as a gettering site. become.

Next, as shown in FIG. 9-6, the gate insulating film 13 is formed on the substrate 11 and the silicon layer 12 by CVD, plasma CVD, low pressure CVD, atmospheric pressure CVD, remote CVD, or the like. Formed at 100 nm. As a material of the gate insulating film 13, for example, silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), silicon oxynitride (SiNO), or the like can be used. The gate insulating film 13 may be a laminated film of these.

Next, as shown in FIG. 9-7, after depositing a metal film with a film thickness of 400 nm on the gate insulating film 13 using a sputtering method, a CVD method or the like, patterning is performed by a photolithography method or the like. A gate electrode 14 is formed. As a material of the gate electrode 14, titanium (Ti), niobium (Nb), molybdenum (Mo), tantalum (Ta), tungsten (W), nitrides thereof, or the like can be used. The gate electrode 14 may be a laminated film of these.

Next, as shown in FIG. 9-8, in order to inject impurities into the silicon layer 12, boron (B) is used for P-channel TFTs, phosphorus (P) is used for N-channel TFTs, and arrows in the figure. Ion doping from the direction. At this time, the impurities are not implanted under the gate electrode 14 in a self-aligned manner, the silicon layer 12 located under the gate electrode 14 becomes the channel region 12a, and the silicon layer 12 located in other regions becomes the source / drain. It becomes area | region 12b. There are more crystal defects formed by such impurity implantation in the source / drain region 12b than in the prior art.

Next, as shown in FIG. 9-9, in order to perform gettering of the catalytic element (Ni), thermal annealing is performed on the whole as shown by the downward arrow in the figure. Examples of the thermal annealing include a method of performing a heat treatment at 550 to 720 ° C. for 5 minutes to 4 hours in a nitrogen atmosphere. As a result, the catalyst element diffuses, and the catalyst element (Ni) moves to the gettering site formed in the source / drain region 12b. According to the first embodiment, since the catalytic element (Ni) can be removed from the channel region 12a more effectively than in the past, a TFT with a low occurrence rate of leakage failure can be obtained.

Moreover, according to such a thermal annealing process, the effect of activating the bonding of silicon and impurities can be achieved simultaneously with the effect of gettering. According to the first embodiment, excessive progress of crystal destruction of the silicon layer 12 does not occur, and a sufficient activation effect is obtained.

In addition, examples of the gettering method include a lamp annealing method and a laser annealing method.

Finally, as shown in FIG. 9-10, an interlayer insulating film 17 is formed on the gate insulating film 13 and the gate electrode 14, and the interlayer insulating film 17 is a region overlapping with the source / drain regions 12b of the silicon layer. A contact hole is provided in the contact hole, and the source / drain electrode 18 is formed in the contact hole, whereby the TFT of the first embodiment is completed.

The TFT manufactured in this way is provided in an electronic device such as a liquid crystal display device, an organic electroluminescence display device, a car navigation system, a mobile phone, a personal computer, and an electronic dictionary.

(Embodiment 2)
The second embodiment is different from the first embodiment in that the amorphous silicon is converted to polysilicon without performing the CGS processing, but other than that is the same as the first embodiment. The first embodiment is mainly for gettering the catalytic element (Ni) used in the CGS process, but it is a case where the catalytic element (Ni) is not added to the silicon layer as in the second embodiment. However, various metal elements exist in the silicon layer, for example, metal elements such as sodium (Na) move from the glass substrate. It is preferable that the channel region does not contain such a metal element as much as possible. According to the gettering of the present invention, such a metal element can be removed.

Hereinafter, a method for performing the polysilicon processing of amorphous silicon without performing the CGS processing will be described in detail.

First, a silicon layer made of amorphous silicon is formed on one surface on a substrate by a CVD (Chemical Vapor Deposition) method, a plasma CVD method, a low pressure CVD method, an atmospheric pressure CVD method, a remote CVD method or the like.

Next, the silicon layer made of amorphous silicon is irradiated with a laser beam to be melted and recrystallized to form a silicon layer made of polysilicon. Examples of the laser light include an excimer laser and a solid laser. At this time, a sequential lateral solidification (SLS) method may be used in which amorphous silicon is melted and solidified by laser light repeatedly to grow a crystal in the lateral direction (vertical direction of the beam length).

Then, thermal annealing is performed on the entire substrate in order to perform gettering of the metal element. Examples of the thermal annealing include a method of performing a heat treatment at 550 to 720 ° C. for 5 minutes to 4 hours in a nitrogen atmosphere. As a result, the catalyst element diffuses and the metal element moves to the gettering site formed in the source / drain region.

Also according to the second embodiment, a large number of gettering sites are formed in the source / drain regions, so that the metal element can be effectively removed from the channel region, and a TFT in which leakage failure and reliability failure are unlikely to occur can be obtained. It will be.

(Embodiment 3)
FIG. 11 is a schematic sectional view of a TFT according to the third embodiment. In the TFT of the third embodiment, in the source / drain region 32b of the silicon layer 32, a thick region 32c is formed in a region on the channel region 32a side, and a thin region 32d is formed in a region not on the channel region 32a side. Is formed. In the third embodiment, the channel region 32a and the thick region 32c in the source / drain region 32b have the same thickness, and in the thin region 32d in the source / drain region 32b, the channel region 32a The thickness is smaller than the thicker region 32c in the region 32a and the source / drain region 32b.

That is, the TFT of Embodiment 3 has a configuration in which a silicon layer (semiconductor layer) 32, a gate insulating film 33, and a gate electrode 34 are stacked in this order on a substrate 31, as shown in FIG. A step is provided at the boundary between the thick region 32c in the drain region 32b and the thin region 32d in the source / drain region 32b. In addition, the thin region 32d is located at the opposite end of the channel region 32a. According to such a form, crystal defects are formed most in the source / drain thin film region 32d, so that the gettering site is mainly the source / drain thin film region 32d, and the entire source / drain region 32b is formed. Therefore, it is not necessary to form many crystal defects, and the characteristics of the source / drain region 32b are hardly affected. The TFT of the third embodiment is the same as the TFT of the first embodiment except for the shape of the silicon layer.

FIG. 12 is a schematic plan view of the TFT according to the third embodiment. As shown in FIG. 12, the silicon layer 32 formed on the substrate 31 in the TFT of Embodiment 3 has a channel region 32a located under the gate electrode 34 and a source / drain region 32b other than the region under the gate electrode 34. Located in. In the source / drain constituting the source / drain region 32b, the thicker region 32c and the thinner region 32d in the source / drain are wider in the thinned region 32d. The layer 32 as a whole is H-shaped. In FIG. 12, the source / drain thin film region 32d has a square shape as a whole, but is not particularly limited, and may be, for example, a circle, an ellipse, or another polygon.

FIG. 13 is a schematic cross-sectional view of a silicon layer showing a distribution of generation of crystal defects due to impurity implantation in the TFT of the third embodiment. As shown in FIG. 13, when the thick region 32 c and the thin region 32 d are formed in the source / drain region 32 b of the silicon layer 32, the subsequent step is performed through the gate insulating film 33. By the impurity implantation step (arrows in the figure), regions having different crystal defects are formed in the source / drain regions 32b as indicated by x in FIG. This is because by reducing the film thickness of the source / drain region 32b, many impurities can reach the lower part (substrate side) of the silicon layer 32, and the density of crystal defects in the source / drain region 32b. Becomes larger in the thin region 32d. In addition, the curve shown with the broken line in FIG. 13 projects the above-mentioned curve of FIG. After the impurity implantation, an activation process such as thermal annealing is performed in order to bond the impurity and silicon. At this time, generally, crystal recovery occurs from the point where the crystallinity is not broken most. . According to the TFT of the third embodiment, the thin region 32d in the source / drain region 32b has a large amount of impurities at the lower end (substrate side) of the silicon layer 32. The recovery rate decreases, and many crystal defects remain.

FIG. 14 is a schematic cross-sectional view showing the positional relationship of metal elements in the semiconductor layer after ion implantation into the source / drain regions and after thermal activation / gettering in the third embodiment. (A) shows after ion implantation, and (b) shows after thermal activation. As shown in FIG. 14A, in the third embodiment, a gate insulating film 33 and a gate electrode 34 are stacked on a semiconductor layer 32, and a channel region 32a and source / drain regions 32b of the semiconductor layer are formed. A step is provided at the boundary. In this case, crystal defects formed by impurity implantation increase in order from the bottom surface (substrate surface) side. The difference in density in the source / drain region 32b of the semiconductor layer 32 indicates a difference in the degree of crystal defects, and the darker the number, the more defects. At this time, it is assumed that the metal element 10 exists uniformly in the semiconductor layer 32.

When the thermal activation / gettering process is performed on such a semiconductor layer 32, the metal element 10 existing in the channel region 32a is good as shown in FIG. Therefore, the metal element is less likely to stay in the channel region 32a after the thermal activation / gettering process, and the leakage defect is improved.

Further, by dividing the source / drain region 32b into the source / drain thick film region 32c and the source / drain thin film region 32d as in the third embodiment, a crystal defect is caused in the silicon layer 32. 32d, the gettering site is mainly the source / drain thin film region 32d. If too many crystal defects are formed in the source / drain region 32b, there is a possibility that the resistance will increase too much and the on-current will not be generated. In this way, the gettering site is formed in the source / drain region 32b. By not using the whole, it is not necessary to form excessive crystal defects in all of the source / drain regions 32b, and the characteristics of the source / drain regions 32b are hardly affected.

Specifically, a contact hole is provided in the gate insulating film 33 on the thick region 32c, and the thick region 32c of the semiconductor layer 32 is connected to the source / drain electrode, thereby causing the presence of crystal defects. Thus, a TFT which is not easily affected by the increase in resistance due to the above can be obtained.

The TFT manufacturing method of the third embodiment is the same as the manufacturing method of the first embodiment except that the arrangement of the openings of the mask is different. Specifically, it can be formed by the following method. FIGS. 15A to 15C are schematic diagrams illustrating a manufacturing flow of the TFT according to the third embodiment in which the silicon layer 32 is formed to be the thinnest in the thin film region 32d in the source / drain region. Each drawing is a schematic cross-sectional view of each stage of manufacturing a TFT. 15-1 to 15-3 correspond to FIGS. 9-1 to 9-4 of the first embodiment.

First, as shown in FIG. 15A, the silicon layer 32 is formed on the entire surface of the substrate 31 by the same method as in the first embodiment.

Next, as shown in FIG. 15B, a resist 35a is formed on the silicon layer 32, a mask 36a having a light-shielding portion is disposed in a region where the silicon layer of the third embodiment is disposed, and the direction of the arrow in the drawing. Then, exposure and development are performed, and further dry etching using carbon tetrafluoride (CF ₄ ) is performed, the resist 35 a is peeled off, and the silicon layer 32 is patterned into an island shape.

Next, as shown in FIG. 15C, a resist 35b is formed on the silicon layer 32, a light shielding portion is provided in a region where a thick region is formed in the channel region and the source / drain, and the others. In this region, a mask 36b having an opening is disposed, exposure and development are performed from the direction of the arrow in the drawing, and dry etching using carbon tetrafluoride (CF ₄ ) is further performed to remove the resist 35b. Thus, a thin region is formed in the source / drain region. In this step, it is necessary to adjust conditions such as etching time so that the thin region is not completely etched away.

By such a selective etching step, the silicon layer 32 of the third embodiment having a thick region and a thin region in the source / drain region 32b can be formed.

Note that the silicon layer 32 of the third embodiment may be a normal polysilicon as in the second embodiment, and in that case, the metal element can be effectively removed from the channel region 32a, resulting in leakage failure and reliability failure. A difficult TFT can be obtained.

(Embodiment 4)
FIG. 16 is a schematic cross-sectional view of a TFT according to the fourth embodiment. As shown in FIG. 16, the silicon layer 42 included in the TFT of the fourth embodiment is formed with a film thickness thinner in the source / drain region 42b than in the channel region 42a, and in the source / drain region 42b. Is similar to the third embodiment in that it includes different regions. However, unlike the third embodiment, the silicon layer 42 of the fourth embodiment has a shape in which the film thickness gradually decreases from the boundary between the channel region 42a and the source / drain region 42b toward the side opposite to the channel region. . That is, a silicon layer (semiconductor layer) 42, a gate insulating film 43, and a gate electrode 44 are stacked in this order on a substrate 41, and a silicon layer 42 including a channel region 42a, a source region 42b, and a drain region 42b. It can also be said that the cross-sectional shape of is a trapezoid as a whole. In addition, the trapezoid that is the shape of the silicon layer 42 of the fourth embodiment has an angle formed by the hypotenuse and the base of 20 °, and a point projected on the base of the hypotenuse and a lower end of the hypotenuse. The distance (500 nm) from the position is at least twice the height (50 nm).

The TFT of the fourth embodiment is the same as the TFT of the third embodiment except for the shape of the silicon layer. In the present embodiment, the planar shape is shown by a schematic plan view similar to FIG. Even in such a form, the crystal defects are thinner in the source / drain region 42b than in the channel region 42a, so that the gettering site is mainly the source / drain region 42b, particularly near the bottom of the oblique side. Thus, the gettering effect is improved. In addition, since the source / drain regions 42b include regions having different film thicknesses, it is not necessary to form many crystal defects in the source / drain regions 42b, and the characteristics of the source / drain regions 42b are improved.

Below, the manufacturing method of TFT of Embodiment 4 is explained in full detail. The TFT manufacturing method according to the fourth embodiment is different from the TFT manufacturing method according to the first embodiment except that the means for forming the silicon layer 42 thinner than the channel region 42a in the source / drain region 42b is different. It is the same. FIGS. 17A and 17B are schematic diagrams illustrating a manufacturing flow in which the film thickness of the silicon layer 42 of the TFT of this embodiment is formed thinner in the source / drain region 42b than in the channel region 42a. These are the cross-sectional schematic diagrams of each manufacturing stage of TFT. 17-1 and 17-2 correspond to FIGS. 9-1 to 9-4 of the first embodiment.

First, as shown in FIG. 17A, the silicon layer 42 is formed on the entire surface of the substrate 41 by the same method as in the third embodiment.

Next, as shown in FIG. 17-2, a resist 45 is formed on the silicon layer 42, a light-shielding portion is formed on the region where the channel region 42a is formed, and a halftone is formed on the region where the source / drain region 42b is formed. And a halftone mask 46 having openings in other regions, exposure and development from the direction of the arrow in the figure, and dry using carbon tetrafluoride (CF ₄ ) Etching is performed.

As a result, the silicon layer 42 has a slope whose thickness gradually decreases from the channel region 42a toward the source / drain region 42b, and the film thickness becomes thinner in the source / drain region 42b than in the channel region 42a. In addition, a thick region and a thin region are formed in the source / drain region 42b. In Embodiment 4, a fine opening pattern is provided in the halftone portion of the halftone mask.

According to such an etching process, the source / drain region 42b having a thickness smaller than that of the channel region 42a is formed more easily than in the first embodiment, and regions having different thicknesses are formed in the source / drain region 42b. Can be formed.

Note that the silicon layer 42 of the present embodiment may be a normal polysilicon as in the second embodiment, and in that case, the metal element can be effectively removed from the channel region 42a, resulting in leakage failure and reliability failure. A difficult TFT can be obtained.

(Embodiment 5)
FIG. 18 is a schematic cross-sectional view of a TFT according to the fifth embodiment. As shown in FIG. 18, the TFT of the fifth embodiment is similar to the second embodiment. Of the source / drain regions 52b in the silicon layer 52, the thicker region 52c in the source / drain region 52b is formed on the channel region 52a side. And a thin region 52d in the source / drain region 52b is formed at the end opposite to the channel region 52a. The TFT of Embodiment 5 has the same configuration as that of Embodiment 1 except for the shape of the silicon layer. That is, a silicon layer (semiconductor layer) 52, a gate insulating film 53, and a gate electrode 54 are stacked on the substrate 51 in this order. The silicon layer 52 includes a channel region 52a, a thick region 52c in the source / drain region 52b, and a thin region 52d in the source / drain region 52b. The thickness is thin. A step is provided at each boundary between the channel region 52a, the thick region 52c in the source / drain region 52b, and the thin region 52d in the source / drain region 52b.

The manufacturing method of Embodiment 5 is the same as that of Embodiment 1 except that the arrangement of the openings of the mask is changed. That is, the mask opening is shifted each time a thick region 52c is formed in the source / drain region 52b of the silicon layer 52 and a thin region is formed in the source / drain region 52b. 5 TFT silicon layers 52 can be formed.

Specifically, it can be formed by the following method. 19-1 to 19-4 show the thickness of the silicon layer 52 of the TFT of the fifth embodiment in the channel region 52a, the source / drain region 52b, the thicker region 52c, and the source / drain region 52b. It is a schematic diagram which shows the manufacturing flow formed thinly in order of the area | region 52d with a thin film thickness, and each figure is a cross-sectional schematic diagram of each manufacturing step of TFT. 19-1 to 19-4 correspond to FIGS. 15-1 to 15-3 of the third embodiment.

First, as shown in FIG. 19A, the silicon layer 52 is formed on the entire surface of the substrate 51 by the same method as in the first embodiment.

Next, as shown in FIG. 19-2, a resist 55a is formed on the silicon layer 52, and a mask 56a having a light-shielding portion in the region where the silicon layer 52 is disposed and having an opening in the other region. Then, exposure and development are performed from the direction of the arrow in the figure, and further dry etching using carbon tetrafluoride (CF ₄ ) is performed, the resist 55a is removed, and the silicon layer 52 is patterned into an island shape. To do.

Next, as shown in FIG. 19-3, a resist 55b is formed on the silicon layer 52, and a light shielding portion is provided in a region where a thick region 52c is formed in the channel region 52a and the source / drain region 52b. In addition, a mask 56b having an opening is disposed in another region, exposure and development are performed from the direction of the arrow in the figure, and dry etching using carbon tetrafluoride (CF ₄ ) is further performed. 55b is peeled off to form a thin region 52d in the source / drain region 52b. In this step, it is necessary to adjust conditions such as etching time so that the thin region 52d in the source / drain region 52b is not completely etched away.

Next, as shown in FIG. 19-4, a resist 55c is formed on the silicon layer 52, and a mask 56c having a light-shielding portion in a region where the channel region 52a is formed and having an opening in the other region. Then, exposure and development are performed from the direction of the arrow in the figure, and further dry etching using carbon tetrafluoride (CF ₄ ) is performed, the resist 55c is peeled off, and the channel region 52a and the source / drain thickness A film region 52c is formed. In this step, the thick region 52c in the source / drain region 52b is not completely etched away, and the film thickness in the source / drain region 52b is smaller than that of the thin region 52d. It is necessary to adjust the conditions such as the etching time so that the thickness becomes thicker.

Note that the silicon layer 52 of the fifth embodiment may be a normal polysilicon as in the second embodiment, and in that case, the metal element can be effectively removed from the channel region 52a, resulting in a leak failure or a reliability failure. A difficult TFT can be obtained.

By such a selective etching process, the silicon layer 52 of the fifth embodiment having the thick region 52c and the thin region 52d in the source / drain region 52b can be formed.

(Embodiment 6)
FIG. 20 is a schematic cross-sectional view of a TFT according to the sixth embodiment. In the TFT of the sixth embodiment, as in the second embodiment, a thick region 62c in the source / drain region 62b is formed on the channel region 62a side of the source / drain region 62b in the silicon layer 62, and the channel region 62a is formed. A region 62d having a small film thickness is formed in the source / drain region 62b at the opposite end, and the channel region 62a and the region 62c having a large film thickness in the source / drain region 62b have the same film thickness. It is. However, in the sixth embodiment, the boundary between the thick film region 62c in the source / drain region 62b and the thin film region 62d in the source / drain region 62b is not a step but gradually thins. Formed on the slope.

That is, the TFT of Embodiment 6 has a configuration in which a silicon layer (semiconductor layer) 62, a gate insulating film 63, and a gate electrode 64 are laminated in this order on a substrate 61 as shown in FIG. It can also be said that the cross-sectional shape of 62 is a trapezoid as a whole. In the sixth embodiment, the planar shape is shown by a schematic plan view similar to FIG. Even in such a form, crystal defects are formed most frequently in the thin region 62d in the source / drain region 62b, so that gettering sites are mainly in the source / drain region 62b. As a result, the region 62d becomes thinner, and it is not necessary to form many crystal defects in the source / drain region 62b, and the characteristics of the source / drain region 62b are improved.

The manufacturing method of the sixth embodiment is the same as that of the second embodiment except that a halftone mask is used as a mask. Specifically, it can be formed by the following method. FIG. 21A and FIG. 21B are schematic diagrams illustrating a manufacturing flow for forming a thick region and a thin region in the source / drain region of the TFT according to the sixth embodiment. These are the cross-sectional schematic diagrams of each manufacturing stage of TFT. 21A and 21B correspond to FIGS. 15A to 15C of the second embodiment.

First, as shown in FIG. 21A, the silicon layer 62 is formed on the entire surface of the substrate 61 by the same method as in the first embodiment.

Next, as shown in FIG. 21B, a resist 65 is formed on the silicon layer 62, and the thick region 62c is formed in the channel region 62a and the source / drain region 62b of the silicon layer 62. A mask 66 having a light-shielding portion, having a halftone portion in a region where the thin region 62d is formed in the source / drain region 62b of the silicon layer 62, and having an opening in the other region is disposed. Then, exposure and development are performed from the direction of the arrow in the figure, and dry etching using carbon tetrafluoride (CF ₄ ) is performed.

As a result, the silicon layer 62 has a slope that gradually decreases in thickness from the thicker region 62c in the source / drain region 62b toward the thinner region 62d in the source / drain region 62b. Become. In the sixth embodiment, a fine opening pattern is provided in the halftone portion of the halftone mask.

By such a selective etching process, the silicon layer 62 of the fifth embodiment having the thick region 62c and the thin region 62d in the source / drain region 62b can be more easily formed.

Note that the silicon layer 62 of the sixth embodiment may be a normal polysilicon as in the second embodiment, in which case the metal element can be effectively removed from the channel region 62a, resulting in a leak failure or a reliability failure. A difficult TFT can be obtained.

The other shapes of the source / drain regions of the semiconductor layer included in the TFT of the present invention will be listed below with reference to FIGS. 22 to 25 show only one half of the source / drain region.

(Embodiment 7)
FIG. 22 shows the shape of a semiconductor layer included in the TFT of Embodiment 7. The TFT of Embodiment 7 has the same configuration as the TFT of Embodiment 1 except for the shape of the semiconductor layer. The semiconductor layer 72 shown in FIG. 22 has a thick region 72c and a thin region 72d in the source / drain region 72b, and a thick region 72c and a thin region 72d. There is a step between them. In the present embodiment, the step is constituted by an inclined surface having an angle of about 45 °. In addition, a thin region 72d is formed at the end opposite to the channel region, and an inclined surface having an angle of about 45 ° is also formed at the end of the thin region 72d. The semiconductor layer of this embodiment can also be said to be a structure in which two trapezoids are stacked, and has a trapezoid as a whole. It should be noted that the level difference of the silicon formed in this way and the angle of the hypotenuse can be easily adjusted by adjusting the light transmittance with a halftone mask.

(Embodiment 8)
FIG. 23 shows the shape of the semiconductor layer included in the TFT of the eighth embodiment. The TFT of the eighth embodiment has the same configuration as the TFT of the first embodiment except for the shape of the semiconductor layer. The semiconductor layer 82 shown in FIG. 23 has a thick region 82c and a thin region 82d in the source / drain region 82b, and a thin region 82d at the end opposite to the channel region. Is formed. Further, the thin region 82d has a slope whose thickness gradually decreases, and the angle of the slope is further increased at the end opposite to the channel region. The semiconductor layer 82 of this embodiment can also be said to be a structure in which two trapezoids are stacked, and has a trapezoid as a whole. It should be noted that the level difference of the silicon formed in this way and the angle of the hypotenuse can be easily adjusted by adjusting the light transmittance with a halftone mask.

(Embodiment 9)
FIG. 24 shows the shape of the semiconductor layer included in the TFT of the ninth embodiment. The TFT of Embodiment 9 has the same configuration as the TFT of Embodiment 1 except for the shape of the semiconductor layer. The semiconductor layer 92 shown in FIG. 24 has a slope that gradually decreases in thickness as the source / drain region 92b moves away from the channel region. Further, at the end opposite to the channel region, the angle of the slope is further increased. Is getting bigger. The source / drain region 92b has a thick region and a thin region. The semiconductor layer 92 of this embodiment can also be said to be a structure in which a trapezoid and a triangle are stacked, and has a trapezoid as a whole. It should be noted that the level difference of the silicon formed in this way and the angle of the hypotenuse can be easily adjusted by adjusting the light transmittance with a halftone mask.

(Embodiment 10)
FIG. 25 shows the shape of the semiconductor layer included in the TFT of the tenth embodiment. The TFT of Embodiment 10 has the same configuration as the TFT of Embodiment 1 except for the shape of the semiconductor layer. The semiconductor layer 102 shown in FIG. 25 has a thick region 102c and a thin region 102d in the source / drain region 102b. The thick region 102c and the thin region 102d A vertical step is provided between the two. Further, the thin region 102d has a slope whose thickness gradually decreases. The semiconductor layer of this embodiment can also be said to be a structure in which a trapezoid and a quadrangle are stacked, and has a trapezoid as a whole. It should be noted that the level difference of the silicon formed in this way and the angle of the hypotenuse can be easily adjusted by adjusting the light transmittance with a halftone mask.

2 is a schematic cross-sectional view of a TFT according to Embodiment 1. FIG. 2 is a schematic plan view of the TFT of Embodiment 1. FIG. It is a cross-sectional schematic diagram of the silicon layer showing the distribution of the occurrence of crystal defects due to the implantation of impurities, (a) shows the conventional form, (b) shows the first embodiment. It is a graph which shows the relationship between the depth of impurity implantation, and the concentration of the implanted impurity. It is a cross-sectional schematic diagram of a silicon layer showing the distribution of occurrence of crystal defects due to etching. 3 is a schematic cross-sectional view showing the positional relationship of metal elements in a semiconductor layer after ion implantation into the source / drain regions and after thermal activation / gettering in Embodiment 1. FIG. It is a graph which shows the relationship between the magnitude | size of the sheet resistance in a source / drain area | region, and the film thickness of a silicon layer. It is a graph which shows the relationship between the defect rate resulting from the gettering lack of TFT, and the film thickness of a silicon layer. It is a schematic diagram which shows the manufacture flow of TFT of Embodiment 1, and shows the step which formed the silicon layer which consists of amorphous silicon on the whole surface. It is a schematic diagram which shows the manufacturing flow of TFT of Embodiment 1, and shows the step which performed the injection | pouring of the catalyst element. It is a schematic diagram which shows the manufacture flow of TFT of Embodiment 1, and shows the step which forms a silicon layer in island shape. It is a schematic diagram which shows the manufacturing flow of TFT of Embodiment 1, and shows the step which forms the level | step difference of a silicon layer. It is a schematic diagram which shows the manufacturing flow of TFT of Embodiment 1, and shows the step which formed the silicon layer. It is a schematic diagram which shows the manufacturing flow of TFT of Embodiment 1, and shows the step which formed the gate insulating film. It is a schematic diagram which shows the manufacturing flow of TFT of Embodiment 1, and shows the step which formed the gate electrode. FIG. 6 is a schematic diagram showing a manufacturing flow of the TFT of Embodiment 1, and shows a stage where impurities are implanted. It is a schematic diagram which shows the manufacturing flow of TFT of Embodiment 1, and shows the step which performed the thermal annealing process. It is a schematic diagram which shows the manufacture flow of TFT of Embodiment 1, and shows the step which performed the source electrode and the drain electrode. It is a schematic diagram which shows the manufacture flow of TFT of Embodiment 1, and shows the step which performed exposure and image development using a halftone mask. It is a schematic diagram which shows the manufacturing flow of TFT of Embodiment 1, and shows the step which performed the batch etching and formed the silicon layer. It is a schematic diagram which shows the manufacturing flow of TFT of Embodiment 1, and is a case where a silicon layer is formed by performing stepwise etching, and shows the step of forming a silicon layer in an island shape. It is a schematic diagram which shows the manufacture flow of TFT of Embodiment 1, and is the case where a silicon layer is formed by performing stepwise etching, and shows the step of forming a step in the silicon layer. 6 is a schematic cross-sectional view of a TFT according to Embodiment 3. FIG. 6 is a schematic plan view of a TFT according to Embodiment 3. FIG. FIG. 6 is a schematic cross-sectional view of a silicon layer showing a distribution of generation of crystal defects due to impurity implantation in the TFT of Embodiment 3. 12 is a schematic cross-sectional view showing the positional relationship of metal elements in a semiconductor layer after ion implantation into the source / drain regions and after thermal activation / gettering in Embodiment 3. FIG. (A) shows after ion implantation, and (b) shows after thermal activation. It is a schematic diagram which shows the manufacturing flow of TFT of Embodiment 3, and shows the step in which the silicon layer was formed in the whole surface. It is a schematic diagram which shows the manufacture flow of TFT of Embodiment 3, and shows the step which forms a silicon layer in island shape. It is a schematic diagram which shows the manufacturing flow of TFT of Embodiment 3, and shows the step which forms the level | step difference of a silicon layer. 6 is a schematic cross-sectional view of a TFT according to Embodiment 4. FIG. It is a schematic diagram which shows the manufacturing flow of TFT of Embodiment 4, and shows the step which formed the silicon layer on the whole surface. It is a schematic diagram which shows the manufacturing flow of TFT of Embodiment 4, and shows the step which patterns a silicon layer. 6 is a schematic cross-sectional view of a TFT according to Embodiment 5. FIG. It is a schematic diagram which shows the manufacture flow of TFT of Embodiment 5, and shows the step which formed the silicon layer on the whole surface. It is a schematic diagram which shows the manufacturing flow of TFT of Embodiment 5, and shows the step which forms a silicon layer in island shape. FIG. 10 is a schematic diagram showing a manufacturing flow of the TFT of Embodiment 5, and shows a step of forming a step (lower side) of the silicon layer. FIG. 10 is a schematic diagram showing a manufacturing flow of the TFT of Embodiment 5 and shows a step of forming a step (upper side) of the silicon layer. 7 is a schematic cross-sectional view of a TFT of Embodiment 6. FIG. It is a schematic diagram which shows the manufacturing flow of TFT of Embodiment 6, and shows the step which formed the silicon layer on the whole surface. It is a schematic diagram which shows the manufacturing flow of TFT of Embodiment 6, and shows the step which performs the patterning of a silicon layer. The shape of the semiconductor layer which TFT of Embodiment 7 has is shown. The shape of the semiconductor layer which TFT of Embodiment 8 has is shown. The shape of the semiconductor layer which the TFT of Embodiment 9 has is shown. The shape of the semiconductor layer which TFT of Embodiment 10 has is shown. It is a cross-sectional schematic diagram which shows the positional relationship of the metal element in a semiconductor layer after ion implantation with respect to the source / drain region in a normal method, and after a thermal activation and gettering process. (A) shows after ion implantation, and (b) shows after thermal activation / gettering step.

Explanation of symbols

11, 31, 41, 51, 61: Substrate 2, 12, 32, 42, 52, 62, 72, 82, 92, 102: Semiconductor layers 2a, 12a, 32a, 42a, 52a, 62a: Channel regions 2b, 12b 32b, 42b, 52b, 62b, 72b, 82b, 92b, 102b: Source / drain regions 32c, 52c, 62c, 72c, 82c, 102c: Thick regions 32d, 52d, 62d in the source / drain, 72d, 82d, 102d: Thin regions 3, 13, 33, 43, 53, 63 in the source / drain: Gate insulating films 4, 14, 34, 44, 54, 64: Gate electrodes 15, 15a, 15b, 15c, 15d, 15e, 15f, 35a, 35b, 35c, 45, 55a, 55b, 65: resists 16a, 16b, 16c, 36a 36b, 46,56a, 56b, 66: Mask 17: interlayer insulating film 18: source / drain electrodes

Claims (18)

A thin film transistor having a semiconductor layer in which a source region and a drain region are formed across a channel region,
A thin film transistor, wherein at least one of the source region and the drain region has a region thinner than a channel region. 2. The thin film transistor according to claim 1, wherein the semiconductor layer is provided with a step at a boundary between a channel region and at least one of a source region and a drain region. 3. The thin film transistor according to claim 1, wherein at least one of the source region and the drain region has a thick region and a thin region in the region. 4. The thin film transistor according to claim 3, wherein the thin region is located at the end opposite to the channel region side. 5. The step according to claim 3, wherein at least one of the source region and the drain region is provided with a step at a boundary between the thick region and the thin region in the region. Thin film transistor. The thin film transistor according to claim 1, wherein the semiconductor layer has a trapezoidal cross-sectional shape. The thin film transistor according to claim 6, wherein the trapezoid has an angle formed between a hypotenuse and a base of 20 ° or less. 8. The trapezoid according to claim 6 or 7, wherein a distance between a point projected on the upper end of the hypotenuse on the base and a point located on the lower end of the hypotenuse is at least twice the height. Thin film transistor. The thin film transistor according to claim 1, wherein the semiconductor layer contains a metal catalyst. The thin film transistor according to claim 1, wherein the semiconductor layer is made of polysilicon. A method of manufacturing a thin film transistor having a semiconductor layer in which a source region and a drain region are formed across a channel region,
The manufacturing method includes a thinning step in which etching is performed in at least one of a source region and a drain region, and a step of performing gettering on a semiconductor layer. 12. The method of manufacturing a thin film transistor according to claim 11, wherein the thinning step is a step in which selective etching is performed in at least a part of at least one of a source region and a drain region. 13. The method of manufacturing a thin film transistor according to claim 11, wherein a halftone mask is used for the selective etching. The method of manufacturing a thin film transistor according to claim 11, wherein the manufacturing method includes a step of implanting impurities into the source region and the drain region after the thinning step. 15. The method of manufacturing a thin film transistor according to claim 12, wherein the thinning step is a step of thinning an end opposite to the channel region side. The method for manufacturing a thin film transistor according to claim 11, wherein the manufacturing method includes a polysilicon crystallization step of a semiconductor layer. The method of manufacturing a thin film transistor according to claim 11, wherein the manufacturing method includes a step of adding a metal catalyst to the semiconductor layer. An electronic device comprising the thin film transistor according to claim 1 or the thin film transistor manufactured by the method for manufacturing a thin film transistor according to any one of claims 11 to 17.

Images