JP2009058685A - Panel display device and panel abnormality detection method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a panel display device that can detect causes of failure in the panel when display failure occurs. <P>SOLUTION: Timing comparison between, a vertical drive signal and a horizontal drive signal inputted to a gate driver 22 and a source driver 23 of a display panel 20 from a controller 10, and, a vertical output signal and a horizontal output signal outputted from the final stage of a shift register included in the gate driver 22 and the source driver 23, is carried out in a detection signal generating circuit 12 and a checking circuit 13. When the compared signals are not synchronized, abnormality in the display panel is detected. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a display defect detection method for a panel display device.

  In recent years, panel display devices such as liquid crystal display devices, organic EL (Electro Luminescence) display devices, and plasma display devices have been used not only as monitors for televisions and personal computers but also as display units for various electronic devices.

  Such a panel display device provides display data and various control signals from a controller unit to a display panel including a display unit in which a plurality of pixels are arranged in a matrix and a drive driver arranged around the display unit. The display operation is performed by supplying.

  In the panel display device, various inspections are performed in the manufacturing stage. For example, Patent Document 1 discloses a method of measuring a current and a voltage of a signal of a TFT (Thin Film Transistor) group on a display panel and inspecting a scan line and a signal line for disconnection or short circuit. However, in the panel display device, there are places where vibrations occur and places where the temperature is high / low depending on the display environment, and contact failures due to vibrations and malfunctions due to temperatures may occur.

Even in a device in a product state, a function has been proposed in which malfunction is detected by detecting the operation abnormality and performing processing when the abnormality is detected. For example, Patent Document 2 discloses a method of inspecting the timing of a synchronization signal input from a controller unit to a drive driver of a display panel, and preventing a display failure caused by an abnormality in the timing of the synchronization signal.
JP 10-97203 A (publication date: April 14, 1998) JP-A-5-119747 (Publication date: May 18, 1993)

  However, the panel display device disclosed in Patent Document 2 detects an abnormality in a synchronization signal input to a simple matrix type liquid crystal panel, and when the abnormality is detected, display is not performed by writing to the panel. Is to avoid. That is, Patent Document 2 inspects the timing of the synchronization signal when it is output from the controller unit, and cannot detect an abnormality on the panel side.

  However, in the panel display device, display defects that occur due to use environments such as vibration and temperature often occur not on the controller unit but on the panel side. For this reason, when a display failure occurs in a device in a product state, a device that can detect the cause of the failure on the panel side is required.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to realize a panel display device capable of detecting that there is a failure cause on the panel side when a display failure occurs in a device in a product state. There is.

  In order to solve the above problems, a panel display device according to the present invention is a panel display device including a display panel and a controller unit that supplies display data and display control signals to the display panel. The display control signal includes a timing signal shifted by the shift register, and further includes a timing signal output from the controller unit, and a display panel. The present invention is characterized in that a detection unit for detecting an abnormality of the display panel is provided by performing timing comparison with a timing signal output from the last stage of the shift register.

  According to the above configuration, the timing between the timing signal (for example, the vertical synchronization signal and the horizontal synchronization signal) output from the controller unit by the detection unit and the timing signal output from the last stage of the shift register of the display panel. A comparison is made. In this comparison, when a timing shift has occurred, it can be identified that an abnormality has occurred on the panel side. Here, the occurrence of an abnormality on the panel side includes not only a malfunction of the shift operation in the shift register on the display panel side but also a malfunction in inputting a timing signal to the shift register on the display panel side.

  In the panel display device according to the present invention, the detection unit is the same as the timing signal output from the last stage of the shift register when the shift operation is normally performed in the shift register on the display panel side. A detection signal generation unit that generates a detection signal that generates a pulse at timing, a detection signal generated by the detection signal generation unit, and a timing signal output from the last stage of the shift register of the display panel; It is possible to adopt a configuration having a comparison unit that performs the synchronous comparison of the above.

  According to the above configuration, when performing timing comparison with the timing signal output from the final stage of the shift register of the display panel, the detection signal generation unit is the same as the timing signal output from the final stage of the shift register. Since a detection signal that generates a pulse at the timing is generated, and the detection signal and a timing signal output from the final stage of the shift register of the display panel are synchronously compared, the timing comparison can be easily performed. .

  As described above, the panel display device according to the present invention includes a display panel and a controller unit that supplies display data and display control signals to the display panel. The display panel includes a shift register. The display control signal includes a timing signal shifted by the shift register, and further includes a timing signal output from the controller unit and a display panel shift register. The detection unit detects the abnormality of the display panel by comparing the timing with the timing signal output from the last stage.

  Therefore, an abnormality occurs on the panel side by comparing the timing signal output from the controller unit (for example, vertical synchronization signal or horizontal synchronization signal) with the timing signal output from the last stage of the shift register of the display panel. There is an effect that it is possible to identify the occurrence of the.

  An embodiment of the present invention will be described below with reference to FIGS. In the following description, the case where the present invention is applied to a liquid crystal display device will be exemplified, but the present invention is not limited to this, and a shift register such as an organic EL display device or a plasma display device is provided. The present invention can also be applied to other panel display devices having a drive driver.

  First, a schematic configuration of the liquid crystal display device according to the present embodiment will be described with reference to FIG. A liquid crystal display device 1 shown in FIG. 1 includes a controller unit 10 and a display panel 20. The controller unit 10 includes a timing signal generation circuit 11, a detection signal generation circuit 12, and a check circuit 13. The display panel 20 includes an LCD display unit 21, a gate driver 22, and a source driver 23.

  The timing signal generation circuit 11 outputs a synchronization signal or a clock signal as a control signal to the gate driver 22 and the source driver 23. The gate driver 22 receives a vertical synchronization signal, a start pulse signal, and a gate clock signal (hereinafter collectively referred to as a vertical drive signal) from the timing signal generation circuit 11. The source driver 23 also receives a horizontal synchronization signal and a source clock signal (hereinafter collectively referred to as a horizontal drive signal) from the timing signal generation circuit 11. Display data is also input to the source driver 23 from the controller unit 10, but this is not shown.

  In the display panel 20, the LCD display unit 21 is driven as follows. First, an example of the configuration and operation of the source driver 23 will be described with reference to FIGS. As shown in FIG. 2, the source driver 23 includes a shift register 231, a sampling circuit 232, an input buffer 233, a latch circuit 234, a level shifter 235, a D / A converter 236, and an output buffer 237.

As shown in FIG. 3, the shift register 231 is configured by connecting a plurality of flip-flops in multiple stages, and at the beginning of one horizontal period, a horizontal synchronization signal (timing signal) is input to the first flip-flop. The A source clock signal is input to each stage flip-flop. As shown in FIG. 4, each stage flip-flop in the shift register 231 performs a shift operation in accordance with an input of a clock signal. That is, the output of the flip-flop at each stage becomes an input to the flip-flop at the next stage in the shift operation, and is output to the sampling circuit 232 as sampling signals C _{1 to} C _{n at} the corresponding stage.

The sampling circuit 232 samples and captures display data supplied via the input buffer 233 based on the sampling signals C _{1 to} C _n input from the shift register 231 so as to correspond to each signal line.

Display data captured by the sampling circuit 232 is latched by the latch circuit 234, boosted by the level shifter 235, and D / A converted by the D / A converter 236. Then, D / A converted display data, via the output buffer 237 is output to the signal line _S 1 to S _n of the LCD display unit 21.

  As for the gate driver 22, a start pulse signal (timing signal) is input to the first stage of the shift register constituting the gate driver 22 at the beginning of one frame (one vertical period). A gate clock signal is input to each stage of the shift register. As a result, the shift register shifts the start pulse signal by one stage every time the gate clock signal is input, and the shifted start pulse signal is output as a scanning signal to a remarkable scanning line. In other words, the gate driver 22 sequentially selects the scanning lines line by line in the on period.

  In the LCD display unit 21, display data is written to the pixels connected to the selected scanning line through the signal line every horizontal period. By sequentially performing this operation for all scanning lines within one frame, image writing for one screen is performed.

  In the driving operation of the LCD display unit 21 as described above, an accurate shift operation is naturally required in the shift registers of the gate driver 22 and the source driver 23. For example, if the synchronization signal or the clock signal is not supplied to the gate driver 22 or the source driver 23 due to poor contact when the controller unit 10 and the display panel 20 are connected by an FPC (Flexible Printed Circuit) or the like, the LCD The display data cannot be written to the display unit 21. In addition, when an operation failure occurs in the shift register of the gate driver 22 or the source driver 23 and a normal shift operation is not performed, display data is not written corresponding to an appropriate scanning line or signal line, and a remarkable image is displayed. Causes deterioration.

  Therefore, the liquid crystal display device according to the present embodiment is characterized in that the timing of the signal output from the controller unit 10 and the signal output from the last stage of the shift register of the driver on the display panel 20 side are compared. Yes. As a result, when a display failure occurs due to factors on the panel side, such as a contact failure between the controller unit 10 and the display panel 20 or a shift register operation failure, this can be detected.

  The above detection operation is executed by the detection signal generation circuit 12 and the check circuit 13 in the controller unit 10.

  The detection signal generation circuit 12 receives the vertical drive signal and the horizontal drive signal output from the timing signal generation circuit 11 in the same manner as the gate driver 22 and the source driver 23. The detection signal generation circuit 12 generates a vertical detection signal and a horizontal detection signal, and outputs the vertical detection signal and the horizontal detection signal to the check circuit 13. The vertical detection signal and the horizontal detection signal are generated so that a pulse is generated at the same timing as the signal output from the last stage of the shift register when the shift operation is normally performed in the shift register of the panel driver. Signal.

  In the detection signal generation circuit 12, the vertical detection signal and the horizontal detection signal can be generated, for example, by the following method. That is, the detection signal generation circuit 12 includes a counter and pulse generation means. The counter counts the clock according to the input of the vertical synchronization signal and the horizontal synchronization signal. When the counter counts the predetermined number of clocks, that is, the same number of clocks as the shift operation in the shift register of the panel side driver, the pulse generating means generates pulses in the vertical detection signal and the horizontal detection signal. Note that the vertical detection signal and the horizontal detection signal are generated by independent processing.

  In addition to the vertical detection signal and horizontal detection signal, the check circuit 13 receives a vertical output signal and a horizontal output signal from the gate driver 22 and the source driver 23 on the panel side. The vertical output signal and the horizontal output signal are signals output from the final stage in the shift register of the panel side driver.

The horizontal output signal output from the final stage of the source driver may be the sampling signal C _n for the final signal line. However, there are several dummy terminals since C _n which is not used in the actual liquid crystal driver signal terminals. It is also possible to return the horizontal output signal using the terminal (for example, the sampling signal C _{n + 1} may be used as the horizontal output signal).

  The check circuit 13 determines whether or not the input vertical detection signal and the vertical output signal are synchronized, and if the synchronization is established, it is determined that the gate driver 22 is performing a normal shift operation. Similarly, it is determined whether the input horizontal detection signal and the horizontal output signal are synchronized. If the synchronization is established, it is determined that the source driver 23 is performing a normal shift operation. For example, in the case of a 320 × 240 QVGA size panel, the source driver 23 transmits data for one line in a cycle in which 320 × 3 (RGB) = 960 clocks are generated in the horizontal direction. That is, the check circuit 13 determines whether or not the signal output from the final stage of the source driver 23 is transmitted in 960 clock cycles.

  If the check circuit 13 detects that these signals are not synchronized, the check circuit 13 determines that an abnormality has occurred on the panel side, and a check indicating the determination result. Output a signal and notify the host. The host here refers to, for example, a control unit that performs main control of the entire liquid crystal display device. .

  When a panel abnormality is detected in the present invention, the detection result can be used for repair. For example, by storing the abnormality detection result in a memory and reading it out at the time of repair, it is possible to easily know whether the cause of the display failure is on the panel side or the controller side.

  Thus, in the liquid crystal display device according to the present embodiment, as shown in FIG. 5, the output signal (vertical drive signal or horizontal drive signal) from the controller unit 10 and the output signal output from the display panel 20 ( (Vertical output signal or horizontal output signal). Thereby, when these synchronization is not taken, it can be specified that an abnormality has occurred on the panel side. Here, the occurrence of an abnormality on the panel side includes not only a malfunction of the shift operation in the shift register of the panel side driver, but also a malfunction of inputting a vertical drive signal or a horizontal drive signal to the panel side driver.

1, showing an embodiment of the present invention, is a block diagram illustrating a main configuration of a liquid crystal display device. FIG. It is a block diagram which shows the principal part structure of the source driver in the said liquid crystal display device. It is a block diagram which shows the structure of the shift register in the said source driver. It is a timing chart which shows the operation timing of the said shift register. It is a figure explaining the panel abnormality detection method in the said liquid crystal display device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Controller part 11 Timing signal generation circuit 12 Detection signal generation circuit (detection part, detection signal generation part)
13 Check circuit (detection unit, comparison unit)
20 Display panel 21 LCD panel 22 Gate driver (drive driver)
23 Source driver (Driver driver)
231 Shift register

Claims (3)

In a panel display device comprising a display panel and a controller unit for supplying display data and display control signals to the display panel,
The display panel has a drive driver including a shift register,
The display control signal includes a timing signal shifted by the shift register,
Further, the present invention is characterized in that a detection unit for detecting an abnormality of the display panel is provided by performing a timing comparison between the timing signal output from the controller unit and the timing signal output from the final stage of the shift register of the display panel. Panel display device. The detector is
Detection signal that generates a detection signal that generates a pulse at the same timing as the timing signal output from the last stage of the shift register when the shift operation is normally performed in the shift register on the display panel side And a comparison unit that performs a synchronous comparison between the generation signal, the detection signal generated by the detection signal generation unit, and the timing signal output from the final stage of the shift register of the display panel, The panel display device according to claim 1. In a panel abnormality detection method for a panel display device comprising a display panel and a controller unit that supplies display data and display control signals to the display panel.
The display panel has a drive driver including a shift register,
The display control signal includes a timing signal shifted by the shift register,
If the timing signal output from the controller section is synchronized with the timing signal output from the last stage of the shift register of the display panel and the compared timing signal is not synchronized, the display panel malfunctions. A panel abnormality detection method for a panel display device, characterized by detecting

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