JP2009053948A - Semiconductor integrated circuit device and data transfer method using the same - Google Patents

Abstract

By performing a decompression process of compressed information with a DMA controller, a program and data replacement sequence can be simplified.
A semiconductor integrated circuit device includes a CPU, a first memory having compressed data, a second memory to which decompressed data of the compressed data is transferred, and decompressed compressed data to generate decompressed data. And a DMA controller 40 for transferring the decompressed data to the second memory without going through the CPU.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor integrated circuit device including a DMA (Direct Memory Access) controller having a decompression function and a data transfer method using the same.

  When a program or data placed in a placement memory such as a flash ROM or SDRAM is transferred to an execution memory to execute processing at a high speed, the data is transferred to the execution memory by a data transfer controller such as a DMA controller (DMAC). (For example, refer to Patent Document 1). In this case, since no program or data processing is performed on the arrangement memory, it is a wasteful use of memory resources to place the data as it is in the arrangement memory. For this reason, a program and data subjected to lossless compression may be arranged in the arrangement memory.

The conventional DMAC used for data transfer does not have a decompression function. For this reason, in the case of adopting a method of arranging compressed programs and compressed data in the arrangement memory, it is necessary to perform decompression processing by F / W (firmware), and the program and data replacement sequence is complicated. This increases the processing load. Further, when F / W replacement occurs during the program operation, it is necessary to minimize the time required for the replacement time. Further, since the F / W for decompression cannot be compressed, it leads to wasteful use of memory resources.
Japanese Patent Laid-Open No. 5-165761

  The present invention provides a semiconductor integrated circuit device and a data transfer method using the same, which can simplify a program and data replacement sequence by performing decompression processing of compressed information with a DMA controller.

  A semiconductor integrated circuit device according to a first aspect of the present invention includes a CPU, a first memory having compressed data, a second memory to which decompressed data of the compressed data is transferred, and decompressing the compressed data A decompression controller for generating the decompressed data, and a DMA controller for transferring the decompressed data to the second memory without passing through the CPU.

  A data transfer method according to a second aspect of the present invention includes a step of transferring target data from a first memory to a DMA controller, a step of determining whether the target data is compressed data, and the target data If the compressed data is the compressed data, the compressed data is decompressed by the DMA controller, the decompressed data is generated, the decompressed data is transferred to the second memory, and the decompressed data transfer is completed. And the DMA controller provides a completion interrupt to the CPU.

  According to the present invention, it is possible to provide a semiconductor integrated circuit device capable of simplifying a program and data replacement sequence by performing decompression processing of compressed information with a DMA controller, and a data transfer method using the same.

  Embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

[1] Configuration of Semiconductor Integrated Circuit Device FIG. 1 is a configuration diagram of a semiconductor integrated circuit device according to an embodiment of the present invention. The schematic configuration of a semiconductor integrated circuit device according to an embodiment of the present invention will be described below.

  As shown in FIG. 1, the semiconductor integrated circuit device 1 includes a CPU (Central Processing Unit) 10, an execution memory 20, a placement memory 30, and a DMA controller (DMAC) 40.

  The CPU 10 performs various arithmetic processes using, for example, a program held in the execution memory 20 and controls the operation of each block (for example, the DMA controller 40) in the semiconductor integrated circuit device 1.

  The execution memory 20 is composed of an internal memory or the like. The arrangement memory 30 is configured by a flash ROM, SDRAM or the like. In this arrangement memory 30, a reversibly compressed program and data are arranged. Programs and data in the placement memory 30 are transferred to the execution memory 20 via the DMA controller 40.

  The DMA controller 40 includes a controller unit 50 and a register unit 60. The controller unit 50 includes a decompression controller 51 and switches SW1 and SW2. The switch SW1 is connected to the a terminal side when not passing through the decompression controller 51, and is connected to the b terminal side when passing through the decompression controller 51. The switch SW2 is turned off when only the size after decompression is calculated and no transfer is performed, and is turned on when decompression transfer is performed. Control of the switches SW1 and SW2 is performed by the CPU 10. The register section 60 includes a destination size register 61, a source size register 62, a destination address register 63, a source address register 64, a control register 65, and an active register 66. In the destination size register 61 and the destination address register 63, the size and address of the transfer destination (after decompression) are set. The source size register 62 and the source address register 64 are set with the size and address of the transfer source. The control register 65 has a switch for selecting either “normal DMA” or “decompression DMA”, and a switch for selecting either “decompression size output” or “decompression transfer”. The active register 66 controls the process selected by the control register 65.

[2] Configuration of Decompression Controller FIG. 2 is a configuration diagram of the decompression controller according to an embodiment of the present invention. The schematic overall configuration of the decompression controller according to one embodiment of the present invention will be described below.

  As shown in FIG. 2, the decompression controller 51 includes a parser 52, an uncompressed block 53, a run length compressed block 54, a Huffman code compressed block 55, and switches SW3 and SW4.

  The parser 52 has a mode selection function. With this mode selection function, based on the current block data compression format (run-length compression / Huffman code compression / non-compression), the switches SW3 and SW4 switch the non-compression block 53, run-length compression block 54, and Huffman code compression block 55. Switch.

  When the uncompressed block 53 is selected, the uncompressed data is output from the decompression controller 51 as it is.

  When the run length compression block 54 is selected, the run length decoding device 56 is selected. The run-length decoding device 56 decompresses the run-length compressed data, and the decompressed data is output from the decompression controller 51.

  When the Huffman code compression block 55 is selected, the Huffman code decoding device 57 is selected. The Huffman code decoding device 57 decompresses the Huffman code-compressed data, and the decompressed data is output from the decompression controller 51.

  In this embodiment, two types of compression blocks, the run length compression block 54 and the Huffman code compression block 55, are provided, but blocks using other compression methods may be used.

[3] Compressed Data Format FIG. 3 shows a compressed data format according to an embodiment of the present invention. The data format handled by the DMA controller according to the embodiment of the present invention will be described below.

  The format 100 of the entire compressed data has a plurality of blocks N (N = 1, 2,...), And the total number of blocks 101 and the size 102 after decompression are shown. Each block is composed of, for example, any one of an uncompressed block format 70, a run-length compressed block format 80, and a Huffman code compressed block format 90.

  The uncompressed block format 70 includes a mode selection 71, a block size 72, and uncompressed data 73. Here, the mode selection 71 and the block size 72 constitute a block header.

  The run-length compressed block format 80 includes a mode selection 81, a block size 82, a repeat count 83, and repeat data 84. Here, the mode selection 81 and the block size 82 constitute a block header. The number of repeats 83 is the number of times the output is repeated. The repeat data 84 is data to be output.

  The Huffman code compression block format 90 includes a mode selection 91, a block size 92, a decoding table 93, and compressed data 94. Here, the mode selection 91 and the block size 92 constitute a block header. The decoding table 93 is arranged in order of the appearance frequency of the data pattern, and is set so that a Huffman code having a short code length is assigned to a pattern having a high appearance frequency. The assignment of the decoding table 93 is variable on the compressed block format side.

  Thus, in this embodiment, in order to implement decompression with a simple H / W (hardware) configuration, the data format is as shown in FIG. The fixed-length data such as 0x00 is repeated, and the run-length compression block format 80 is used for an area where run-length compression is effective, and the Huffman code compression block format 90 is used for an area where compression using Huffman code is effective. The area where the compression rate is deteriorated in either block 80 or 90 is not compressed, and becomes an uncompressed block format 70.

[4] Processing Flow of CPU FIG. 4 is a flowchart of processing on the CPU side according to an embodiment of the present invention. The processing flow on the host CPU side according to an embodiment of the present invention will be described below.

  First, the CPU 10 sets a transfer source address and a transfer destination address in the source address register 64 and the destination address register 63 (ST1-1). Then, it is determined whether or not the current data is compressed data (ST1-2).

  As a result, if the current data is not compressed data, the decompression switch SW2 is turned OFF (ST1-3). Then, the size of the transfer source and the size of the transfer destination are set in the source size register 62 and the destination size register 61 (ST1-4). Thereafter, “normal DMA” is selected by the control register 65 (ST1-5), and the active register 66 is set to ON (ST1-13). As a result, normal DMA is executed and data is transferred to the execution memory 20.

  On the other hand, if the current data is compressed data, it is determined whether it is necessary to know the size after decompression before transfer (ST1-6). When it is necessary to know the size after decompression, for example, because the F / W dynamically secures the transfer destination area, select “Decompression size output” and “Decompression DMA” in the control register 65 (ST1-7). Then, the active register 66 is set to ON (ST1-8). Thus, by outputting only the size after decompression to the destination size register 61 without outputting data, the user can know the size after decompression. When the decompressed size output is completed, the DMA controller 40 issues a completion interrupt to the CPU 10. Therefore, when a completion interrupt does not occur, a completion interrupt wait is performed (ST1-9, ST1-10), and when a completion interrupt occurs, the size after decompression is checked (ST1-11).

  Next, the F / W secures an area that needs to be secured as a transfer destination, the transfer destination register is set in the destination address register 63, and “decompression transfer” and “decompression DMA” are selected by the control register 65. (ST1-12). If it is not necessary to know the size after decompression, steps ST1-7 to ST1-11 described above are omitted, and the process continues to step ST1-12.

  Next, the active register 66 is set to ON (ST1-13). As a result, decompression and DMA transfer are executed, and the decompressed data is transferred to the execution memory 20. When this transfer is completed, the DMA controller 40 issues a completion interrupt to the CPU 10. Therefore, when a completion interrupt does not occur, a completion interrupt wait is performed (ST1-14, ST1-15), and when a completion interrupt occurs, the process ends.

[5] Processing Flow of Decompression Controller FIG. 5 is a flowchart of processing of the decompression controller according to an embodiment of the present invention. The processing flow of the decompression controller according to one embodiment of the present invention will be described below. This flow mainly corresponds to the step of executing the decompression process of steps ST1-12 and ST1-13 in FIG.

  First, processing for the decompression controller 51 includes output of the size after decompression and data decompression. Therefore, it is determined whether the output is a size after decompression (ST2-1). As a result, if the output is the size after decompression, “decompression size output” and “decompression DMA” are selected by the control register 65, and the active register 66 is set to ON. As a result, the decompressed size is output to the destination size register 61 (ST2-2). Thereafter, the active register 66 is turned OFF (ST2-26), and a completion interrupt is input to the CPU 10 (ST2-27). In this way, the processing flow for outputting the size after decompression of the decompression controller 40 ends.

  On the other hand, if the processing for the decompression controller 51 is data decompression, first, the total number of blocks 101 of the current data is fetched (ST2-3). Based on the total number of blocks 101, counting of the remaining number of blocks is started (ST2-4). Then, the parser 52 captures the mode selection for the block 1 (ST2-5), and determines which of the three modes, the uncompressed block 53, the run-length compressed block 54, and the Huffman code compressed block 55 (ST2). -6).

  When the uncompressed block 53 is selected, processing is performed as follows. First, the block size 72 is fetched (ST2-7), and counting of the remaining block size is started (ST2-8). Then, data transfer is performed (ST2-9). Thereafter, the transfer source address and the transfer destination address of the source address register 64 and the destination address register 63 are incremented (ST2-10), and the remaining block size 72 is decremented (ST2-11). These flows are repeated until there is no remaining block size 72.

  When the run-length compression block 54 is selected, processing is performed as follows. First, the block size 82 is fetched (ST2-12), and counting of the remaining block size is started (ST2-13). Then, repeat data is output (ST2-14). Thereafter, the transfer destination address of the destination address register 63 is incremented (ST2-15), and the remaining block size 82 is decremented (ST2-16). These flows are repeated until there is no remaining block size 82.

  When the Huffman code compression block 55 is selected, processing is performed as follows. First, the block size (number of input bits) 92 is fetched (ST2-17), and the value of the decoding table 93 is set in the decoding result register (ST2-18). Then, counting of the remaining block size (number of input bits) 92 is started (ST2-19). One bit is input to the Huffman code decoding apparatus 57 repeatedly until decoding is completed (ST2-20, ST2-21), and the decoding result is output (ST2-22). Thereafter, the transfer destination address of the destination address register 63 is incremented (ST2-23), and the remaining block size 92 is decremented (ST2-24). These flows are repeated until there is no remaining block size 92.

  In any of the three modes of the non-compressed block 53, the run-length compressed block 54, and the Huffman code compressed block 55, when the remaining block sizes 72, 82, and 92 disappear, the remaining block number 101 is decremented (ST2- 25) The mode of the next block is selected (ST2-5).

  When there is no remaining block number 101, the active register 66 is turned OFF (ST2-26), and a completion interrupt is input to the CPU 10 (ST2-27). In this way, the data decompression processing flow of the decompression controller 40 is completed.

[6] Compression / decompression In this embodiment, the decoding device of the decompression controller 51 uses a run-length method and a Huffman code method.

[6-1] Run length method (compression)
FIG. 6 is a diagram for explaining compression by the run-length method according to an embodiment of the present invention. Below, the outline about the data compression by a run length system is demonstrated.

  In the data compression method by run length, when a certain bit pattern continues, the data is compressed by converting into information of the repeated data pattern and the number of repetitions. At the time of decompression, the compressed data can be expanded by outputting the data pattern to be repeated as many times as the number of repetitions.

  For example, as shown in FIG. 6, in the program code, if there is an area where 0x00 is repeated 100 bytes, the repetition count can be compressed to 2 bytes by converting the repetition count to 100 and repeating data to 00. Therefore, when there is an area where a certain data pattern is repeated in the program code, compression by run length is effective.

(Thawing)
FIG. 7 is a diagram for explaining decompression by the run-length method according to an embodiment of the present invention. The data decompression by the run length method will be described below.

  As shown in FIG. 7, the run-length decoding device 56 includes an output counter 56a and output data 56b. The output counter 56a counts the number of repeats 83 of the run-length compressed block format 80. The output data 56b recognizes the repeat data 84 in the run-length compressed block format 80.

  For example, the repeat number 83 is 100, and the repeat data 84 is 0x00. In such a case, the run-length decoding device 56 recognizes the repeat number 83 of the compressed data by the output counter 56a and recognizes the repeat data 84 of the compressed data by the output data 56b. Then, output data is repeatedly output as many times as the number of repeats. That is, in this example, 0x00 is output 100 times. As a result, the run-length decoding device 56 decompresses the run-length compressed data.

[6-2] Huffman Code Method FIG. 8 is a diagram for explaining compression by the Huffman code method according to an embodiment of the present invention. Below, the outline about the data compression by a Huffman code system is demonstrated.

(compression)
The data compression method using the Huffman code calculates the number of appearances for each data pattern in the binary data of the program code, assigns a Huffman code with a short code length to the pattern with the highest appearance frequency, and assigns the code length to the pattern with a low appearance frequency. Data is compressed by assigning a long Huffman code.

  For example, as shown in FIG. 8, when compressing 33-bit “uncompress data”, when the appearance frequency for each 4 bits (0x0 to 0xF) is seen, the number of appearances of each pattern of binary data of the program code is 000 (Symbol A) is 6 times, 001 (Symbol B) is 3 times, 010 (Symbol C) is 1 time, 011 (Symbol D) is 0 times, and 100 (Symbol E) is 1 time. For this reason, a Huffman code having a short code length (1 bit) is assigned to the symbol A having the highest number of appearances, and a Huffman code having a long code length (4 bits) is assigned to the symbol D having the low number of appearances. As a result, “compress data” compressed to 19 bits is obtained.

(Thawing)
9 and 10 are views for explaining decompression by the Huffman tree circuit according to an embodiment of the present invention. The outline of data decompression by the Huffman code method will be described below.

  As shown in FIG. 9, in the data decompression by the Huffman tree circuit, “compress data” is serially input to the Huffman tree circuit bit by bit to decode the compressed data, and the original “uncompress data” is Obtainable.

  As shown in FIG. 10, the box is a decoding result register value, and the box indicates the Huffman code length. A decoded value having a high appearance frequency is set in a register having a short Huffman code length.

  For example, data in units of 4 bits is encoded with a Huffman code, and there is data that becomes a decoding result in a decoding table 93 (4 bits (0x0 to 0xF) each) 4 bits × 16 (8 bytes). The decoding tables 93 are arranged in descending order of appearance frequency, and the higher the appearance frequency, the shorter the Huffman code length is set in the decoding result register. The Huffman code decoding circuit 57 performs decoding of the Huffman code by outputting the 4 bits registered in the decode output register when the signal is distributed by the distribution circuit and reaches the output circuit according to the input code.

  Note that the Huffman tree used in this decoding apparatus is one example shown in FIGS. 9 and 10, and is not limited to this Huffman tree, and a Huffman tree suitable for the data pattern to be compressed may be adopted. Is possible.

[7] Effect According to the embodiment of the present invention, the DMA controller 40 includes the decompression controller 51. As a result, the DMA controller 40 can perform data transfer subjected to the decompression process. Accordingly, since it is not necessary to perform the decompression process on the F / W side as in the prior art, the program and data replacement sequence can be simplified.

  Further, since the DMA controller 40 includes the decompression controller 51, it is not necessary to incorporate the decompression F / W into the execution memory 20, the arrangement memory 30, and the like. For this reason, the capacity of the memory used as the decompression F / W in the execution memory 20 and the arrangement memory 30 can be reduced, and the memory resources can be effectively used.

  Further, data transfer is possible without using the CPU 10 by using the DMA controller 40. Therefore, if necessary, other processes can be operated in parallel on the CPU 10 side during execution of compression / decompression and data transfer, and CPU resources can be effectively utilized.

  Furthermore, this embodiment can be implemented with a simple H / W configuration, and high speed and low power consumption of the entire system using the DMA controller 40 can be expected.

  In addition, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be obtained as an invention.

1 is a configuration diagram of a semiconductor integrated circuit device according to an embodiment of the present invention. The block diagram of the decompression controller which concerns on one Embodiment of this invention. The figure which shows the format of the compressed data which concerns on one Embodiment of this invention. The flowchart of the process by the side of CPU which concerns on one Embodiment of this invention. The flowchart of the process of the decompression controller which concerns on one Embodiment of this invention. The figure for demonstrating the compression by the run length system which concerns on one Embodiment of this invention. The figure for demonstrating the decompression | decompression by the run length system which concerns on one Embodiment of this invention. The figure for demonstrating the compression by the Huffman code system which concerns on one Embodiment of this invention. The figure for demonstrating the decompression | decompression by the Huffman tree circuit which concerns on one Embodiment of this invention. The figure for demonstrating the decompression | decompression by the Huffman tree circuit which concerns on one Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit device, 10 ... CPU, 20 ... Execution memory, 30 ... Arrangement memory, 40 ... DMA controller, 50 ... Controller part, 51 ... Decompression controller, 52 ... Parser, 53 ... Uncompressed block, 54 ... Run length Compressed block, 55 ... Huffman code compressed block, 56 ... Run length decoding device, 56a ... Output counter, 56b ... Output data, 57 ... Huffman code decoding device, 60 ... Register unit, 61 ... Destination size register, 62 ... Source size register, 63 ... Destination address register, 64 ... Source address register, 65 ... Control register, 66 ... Active register, 70 ... Uncompressed block format, 71 ... Mode selection, 72 ... Block size, 73 ... No pressure Data: 80 ... Run length compression block format, 81 ... Mode selection, 82 ... Block size, 83 ... Number of repeats, 84 ... Repeat data, 90 ... Huffman code compression block format, 91 ... Mode selection, 92 ... Block size, 93 ... Decoding table, 94 ... compressed data, 100 ... format of the entire compressed data, 101 ... number of blocks, 102 ... size after decompression, SW1, SW2, SW3, SW4 ... switch.

Claims (5)

CPU,
A first memory having compressed data;
A second memory to which decompressed data of the compressed data is transferred;
A semiconductor integrated circuit comprising: a decompression controller that decompresses the compressed data to generate the decompressed data, and a DMA controller that transfers the decompressed data to the second memory without going through the CPU apparatus.   The semiconductor integrated circuit device according to claim 1, wherein the DMA controller further includes a register that outputs a size after decompression before transferring the decompressed data. The decompression controller has an uncompressed block, a compressed block, and a parser,
The semiconductor integrated circuit device according to claim 1, wherein the parser selects the uncompressed block or the compressed block for each block in the compressed data. Transferring target data from the first memory to the DMA controller;
Determining whether the target data is compressed data;
If the target data is the compressed data, decompressing the compressed data with the DMA controller to generate decompressed data;
Transferring the decompressed data to a second memory;
A data transfer method comprising: a step in which the DMA controller issues a completion interrupt to the CPU when the transfer of the decompressed data is completed.   5. The data transfer method according to claim 4, wherein when the target data is the compressed data, the decompressed data is generated after outputting the decompressed size to a register in the DMA controller.

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