JP2009049671A - Output-limiting circuit, class d power amplifier, sound apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an output limiting circuit which can simply realize upper/lower symmetrical soft clips with high accuracy by resistance ratio, using operational amplifier bias voltage as the standard. <P>SOLUTION: The output limiting circuit 60 is constituted, having a standard current creation unit (Rex1, BUF1, Q0, CM1, CM2) which converts constant voltage (bias voltage BIAS in Fig.2) into a current I by using the resister Rex1; an upper-side clip voltage creation unit (Rex2, BUF2), which converts the current I to voltage VH by using Rex2 by a bias voltage standard; a lower-side clip voltage generating unit (Rex3, BUF2) which converts the current I into voltage VL by using Rex3 by the bias voltage standard; and a gain adjustment unit (Q1, Q2), which adjusts the gain of the operational amplifier 13 so that the voltage level of an output signal AOUT will not exceed the upper-side limit level according to the voltage VH, and will not exceed the lower-side limit level according to the voltage VL. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an output limiting circuit that limits an output amplitude of an operational amplifier that amplifies an input signal and generates an output signal, and further relates to a class D power amplifier and an acoustic device using the same.

  Conventionally, a class D power amplifier that receives an analog signal (for example, an analog audio signal) is provided with a limiter circuit for limiting the output power.

  As conventional techniques related to the above, Patent Documents 1 and 2 can be cited.

  In Patent Document 1, in a limiter circuit that clips an input signal applied to an input terminal with a constant voltage by a control signal input from the outside, a control element connected between a power supply terminal and the input terminal; A limiter circuit comprising: a control circuit that always turns off the control element and controls the control element to be turned on when the input signal exceeds the constant voltage. Yes.

Patent Document 2 discloses a preamplifier that amplifies an input signal, a waveform shaping circuit that shapes the output signal of the preamplifier, and a power that amplifies the output of the waveform shaping circuit in a low-frequency amplifier for driving a subwoofer. There has been disclosed and proposed a low-frequency amplifier including an amplifier and a power supply voltage supply circuit that supplies a power supply voltage having an absolute value smaller than a power supply voltage supplied to the power amplifier to the preamplifier. .
JP 2006-5741 A Japanese Patent Laid-Open No. 10-335961

  Certainly, according to the above-described prior art, even when an excessive input signal is applied, it is possible to prevent an increase in distortion associated with output saturation and a breakage of the speaker.

  However, in the prior art of Patent Document 1, the waveform at the time of clipping is not a soft clip, and the output signal includes a lot of harmonic components, which may cause annoying abnormal noise in the speaker.

  Further, in the prior art of Patent Document 1, since the limit level of the output power reacts relatively sensitively to the variable control of the control voltage, it is not always easy to set the desired output power with high accuracy.

  In the prior art of Patent Document 1, since the upper and lower limit levels are set by using one control signal, adjustment of circuit constants is required in order to realize a vertically symmetric clip based on the bias voltage of the operational amplifier. Had to do.

  On the other hand, the prior art of Patent Document 2 realizes a soft clip by controlling the power supply voltage of the preamplifier, and has an essential configuration different from that of the present invention.

  In view of the above-described problems, the present invention provides an output limiting circuit, a class D power amplifier, and a class D power amplifier that can easily and accurately realize a vertically symmetrical soft clip based on a bias voltage of an operational amplifier with a resistance ratio. It aims at providing an audio equipment.

  In order to achieve the above object, an output limiting circuit according to the present invention is an output limiting circuit that limits an output amplitude of an operational amplifier that amplifies an input signal and generates an output signal, using a first resistor, A reference current generation unit that converts a predetermined constant voltage into a reference current; an upper clip voltage generation unit that converts the reference current into an upper clip voltage using a second resistor with a bias voltage reference of the operational amplifier; A lower clip voltage generation unit that converts the reference current into a lower clip voltage with a bias voltage reference of the operational amplifier using a resistor; and the voltage level of the output signal has an upper limit level corresponding to the upper clip voltage. The gain of the operational amplifier is adjusted so that the voltage level of the output signal does not exceed the lower limit level corresponding to the lower clip voltage. That the gain adjuster; has a configuration comprising a (first configuration).

  In the output limiting circuit having the first configuration, the gain adjusting unit is connected between the input and output of the operational amplifier, and the control terminal is connected directly or indirectly to the application terminal of the upper clip voltage. 1 transistor and a second transistor which is connected between the input and output terminals of the operational amplifier and whose control terminal is directly or indirectly connected to the application terminal of the lower clip voltage. 2).

  The output limiting circuit having the second configuration includes a third transistor having a control terminal connected to the application terminal of the upper clip voltage, a first constant current source connected in series to the third transistor, and a control circuit. A fourth transistor having an end connected to the application terminal of the lower clip voltage, and a second constant current source connected in series to the fourth transistor. A control end of the first transistor is a third transistor When connected to the connection node between the transistor and the first constant current source, and the control end of the second transistor is connected to the connection node between the fourth transistor and the second constant current source (third configuration). Good.

  In the output limiting circuit having any one of the first to third configurations, the first resistor, the second resistor, and the third resistor may all be external elements (fourth configuration). .

  The class D power amplifier according to the present invention includes a preamplifier circuit that amplifies an input signal to generate an output signal, a PWM modulation circuit that modulates the output signal into a PWM signal, and power amplifies the PWM signal. A driving circuit for generating a driving signal, a smoothing circuit for smoothing the driving signal to generate a smoothing signal, and any one of the first to fourth limiting the output amplitude of an operational amplifier constituting the preamplifier circuit And an output limiting circuit having a configuration (a fifth configuration).

  An acoustic device according to the present invention includes a class D power amplifier having the fifth configuration described above and a speaker driven by a smooth signal generated by the class D power amplifier (sixth configuration). It is said that.

  According to the present invention, a vertically symmetric soft clip with reference to the bias voltage of an operational amplifier can be realized simply and with high accuracy using a resistance ratio.

  In the following, a detailed description will be given by taking, as an example, a configuration to which the output limiting circuit according to the present invention is applied as an output power limiting means of an acoustic device including a class D power amplifier.

  FIG. 1 is a block diagram showing an embodiment of an audio device according to the present invention.

  As shown in FIG. 1, the acoustic device according to the present embodiment includes a preamplifier circuit 10, a PWM modulation circuit 20, a drive circuit 30, a smoothing circuit 40, a speaker 50, and an output limiting circuit 60. It consists of A class D power amplifier is formed by a circuit group excluding the speaker 50.

  The preamplifier circuit 10 is an inverting amplifier circuit that inverts and amplifies an input signal AIN (analog audio signal) to generate an output signal AOUT, and includes resistors 11 and 12 and an operational amplifier 13. The non-inverting input terminal (+) of the operational amplifier 13 is connected to the application terminal for the bias voltage BIAS. The inverting input terminal (−) of the operational amplifier 13 is connected to the application terminal of the input signal AIN through the resistor 11, and is also connected to its own output terminal through the resistor 12.

  The PWM modulation circuit 20 is a means for modulating the output signal AOUT into a PWM signal, and includes a phase inverter 21, integrators 22a and 22b, an oscillator 23, comparators 24a and 24b, and dead time generators 25a and 25b. And comprising.

  The phase inverter 21 is a means for generating an inverted output signal AOUTB by inverting the phase of the output signal AOUT.

  The integrator 22a is a means for performing differential integration between the output signal AOUT and a drive signal DRVa input via a first feedback path (not shown in FIG. 2) to generate a first integration result signal. The integrator 22b is a means for performing differential integration between the inverted output signal AOUTB and the drive signal DRVb input via a second feedback path (not shown in FIG. 2) to generate a second integration result signal. is there.

  The oscillator 23 is a means for generating a triangular wave signal or a ramp wave signal having a predetermined frequency.

  The comparator 24a is means for comparing the first integration result signal and the triangular wave signal to generate a first comparison signal. The comparator 24b is means for comparing the second integration result signal and the triangular wave signal to generate a second comparison signal.

  The dead time generation unit 25a controls each control so as to provide a dead time in which both switches are simultaneously turned off when the upper switch 33a and the lower switch 34a of the drive circuit 30 are push-pull driven based on the first comparison signal. It is means for generating a signal (PWM signal). The dead time generator 25b controls each control so as to provide a dead time in which both switches are simultaneously turned off when the upper switch 33b and the lower switch 34b of the drive circuit 30 are push-pull driven based on the second comparison signal. It is means for generating a signal (PWM signal). As described above, by providing the dead time using the dead time generation units 25a and 25b, it is possible to prevent a through current in the drive circuit 30.

  The drive circuit 30 is means for amplifying the control signal (PWM signal) to generate drive signals DRVa and DRVb, and includes upper drivers 31a and 31b, lower drivers 32a and 32b, and upper switches (P-channel type electric field). Effect transistors) 33a and 33b, and lower switches (N-channel field effect transistors) 34a and 34b. The output power of the class D power amplifier is determined according to the duty (modulation degree) of the drive signals DRVa and DRVb and the power supply voltage Vcc.

  The smoothing circuit 40 is a low-pass filter that smoothes the drive signals DRVa and DRVb to generate smooth signals BTLa and BTLb, and includes coils 41a and 41b and capacitors 42a and 42b.

  The speaker 50 is driven by the smooth signals BTLa and BTLb and is a means for outputting sound.

  The output limiting circuit 60 is a means for limiting the output amplitude of the operational amplifier 13 constituting the preamplifier circuit 10. The internal configuration and operation of the output limiting circuit 60 will be described in detail later.

  As can be seen from the above, in the acoustic apparatus of the present embodiment, the class D power amplifier is in the BTL [Balanced Transformer Less] format. Thus, if the configuration using a BTL class D power amplifier as the driving means of the speaker 50, it is possible to improve the power supply efficiency of the audio equipment.

  Next, the internal configuration of the output limiting circuit 60 will be described in detail.

  FIG. 2 is a circuit diagram showing a configuration example of the output limiting circuit 60.

  As shown in FIG. 2, the output limiting circuit 60 includes buffers BUF1 and BUF2, current mirrors CM1 and CM2, an NPN bipolar transistor Q0, a PNP bipolar transistor Q1, an NPN bipolar transistor Q2, and an NPN bipolar. The transistor Q3, the PNP bipolar transistor Q4, constant current sources I1 and I2, and resistors Rex1, Rex2, and Rex3 are included. Note that the resistance value of the resistor Rex1 is set to R1, and the resistance values of the resistor Rex2 and the resistor Rex3 are both set to R2.

  The emitter of the transistor Q0 is connected to the ground terminal via the external terminal and the resistor Rex1. The base of the transistor Q0 is connected to the output terminal of the buffer BUF1. The non-inverting input terminal (+) of the buffer BUF1 is connected to an application terminal for a constant voltage (bias voltage BIAS in FIG. 2). The inverting input terminal (−) of the buffer BUF1 is connected to the emitter of the transistor Q0. Note that the internal voltage REG may be used as a low voltage applied to the non-inverting input terminal (+) of the buffer BUF1.

  The input end of the current mirror CM1 is connected to the collector of the transistor Q0. The input end of the current mirror CM2 is connected to the first output end of the current mirror CM1.

  The non-inverting input terminal (+) of the buffer BUF2 is connected to the application terminal of the bias voltage BIAS. The inverting input terminal (−) of the buffer BUF2 is connected to its own output terminal. The output end of the buffer BUF2 is connected to one end of each of the resistors Rex2 and Rex3 via an external terminal. The other end of the resistor Rex2 is connected to a second output end (a drawing end of the drive current I) of the current mirror CM1 via an external terminal. The other end of the resistor Rex3 is connected to the output end of the current mirror CM2 (the drive current I draw-in end) via an external terminal.

  The collector of the transistor Q3 is connected to the application terminal for the internal voltage REG. The base of the transistor Q3 is connected to the other end (extraction end of the upper clip voltage VH) of the resistor Rex2 via an external terminal. The emitter of the transistor Q3 is connected to the ground terminal via the constant current source I1.

  The collector of the transistor Q 1 is connected to the inverting input terminal (−) of the operational amplifier 13 that constitutes the preamplifier circuit 10. The emitter of the transistor Q1 is connected to the output terminal of the operational amplifier 13. The base of the transistor Q1 is connected to a connection node between the emitter of the transistor Q3 and the constant current source I1.

  The collector of the transistor Q4 is connected to the ground terminal. The base of the transistor Q4 is connected to the other end of the resistor Rex3 (extraction end of the lower clip voltage VL) via an external terminal. The emitter of the transistor Q4 is connected to the application terminal of the internal voltage REG via the constant current source I2.

  The collector of the transistor Q2 is connected to the inverting input terminal (−) of the operational amplifier 13 constituting the preamplifier circuit 10. The emitter of the transistor Q2 is connected to the output terminal of the operational amplifier 13. The base of the transistor Q2 is connected to a connection node between the emitter of the transistor Q4 and the constant current source I2.

  Next, the operation of the output limiting circuit 60 having the above configuration will be described in detail.

  In the output limiting circuit 60, a predetermined constant voltage (bias voltage BIAS in the example of FIG. 2) is converted into a current by using the resistor Rex1, and further, this current is mirrored by the current mirrors CM1 and CM2, thereby generating a reference current. I (= BIAS / R1) is generated.

  In the output limiting circuit 60, the reference current I is converted into the upper clip voltage VH (= BIAS + I × R2) using the resistor Rex2 and the bias voltage BIAS as a reference, and the resistor Rex3 is used. The reference current I is converted into the lower clip voltage VL (= BIAS−I × R2) in a form based on the bias voltage BIAS.

  The upper clip voltage VH is applied to the base of the transistor Q3, and a voltage (VH−Vf) lower than the upper clip voltage VH by the forward voltage Vf is applied to the base of the transistor Q1. Therefore, the upper limit level of the output voltage AOUT is set to a voltage that is higher than the base voltage (VH−Vf) of the transistor Q1 by the forward voltage Vf of the transistor Q1, that is, the same value as the upper clip voltage VH.

  On the other hand, the lower clip voltage VL is applied to the base of the transistor Q4, and a voltage (VL + Vf) higher than the lower clip voltage VL by the forward voltage Vf is applied to the base of the transistor Q2. Therefore, the lower limit level of the output voltage AOUT is set to a voltage lower than the base voltage (VL + Vf) of the transistor Q2 by the forward voltage Vf of the transistor Q2, that is, the same value as the lower clip voltage VH.

  FIG. 3 is a waveform diagram showing how the output signal AOUT is vertically clipped with respect to the bias voltage BIAS. The solid line A1 in the figure shows the output signal AOUT when the output restriction according to the present invention is applied, and the broken line A0 shows the output signal AOUT when the output restriction is not applied for reference. Show.

  As the voltage level of the output signal AOUT becomes higher than the bias voltage BIAS and approaches the upper limit level variably set by the upper clip voltage VH (in this embodiment, the same value as the upper clip voltage VH as described above), the transistor Q1 The ON resistance of the transistor Q1 gradually decreases, and finally, the transistor Q1 is fully turned on when the voltage level of the output signal AOUT reaches the upper limit level.

  That is, as the output signal AOUT approaches the upper limit level, the feedback resistance value of the operational amplifier 13 (the combined resistance value of the resistance value of the resistor 12 and the on-resistance value of the transistor Q1) gradually decreases, and the preamplifier circuit The gain of 10 gradually decreases. As a result, the output signal AOUT is clamped at the upper limit level, and the upper soft clip of the output signal AOUT is realized.

  Conversely, the voltage level of the output signal AOUT is lower than the bias voltage BIAS, and is a lower limit level variably set by the lower clip voltage VL (in this embodiment, the same value as the lower clip voltage VL as described above). As the voltage approaches, the on-resistance of the transistor Q2 gradually decreases. Finally, the transistor Q2 is fully turned on when the voltage level of the output signal AOUT reaches the lower limit level.

  That is, as the output signal AOUT approaches the lower limit level, the feedback resistance value of the operational amplifier 13 (the combined resistance value of the resistance value of the resistor 12 and the on-resistance value of the transistor Q2) gradually decreases, and the preamplification is performed. The gain of the circuit 10 gradually decreases. As a result, the output signal AOUT is clamped at the lower limit level, and the lower soft clip of the output signal AOUT is realized.

  As described above, in the audio apparatus of the present embodiment, the output limiting circuit 60 uses the resistor Rex1 to generate a reference current that converts a predetermined constant voltage (the bias voltage BIAS in the example of FIG. 2) into the reference current I. Unit (Rex1, BUF1, Q0, CM1, CM2); and an upper clip voltage generation unit that converts a reference current I into an upper clip voltage VH (= BIAS + I × R2) based on a bias voltage of the operational amplifier 13 using a resistor Rex2. (Rex2, BUF2) and; using the resistor Rex3, the lower clip voltage generation unit (Rex3, Rex3, Rx3) that converts the reference current I into the lower clip voltage VL (= BIAS-I × R2) with reference to the bias voltage of the operational amplifier 13 BUF2); the voltage level of the output signal AOUT does not exceed the upper limit level (VH + Vf) corresponding to the upper clip voltage VH In addition, the gain adjustment unit (Q1, Q2) for adjusting the gain of the operational amplifier 13 so that the voltage level of the output signal AOUT does not exceed the lower limit level (VL-Vf) corresponding to the lower clip voltage VL. It is set as the structure which has;

  More specifically, in the gain adjusting unit of the output limiting circuit 60, the emitter is connected to the output terminal of the operational amplifier 13, the collector is connected to the input terminal of the operational amplifier 13, and the base is indirectly connected to the application terminal of the upper clip voltage VH. PNP bipolar transistor Q1 connected in common, the emitter is connected to the output terminal of the operational amplifier 13, the collector is connected to the input terminal of the operational amplifier 13, and the base is indirectly connected to the application terminal of the lower clip voltage VL. The preamplifier circuit 10 is configured by adopting a diode clipping method (a clipping method using a diode characteristic between the base and emitter of the transistors Q1 and Q2). By limiting the output dynamic range of the operational amplifier 13, the PWM signal Place limits the duty (modulation), and by extension, has a configuration that limits the output power of the class D power amplifier.

  By providing such an output power limiting function, even when an excessive input signal AIN is applied, the amplitude level of the output signal AOUT of the operational amplifier 13 is suppressed, and as a result, the output of the class D power amplifier. Since the electric power is limited, it is possible to prevent an increase in distortion due to output saturation, destruction of the speaker 50, and the like.

  Further, in the output limiting circuit 60 of the present embodiment, the output signal AOUT has a soft clipping waveform, so that it is possible to reduce abnormal noise at the speaker 50 compared to the conventional configuration in which hard clipping is performed.

  Further, the output limiting circuit 60 of this embodiment includes a transistor Q3 whose base is connected to the application terminal of the upper clip voltage VH, a constant current source I1 connected in series to the transistor Q3, and a base whose lower clip voltage VL is the same. A transistor Q4 connected to the application terminal; and a constant current source I2 connected in series to the transistor Q4. The base of the transistor Q1 is connected to a connection node between the transistor Q3 and the constant current source I1. The base of the transistor Q2 is connected to the connection node of the transistor Q4, the constant current source, and I2.

  With this configuration, the temperature characteristics of the forward voltage Vf of the transistors Q1 and Q2 can be canceled by the temperature characteristics of the transistors Q3 and Q4, and the upper clip voltage drawn from the other end of the resistors Rex2 and Rex3. Since the values of VH and the lower clip voltage VL become the upper limit level and the lower limit level of the output voltage AOUT of the preamplifier circuit 10 as they are, it is very easy to use.

  However, the configuration of the present invention is not limited to this, and the bases of the transistors Q1 and Q2 may be directly connected to the application terminals of the upper clip voltage VH and the lower clip voltage VL.

  Further, with the output limiting circuit 60 of the present embodiment, the upper and lower sides of the operational amplifier 13 with reference to the bias voltage BIAS can be obtained simply by making the resistance values of the resistors Rex2 and Rex3 the same without performing troublesome adjustment of circuit constants. A symmetrical clip can be easily realized.

  Further, with the output limiting circuit 60 of the present embodiment, the upper clip voltage VH and the lower clip voltage VL can be variably controlled within a very wide range. For example, when the bias voltage is 3.5 [V] and the internal voltage REG is 7 [V], the upper clip voltage VH and the lower clip voltage VL are equal to the saturation voltage of the transistors forming the current mirrors CM1 and CM2. In consideration of (0.1 [V]), the range of the bias voltage BIAS ± 3.4 [V] can be set as the dynamic range. Therefore, since the limit level of the output power does not react sensitively to the variable control of the upper clip voltage VH and the lower clip voltage VL, the desired output power can be set accurately and easily. .

  In the output limiting circuit 60, the resistors Rex1, Rex2, and Rex3 are all preferably external elements. With such a configuration, it is possible to adjust the output power limit level steplessly and with high accuracy by arbitrarily changing the resistance value of the external element.

  For example, if the upper clip voltage VH and the lower clip voltage VL are appropriately set according to the wattage of the speaker 50, the speaker can be prevented from being destroyed due to unexpected excessive input, or the power supply design corresponding to the speaker output can be reduced. It becomes unnecessary.

  As the resistors Rex1, Rex2, Rex3, it is desirable to use highly accurate elements (± 1% recommended) in order to set the output power limit level with high accuracy.

  Further, it is desirable to set the resistance value R1 of the resistor Rex1 to a relatively large value (20 [kΩ] or more) so that the reference current I does not become excessive.

  If the output power limiting function is not used, the resistance value R1 of the resistor Rex1 and the resistance value R2 of the resistors Rex2 and Rex3 may be set to the same value.

  FIG. 4 is a waveform diagram showing how the smooth signal BTLa (BTLb) is soft clipped. Note that the solid line B0 in the figure indicates the smooth signal BTLa (BTLb) when the output restriction according to the present invention is not applied, and the solid lines B1 to B3 are provided with the output restriction gradually and heavily according to the present invention. The smoothing signal BTLa (BTLb) in the case is shown.

  As shown in FIG. 4, it can be seen that the amplitude of the smoothing signal BTLa (BTLb) can be reduced as the resistance value R2 of the resistors Rex2 and Rex3 is set smaller and the output restriction according to the present invention is more heavily applied.

  FIG. 5 is a diagram illustrating the correlation between the input amplitude (logarithm) and the output voltage (logarithm). The solid line C0 in the figure indicates the correlation when the output restriction according to the present invention is not performed, and the solid lines C1 to C3 indicate the correlation when the output restriction according to the present invention is gradually applied. Yes.

  As shown in FIG. 5, it can be seen that the output power can be kept small even when the input amplitude is increased as the resistance value R2 of the resistors Rex2 and Rex3 is set smaller and the output restriction according to the present invention is more heavily applied.

  In the above embodiment, the configuration in which the output limiting circuit according to the present invention is applied as the output power limiting means of the audio equipment including the class D power amplifier has been described as an example. The present invention is not limited to this, and the present invention can be widely applied to all output limiting circuits that limit the output amplitude of an operational amplifier that amplifies an input signal and generates an output signal.

  The configuration of the present invention can be variously modified within the scope of the present invention in addition to the above embodiment.

  The present invention is a technique suitable for limiting the output power of a power amplifier used in a TV device, a desktop PC, an AV receiver, a car audio, and the like.

These are block diagrams which show one Embodiment of the audio equipment which concerns on this invention. These are circuit diagrams showing a configuration example of the output limiting circuit 60. FIG. These are waveform diagrams showing how the output signal AOUT is clipped symmetrically with respect to the bias voltage BIAS. These are waveform diagrams showing how the smooth signal BTLa (BTLb) is soft clipped. These are figures which show the correlation of input amplitude (logarithm) and output voltage (logarithm).

Explanation of symbols

10 Preamplifier circuit (inverting amplifier circuit)
DESCRIPTION OF SYMBOLS 11, 12 Resistance 13 Operational amplifier 20 PWM modulation circuit 21 Phase inverter 22a, 22b Integrator 23 Oscillator 24a, 24b Comparator 25a, 25b Dead time generation part 30 Drive circuit 31a, 31b Upper side driver 32a, 32b Lower side driver 33a, 33b Upper switch (P-channel field effect transistor)
34a, 34b Lower switch (N-channel field effect transistor)
40 Smoothing circuit 41a, 41b Coil 42a, 42b Capacitor 50 Speaker 60 Output limiting circuit BUF1, BUF2 Buffer CM1, CM2 Current mirror Q0 NPN type bipolar transistor Q1 PNP type bipolar transistor Q2 NPN type bipolar transistor Q3 NPN type bipolar transistor Q4 PNP type bipolar Transistors I1, I2 Constant current source Rex1, Rex2, Rex3 Resistance (external element)

Claims (6)

An output limiting circuit that limits the output amplitude of an operational amplifier that amplifies an input signal and generates an output signal,
A reference current generator that converts a predetermined constant voltage into a reference current using a first resistor;
An upper clip voltage generation unit that converts the reference current into an upper clip voltage using a second resistor based on a bias voltage reference of the operational amplifier;
A lower clip voltage generation unit that converts the reference current into a lower clip voltage using a third resistor based on a bias voltage reference of the operational amplifier;
The voltage level of the output signal does not exceed the upper limit level according to the upper clip voltage, and the voltage level of the output signal does not exceed the lower limit level according to the lower clip voltage. A gain adjusting unit for adjusting the gain of the operational amplifier;
An output limiting circuit comprising:   The gain adjusting unit is connected between the input and output terminals of the operational amplifier, and the control terminal is connected directly or indirectly to the application terminal of the upper clip voltage, and also between the input and output terminals of the operational amplifier. The output limiting circuit according to claim 1, further comprising: a second transistor that is connected and whose control terminal is directly or indirectly connected to the application terminal of the lower clip voltage.   A third transistor having a control terminal connected to the upper clip voltage application terminal, a first constant current source connected in series to the third transistor, and a control terminal connected to the lower clip voltage application terminal. 4 transistors and a second constant current source connected in series to the fourth transistor, the control terminal of the first transistor is connected to a connection node between the third transistor and the first constant current source, 3. The output limiting circuit according to claim 2, wherein the control terminal of the second transistor is connected to a connection node between the fourth transistor and the second constant current source.   4. The output limiting circuit according to claim 1, wherein each of the first resistor, the second resistor, and the third resistor is an external element. 5.   A preamplifier circuit that amplifies an input signal to generate an output signal; a PWM modulation circuit that modulates the output signal into a PWM signal; a drive circuit that amplifies the PWM signal to generate a drive signal; and the drive A smoothing circuit that smoothes a signal to generate a smooth signal, and an output limiting circuit according to any one of claims 1 to 4 that limits an output amplitude of an operational amplifier that constitutes the preamplifier circuit. Class D power amplifier characterized by comprising   6. An acoustic apparatus comprising: the class D power amplifier according to claim 5; and a speaker driven by a smooth signal generated by the class D power amplifier.

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