JP2009049353A - Solid-state imaging device, imaging apparatus, and solid-state imaging device driving method - Google Patents

Abstract

Even when the number of pixels is increased without increasing the size of a horizontal charge transfer path, it is possible to solve problems such as a decrease in charge transfer capacity, an increase in power consumption, and a deterioration in transfer efficiency of the horizontal charge transfer path. A possible solid-state imaging device is provided.
A photoelectric conversion element, a number of vertical charge transfer paths 1 for transferring charges generated in the photoelectric conversion element in a vertical direction Y, and a charge transferred through the vertical charge transfer path 1 orthogonal to the vertical direction Y. And a horizontal charge transfer path 2 for transferring in the horizontal direction X. The horizontal charge transfer path 2 includes a plurality of charge transfer stages that operate as a barrier region or a storage region according to the level of an applied voltage. In addition, two vertical charge transfer paths 1 are connected to each of the plurality of charge transfer stages.
[Selection] Figure 1

Description

  The present invention relates to a photoelectric conversion element, a number of vertical charge transfer paths for transferring charges generated in the photoelectric conversion element in the vertical direction, and a charge transferred through the vertical charge transfer path in a horizontal direction orthogonal to the vertical direction. The present invention relates to a solid-state imaging device having a horizontal charge transfer path for transferring in a direction.

FIG. 29 is a partially enlarged view of a general solid-state imaging device.
The solid-state imaging device shown in FIG. 29 includes a photoelectric conversion element (not shown) arranged two-dimensionally on a semiconductor substrate, a number of vertical charge transfer paths 11 that transfer charges generated in the photoelectric conversion element in the vertical direction Y, A horizontal charge transfer path 12 that transfers charges transferred through the vertical charge transfer path 11 in a horizontal direction X orthogonal to the vertical direction Y, a charge storage region 16 that connects the vertical charge transfer path 11 and the horizontal charge transfer path 12, and And a line memory LM formed of the memory electrode 13 formed above the charge storage region 16. The vertical charge transfer path 11, the charge storage region 16, and the horizontal charge transfer path 12 are configured by, for example, an n-type impurity layer.

  Above the horizontal charge transfer path 12, a plurality of electrode sets in which the inverted L-shaped electrode 14 and the rectangular electrode 15 are arranged in this order in the horizontal direction X are arranged in the horizontal direction X. This electrode set includes a first electrode set to which the transfer pulse φH1 is applied and a second electrode set to which the transfer pulse φH2 is applied, which are alternately arranged in the horizontal direction X. When the transfer pulse φH1 is at a high level and the transfer pulse φH2 is at a low level, the horizontal charge transfer path 12 below the first electrode set operates as a charge storage region capable of storing charges, and the horizontal charge below the second electrode set. The transfer path 12 operates as a barrier region between the charge storage regions. On the other hand, when the transfer pulse φH1 is at a low level and the transfer pulse φH2 is at a high level, the horizontal charge transfer path 12 below the second electrode set operates as a charge storage region capable of storing charges, and below the first electrode set. The horizontal charge transfer path 12 operates as a barrier region between the charge storage regions. As described above, in the horizontal charge transfer path 12, a plurality of charge transfer stages that operate as a barrier region or a charge storage region according to the level of the applied voltage are formed by the first electrode set and the second electrode set. ing.

  Patent Document 1 discloses a solid-state imaging device having a vertical charge transfer path, a line memory, and a horizontal charge transfer path.

JP 2007-27977 A

  In the solid-state imaging device having the configuration shown in FIG. 29, one charge transfer stage is provided corresponding to one vertical charge transfer path 11. Therefore, when the pixel size is reduced without changing the horizontal width of the horizontal charge transfer path 12 corresponding to the increase in the number of pixels, the horizontal width of the charge transfer stage (the portion indicated by A in FIG. 29). Decreases, and the charge transfer capacity of the horizontal charge transfer path 12 decreases. In order to secure the charge transfer capacity, it is conceivable to increase the width of each charge transfer stage. However, in this case, the entire width of the horizontal charge transfer path 12 is expanded in the horizontal direction. An increase in power will occur. In addition, since the number of charge transfer stages increases corresponding to the increase in the number of pixels, there is a concern that transfer efficiency may deteriorate when high-speed driving is performed.

  The present invention has been made in view of the above circumstances, and even when the number of pixels is increased without increasing the size of the horizontal charge transfer path, the charge transfer capacity of the horizontal charge transfer path is reduced and the power consumption is increased. An object of the present invention is to provide a solid-state imaging device capable of solving problems such as deterioration of transfer efficiency.

  The solid-state imaging device of the present invention includes a photoelectric conversion element, a number of vertical charge transfer paths that transfer charges generated in the photoelectric conversion element in the vertical direction, and charges transferred through the vertical charge transfer path in the vertical direction. A horizontal charge transfer path that transfers in a horizontal direction orthogonal to the horizontal charge transfer path, wherein the horizontal charge transfer path is a plurality of charge transfer stages that operate as a charge storage region or a barrier region according to the level of an applied voltage A plurality of the vertical charge transfer paths are connected to each of the plurality of charge transfer stages.

  The solid-state imaging device according to the present invention is provided independently on each of the plurality of charge storage regions connecting each of the plurality of vertical charge transfer paths and the horizontal charge transfer path and above each of the plurality of charge storage areas. A line memory including a memory electrode is provided, and a voltage can be independently applied to each of the memory electrodes above each of the charge storage regions connecting the charge transfer stage and the plurality of vertical charge transfer paths. .

  In the solid-state imaging device of the present invention, two charge storage regions connecting each of the plurality of vertical charge transfer paths and the horizontal charge transfer path, and two adjacent charge transfer stages are connected to each other. A line memory including a memory electrode provided independently above the charge storage region is provided, and the memory electrode includes a first memory electrode and a second memory electrode to which a voltage can be applied independently.

  In the solid-state imaging device of the present invention, the photoelectric conversion element includes three types of photoelectric conversion elements that detect light in different wavelength ranges, and the charge is accumulated in each of the multiple charge accumulation regions. The three types of photoelectric elements are arranged such that the charge arrangement is an arrangement in which the charge of the first color component and the charge of the second color component are alternately arranged in the horizontal direction with the charge of the third color component interposed therebetween. The arrangement of the conversion elements is determined.

  The image pickup apparatus of the present invention includes the solid-state image pickup device and a driving unit that drives the solid-state image pickup device, and the charge transfer stage is connected with the two vertical charge transfer paths, and the memory electrode includes A first memory electrode and a second memory electrode to which a voltage can be applied independently, and the driving means stores the charge in each of the plurality of charge storage regions, and then the first memory electrode And the voltage applied to the second memory electrode and the voltage applied to each of the plurality of charge transfer stages to control 4 of the same color component among the many charges accumulated in the charge accumulation region. A drive for mixing and transferring two charges on the horizontal charge transfer path is performed.

  The imaging apparatus of the present invention includes the solid-state imaging device and a driving unit that drives the solid-state imaging device, and the vertical transfer path is connected to the charge transfer stage, and the driving unit includes: A voltage applied to the first memory electrode and the second memory electrode and a voltage applied to each of the plurality of charge transfer stages after storing charges in each of the plurality of charge storage regions. By controlling, among the many charges stored in the charge storage region, four charges of the same color component are mixed and transferred on the horizontal charge transfer path.

  In the imaging device of the present invention, the photoelectric conversion element includes three types of photoelectric conversion elements that detect light of different wavelength ranges, and the charge is accumulated in each of the multiple charge accumulation regions. The three types of photoelectric conversion so that the first color component charge and the second color component charge are alternately arranged in the horizontal direction across the third color component charge. The arrangement of the elements is determined.

  The solid-state imaging device driving method according to the present invention includes a photoelectric conversion element, a number of vertical charge transfer paths that transfer charges generated in the photoelectric conversion element in a vertical direction, and a charge transferred through the vertical charge transfer path. A solid-state imaging device driving method having a horizontal charge transfer path for transferring in a horizontal direction orthogonal to the vertical direction, wherein the horizontal charge transfer path operates as a charge accumulation region or a barrier region according to the level of an applied voltage Two vertical charge transfer paths are connected to each of the plurality of charge transfer stages, and the solid-state imaging device is connected to each of the plurality of vertical charge transfer paths and the horizontal charge transfer stage. A line memory comprising a large number of charge storage regions connecting charge transfer paths and a memory electrode provided independently above each of the large number of charge storage regions is provided, and is connected to the charge transfer stage. A voltage can be applied independently to each of the memory electrodes above each of the charge storage regions connecting the two vertical charge transfer paths, and each of the memory electrodes can be independently applied with a voltage. A plurality of memory electrodes and a voltage applied to the first memory electrode and the second memory electrode after storing charges in each of the plurality of charge storage regions; and Drive for controlling the voltage applied to each of the charge transfer stages to mix and transfer four charges of the same color component on the horizontal charge transfer path among a large number of charges stored in the charge storage region. Do.

  The solid-state imaging device driving method according to the present invention includes a photoelectric conversion element, a number of vertical charge transfer paths that transfer charges generated in the photoelectric conversion element in a vertical direction, and a charge transferred through the vertical charge transfer path. A solid-state imaging device driving method having a horizontal charge transfer path for transferring in a horizontal direction orthogonal to the vertical direction, wherein the horizontal charge transfer path operates as a charge accumulation region or a barrier region according to the level of an applied voltage Two vertical charge transfer paths are connected to each of the plurality of charge transfer stages, and the solid-state imaging device is connected to each of the plurality of vertical charge transfer paths and the horizontal charge transfer stage. A plurality of charge storage regions connecting the charge transfer paths, and memory electrodes provided independently above each of the two adjacent charge storage regions connected to the different charge transfer stages. A line memory, wherein the memory electrode includes a first memory electrode and a second memory electrode to which different voltages can be applied, and after the charge is accumulated in each of the plurality of charge accumulation regions, The voltage applied to the memory electrode and the second memory electrode and the voltage applied to each of the plurality of charge transfer stages are controlled so as to have the same color among the many charges accumulated in the charge accumulation region. The four charges of the components are mixed and transferred on the horizontal charge transfer path.

  In the solid-state imaging device driving method of the present invention, the photoelectric conversion element includes three types of photoelectric conversion elements that detect light in different wavelength ranges, and charges are accumulated in each of the multiple charge accumulation regions. The charge arrangement is such that the charge of the first color component and the charge of the second color component are alternately arranged in the horizontal direction across the charge of the third color component. The arrangement of the types of photoelectric conversion elements is determined.

  According to the present invention, even when the number of pixels is increased without increasing the size of the horizontal charge transfer path, problems such as a decrease in charge transfer capacity, an increase in power consumption, and a decrease in transfer efficiency of the horizontal charge transfer path are solved. It is possible to provide a solid-state imaging device that can be used.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a schematic partial plan view showing a schematic configuration of a solid-state imaging device according to the first embodiment of the present invention.
The solid-state imaging device shown in FIG. 1 includes a photoelectric conversion element (not shown) arranged two-dimensionally in a horizontal direction X and a vertical direction Y orthogonal thereto on a semiconductor substrate, and charges generated by the photoelectric conversion element in the vertical direction Y. A plurality of vertical charge transfer paths 1 arranged in the horizontal direction X to be transferred to each other, a horizontal charge transfer path 2 for transferring the charges transferred through each of the many vertical charge transfer paths 1 in the horizontal direction X, and a number of A charge storage region 5 connecting each of the vertical charge transfer paths 1 and the horizontal charge transfer path 2 and a line memory LM including memory electrodes 3 (3a, 3b) provided independently above the charge storage region 5 are provided. The vertical charge transfer path 1, the charge accumulation region 5, and the horizontal charge transfer path 2 are configured by, for example, an n-type impurity layer formed in a p-well layer formed on an n-type semiconductor substrate.

  Above the horizontal charge transfer path 2, a plurality of electrode sets in which the inverted L-shaped electrode 4 a and the rectangular electrode 4 b are arranged in this order in the horizontal direction X are arranged in the horizontal direction X. This electrode set includes an electrode set D1 to which the transfer pulse φH2 is applied and an electrode set D2 to which the transfer pulse φH1 is applied, and these are alternately arranged in the horizontal direction X.

  When the transfer pulse φH2 becomes high level and the transfer pulse φH1 becomes low level, the horizontal charge transfer path 2 below the electrode set D1 operates as a charge storage region capable of storing charges, and the horizontal charge transfer path 2 below the electrode set D2 It operates as a barrier region between the charge storage regions. On the other hand, when the transfer pulse φH2 is at the low level and the transfer pulse φH1 is at the high level, the horizontal charge transfer path 2 below the electrode set D2 operates as a charge storage region capable of storing charges, and the horizontal charge transfer path below the electrode set D1. 2 operates as a barrier region between the charge storage regions. As described above, in the horizontal charge transfer path 2, a plurality of charge transfer stages that operate as a barrier region or a charge storage region according to the level of the applied voltage are formed by the overlapping portion of the electrode set D1 and the electrode set D2. .

  Each of the adjacent vertical charge transfer paths 1 is connected to each charge transfer stage of the horizontal charge transfer path 2 via a charge storage region 5. Of the two charge storage regions 5 connected to each charge transfer stage, the line memory pulse φLM1 is applied above the charge storage region 5 on the upstream side (right side in the figure) of the horizontal charge transfer path 2 in the charge transfer direction. A memory electrode 3b to which the line memory pulse φLM2 is applied is formed above the charge storage region 5 on the downstream side (left side in the figure) of the horizontal charge transfer path 2 in the charge transfer direction. . The line memory pulses φLM1 and φLM2 can take a high level state and a low level state, respectively.

  FIG. 2 is a schematic plan view illustrating an example of the entire configuration of the solid-state imaging device according to the first embodiment. FIG. 3 is a partially enlarged view of the solid-state imaging device shown in FIG.

  A solid-state imaging device 100 illustrated in FIG. 2 includes a large number of photoelectric conversion elements 10 arranged in a square lattice pattern in the vertical direction Y and the horizontal direction X. A photoelectric conversion element array composed of photoelectric conversion elements arranged in the vertical direction Y is provided with a vertical charge transfer device 20 including a vertical charge transfer path 1 and transfer electrodes V1 to V4 thereabove on the side thereof. Yes. Between each photoelectric conversion element 10 constituting the photoelectric conversion element array and the vertical charge transfer path 1 corresponding to the photoelectric conversion element array, charges accumulated in the photoelectric conversion element 10 are transferred to the vertical charge transfer path 1. A charge reading unit 60 for reading is formed.

  The end of the vertical charge transfer device 20 is connected to a line memory LM composed of the charge storage region 5 and the memory electrodes 3a and 3b. The line memory LM is connected to the horizontal charge composed of the horizontal charge transfer path 2 and the electrodes 4a and 4b. A transfer device 40 is connected. The horizontal charge transfer device 40 is connected to an output unit 50 that outputs a signal corresponding to the charge transferred through the horizontal charge transfer path 2.

  The image pickup apparatus 200 including the solid-state image pickup device is provided with a drive unit 70. The drive unit 70 supplies transfer pulses φV1 to φV4 to the transfer electrodes V1 to V4 of the vertical charge transfer device 20, and the horizontal charge transfer device 40. The transfer pulses φH1 and φH2 are supplied to the electrode sets D1 and D2 to drive the solid-state imaging device 100.

FIG. 4 is a schematic plan view showing another example of the overall configuration of the solid-state imaging device of the first embodiment. FIG. 5 is a partially enlarged view of the solid-state imaging device shown in FIG.
The difference between the solid-state imaging device 100 shown in FIG. 4 and the solid-state imaging device 100 shown in FIG. 2 is the arrangement of the photoelectric conversion elements 10 and the shape of the vertical charge transfer device 20.
A solid-state imaging device 100 shown in FIG. 4 includes a first photoelectric conversion element group in which photoelectric conversion elements 10 are arranged in a square lattice pattern in the vertical direction Y and the horizontal direction X, and a square lattice pattern in the vertical direction Y and the horizontal direction X. The second photoelectric conversion element group in which the photoelectric conversion elements 10 are arranged is arranged so as to be shifted in the vertical direction Y and the horizontal direction X by 1/2 of the arrangement pitch of the photoelectric conversion elements 10 of each photoelectric conversion element group. ing. The vertical charge transfer device 20 is formed by meandering in the vertical direction Y so as to avoid the photoelectric conversion elements 10 between the photoelectric conversion element arrays composed of the photoelectric conversion elements 10 arranged in the vertical direction Y.

  As shown in FIG. 5, the vertical charge transfer device 20 includes a meandering vertical charge transfer path 1 and meandering transfer electrodes Va and Vb arranged in the vertical direction Y above the meandering vertical charge transfer path 1. By supplying four-phase transfer pulses φV1 to φV4 to the transfer electrodes Va and Vb from a driving unit (not shown), the charge transfer operation of the vertical charge transfer device 20 is controlled.

  The solid-state imaging device of this embodiment includes three types of photoelectric conversion elements that detect light in different wavelength ranges (for example, an R photoelectric conversion element that detects light in the red (R) wavelength range, and a green (G) wavelength. G photoelectric conversion element for detecting light in the region, and B photoelectric conversion element for detecting light in the blue (B) wavelength region), in a state where charges are accumulated in all the charge accumulation regions 5, The charge arrangement is such that the charge of the first color component (R component) and the charge of the second color component (B component) are alternately arranged in the horizontal direction X across the charge of the third color component (G component). The arrangement of the above three types of photoelectric conversion elements is determined so that the arrangement becomes the same.

  FIG. 6 is a diagram illustrating an arrangement example of photoelectric conversion elements of the solid-state imaging element according to the first embodiment. In FIG. 6, “R” indicates an R photoelectric conversion element, “G” indicates a G photoelectric conversion element, and “B” indicates a B photoelectric conversion element.

  The arrangement shown in FIG. 6A shows an arrangement example of the R photoelectric conversion elements, the G photoelectric conversion elements, and the B photoelectric conversion elements in the solid-state imaging device 100 shown in FIG. 4, and is arranged in a square lattice pattern. The first photoelectric conversion element group is composed of an R photoelectric conversion element and a B photoelectric conversion element, the second photoelectric conversion element group arranged in a square lattice is composed of a G photoelectric conversion element, and the first photoelectric conversion element The photoelectric conversion element array of the group has an R photoelectric conversion element and a B photoelectric conversion element arranged in a checkered pattern.

  According to this arrangement, in a state where charges are accumulated in all the charge accumulation regions 5 (a state where charges from the photoelectric conversion elements for two lines are accumulated in the charge accumulation region 5), the arrangement of the color components of the charges is arranged. Are RGBGRGBG... Or BGRGBGRG..., And R charges and B charges are alternately arranged in the horizontal direction X with the G charges interposed therebetween, so that the above-described arrangement condition can be satisfied.

  The arrangement shown in FIG. 6B shows an arrangement example of the R photoelectric conversion element, the G photoelectric conversion element, and the B photoelectric conversion element in the solid-state imaging device 100 shown in FIG. A G photoelectric conversion element comprising a G photoelectric conversion element in which the B photoelectric conversion element array comprising the B photoelectric conversion elements and the R photoelectric conversion element array comprising the R photoelectric conversion elements arranged in the vertical direction Y are arranged in the vertical direction Y. The array is arranged alternately in the horizontal direction X across the rows.

  According to this arrangement, in a state where charges are accumulated in all charge accumulation regions 5 (a state where charges from one line of photoelectric conversion elements are accumulated in the charge accumulation region 5), the arrangement of the color components of the charges is arranged. Are RGBGRGBG... Or BGRGBGRG... And the R charges and B charges are alternately arranged in the horizontal direction X with the G charges interposed therebetween, so that the arrangement condition described above can be satisfied.

  Although FIG. 6 shows a photoelectric conversion element array for detecting primary color light, a photoelectric conversion element array for detecting complementary color light may be used.

Hereinafter, the operation of the solid-state imaging device having such a configuration will be described.
FIG. 7 is a diagram for explaining the charge transfer operation from the line memory of the solid-state imaging device shown in FIG. 1 to the horizontal charge transfer path. In FIG. 7, the timing chart of the transfer pulses φH1 and φH2 and the line memory pulses φLM1 and φLM2 is shown on the left side, and the state of charge at each timing shown on the left side is shown on the right side. Here, the case where the arrangement of the photoelectric conversion elements included in the solid-state imaging element is the arrangement shown in FIG. 6 will be described as an example.

  FIG. 7A shows a state where charges obtained from the photoelectric conversion elements for two lines of the solid-state imaging element are accumulated in a large number of charge accumulation regions 5. In this state, φH1 and φH2 are at a low level, φLM1 and φLM2 are at a high level, a potential well is formed in the charge storage region 5, and each charge transfer stage of the horizontal charge transfer path 2 has a barrier for this potential well. Forming.

  Next, as shown in FIG. 7B, φLM2 is set to the low level and φH2 is set to the high level, and the charge storage region below the memory electrode 3b corresponding to the charge transfer stage is placed in the charge transfer stage below the electrode set D1. The charge “R” in 5 is moved. Thereafter, φH2 is set to the low level and φH1 is set to the high level to transfer the charge “R” to the adjacent charge transfer stage. By repeating such transfer operation, a signal corresponding to the charge “R” is transferred to the horizontal charge. Output from the output amplifier connected to the end of the path 2.

  After the signal corresponding to the charge “R” is output, φLM2, φLM1, φH1, and φH2 are set to the state shown in FIG. 7A, then φLM1 is set to the low level and φH2 is set to the high level as shown in FIG. Thus, the charge “G1” in the charge accumulation region 5 below the memory electrode 3a corresponding to the charge transfer stage is moved to the charge transfer stage below the electrode set D1. Thereafter, φH2 is set to the low level and φH1 is set to the high level to transfer the charge “G1” to the adjacent charge transfer stage. By repeating such transfer operation, the signal corresponding to the charge “G1” is transferred to the horizontal charge. Output from the output amplifier connected to the end of the path 2.

  After the signal corresponding to the charge “G1” is output, φLM2, φLM1, φH1, and φH2 are set to the state shown in FIG. 7A, then φLM2 is set to the low level and φH1 is set to the high level as shown in FIG. Thus, the charge “B” in the charge accumulation region 5 below the memory electrode 3b corresponding to the charge transfer stage is moved to the charge transfer stage below the electrode set D2. Thereafter, φH1 is set to low level and φH2 is set to high level to transfer the charge “B” to the adjacent charge transfer stage. By repeating such transfer operation, a signal corresponding to the charge “B” is transferred to the horizontal charge. Output from the output amplifier connected to the end of the path 2.

  After the signal corresponding to the charge “B” is output, φLM2, φLM1, φH1, and φH2 are set to the state shown in FIG. 7A, then φLM1 is set to the low level and φH1 is set to the high level as shown in FIG. Thus, the charge “G2” in the charge accumulation region 5 below the memory electrode 3a corresponding to the charge transfer stage is moved to the charge transfer stage below the electrode set D2. Thereafter, φH1 is set to low level and φH2 is set to high level to transfer the charge “G2” to the adjacent charge transfer stage. By repeating such transfer operation, a signal corresponding to the charge “G2” is transferred to the horizontal charge. Output from the output amplifier connected to the end of the path 2.

  With this operation, the transfer of charges for two lines is completed.

  As described above, according to the solid-state imaging device of the present embodiment, two vertical charge transfer paths 1 are connected to one charge transfer stage, and the charge storage region 5 connected to the two vertical charge transfer paths 1 is above. By making it possible to independently apply a voltage to each of the memory electrodes 3a and 3b, it is possible to select the charges transferred to the horizontal charge transfer path 2 in the line memory LM.

  Therefore, even when the same pixel pitch as that in FIG. 29 is realized, the horizontal width (A ′ in FIG. 1) of the charge transfer stage is shown in FIG. 29 while maintaining the horizontal width of the horizontal charge transfer path 2. It can be expanded more than anything. As a result, the charge transfer capacity of the horizontal charge transfer path 2 can be increased without increasing the power consumption. In addition, since the number of charge transfer stages can be reduced, it is possible to prevent deterioration of transfer efficiency.

  Further, according to the solid-state imaging device of the present embodiment, the memory electrodes of the line memory LM are divided into the memory electrode 3a and the memory electrode 3b to which voltages can be applied independently, so that the line memory pulses φLM1, φLM2 By controlling the above, it is possible to distribute charges from the line memory LM to the horizontal charge transfer path 2.

  When multi-field reading is performed with the configuration shown in FIG. 29, the driving of the vertical charge transfer path 11 is complicated, but according to the configuration shown in FIG. 1, the driving of the vertical charge transfer path 1 is complicated. Therefore, multi-field reading can be realized only by controlling the line memory pulses φLM1 and φLM2. Further, by controlling the line memory pulses φLM1 and φLM2, it is possible to easily realize thinning driving or the like. Thus, by providing a plurality of types of memory electrodes, various driving methods can be easily realized.

  In the above description, two vertical charge transfer paths 1 are connected to each charge transfer stage of the horizontal charge transfer path 2, but the number of vertical charge transfer paths 1 connected to each charge transfer stage is as follows. Even if there are three or more, the above-described effects can be obtained. In the following, a case where the number of vertical charge transfer paths 1 connected to each charge transfer stage is four will be described as an example.

FIG. 8 is a schematic partial plan view showing a schematic configuration of a modified example of the solid-state imaging device according to the first embodiment of the present invention. In FIG. 8, the same components as those of FIG.
The solid-state imaging device shown in FIG. 8 is different from the solid-state imaging device shown in FIG. 1 in that four vertical charge transfer paths 1 are connected to each charge transfer stage of the horizontal charge transfer path 2.

  As shown in FIG. 8, four vertical charge transfer paths 1 are connected to each charge transfer stage of the horizontal charge transfer path 2 via a charge accumulation region 5. Line memory pulse φLM1 is above the charge storage region 5 on the most downstream side (leftmost in FIG. 8) in the charge transfer direction by the horizontal charge transfer path 2 among the four charge storage regions 5 connected to A memory electrode 3f to be applied is formed, and a memory electrode 3e to which the line memory pulse φLM2 is applied is formed above the charge accumulation region 5 that is second from the left in FIG. A memory electrode 3d to which a line memory pulse φLM3 is applied is formed above the fourth charge storage region 5, and a line memory pulse φLM4 is applied above the fourth charge storage region 5 from the left in FIG. Memory Pole 3c are formed. The line memory pulses φLM1 to φLM4 can take a high level state and a low level state, respectively.

Hereinafter, the operation of the solid-state imaging device having such a configuration will be described.
FIG. 9 is a diagram for explaining the charge transfer operation from the line memory to the horizontal charge transfer path of the solid-state imaging device shown in FIG. In FIG. 9, a timing chart of the transfer pulses φH1 and φH2 and the line memory pulses φLM1 to φLM4 is shown on the left side, and the state of charge at each timing shown on the left side is shown on the right side. Here, the case where the arrangement of the photoelectric conversion elements included in the solid-state imaging element is the arrangement shown in FIG. 6 will be described as an example.

  FIG. 9A shows a state where charges obtained from the photoelectric conversion elements for two lines of the solid-state imaging device are accumulated in a large number of charge accumulation regions 5. In this state, φH1 and φH2 are at a low level, φLM1 to φLM4 are at a high level, a potential well is formed in the charge storage region 5, and each charge transfer stage of the horizontal charge transfer path 2 has a barrier for this potential well. Forming.

  Next, as shown in FIG. 9B, φLM1 is set to the low level and φH2 is set to the high level, and the charge storage region below the memory electrode 3f corresponding to the charge transfer stage is placed in the charge transfer stage below the electrode set D1. The charge “R” in 5 is moved. Thereafter, φH2 is set to the low level and φH1 is set to the high level to transfer the charge “R” to the adjacent charge transfer stage. By repeating such transfer operation, a signal corresponding to the charge “R” is transferred to the horizontal charge. Output from the output amplifier connected to the end of the path 2.

  After the signal corresponding to the charge “R” is output, φLM1 to φLM4, φH1, and φH2 are set to the state shown in FIG. 9A, and then φLM2 is set to the low level and φH2 is set to the high level as shown in FIG. At a level, the charge “G1” in the charge accumulation region 5 below the memory electrode 3e corresponding to the charge transfer stage is moved to the charge transfer stage below the electrode set D1. Thereafter, φH2 is set to the low level and φH1 is set to the high level to transfer the charge “G1” to the adjacent charge transfer stage. By repeating such transfer operation, the signal corresponding to the charge “G1” is transferred to the horizontal charge. Output from the output amplifier connected to the end of the path 2.

  After the signal corresponding to the charge “G1” is output, φLM1 to φLM4, φH1, and φH2 are set to the state shown in FIG. 9A, and then φLM3 is set to the low level and φH2 is set to the high level as shown in FIG. At a level, the charge “B” in the charge storage region 5 below the memory electrode 3d corresponding to the charge transfer stage is moved to the charge transfer stage below the electrode set D1. Thereafter, φH2 is set to low level and φH1 is set to high level to transfer the charge “B” to the adjacent charge transfer stage. By repeating such transfer operation, a signal corresponding to the charge “B” is transferred to the horizontal charge. Output from the output amplifier connected to the end of the path 2.

  After the signal corresponding to the charge “B” is output, φLM1 to φLM4, φH1, and φH2 are set to the state shown in FIG. 9A, and then φLM4 is set to the low level and φH2 is set to the high level as shown in FIG. At a level, the charge “G2” in the charge storage region 5 below the memory electrode 3c corresponding to the charge transfer stage is moved to the charge transfer stage below the electrode set D1. Thereafter, φH2 is set to low level and φH1 is set to high level to transfer the charge “G2” to the adjacent charge transfer stage. By repeating such transfer operation, a signal corresponding to the charge “G2” is transferred to the horizontal charge. Output from the output amplifier connected to the end of the path 2.

  After the signal corresponding to the charge “G2” is output, φLM1 to φLM4, φH1, and φH2 are set to the state shown in FIG. 9A, and then φLM1 is set to the low level and φH1 is set to the high level as shown in FIG. At a level, the charge “R” in the charge storage region 5 below the memory electrode 3f corresponding to the charge transfer stage is moved to the charge transfer stage below the electrode set D2. Thereafter, φH1 is set to the low level and φH2 is set to the high level to transfer the charge “R” to the adjacent charge transfer stage. By repeating such transfer operation, a signal corresponding to the charge “R” is transferred to the horizontal charge. Output from the output amplifier connected to the end of the path 2.

  After the signal corresponding to the charge “R” is output, after φLM1 to φLM4, φH1, and φH2 are set to the state of FIG. 9A, φLM2 is set to the low level and φH1 is set to the high level as shown in FIG. At a level, the charge “G1” in the charge accumulation region 5 below the memory electrode 3e corresponding to the charge transfer stage is moved to the charge transfer stage below the electrode set D2. Thereafter, φH1 is set to low level and φH2 is set to high level to transfer the charge “G1” to the adjacent charge transfer stage. By repeating such transfer operation, a signal corresponding to the charge “G1” is transferred to the horizontal charge. Output from the output amplifier connected to the end of the path 2.

  After the signal corresponding to the charge “G1” is output, φLM1 to φLM4, φH1, and φH2 are set to the state shown in FIG. 9A, and then φLM3 is set to the low level and φH1 is set to the high level as shown in FIG. At a level, the charge “B” in the charge storage region 5 below the memory electrode 3d corresponding to the charge transfer stage is moved to the charge transfer stage below the electrode set D2. Thereafter, φH1 is set to low level and φH2 is set to high level to transfer the charge “B” to the adjacent charge transfer stage. By repeating such transfer operation, a signal corresponding to the charge “B” is transferred to the horizontal charge. Output from the output amplifier connected to the end of the path 2.

  After the signal corresponding to the charge “B” is output, φLM1 to φLM4, φH1, and φH2 are set to the state shown in FIG. 9A, and then φLM4 is set to the low level and φH1 is set to the high level as shown in FIG. At a level, the charge “G2” in the charge storage region 5 below the memory electrode 3c corresponding to the charge transfer stage is moved to the charge transfer stage below the electrode set D2. Thereafter, φH1 is set to low level and φH2 is set to high level to transfer the charge “G2” to the adjacent charge transfer stage. By repeating such transfer operation, a signal corresponding to the charge “G2” is transferred to the horizontal charge. Output from the output amplifier connected to the end of the path 2.

  With this operation, the transfer of charges for two lines is completed.

  As described above, by connecting the four vertical charge transfer paths 1 to each charge transfer stage of the horizontal charge transfer path 2, the horizontal width A ″ of the charge transfer stage can be increased as compared with the solid-state imaging device of the first embodiment. According to the configuration of the present embodiment, for example, when the driving is terminated at the time of FIG. It becomes.

(Second embodiment)
FIG. 10 is a schematic partial plan view showing a schematic configuration of the solid-state imaging device according to the second embodiment of the present invention. In FIG. 10, the same components as those in FIG.
The solid-state imaging device shown in FIG. 10 is the same as the solid-state imaging device shown in FIG. 1, but the memory electrodes 3a and 3b above each of the two charge storage regions 5 that are connected to different charge transfer stages and are adjacent to each other. It has become a structure.

  As shown in FIG. 10, a single-layer memory electrode 6a or memory electrode 6b is formed above two adjacent charge storage regions 5 connected to different charge transfer stages. Has been. The memory electrodes 6a and the memory electrodes 6b are arranged alternately in the horizontal direction X. A line memory pulse φLM2 is applied to the memory electrode 6a, and a line memory pulse φLM1 is applied to the memory electrode 6b. The line memory pulses φLM1 and φLM2 can take a high level state and a low level state, respectively.

Hereinafter, the operation of the solid-state imaging device having such a configuration will be described.
FIG. 11 is a diagram for explaining the charge transfer operation from the line memory of the solid-state imaging device shown in FIG. 10 to the horizontal charge transfer path. In FIG. 11, the timing chart of the transfer pulses φH1 and φH2 and the line memory pulses φLM1 and φLM2 is shown on the left side, and the state of charge at each timing shown on the left side is shown on the right side. Here, the case where the arrangement of the photoelectric conversion elements included in the solid-state imaging element is the arrangement shown in FIG. 6 will be described as an example.

  FIG. 11A shows a state where charges obtained from the photoelectric conversion elements for two lines of the solid-state imaging element are accumulated in a large number of charge accumulation regions 5. In this state, φH1 and φH2 are at a low level, φLM1 and φLM2 are at a high level, a potential well is formed in the charge storage region 5, and each charge transfer stage of the horizontal charge transfer path 2 has a barrier for this potential well. Forming.

  Next, as shown in FIG. 11B, φLM2 is set to a low level and φH2 is set to a high level, so that two charge storage regions 5 connected to the charge transfer stage are connected to the charge transfer stage below the electrode set D1. Among them, the charge “R” in the charge storage region 5 below the memory electrode 6a is moved. Thereafter, φH2 is set to the low level and φH1 is set to the high level to transfer the charge “R” to the adjacent charge transfer stage. By repeating such transfer operation, a signal corresponding to the charge “R” is transferred to the horizontal charge. Output from the output amplifier connected to the end of the path 2.

  After the signal corresponding to the charge “R” is output, φLM2, φLM1, φH1, and φH2 are set to the state shown in FIG. 11A, and then φLM1 is set to the low level and φH2 is set to the high level as shown in FIG. At a level, the charge “G1” in the charge storage region 5 below the memory electrode 6b, of the two charge storage regions 5 connected to the charge transfer stage, is moved to the charge transfer stage below the electrode set D1. Thereafter, φH2 is set to the low level and φH1 is set to the high level to transfer the charge “G1” to the adjacent charge transfer stage. By repeating such transfer operation, the signal corresponding to the charge “G1” is transferred to the horizontal charge. Output from the output amplifier connected to the end of the path 2.

  After the signal corresponding to the charge “G1” is output, φLM2, φLM1, φH1, and φH2 are set to the state shown in FIG. 11A, then φLM1 is set to the low level and φH1 is set to the high level as shown in FIG. At a level, the charge “B” in the charge storage region 5 below the memory electrode 6b is transferred to the charge transfer stage below the electrode set D2 out of the two charge storage regions 5 connected to the charge transfer stage. Thereafter, φH1 is set to low level and φH2 is set to high level to transfer the charge “B” to the adjacent charge transfer stage. By repeating such transfer operation, a signal corresponding to the charge “B” is transferred to the horizontal charge. Output from the output amplifier connected to the end of the path 2.

  After the signal corresponding to the charge “B” is output, φLM2, φLM1, φH1, and φH2 are set to the state shown in FIG. 11A, then φLM2 is set low and φH1 is set high as shown in FIG. At a level, the charge “G2” in the charge storage region 5 below the memory electrode 6a, of the two charge storage regions 5 connected to the charge transfer stage, is moved to the charge transfer stage below the electrode set D2. Thereafter, φH1 is set to low level and φH2 is set to high level to transfer the charge “G2” to the adjacent charge transfer stage. By repeating such transfer operation, a signal corresponding to the charge “G2” is transferred to the horizontal charge. Output from the output amplifier connected to the end of the path 2.

  With this operation, the transfer of charges for two lines is completed.

  As described above, according to the solid-state imaging device of the present embodiment, two vertical charge transfer paths 1 are connected to one charge transfer stage, and the charge storage region 5 connected to the two vertical charge transfer paths 1 is above. By making it possible to independently apply a voltage to each of the memory electrodes 6a and 6b, it is possible to select the charges transferred to the horizontal charge transfer path 2 in the line memory LM.

  Therefore, even when the same pixel pitch as in FIG. 29 is realized, the horizontal width (A ′ in FIG. 10) of the charge transfer stage is shown in FIG. 29 while maintaining the horizontal width of the horizontal charge transfer path 2. It can be expanded more than anything. As a result, the charge transfer capacity of the horizontal charge transfer path 2 can be increased without increasing the power consumption. In addition, since the number of charge transfer stages can be reduced, it is possible to prevent deterioration of transfer efficiency.

  Further, according to the solid-state imaging device of the present embodiment, the number of memory electrodes is halved compared to the solid-state imaging device shown in FIG. Therefore, a margin can be given to the design of the mask pattern. Further, since the gap between the memory electrodes is also halved, it is possible to provide a margin for the design of the mask pattern for forming the memory electrode.

  The solid-state imaging device described in the above embodiments can be used by being mounted on an imaging apparatus such as a digital camera or a digital video camera. When mounted in an image pickup apparatus, an image sensor driving unit provided in the image pickup apparatus performs various driving such as thinning-out reading driving and multi-field reading driving by controlling line memory pulses in accordance with the shooting mode. Therefore, it is possible to perform shooting according to various shooting scenes without complicating the driving of the vertical charge transfer path 1. In the following embodiments, a driving method for driving the solid-state imaging device having the above-described configuration will be described in detail.

(Third embodiment)
In the present embodiment, a method of driving the horizontal charge transfer path 2 of the solid-state imaging device having the configuration shown in FIG. 1 with the transfer pulses φH1 to φH6 in six phases will be described.

FIG. 12 is a diagram showing an example of wiring necessary for driving the horizontal charge transfer path 2 of the solid-state imaging device having the configuration shown in FIG. 1 in six phases. In FIG. 12, the same components as those in FIG.
A plurality of electrode sets are provided above the horizontal charge transfer path 2 of the solid-state image pickup device shown in FIG. 1, but the solid-state image pickup device shown in FIG. The electrode set H1 to which the transfer pulse φH1 is applied from the drive unit, the electrode set H2 to which the transfer pulse φH2 is applied from the image sensor driving unit, the electrode set H3 to which the transfer pulse φH3 is applied from the image sensor drive unit, and the imaging An electrode set H4 to which the transfer pulse φH4 is applied from the element driving unit, an electrode set H5 to which the transfer pulse φH5 is applied from the image sensor driving unit, and an electrode set H6 to which the transfer pulse φH6 is applied from the image sensor driving unit. It is a configuration that includes. The transfer pulses φH1 to φH6 can take a high level state and a low level state, respectively.

  These electrode groups are arranged in such a manner that an electrode group group in which electrode groups H1, H2, H3, H4, H5, H6, H3, and H4 are arranged in this order is repeatedly arranged in the horizontal direction.

  Next, a method for driving the solid-state imaging device shown in FIG. 12 will be described. Hereinafter, the arrangement of the photoelectric conversion elements of the solid-state imaging element will be described as shown in FIG.

<First driving method>
FIGS. 13 to 15 are diagrams for explaining a first driving method for driving the solid-state imaging device shown in FIG. 12. Line memory pulses φLM1, φLM2 and transfer pulses supplied to the solid-state imaging device shown in FIG. It is the figure which showed together the timing chart of (phi) H1- (phi) H6, and the potential of the horizontal charge transfer path 2 under the electrode group H1-H6 in the time t1-t42.

  At time t3, φLM1 is set to the low level, and the charge accumulation region 5 below the memory electrode 3a to which φLM1 is applied is accumulated in the charge accumulation region 5 connected to the charge transfer stage below the electrode sets H3 and H5. The R charge is transferred to the charge transfer stage.

  Next, the transfer pulses φH1 to φH6 are controlled as shown in the figure between time t4 and t8, and among the R charges transferred to the horizontal charge transfer path 2 at time t3, three adjacent R charges are transferred horizontally. Mix on path 2. This mixed charge is transferred to the horizontal charge transfer path 2 below the electrode set H2 at time t9.

  Next, at time t11, φLM1 is set to a low level, and among the charge accumulation regions 5 below the memory electrode 3a to which φLM1 is applied, the charge accumulation regions 5 connected to the charge transfer stages below the electrode sets H4 and H6 are applied. The accumulated B charge is transferred to the charge transfer stage.

  Next, the transfer pulses φH1 to φH6 are controlled as shown in the figure between time t12 and t17, and among the B charges transferred to the horizontal charge transfer path 2 at time t11, three adjacent B charges are transferred horizontally. Mix on path 2.

  Next, at time t19, φLM1 is set to the low level, and the charge accumulation region 5 below the memory electrode 3a to which φLM1 is applied is accumulated in the charge accumulation region 5 connected to the charge transfer stage below the electrode set H1. The R charge is transferred to the charge transfer stage. Since there are three mixed R charges in the charge transfer stage, the mixing of the four R charges is completed at time t19.

  Next, during the time t20 to t23, the transfer pulses φH1 to φH6 are controlled as shown in the figure to transfer the four mixed R charges to the horizontal charge transfer path 2 below the electrode set H6, and the three mixed B The charge is transferred to the horizontal charge transfer path 2 below the electrode set H2.

  Next, at time t25, φLM1 is set to the low level, and the charge accumulation region 5 below the memory electrode 3a to which φLM1 is applied is accumulated in the charge accumulation region 5 connected to the charge transfer stage below the electrode set H2. The B charge is transferred to the charge transfer stage. Since there are three mixed B charges in the charge transfer stage, the mixing of the four B charges is completed at time t25.

  Next, at time t28, φLM2 is set to low level, and the charge accumulation region 5 below the memory electrode 3b to which φLM2 is applied is accumulated in the charge accumulation region 5 connected to the charge transfer stage below the electrode set H4. The G charge is transferred to the charge transfer stage.

  Next, at time t30, the G charge in the horizontal charge transfer path 2 below the electrode set H4 is transferred to the horizontal charge transfer path 2 below the electrode set H3.

  Next, at time t32, φLM2 is set to the low level, and the charge accumulation region 5 below the memory electrode 3b to which φLM2 is applied is accumulated in the charge accumulation region 5 connected to the charge transfer stage below the electrode set H3. The G charge is transferred to the charge transfer stage.

  Next, at time t34, the two mixed G charges existing in the horizontal charge transfer path 2 below the electrode set H3 are transferred to the horizontal charge transfer path 2 below the electrode set H2 or the electrode set H6.

  Next, at time t36, φLM2 is set to a low level, and among the charge accumulation regions 5 below the memory electrode 3b to which φLM2 is applied, the charge accumulation region 5 connected to the charge transfer stage below the electrode sets H2 and H6 is applied. The accumulated G charge is transferred to the charge transfer stage.

  Next, at time t38, the mixed three G charges in the horizontal charge transfer path 2 below the electrode set H2 are transferred to the horizontal charge transfer path 2 below the adjacent electrode set H1, and below the electrode set H6. The three mixed G charges in the horizontal charge transfer path 2 are transferred to the horizontal charge transfer path 2 below the adjacent electrode set H5.

  Next, at time t40, φLM2 is set to a low level, and among the charge accumulation regions 5 below the memory electrode 3b to which φLM2 is applied, the charge accumulation regions 5 connected to the charge transfer stages below the electrode sets H1 and H5 The accumulated G charge is transferred to the charge transfer stage. Since there are three mixed G charges in the charge transfer stage, the mixing of the four G charges is completed at time t40.

  Thereafter, by controlling the transfer pulses φH1 to φH6, the mixed R charge, G charge, and B charge are sequentially transferred in the horizontal direction X, and the output of the signal corresponding to the charge for one line is completed. By performing such processing for all lines, signals can be acquired from all photoelectric conversion elements.

  As described above, according to the solid-state imaging device having the configuration shown in FIG. 12, the charge transfer process from the charge storage region 5 to the horizontal charge transfer path 2 is performed using the line memory pulses φLM1, φLM2 and the transfer pulses φH1 to φH6. It can be finely controlled by the combination. Therefore, the process of mixing four charges of the same color component among the charges accumulated in all the charge accumulation regions 5 in the horizontal charge transfer path 2 can be realized with only 40 pulse changes. Compared with the case where the process of mixing four charges is performed in the configuration, the processing time can be greatly shortened. As a result, by adopting this four-pixel mixing process in the moving image shooting mode or the like, a high frame rate can be achieved even when the number of pixels is increased.

  In addition, according to the first driving method, since the charge arrangement does not change even after the charge mixing process, it is possible to generate image data without performing special signal processing. Rate can be realized.

<Second driving method>
Next, another example of the driving method of the solid-state imaging device having the configuration shown in FIG. 12 will be described.

  16 to 18 are diagrams for explaining a second driving method for driving the solid-state imaging device shown in FIG. 12. Line memory pulses φLM1 and φLM2 and transfer pulses supplied to the solid-state imaging device shown in FIG. It is the figure which showed together the timing chart of (phi) H1- (phi) H6, and the potential of the horizontal charge transfer path 2 under the electrode groups H1-H6 in the time t1-t46.

  At time t3, φLM1 is set to the low level, and the charge accumulation region 5 below the memory electrode 3a to which φLM1 is applied is accumulated in the charge accumulation region 5 connected to the charge transfer stage below the electrode sets H3 and H5. The R charge is transferred to the charge transfer stage.

  Next, the transfer pulses φH1 to φH6 are controlled as shown in the figure between time t4 and t8, and among the R charges transferred to the horizontal charge transfer path 2 at time t3, three adjacent R charges are transferred horizontally. Mix on path 2. This mixed charge is transferred to the horizontal charge transfer path 2 below the electrode set H2 at time t9.

  Next, at time t11, φLM1 is set to a low level, and among the charge accumulation regions 5 below the memory electrode 3a to which φLM1 is applied, the charge accumulation regions 5 connected to the charge transfer stages below the electrode sets H4 and H6 are applied. The accumulated B charge is transferred to the charge transfer stage.

  Next, the transfer pulses φH1 to φH6 are controlled as shown in the figure between times t12 and t18, and among the B charges transferred to the horizontal charge transfer path 2 at time t11, three adjacent B charges are transferred horizontally. Mix on path 2.

  In the first driving method shown in FIGS. 13 to 15, when the three R charges below the electrode set H2 are transferred below the adjacent electrode set H1 from time t12 to t13, The potential of the horizontal charge transfer path 2 is transferred while changing from low level to high level. In this case, R charge may flow into another charge transfer stage. Therefore, in the second driving method, the potential of the packet in which the R charge is accumulated is set to the high level at time t13, and then the R charge in the packet is transferred below the adjacent electrode set H1. By doing in this way, it becomes possible to prevent the above-mentioned transfer omission.

  Next, at time t20, φLM1 is set to the low level, and the charge accumulation region 5 below the memory electrode 3a to which φLM1 is applied is accumulated in the charge accumulation region 5 connected to the charge transfer stage below the electrode set H1. The R charge is transferred to the charge transfer stage. Since there are three mixed R charges in the charge transfer stage, the mixing of the four R charges is completed at time t20.

  Next, between the times t21 and t24, the transfer pulses φH1 to φH6 are controlled as shown in the figure to transfer the four mixed R charges to the horizontal charge transfer path 2 below the electrode set H6, and the three mixed B The charge is transferred to the horizontal charge transfer path 2 below the electrode set H2.

  Next, at time t26, φLM1 is set to the low level, and the charge accumulation region 5 below the memory electrode 3a to which φLM1 is applied is accumulated in the charge accumulation region 5 connected to the charge transfer stage below the electrode set H2. The B charge is transferred to the charge transfer stage. Since there are three mixed B charges in the charge transfer stage, the mixing of the four B charges is completed at time t26.

  Next, at time t29, φLM2 is set to low level, and the charge accumulation region 5 below the memory electrode 3b to which φLM2 is applied is accumulated in the charge accumulation region 5 connected to the charge transfer stage below the electrode set H4. The G charge is transferred to the charge transfer stage.

  Next, in order to prevent charge leakage as described above, the potential of the horizontal charge transfer path 2 below the electrode set H6 and the electrode set H2 is raised to a high level at time t31. Next, at time t32, the G charge in the horizontal charge transfer path 2 below the electrode set H4 is transferred to the horizontal charge transfer path 2 below the electrode set H3.

  Next, at time t34, φLM2 is set to the low level, and the charge accumulation region 5 below the memory electrode 3b to which φLM2 is applied is accumulated in the charge accumulation region 5 connected to the charge transfer stage below the electrode set H3. The G charge is transferred to the charge transfer stage.

  Next, in order to prevent the charge leakage as described above, the potential of the horizontal charge transfer path 2 below the electrode set H5 and the electrode set H1 is set to a high level at time t36. Next, at time t37, the two mixed G charges that were in the horizontal charge transfer path 2 below the electrode set H3 are transferred to the horizontal charge transfer path 2 below the electrode set H2 or the electrode set H6.

  Next, at time t39, φLM2 is set to the low level, and among the charge accumulation regions 5 below the memory electrode 3b to which φLM2 is applied, the charge accumulation regions 5 connected to the charge transfer stages below the electrode sets H2 and H6 The accumulated G charge is transferred to the charge transfer stage.

  Next, in order to prevent charge leakage as described above, the potential of the horizontal charge transfer path 2 below the electrode set H4 is set to a high level at time t41. Next, at time t42, the mixed three G charges in the horizontal charge transfer path 2 below the electrode set H2 are transferred to the horizontal charge transfer path 2 below the adjacent electrode set H1, and below the electrode set H6. The three mixed G charges in the horizontal charge transfer path 2 are transferred to the horizontal charge transfer path 2 below the adjacent electrode set H5.

  Next, at time t44, φLM2 is set to a low level, and among the charge accumulation regions 5 below the memory electrode 3b to which φLM2 is applied, the charge accumulation regions 5 connected to the charge transfer stages below the electrode sets H1 and H5 The accumulated G charge is transferred to the charge transfer stage. Since there are three mixed G charges in the charge transfer stage, the mixing of the four G charges is completed at time t44.

  Thereafter, by controlling the transfer pulses φH1 to φH6, the mixed R charge, G charge, and B charge are sequentially transferred in the horizontal direction X, and the output of the signal corresponding to the charge for one line is completed. By performing such processing for all lines, signals can be acquired from all photoelectric conversion elements.

  As described above, according to the second driving method, it is possible to prevent charge transfer leakage that may occur in the first driving method, and it is possible to shoot a moving image with a high frame rate and high image quality.

(Fourth embodiment)
In the present embodiment, a method of driving the horizontal charge transfer path 2 of the solid-state imaging device having the configuration shown in FIG. 10 with 6-phase transfer pulses φH1 to φH6 will be described.

FIG. 19 is a diagram showing an example of wiring necessary for driving the horizontal charge transfer path 2 of the solid-state imaging device having the configuration shown in FIG. 10 in six phases. 19, the same components as those in FIG. 10 are denoted by the same reference numerals.
A plurality of electrode sets are provided above the horizontal charge transfer path 2 of the solid-state image pickup device shown in FIG. 10, but the solid-state image pickup device shown in FIG. The electrode set H1 to which the transfer pulse φH1 is applied from the drive unit, the electrode set H2 to which the transfer pulse φH2 is applied from the image sensor driving unit, the electrode set H3 to which the transfer pulse φH3 is applied from the image sensor drive unit, and the imaging An electrode set H4 to which the transfer pulse φH4 is applied from the element driving unit, an electrode set H5 to which the transfer pulse φH5 is applied from the image sensor driving unit, and an electrode set H6 to which the transfer pulse φH6 is applied from the image sensor driving unit. It is a configuration that includes. The transfer pulses φH1 to φH6 can take a high level state and a low level state, respectively.

  These electrode groups are arranged in such a manner that an electrode group group in which electrode groups H1, H2, H3, H4, H5, H6, H3, and H4 are arranged in this order is repeatedly arranged in the horizontal direction.

  Next, a method for driving the solid-state imaging device shown in FIG. 19 will be described. Hereinafter, the arrangement of the photoelectric conversion elements of the solid-state imaging element will be described as shown in FIG.

<First driving method>
20 to 22 are diagrams for explaining a first driving method for driving the solid-state imaging device shown in FIG. 19. Line memory pulses φLM1 and φLM2 and transfer pulses supplied to the solid-state imaging device shown in FIG. It is the figure which showed together the timing chart of (phi) H1- (phi) H6, and the potential of the horizontal charge transfer path 2 under the electrode group H1-H6 in the time t1-t42.

  At time t3, φLM1 is set to low level, and the charge accumulation region 5 below the memory electrode 6b to which φLM1 is applied is accumulated in the charge accumulation region 5 connected to the charge transfer stage below the electrode sets H3 and H5. The R charge is transferred to the charge transfer stage.

  Next, the transfer pulses φH1 to φH6 are controlled as shown in the figure between time t4 and t8, and among the R charges transferred to the horizontal charge transfer path 2 at time t3, three adjacent R charges are transferred horizontally. Mix on path 2. This mixed charge is transferred to the horizontal charge transfer path 2 below the electrode set H2 at time t9.

  Next, at time t11, φLM2 is set to a low level, and among the charge accumulation regions 5 below the memory electrode 6a to which φLM2 is applied, the charge accumulation regions 5 connected to the charge transfer stages below the electrode sets H4 and H6 The accumulated B charge is transferred to the charge transfer stage.

  Next, the transfer pulses φH1 to φH6 are controlled as shown in the figure between time t12 and t17, and among the B charges transferred to the horizontal charge transfer path 2 at time t11, three adjacent B charges are transferred horizontally. Mix on path 2.

  Next, at time t19, φLM1 is set to the low level, and the charge accumulation region 5 below the memory electrode 6b to which φLM1 is applied is accumulated in the charge accumulation region 5 connected to the charge transfer stage below the electrode set H1. The R charge is transferred to the charge transfer stage. Since there are three mixed R charges in the charge transfer stage, the mixing of the four R charges is completed at time t19.

  Next, during the time t20 to t24, the transfer pulses φH1 to φH6 are controlled as shown in the figure to transfer the four mixed R charges to the horizontal charge transfer path 2 below the electrode set H6, and the three mixed B The charge is transferred to the horizontal charge transfer path 2 below the electrode set H2.

  Next, at time t25, φLM2 is set to a low level, and the charge storage region 5 below the memory electrode 6a to which φLM2 is applied is stored in the charge storage region 5 connected to the charge transfer stage below the electrode set H2. The B charge is transferred to the charge transfer stage. Since there are three mixed B charges in the charge transfer stage, the mixing of the four B charges is completed at time t25.

  Next, at time t28, φLM1 is set to the low level, and the charge accumulation region 5 below the memory electrode 6b to which φLM1 is applied is accumulated in the charge accumulation region 5 connected to the charge transfer stage below the electrode set H4. The G charge is transferred to the charge transfer stage.

  Next, at time t30, the G charge in the horizontal charge transfer path 2 below the electrode set H4 is transferred to the horizontal charge transfer path 2 below the electrode set H3.

  Next, at time t32, φLM2 is set to a low level, and the charge accumulation region 5 below the memory electrode 6a to which φLM2 is applied is accumulated in the charge accumulation region 5 connected to the charge transfer stage below the electrode set H3. The G charge is transferred to the charge transfer stage.

  Next, at time t34, the two mixed G charges existing in the horizontal charge transfer path 2 below the electrode set H3 are transferred to the horizontal charge transfer path 2 below the electrode set H2 or the electrode set H6.

  Next, at time t36, φLM1 is set to a low level, and among the charge accumulation regions 5 below the memory electrode 6b to which φLM1 is applied, the charge accumulation regions 5 connected to the charge transfer stages below the electrode sets H2 and H6 are applied. The accumulated G charge is transferred to the charge transfer stage.

  Next, at time t38, the mixed three G charges in the horizontal charge transfer path 2 below the electrode set H2 are transferred to the horizontal charge transfer path 2 below the adjacent electrode set H1, and below the electrode set H6. The three mixed G charges in the horizontal charge transfer path 2 are transferred to the horizontal charge transfer path 2 below the adjacent electrode set H5.

  Next, at time t40, φLM2 is set to a low level, and among the charge storage regions 5 below the memory electrode 6a to which φLM2 is applied, the charge storage regions 5 connected to the charge transfer stages below the electrode sets H1 and H5 The accumulated G charge is transferred to the charge transfer stage. Since there are three mixed G charges in the charge transfer stage, the mixing of the four G charges is completed at time t40.

  Thereafter, by controlling the transfer pulses φH1 to φH6, the mixed R charge, G charge, and B charge are sequentially transferred in the horizontal direction X, and the output of the signal corresponding to the charge for one line is completed. By performing such processing for all lines, signals can be acquired from all photoelectric conversion elements.

  As described above, according to the solid-state imaging device having the configuration shown in FIG. 19, the charge transfer process from the charge storage region 5 to the horizontal charge transfer path 2 is performed using the line memory pulses φLM1 and φLM2 and the transfer pulses φH1 to φH6. It can be finely controlled by the combination. Therefore, the process of mixing four charges of the same color component among the charges accumulated in all the charge accumulation regions 5 in the horizontal charge transfer path 2 can be realized with only 40 pulse changes. Compared with the case where the process of mixing four charges is performed in the configuration, the processing time can be greatly shortened. As a result, by adopting this four-pixel mixing process in the moving image shooting mode or the like, a high frame rate can be achieved even when the number of pixels is increased.

  In addition, according to this driving method, the charge arrangement does not change even after the charge mixing process, so that it is possible to generate image data without performing special signal processing. Can be realized.

<Second driving method>
23 to 25 are diagrams for explaining a second driving method for driving the solid-state imaging device shown in FIG. 19. Line memory pulses φLM1 and φLM2 and transfer pulses supplied to the solid-state imaging device shown in FIG. It is the figure which showed together the timing chart of (phi) H1- (phi) H6, and the potential of the horizontal charge transfer path 2 under the electrode groups H1-H6 in the time t1-t46.

  At time t3, φLM1 is set to low level, and the charge accumulation region 5 below the memory electrode 6b to which φLM1 is applied is accumulated in the charge accumulation region 5 connected to the charge transfer stage below the electrode sets H3 and H5. The R charge is transferred to the charge transfer stage.

  Next, the transfer pulses φH1 to φH6 are controlled as shown in the figure between time t4 and t8, and among the R charges transferred to the horizontal charge transfer path 2 at time t3, three adjacent R charges are transferred horizontally. Mix on path 2. This mixed charge is transferred to the horizontal charge transfer path 2 below the electrode set H2 at time t9.

  Next, at time t11, φLM2 is set to a low level, and among the charge accumulation regions 5 below the memory electrode 6a to which φLM2 is applied, the charge accumulation regions 5 connected to the charge transfer stages below the electrode sets H4 and H6 The accumulated B charge is transferred to the charge transfer stage.

  Next, the transfer pulses φH1 to φH6 are controlled as shown in the figure between times t12 and t18, and among the B charges transferred to the horizontal charge transfer path 2 at time t11, three adjacent B charges are transferred horizontally. Mix on path 2.

  In the first driving method, when the three R charges below the electrode set H2 are transferred below the adjacent electrode set H1 from time t12 to t13, the potential of the horizontal charge transfer path 2 below the electrode set H2 is Data is transferred from low level to high level. In this case, R charge may flow into another charge transfer stage. Therefore, in the second driving method, the potential of the packet in which the R charge is accumulated is set to the high level at time t13, and then the R charge in the packet is transferred below the adjacent electrode set H1. By doing in this way, it becomes possible to prevent the above-mentioned transfer omission.

  Next, at time t20, φLM1 is set to the low level, and the charge accumulation region 5 below the memory electrode 6b to which φLM1 is applied is accumulated in the charge accumulation region 5 connected to the charge transfer stage below the electrode set H1. The R charge is transferred to the charge transfer stage. Since there are three mixed R charges in the charge transfer stage, the mixing of the four R charges is completed at time t20.

  Next, between the times t21 and t24, the transfer pulses φH1 to φH6 are controlled as shown in the figure to transfer the four mixed R charges to the horizontal charge transfer path 2 below the electrode set H6, and the three mixed B The charge is transferred to the horizontal charge transfer path 2 below the electrode set H2.

  Next, at time t26, φLM2 is set to low level, and the charge accumulation region 5 below the memory electrode 6a to which φLM2 is applied is accumulated in the charge accumulation region 5 connected to the charge transfer stage below the electrode set H2. The B charge is transferred to the charge transfer stage. Since there are three mixed B charges in the charge transfer stage, the mixing of the four B charges is completed at time t26.

  Next, at time t29, φLM1 is set to low level, and the charge accumulation region 5 below the memory electrode 6b to which φLM1 is applied is accumulated in the charge accumulation region 5 connected to the charge transfer stage below the electrode set H4. The G charge is transferred to the charge transfer stage.

  Next, in order to prevent charge leakage as described above, the potential of the horizontal charge transfer path 2 below the electrode set H6 and the electrode set H2 is raised to a high level at time t31. Next, at time t32, the G charge in the horizontal charge transfer path 2 below the electrode set H4 is transferred to the horizontal charge transfer path 2 below the electrode set H3.

  Next, at time t34, φLM2 is set to the low level, and the charge accumulation region 5 below the memory electrode 6a to which φLM2 is applied is accumulated in the charge accumulation region 5 connected to the charge transfer stage below the electrode set H3. The G charge is transferred to the charge transfer stage.

  Next, in order to prevent charge leakage as described above, the potential of the horizontal charge transfer path 2 below the electrode set H5 and the electrode set H1 is raised to high level at time t36. Next, at time t37, the two mixed G charges that were in the horizontal charge transfer path 2 below the electrode set H3 are transferred to the horizontal charge transfer path 2 below the electrode set H2 or the electrode set H6.

  Next, at time t39, φLM1 is set to the low level, and among the charge accumulation regions 5 below the memory electrode 6b to which φLM1 is applied, the charge accumulation regions 5 connected to the charge transfer stages below the electrode sets H2 and H6 are applied. The accumulated G charge is transferred to the charge transfer stage.

  Next, in order to prevent charge leakage as described above, the potential of the horizontal charge transfer path 2 below the electrode set H4 is set to a high level at time t41. Next, at time t42, the mixed three G charges in the horizontal charge transfer path 2 below the electrode set H2 are transferred to the horizontal charge transfer path 2 below the adjacent electrode set H1, and below the electrode set H6. The three mixed G charges in the horizontal charge transfer path 2 are transferred to the horizontal charge transfer path 2 below the adjacent electrode set H5.

  Next, at time t44, φLM2 is set to a low level, and among the charge accumulation regions 5 below the memory electrode 6a to which φLM2 is applied, the charge accumulation regions 5 connected to the charge transfer stages below the electrode sets H1 and H5 The accumulated G charge is transferred to the charge transfer stage. Since there are three mixed G charges in the charge transfer stage, the mixing of the four G charges is completed at time t44.

  Thereafter, by controlling the transfer pulses φH1 to φH6, the mixed R charge, G charge, and B charge are sequentially transferred in the horizontal direction X, and the output of the signal corresponding to the charge for one line is completed. By performing such processing for all lines, signals can be acquired from all photoelectric conversion elements.

  As described above, according to the second driving method, it is possible to prevent charge transfer leakage that may occur in the first driving method, and it is possible to shoot a moving image with a high frame rate and high image quality.

(Fifth embodiment)
In the present embodiment, a method of driving the horizontal charge transfer path 2 of the solid-state imaging device having the configuration shown in FIG. 10 with eight transfer pulses φH1 to φH8 will be described.

FIG. 26 is a diagram showing an example of wiring necessary for driving the horizontal charge transfer path 2 of the solid-state imaging device having the configuration shown in FIG. In FIG. 26, the same components as those in FIG.
A plurality of electrode sets are provided above the horizontal charge transfer path 2 of the solid-state imaging device shown in FIG. 1, but the solid-state imaging device shown in FIG. 26 has an imaging device mounted on an imaging device (not shown). The electrode set H1 to which the transfer pulse φH1 is applied from the drive unit, the electrode set H2 to which the transfer pulse φH2 is applied from the image sensor driving unit, the electrode set H3 to which the transfer pulse φH3 is applied from the image sensor drive unit, and the imaging An electrode set H4 to which the transfer pulse φH4 is applied from the element drive unit, an electrode set H5 to which the transfer pulse φH5 is applied from the image sensor drive unit, an electrode set H6 to which the transfer pulse φH6 is applied from the image sensor drive unit, The configuration includes an electrode set H7 to which the transfer pulse φH7 is applied from the image sensor driving unit and an electrode set H8 to which the transfer pulse φH8 is applied from the image sensor driving unit. The transfer pulses φH1 to φH8 can take a high level state and a low level state, respectively.

  These electrode sets are arranged in such a manner that an electrode set group in which electrode sets H1, H2, H3, H4, H5, H6, H7, and H8 are arranged in this order is repeatedly arranged in the horizontal direction.

  Next, a method for driving the solid-state imaging device shown in FIG. 26 will be described. Hereinafter, the arrangement of the photoelectric conversion elements of the solid-state imaging element will be described as shown in FIG.

  27 to 28 are diagrams for explaining a method of driving the solid-state imaging device shown in FIG. 26. Timings of the line memory pulses φLM1 and φLM2 and the transfer pulses φH1 to φH8 supplied to the solid-state imaging device shown in FIG. It is the figure which combined and showed the chart and the potential of the horizontal charge transfer path 2 below the electrode sets H1 to H8 at times t1 to t30.

  At time t3, φLM1 is set to a low level, and among the charge storage regions 5 below the memory electrode 6b to which φLM1 is applied, the charge storage regions 5 connected to the charge transfer stages below the electrode sets H3, H5, and H7 The accumulated R charge is transferred to the charge transfer stage.

  Next, the transfer pulses φH1 to φH8 are controlled as shown in the figure between time t4 and t7, and among the R charges transferred to the horizontal charge transfer path 2 at time t3, three adjacent R charges are transferred horizontally. Mix on path 2. This mixed charge is transferred to the horizontal charge transfer path 2 below the electrode set H2 at time t8.

  Next, at time t9, φLM2 is set to a low level, and among the charge storage regions 5 below the memory electrode 6a to which φLM2 is applied, the charge storage connected to the charge transfer stage below the electrode sets H3, H6, and H8. The B charge or G charge stored in the region 5 is transferred to the charge transfer stage.

  Next, the transfer pulses φH1 to φH8 are controlled as shown in the drawing between times t10 and t12, and two adjacent B charges transferred among the B charges transferred to the horizontal charge transfer path 2 at time t9 are transferred horizontally. Mix on path 2.

  Next, at time t14, φLM1 is set to low level, and among the charge accumulation regions 5 below the memory electrode 6b to which φLM1 is applied, the charge accumulation regions 5 connected to the charge transfer stages below the electrode sets H4 and H8 are applied. The accumulated G charge is transferred to the charge transfer stage.

  Next, between the times t15 and t16, the transfer pulses φH1 to φH8 are controlled as shown in the figure to mix the two G charges below the electrode sets H3 and H4 on the horizontal charge transfer path 2.

  Next, at time t17, the B charges in the horizontal charge transfer path 2 below the electrode set H5 are transferred to the horizontal charge transfer path 2 below the electrode set H4.

  Next, at time t18, φLM2 is set to low level, and the charge accumulation region 5 below the memory electrode 6a to which φLM2 is applied is accumulated in the charge accumulation region 5 connected to the charge transfer stage below the electrode set H4. B charge is transferred to the charge transfer stage and is stored in the charge storage area 5 connected to the charge transfer stage below the electrode set H7 out of the charge storage area 5 below the memory electrode 6a to which φLM2 is applied. The G charge is transferred to the charge transfer stage.

  Next, at time t20, the mixed two G charges in the horizontal charge transfer path 2 below the electrode set H3 are transferred to the horizontal charge transfer path 2 below the adjacent electrode set H2, and below the electrode set H7. The two mixed G charges in the horizontal charge transfer path 2 are transferred to the horizontal charge transfer path 2 below the adjacent electrode set H6.

  Next, at time t21, φLM1 is set to a low level, and among the charge accumulation regions 5 below the memory electrode 6b to which φLM1 is applied, the charge accumulation regions 5 connected to the charge transfer stages below the electrode sets H2 and H6 are applied. The accumulated G charge is transferred to the charge transfer stage, and the charge accumulation area 5 below the memory electrode 6b to which φLM1 is applied is transferred to the charge accumulation area 5 connected to the charge transfer stage below the electrode set H1. The accumulated R charge is transferred to the charge transfer stage.

  Next, during the time t23 to t25, the transfer pulses φH1 to φH8 are controlled as shown in the figure to transfer the four R charges below the electrode set H1 to below the electrode set H7, and below the electrode set H2. The three G charges are transferred to the lower side of the adjacent electrode set H1, the three G charges that are below the electrode set H6 are transferred to the lower side of the adjacent electrode set H5, and the three B charges that are below the electrode set H4 are transferred. Transfer to the lower side of the adjacent electrode set H3.

  Next, at time t26, φLM2 is set to low level, and among the charge accumulation regions 5 below the memory electrode 6a to which φLM2 is applied, the charge accumulation regions 5 connected to the charge transfer stages below the electrode sets H1 and H5 The accumulated G charge is transferred to the charge transfer stage.

  Next, during the time t27 to t28, the transfer pulses φH1 to φH8 are controlled as shown in the figure to transfer the four R charges below the electrode set H7 to below the adjacent electrode set H6, and below the electrode set H1. 4 G charges were transferred to the lower side of the adjacent electrode set H8, and the four G charges existing below the electrode set H5 were transferred to the lower side of the adjacent electrode set H4, and the three B charges located below the electrode set H3 were transferred. The charge is transferred to the lower side of the adjacent electrode set H2.

  Next, at time t29, φLM2 is set to the low level, and the charge accumulation region 5 below the memory electrode 6b to which φLM2 is applied is accumulated in the charge accumulation region 5 connected to the charge transfer stage below the electrode set H2. The B charge is transferred to the charge transfer stage.

  Thereafter, by controlling the transfer pulses φH1 to φH8, the mixed R charge, G charge, and B charge are sequentially transferred in the horizontal direction X, and the output of the signal corresponding to the charge for one line is completed. By performing such processing for all lines, signals can be acquired from all photoelectric conversion elements.

  As described above, according to the solid-state imaging device having the configuration shown in FIG. 26, the charge transfer process from the charge storage region 5 to the horizontal charge transfer path 2 is performed using the line memory pulses φLM1 and φLM2 and the transfer pulses φH1 to φH8. It can be finely controlled by the combination. For this reason, the process of mixing four charges of the same color component among the charges accumulated in all the charge accumulation regions 5 in the horizontal charge transfer path 2 can be realized with only 29 pulse changes. Compared with the case where the process of mixing four charges is performed in the configuration, the processing time can be greatly shortened. As a result, by adopting this four-pixel mixing process in the moving image shooting mode or the like, a high frame rate can be achieved even when the number of pixels is increased.

  In addition, according to this driving method, the charge arrangement does not change even after the charge mixing process, so that it is possible to generate image data without performing special signal processing. Can be realized.

The partial plane schematic diagram which shows schematic structure of the solid-state image sensor which is 1st embodiment of this invention. Plane schematic diagram showing an example of the overall configuration of the solid-state imaging device of the first embodiment Partial enlarged view of the solid-state imaging device shown in FIG. Plane schematic diagram showing another example of the overall configuration of the solid-state imaging device of the first embodiment Partial enlarged view of the solid-state imaging device shown in FIG. The figure which shows the example of an arrangement | sequence of the photoelectric conversion element of the solid-state image sensor of 1st embodiment. The figure for demonstrating the charge transfer operation | movement to the horizontal charge transfer path from the line memory of the solid-state image sensor shown in FIG. The partial plane schematic diagram which shows schematic structure of the modification of the solid-state image sensor which is 1st embodiment of this invention. The figure for demonstrating the charge transfer operation | movement to the horizontal charge transfer path from the line memory of the solid-state image sensor shown in FIG. The partial plane schematic diagram which shows schematic structure of the solid-state image sensor which is 2nd embodiment of this invention. The figure for demonstrating the charge transfer operation | movement to the horizontal charge transfer path from the line memory of the solid-state image sensor shown in FIG. The figure which showed the example of wiring required in order to drive the horizontal charge transfer path of the solid-state image sensor of the structure shown in FIG. The figure for demonstrating the 1st drive method which drives the solid-state image sensor shown in FIG. The figure for demonstrating the 1st drive method which drives the solid-state image sensor shown in FIG. The figure for demonstrating the 1st drive method which drives the solid-state image sensor shown in FIG. The figure for demonstrating the 2nd drive method which drives the solid-state image sensor shown in FIG. The figure for demonstrating the 2nd drive method which drives the solid-state image sensor shown in FIG. The figure for demonstrating the 2nd drive method which drives the solid-state image sensor shown in FIG. The figure which showed the example of wiring required in order to drive the horizontal charge transfer path of the solid-state image sensor of the structure shown in FIG. The figure for demonstrating the 1st drive method which drives the solid-state image sensor shown in FIG. The figure for demonstrating the 1st drive method which drives the solid-state image sensor shown in FIG. The figure for demonstrating the 1st drive method which drives the solid-state image sensor shown in FIG. The figure for demonstrating the 2nd drive method which drives the solid-state image sensor shown in FIG. The figure for demonstrating the 2nd drive method which drives the solid-state image sensor shown in FIG. The figure for demonstrating the 2nd drive method which drives the solid-state image sensor shown in FIG. The figure which showed the example of wiring required in order to drive the horizontal charge transfer path of the solid-state image sensor of the structure shown in FIG. The figure for demonstrating the drive method of the solid-state image sensor shown in FIG. The figure for demonstrating the drive method of the solid-state image sensor shown in FIG. Partial enlarged view of a typical solid-state image sensor

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Vertical charge transfer path 2 Horizontal charge transfer path 3, 3a, 3b Memory electrode LM Line memory 5 Charge storage area 4a, 4b Transfer electrode D1, D2 Electrode set

Claims (10)

A photoelectric conversion element, a number of vertical charge transfer paths that transfer charges generated in the photoelectric conversion element in the vertical direction, and a charge transferred through the vertical charge transfer path is transferred in a horizontal direction orthogonal to the vertical direction. A solid-state imaging device having a horizontal charge transfer path,
The horizontal charge transfer path includes a plurality of charge transfer stages that operate as a charge accumulation region or a barrier region according to the level of an applied voltage,
A solid-state imaging device in which a plurality of the vertical charge transfer paths are connected to each of the plurality of charge transfer stages. The solid-state imaging device according to claim 1,
A line memory comprising a number of charge storage regions connecting each of the number of vertical charge transfer paths and the horizontal charge transfer path, and a memory electrode provided independently above each of the number of charge storage areas; Prepared,
A solid-state imaging device in which a voltage can be independently applied to each of the memory electrodes above each of the charge storage regions connecting the charge transfer stage and the plurality of vertical charge transfer paths. The solid-state imaging device according to claim 1,
A large number of charge storage regions connecting each of the large number of vertical charge transfer paths and the horizontal charge transfer path, and connected to the different charge transfer stages and independently above the two charge storage regions adjacent to each other. A line memory composed of memory electrodes provided as
The memory electrode is a solid-state imaging device including a first memory electrode and a second memory electrode to which a voltage can be applied independently. The solid-state imaging device according to claim 2 or 3,
The photoelectric conversion element includes three types of photoelectric conversion elements that detect light in different wavelength ranges,
In a state where charges are accumulated in each of the plurality of charge accumulation regions, the charge arrangement includes the charge of the first color component and the charge of the second color component sandwiching the charge of the third color component. A solid-state imaging device in which the arrangement of the three types of photoelectric conversion elements is determined so as to be arranged alternately in the horizontal direction. A solid-state imaging device according to claim 2;
Driving means for driving the solid-state imaging device,
Two vertical charge transfer paths are connected to the charge transfer stage,
The memory electrode includes a first memory electrode and a second memory electrode to which a voltage can be applied independently,
The driving means accumulates charges in each of the plurality of charge accumulation regions, and then applies a voltage to the first memory electrode and the second memory electrode and to each of the plurality of charge transfer stages. An image pickup apparatus that performs driving for mixing and transferring four charges of the same color component on the horizontal charge transfer path among a large number of charges stored in the charge storage region. A solid-state imaging device according to claim 3;
Driving means for driving the solid-state imaging device,
Two vertical charge transfer paths are connected to the charge transfer stage,
The driving means accumulates charges in each of the plurality of charge accumulation regions, and then applies a voltage to the first memory electrode and the second memory electrode and to each of the plurality of charge transfer stages. An image pickup apparatus that performs driving for mixing and transferring four charges of the same color component on the horizontal charge transfer path among a large number of charges stored in the charge storage region. The imaging device according to claim 5 or 6,
The photoelectric conversion element includes three types of photoelectric conversion elements that detect light in different wavelength ranges,
In a state where charges are accumulated in each of the plurality of charge accumulation regions, the charge arrangement includes the charge of the first color component and the charge of the second color component sandwiching the charge of the third color component. An imaging apparatus in which the arrangement of the three types of photoelectric conversion elements is determined so as to be arranged alternately in the horizontal direction. A photoelectric conversion element, a number of vertical charge transfer paths that transfer charges generated in the photoelectric conversion element in a vertical direction, and a charge that has been transferred through the vertical charge transfer path is transferred in a horizontal direction orthogonal to the vertical direction. A method for driving a solid-state imaging device having a horizontal charge transfer path,
The horizontal charge transfer path includes a plurality of charge transfer stages that operate as a charge accumulation region or a barrier region according to the level of an applied voltage,
Two vertical charge transfer paths are connected to each of the plurality of charge transfer stages,
The solid-state imaging device includes a large number of charge accumulation regions connecting each of the large number of vertical charge transfer paths and the horizontal charge transfer path, and a memory electrode provided independently above each of the large number of charge accumulation areas. Line memory consisting of
A voltage can be applied independently to each of the memory electrodes above each of the charge storage regions connecting the charge transfer stage and the two vertical charge transfer paths connected thereto,
The memory electrode includes a first memory electrode and a second memory electrode to which a voltage can be applied independently,
Controlling the voltage applied to the first memory electrode and the second memory electrode and the voltage applied to each of the plurality of charge transfer stages after storing charges in each of the plurality of charge storage regions. Then, the solid-state imaging device driving method for driving to mix and transfer four charges of the same color component on the horizontal charge transfer path among a large number of charges stored in the charge storage region. A photoelectric conversion element, a number of vertical charge transfer paths that transfer charges generated in the photoelectric conversion element in the vertical direction, and a charge transferred through the vertical charge transfer path is transferred in a horizontal direction orthogonal to the vertical direction. A method for driving a solid-state imaging device having a horizontal charge transfer path,
The horizontal charge transfer path includes a plurality of charge transfer stages that operate as a charge accumulation region or a barrier region according to the level of an applied voltage,
Two vertical charge transfer paths are connected to each of the plurality of charge transfer stages,
The solid-state imaging device includes a plurality of charge storage regions connecting each of the plurality of vertical charge transfer paths and the horizontal charge transfer path, and two adjacent charge storage areas connected to different charge transfer stages. A line memory comprising a memory electrode provided independently above each of the line memories,
The memory electrode includes a first memory electrode and a second memory electrode to which different voltages can be applied,
Controlling the voltage applied to the first memory electrode and the second memory electrode and the voltage applied to each of the plurality of charge transfer stages after storing charges in each of the plurality of charge storage regions. Then, a solid-state imaging device driving method for transferring four charges of the same color component among a large number of charges stored in the charge storage region on the horizontal charge transfer path. A method for driving a solid-state imaging device according to claim 8 or 9,
The photoelectric conversion element includes three types of photoelectric conversion elements that detect light in different wavelength ranges,
With the charges accumulated in each of the multiple charge accumulation regions, the charge arrangement alternates between the charge of the first color component and the charge of the second color component across the charge of the third color component. The solid-state imaging device driving method in which the arrangement of the three types of photoelectric conversion elements is determined so as to be arranged in the horizontal direction.

Images