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JP2009049201A - Manufacturing method of semiconductor laser device - Google Patents

Manufacturing method of semiconductor laser device Download PDF

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JP2009049201A
JP2009049201A JP2007214073A JP2007214073A JP2009049201A JP 2009049201 A JP2009049201 A JP 2009049201A JP 2007214073 A JP2007214073 A JP 2007214073A JP 2007214073 A JP2007214073 A JP 2007214073A JP 2009049201 A JP2009049201 A JP 2009049201A
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mesa
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type inp
buried layer
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JP4877146B2 (en
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Takashi Nagira
崇 柳楽
Tsutomu Wataya
力 綿谷
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Mitsubishi Electric Corp
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Abstract

【課題】メサの表面の酸化膜を十分に除去して、レーザ特性及び信頼性を向上させることができる半導体レーザ素子の製造方法を得る。
【解決手段】p型InP基板11上に、p型InPクラッド層12、AlGaInAs下光閉込層13、AlGaInAs―MQW活性層14、n型AlGaInAs上光閉込層15、n型InPクラッド層16からなる半導体積層構造を形成する。次に、SiO膜をマスクとしてウェットエッチングを行い、半導体積層構造にメサを形成する。次に、水素プラズマを用いてメサの表面を清浄化させる。次に、メサの表面を覆うようにp型InP埋込層17を形成する。そして、p型InP埋込層17上に、n型InP電流ブロック層18、p型InP埋込層19及びn型InP埋込層20を形成してメサの周囲を埋め込む。
【選択図】図7
A method of manufacturing a semiconductor laser device capable of sufficiently removing an oxide film on the surface of a mesa and improving laser characteristics and reliability.
A p-type InP cladding layer, an AlGaInAs lower optical confinement layer, an AlGaInAs-MQW active layer, an n-type AlGaInAs upper optical confinement layer, and an n-type InP clad layer are formed on a p-type InP substrate. A semiconductor multilayer structure is formed. Next, wet etching is performed using the SiO 2 film as a mask to form a mesa in the semiconductor stacked structure. Next, the surface of the mesa is cleaned using hydrogen plasma. Next, a p-type InP buried layer 17 is formed so as to cover the surface of the mesa. Then, an n-type InP current blocking layer 18, a p-type InP buried layer 19 and an n-type InP buried layer 20 are formed on the p-type InP buried layer 17 to bury the periphery of the mesa.
[Selection] Figure 7

Description

本発明は、Alを含む半導体材料からなる活性層を持つ半導体積層構造をエッチングしてメサを形成し、このメサの周囲を埋め込み層で埋め込む半導体レーザ素子の製造方法に関し、特にメサの表面の酸化膜を十分に除去して、レーザ特性及び信頼性を向上させることができる半導体レーザ素子の製造方法に関するものである。   The present invention relates to a method of manufacturing a semiconductor laser device in which a mesa is formed by etching a semiconductor laminated structure having an active layer made of a semiconductor material containing Al, and the periphery of the mesa is buried with a buried layer, and in particular, oxidation of the surface of the mesa The present invention relates to a method of manufacturing a semiconductor laser device that can sufficiently remove a film and improve laser characteristics and reliability.

半導体レーザ素子では、活性層へ電流を効率よく供給させるために電流経路を狭窄させる必要がある。そこで、多くの半導体レーザでは、活性層を持つ半導体積層構造を作製した後、誘電体膜への微細パターン転写技術、エッチング技術を用いてメサを形成し、電流が流れる領域を限定させることで電流経路を狭窄させている。この時、メサの表面に露出される活性層の保護や、放熱性、素子の寄生容量等の観点から、メサ周囲を半導体で覆った埋込構造を形成している(例えば、特許文献1参照)。   In the semiconductor laser device, it is necessary to narrow the current path in order to efficiently supply current to the active layer. Therefore, in many semiconductor lasers, a semiconductor stacked structure having an active layer is formed, and then a mesa is formed using a fine pattern transfer technique and an etching technique to a dielectric film, thereby limiting the current flowing region. The path is narrowed. At this time, an embedded structure in which the periphery of the mesa is covered with a semiconductor is formed from the viewpoint of protection of the active layer exposed on the surface of the mesa, heat dissipation, parasitic capacitance of the element, and the like (for example, see Patent Document 1). ).

図13は、活性層を持つ半導体積層構造のメサの周囲をn/p/n/p型の半導体層で埋め込んだ半導体レーザ素子を示す断面図である。p型InP基板11上に、p型InPクラッド層12、AlGaInAs下光閉込層13、AlGaInAs―MQW活性層14、n型AlGaInAs上光閉込層15、n型InPクラッド層16を順番に成長させた半導体積層構造のメサが形成されている。そして、メサの周囲は、p型InP埋込層17、n型InP電流ブロック層18、p型InP埋込層19、及びn型InP埋込層20により埋め込まれている。この上に、n型InPコンタクト層21、n型InGaAsコンタクト層22、n型InPキャップ層23が形成されている。   FIG. 13 is a cross-sectional view showing a semiconductor laser device in which the periphery of a mesa having a semiconductor laminated structure having an active layer is buried with an n / p / n / p type semiconductor layer. On the p-type InP substrate 11, a p-type InP cladding layer 12, an AlGaInAs lower optical confinement layer 13, an AlGaInAs-MQW active layer 14, an n-type AlGaInAs optical confinement layer 15, and an n-type InP clad layer 16 are grown in order. A mesa having a laminated semiconductor structure is formed. Then, the periphery of the mesa is buried by a p-type InP buried layer 17, n-type InP current blocking layer 18, p-type InP burying layer 19, and n-type InP burying layer 20. On top of this, an n-type InP contact layer 21, an n-type InGaAs contact layer 22, and an n-type InP cap layer 23 are formed.

ここで、メサの表面は、p型InP埋込層17で覆われている必要がある。これはn型InP電流ブロック層18がメサに接するとメサから埋込層へ電流が流れ、活性層14に電流を狭窄することができなくなるためである。   Here, the surface of the mesa needs to be covered with the p-type InP buried layer 17. This is because when the n-type InP current blocking layer 18 is in contact with the mesa, a current flows from the mesa to the buried layer, and the current cannot be confined in the active layer 14.

特開平05−136526号公報JP 05-136526 A

Alを含む半導体材料からなる活性層14は、メサの表面で大気に晒されて表面が酸化される。このような酸化層上ではIn原子がマイグレーションするため、p型InP埋込層17がエピタキシャル成長され難い。従って、活性層14より下の半導体層が完全に埋め込まれてから活性層14を覆うような成長が始まる。   The active layer 14 made of a semiconductor material containing Al is exposed to the atmosphere on the surface of the mesa and the surface is oxidized. Since In atoms migrate on such an oxide layer, the p-type InP buried layer 17 is hardly epitaxially grown. Therefore, the growth starts to cover the active layer 14 after the semiconductor layer below the active layer 14 is completely buried.

このため、図14に示すように、n型InP電流ブロック層18がメサに接してしまい、メサから埋込層へ電流が流れる無効電流経路24が形成される。また、界面の酸素や不純物は結晶欠陥の要因ともなる。これらにより特性及び信頼性が劣化するという問題があった。   For this reason, as shown in FIG. 14, the n-type InP current blocking layer 18 is in contact with the mesa, and the reactive current path 24 through which current flows from the mesa to the buried layer is formed. In addition, oxygen and impurities at the interface also cause crystal defects. As a result, there is a problem that characteristics and reliability deteriorate.

上記のようにAlを含む半導体材料からなる活性層を持つ半導体積層構造をエッチングしてメサを形成し、このメサの周囲を埋め込み層で埋め込む場合は、一般的な再成長で許容されるレベルよりもメサの表面の酸化層を低減させる必要がある。   When a semiconductor laminated structure having an active layer made of a semiconductor material containing Al as described above is etched to form a mesa and the periphery of this mesa is filled with a buried layer, the level allowed for general regrowth is exceeded. It is also necessary to reduce the oxide layer on the surface of the mesa.

なお、埋め込み成長の前にHClガスによりメサの表面の酸化層を除去する方法や、HClガスによるエッチング時の温度を450℃以下にして酸化膜の除去効果を高める方法がある。しかし、これらの方法だけでは、メサの表面の酸化膜を十分に除去することができなかった。   There are a method of removing the oxide layer on the surface of the mesa with HCl gas before the burying growth, and a method of enhancing the effect of removing the oxide film by setting the temperature during etching with the HCl gas to 450 ° C. or lower. However, these methods alone could not sufficiently remove the oxide film on the surface of the mesa.

本発明は、上述のような課題を解決するためになされたもので、その目的は、メサの表面の酸化膜を十分に除去して、レーザ特性及び信頼性を向上させることができる半導体レーザ素子の製造方法を得るものである。   The present invention has been made to solve the above-described problems, and an object of the present invention is to sufficiently remove an oxide film on the surface of the mesa to improve laser characteristics and reliability. The manufacturing method is obtained.

本発明に係る半導体レーザ素子の製造方法は、基板上に、Alを含む半導体材料からなる活性層を持つ半導体積層構造を形成する工程と、半導体積層構造をエッチングしてメサを形成する工程と、水素プラズマを用いてメサの表面を清浄化させる工程と、メサの表面を清浄化させた後にメサの表面を覆うように埋め込み層を形成する工程とを備える。本発明のその他の特徴は以下に明らかにする。   The method of manufacturing a semiconductor laser device according to the present invention, on a substrate, forming a semiconductor multilayer structure having an active layer comprising a semiconductor material containing Al, and forming a mesa by etching a semiconductor laminated structure, comprising a step of cleaning the surface of the mesa by using a hydrogen plasma, and forming a buried layer so as to cover the surface of the mesa after the surface of the mesa is cleaned. Other features of the present invention will become apparent below.

本発明により、メサの表面の酸化膜を十分に除去して、レーザ特性及び信頼性を向上させることができる。   According to the present invention, it is possible to sufficiently remove the oxide film on the surface of the mesa and improve the laser characteristics and reliability.

実施の形態1.
以下、本発明の実施の形態1に係る半導体レーザ素子の製造方法について図1のフローチャートに沿って説明する。
Embodiment 1 FIG.
A method for manufacturing a semiconductor laser device according to the first embodiment of the present invention will be described below with reference to the flowchart of FIG.

まず、図2に示すように、p型InP基板11上に、p型InPクラッド層12、AlGaInAs下光閉込層13、AlGaInAs―MQW活性層14、n型AlGaInAs上光閉込層15、n型InPクラッド層16を、MOVPE(Metalorganic Vapor Phase Epitaxy)を用いて順番に成長させて、Alを含む半導体材料AlGaIn1−x−yAs(0<x<1,0<y<1)からなる活性層を持つ半導体積層構造を形成する(ステップS1)。 First, as shown in FIG. 2, on a p-type InP substrate 11, a p-type InP cladding layer 12, an AlGaInAs lower light confinement layer 13, an AlGaInAs-MQW active layer 14, an n-type AlGaInAs upper light confinement layer 15, n -type InP cladding layer 16, is grown sequentially by using a MOVPE (Metalorganic Vapor Phase Epitaxy), a semiconductor material containing Al Al x Ga y in 1- x-y As (0 <x <1,0 <y < A semiconductor multilayer structure having an active layer of 1) is formed (step S1).

次に、MOVPE装置からウェハを取り出し、図3に示すように、このウェハ上にSiO膜を形成し、写真製版、転写技術を利用してSiOマスク25を作製する。そして、これをマスクとしてウェットエッチングを行い、図4に示すように、半導体積層構造にメサを形成する(ステップS2)。また、メサの表面に残留する有機物や酸化物を除去するため、溶液による処理を行う(ステップS3)。 Next, the wafer is taken out from the MOVPE apparatus, and as shown in FIG. 3, a SiO 2 film is formed on the wafer, and a SiO 2 mask 25 is produced using photolithography and transfer technology. Then, wet etching is performed using this as a mask to form a mesa in the semiconductor multilayer structure as shown in FIG. 4 (step S2). Moreover, in order to remove the organic substance and oxide which remain | survive on the surface of a mesa, the process by a solution is performed (step S3).

次に、メサが形成されたウェハを再びMOVPE装置内へ設置して、メサの埋込成長を行うが、ウェットエッチング、溶液による処理及びウェハ搬送において、メサの表面が大気に晒されて酸化される。そこで、埋め込み成長前に装置内に水素プラズマを導入し、この水素プラズマを用いてメサの表面を清浄化させる(ステップS4)。なお、HCl、TBCl、CClなどのエッチング効果を持つガスを用いて追加の表面処理を行ってもよい。 Next, the mesa-formed wafer is placed in the MOVPE apparatus again, and the mesa is embedded and grown. However, in wet etching, solution processing, and wafer transfer, the mesa surface is exposed to the atmosphere and oxidized. The Therefore, hydrogen plasma is introduced into the apparatus before the burying growth, and the surface of the mesa is cleaned using this hydrogen plasma (step S4). Note that an additional surface treatment may be performed using a gas having an etching effect such as HCl, TBCl, or CCl 4 .

ここで、上記の水素プラズマ処理を行うために、水素プラズマ発生機構を持つMOVPE装置を用いる。これにより、水素プラズマ処理を行った後、大気にさらすことなくMOVPEによる結晶成長を行うことができる。   Here, a MOVPE apparatus having a hydrogen plasma generation mechanism is used to perform the hydrogen plasma treatment. Thereby, after performing a hydrogen plasma process, the crystal growth by MOVPE can be performed, without exposing to air | atmosphere.

図5は、水素プラズマ発生機構を持つMOVPE装置の一例を示す断面図である。MOVPE反応炉31内に、ウェハ32を搭載するサセプタ33が設けられている。そして、MOVPE反応炉31にECR(electron cyclotron resonance)プラズマ発生機構34が一体化されている。このECRプラズマ発生機構34は、マイクロ波をMOVPE反応炉31内に導いて水素プラズマを発生させる。   FIG. 5 is a cross-sectional view showing an example of an MOVPE apparatus having a hydrogen plasma generation mechanism. A susceptor 33 on which a wafer 32 is mounted is provided in the MOVPE reaction furnace 31. The MOVPE reactor 31 is integrated with an ECR (electron cyclotron resonance) plasma generation mechanism 34. The ECR plasma generation mechanism 34 introduces microwaves into the MOVPE reactor 31 to generate hydrogen plasma.

図6は、水素プラズマ発生機構を持つMOVPE装置の他の例を示す断面図である。MOVPE反応炉31内にアンテナ35が内挿されている。このアンテナ35にRF電源36からRF電流が流される。これにより、MOVPE反応炉31内にICP(Inductively Coupled Plasma)プラズマを発生させる。   FIG. 6 is a cross-sectional view showing another example of an MOVPE apparatus having a hydrogen plasma generation mechanism. An antenna 35 is inserted in the MOVPE reactor 31. An RF current flows from the RF power source 36 to the antenna 35. Thereby, ICP (Inductively Coupled Plasma) plasma is generated in the MOVPE reactor 31.

次に、図7に示すように、メサの表面を覆うようにp型InP埋込層17をMOVPEにより形成する。そして、p型InP埋込層17上に、n型InP電流ブロック層18、p型InP埋込層19及びn型InP埋込層20をMOVPEにより形成してメサの周囲を埋め込む(ステップS5)。これによりFSBH(Facet Selected Buried Hetero-structure)構造を形成する。   Next, as shown in FIG. 7, a p-type InP buried layer 17 is formed by MOVPE so as to cover the surface of the mesa. Then, an n-type InP current blocking layer 18, a p-type InP buried layer 19, and an n-type InP buried layer 20 are formed by MOVPE on the p-type InP buried layer 17, and the periphery of the mesa is buried (step S5). . Thereby, an FSBH (Facet Selected Buried Hetero-structure) structure is formed.

次に、図8に示すように、ウェハをMOVPE装置から取り出し、マスク25をエッチング除去する。その後、ウェハを再びMOVPE装置内へ設置して、n型InPコンタクト層21、n型InGaAsコンタクト層22、n型InPキャップ層23を形成する。以上の製造工程により、n/p/n/p埋込構造を持つ半導体レーザ素子が製造される。   Next, as shown in FIG. 8, the wafer is taken out of the MOVPE apparatus, and the mask 25 is removed by etching. Thereafter, the wafer is again placed in the MOVPE apparatus, and an n-type InP contact layer 21, an n-type InGaAs contact layer 22, and an n-type InP cap layer 23 are formed. Through the above manufacturing process, a semiconductor laser device having an n / p / n / p buried structure is manufactured.

上記のように、本実施の形態では、水素プラズマを用いてメサの表面を清浄化させる。水素プラズマは強力な還元作用と物理的なエッチング作用を持つため、メサの表面の酸化膜を十分に除去することができる。   As described above, in this embodiment, the surface of the mesa is cleaned using hydrogen plasma. Since hydrogen plasma has a strong reducing action and physical etching action, the oxide film on the surface of the mesa can be sufficiently removed.

また、メサの表面に露出している結晶面方位は(100)面ではなく、最表面の原子配列や酸素との結合の強さが(100)面とは異なることなどにより、(100)面の表面清浄化時と比較すると酸化膜の除去効果が違うと考えられる。これに対し、上記の清浄化を行うことで、メサの表面の酸化膜を十分に除去することができる。   Further, the crystal plane orientation exposed on the surface of the mesa is not the (100) plane, and the (100) plane is different because the atomic arrangement on the outermost surface and the strength of bonding with oxygen are different from the (100) plane. It is considered that the removal effect of the oxide film is different as compared with the surface cleaning. On the other hand, the oxide film on the surface of the mesa can be sufficiently removed by performing the above-described cleaning.

従って、n型InP電流ブロック層18をメサに接することなく成長することができるため、メサから埋込層へ電流が流れる無効電流経路が形成されるのを防ぐことができる。また、メサと埋込層との界面の不純物が低減され、埋込層の結晶性の向上が望める。よって、レーザ特性及び信頼性を向上させることができる。   Therefore, since the n-type InP current blocking layer 18 can be grown without contacting the mesa, it is possible to prevent the formation of a reactive current path through which current flows from the mesa to the buried layer. Further, impurities at the interface between the mesa and the buried layer are reduced, and the crystallinity of the buried layer can be improved. Therefore, laser characteristics and reliability can be improved.

なお、本発明は、n/p/n/p型埋込成長に限定するものではなく、あらゆる埋込成長に適用することができる。また、本発明は、InP、AlGaInAs、InGaAs、InGaAsP、AlInAs、AlGaAs、GaAs、AlGaInP、InGaP、AlGaN、GaN、InGaNなど、あらゆる半導体材料で構成される半導体積層構造のメサの埋込成長に適用できる。また、本発明は、半導体レーザだけでなく、変調器、受光素子など、あらゆる半導体素子の作製に適用することができる。   The present invention is not limited to n / p / n / p type buried growth, but can be applied to all kinds of buried growth. Further, the present invention can be applied to embedded growth of a mesa having a semiconductor stacked structure composed of any semiconductor material such as InP, AlGaInAs, InGaAs, InGaAsP, AlInAs, AlGaAs, GaAs, AlGaInP, InGaP, AlGaN, GaN, and InGaN. . Further, the present invention can be applied not only to semiconductor lasers but also to the production of all semiconductor elements such as modulators and light receiving elements.

実施の形態2.
本実施の形態では、水素プラズマ処理を行った後、図9に示すように、メサの表面を覆うようにp型InP第1埋込層17a(第1の埋め込み層)を成長温度Tg_p1(第1の成長温度)で形成する。次に、p型InP第1埋込層17a上に、p型InP第2埋込層17b、n型InP電流ブロック層18、p型InP埋込層19及びn型InP埋込層20(第2の埋め込み層)を成長温度Tg_p2(第2の成長温度)で形成してメサの周囲を埋め込む。その他の工程は実施の形態1と同様である。
Embodiment 2. FIG.
In the present embodiment, after performing the hydrogen plasma treatment, as shown in FIG. 9, the p-type InP first buried layer 17a (first buried layer) is grown at a growth temperature Tg_p1 (the first buried layer) so as to cover the surface of the mesa. 1 growth temperature). Next, on the p-type InP first buried layer 17a, a p-type InP second buried layer 17b, an n-type InP current blocking layer 18, a p-type InP buried layer 19 and an n-type InP buried layer 20 (first 2 buried layers) is formed at the growth temperature Tg_p2 (second growth temperature) to embed the periphery of the mesa. Other steps are the same as those in the first embodiment.

ここで、図10は、実施の形態2における埋込成長時の成長温度と各層の成長の時間推移を模式的に示した図である。図示のように、p型InP第1埋込層17aの成長温度Tg_p1は、p型InP第2埋込層17bの成長温度Tg_p2よりも低い(Tg_p1<Tg_p2)。また、p型InP第1埋込層17a以外の層の成長温度は、MOVPE法でのInP成長に最適とされる600〜630℃にすることが結晶品質上好ましい。   Here, FIG. 10 is a diagram schematically showing the growth temperature at the time of buried growth and the time transition of growth of each layer in the second embodiment. As illustrated, the growth temperature Tg_p1 of the p-type InP first buried layer 17a is lower than the growth temperature Tg_p2 of the p-type InP second buried layer 17b (Tg_p1 <Tg_p2). Further, the growth temperature of the layers other than the p-type InP first buried layer 17a is preferably 600 to 630 ° C. which is optimal for InP growth by the MOVPE method in terms of crystal quality.

このようにメサと接するp型InP第1埋込層17aの成長温度Tg_p1が低いため、メサの表面での成長種のマイグレーションが抑制され、メサの表面はp型InP第1埋込層17aで覆われる。これにより、n型InP電流ブロック層18をメサに接することなく成長することができるため、無効電流経路の発生を防止することができる。   Since the growth temperature Tg_p1 of the p-type InP first buried layer 17a in contact with the mesa is thus low, the migration of the growth species on the surface of the mesa is suppressed, and the mesa surface is the p-type InP first buried layer 17a. Covered. As a result, the n-type InP current blocking layer 18 can be grown without contacting the mesa, thereby preventing the generation of a reactive current path.

なお、本実施の形態1では、p型InP埋込層をp型InP第1埋込層17aとp型InP第2埋込層17bに2分割したが、n分割しても良い。この時、p型InP埋込第1層の成長温度Tg_p1は、p型InP埋込第m層(1<m<=n)の成長温度Tg_pmより低いものとする。   Although the p-type InP buried layer is divided into the p-type InP first buried layer 17a and the p-type InP second buried layer 17b in the first embodiment, it may be divided into n. At this time, the growth temperature Tg_p1 of the p-type InP buried first layer is lower than the growth temperature Tg_pm of the p-type InP buried mth layer (1 <m <= n).

また、本実施の形態1では、p型InP第1埋込層17aとp型InP第2埋込層17bの間に成長中断を実施し埋込成長の成長温度をTg_p1からTg_p2へ段階的に増加させたが、成長中断を実施せずにp型InP第1埋込層17aからp型InP第2埋込層17bへ成長を実施しながら、成長温度をTg_p1からTg_p2へ連続的に増加させても良い。   In the first embodiment, the growth is interrupted between the p-type InP first buried layer 17a and the p-type InP second buried layer 17b, and the growth temperature of the buried growth is gradually changed from Tg_p1 to Tg_p2. Although the growth is performed, the growth temperature is continuously increased from Tg_p1 to Tg_p2 while performing the growth from the p-type InP first buried layer 17a to the p-type InP second buried layer 17b without performing the growth interruption. May be.

また、半導体材料の成長に最適とされる成長温度は、InP、InGaAsP、InGaAsは600〜630℃、AlGaInAs、AlInAsは600〜750℃、AlGaAs、GaAs、AlGaInP、InGaPは650〜750℃、AlGaN、GaNは1000〜1100℃、InGaNは700〜800℃である。これらの材料を埋込層として用いる場合は、第1の埋込層はこれらの最適とされる成長温度より低温であることが望ましい。   Further, the growth temperature optimum for the growth of the semiconductor material is 600 to 630 ° C. for InP, InGaAsP and InGaAs, 600 to 750 ° C. for AlGaInAs and AlInAs, 650 to 750 ° C. for AlGaAs, GaAs, AlGaInP and InGaP, AlGaN, GaN is 1000 to 1100 ° C, and InGaN is 700 to 800 ° C. When these materials are used as the buried layer, it is desirable that the first buried layer has a temperature lower than the optimum growth temperature.

実施の形態3.
本実施の形態では、メサの表面を清浄化させる工程において、第1の表面清浄化温度Tcl_1において水素プラズマを用いてメサの表面を清浄化させた(第1清浄化工程)後に、第2表面清浄化温度Tcl_2において水素プラズマを用いてメサの表面を清浄化させる(第2清浄化工程)。その他の工程は実施の形態1と同様である。
Embodiment 3 FIG.
In the present embodiment, in the step of cleaning the surface of the mesa, the second surface is cleaned after the surface of the mesa is cleaned using hydrogen plasma at the first surface cleaning temperature Tcl_1 (first cleaning step). The surface of the mesa is cleaned using hydrogen plasma at the cleaning temperature Tcl_2 (second cleaning step). Other steps are the same as those in the first embodiment.

図11は、本発明の実施の形態3における埋込成長時の成長温度と各層の成長の時間推移を模式的に示した図である。図示のように、第1の表面清浄化温度Tcl_1はTcより低く、第2表面清浄化温度Tcl_2はTcより高い。ただし、Tcはメサ側面の酸化層が強固なものに変化する臨界温度である。このようにTcより低い温度で清浄化を行うことでOとの結合を切り、その後にTcより高い温度にして清浄化を行うことにより、表面に残留したCl化合物やO化合物の蒸気圧が上がり、酸化層の除去効果が高くなる。   FIG. 11 is a diagram schematically showing the growth temperature at the time of burying growth and the time transition of the growth of each layer in the third embodiment of the present invention. As illustrated, the first surface cleaning temperature Tcl_1 is lower than Tc, and the second surface cleaning temperature Tcl_2 is higher than Tc. However, Tc is a critical temperature at which the oxide layer on the side surface of the mesa changes to a strong one. By performing the cleaning at a temperature lower than Tc in this way, the bond with O is cut, and then the cleaning is performed at a temperature higher than Tc, thereby increasing the vapor pressure of Cl compound and O compound remaining on the surface. The effect of removing the oxide layer is increased.

図12は、AlInAsを各温度に昇温した場合のOとAlの結合状態の変化を示すXPS分析結果である。450℃より低い温度ではOは水酸基として、560℃より高い温度ではOのみで、Alと結合してより強固な結合になっている。このことから、上記Tcは450℃程度であることが分かる。   FIG. 12 shows XPS analysis results showing changes in the bonding state between O and Al when AlInAs is heated to various temperatures. At a temperature lower than 450 ° C., O is a hydroxyl group, and at a temperature higher than 560 ° C., only O is bonded to Al and forms a stronger bond. From this, it can be seen that the Tc is about 450 ° C.

なお、本実施の形態3では、Tc以下での表面清浄化の後にTc以上での表面清浄化を一度行っているが、これは3通り以上の温度で行っても良い。また、温度変更時に水素プラズマの供給を中断しているが、ガス供給を中断せずに温度を変更しても良い。   In the third embodiment, the surface cleaning at Tc or higher is performed once after the surface cleaning at Tc or lower. However, this may be performed at three or more temperatures. Further, the supply of hydrogen plasma is interrupted when the temperature is changed, but the temperature may be changed without interrupting the gas supply.

また、活性層の材料が違えばOとの結合が強固になる温度Tcも違い、また表面に残留するClやOの化合物も違うため、素子を構成する半導体材料によって最適な清浄化温度を選択する必要がある。   In addition, if the material of the active layer is different, the temperature Tc at which the bond with O is strengthened is different, and the Cl and O compounds remaining on the surface are also different, so the optimum cleaning temperature is selected depending on the semiconductor material constituting the device There is a need to.

本発明の実施の形態1に係る半導体レーザ素子の製造方法のフローチャートである。2 is a flowchart of a method for manufacturing the semiconductor laser element according to the first embodiment of the present invention. 本発明の実施の形態1に係る半導体レーザ素子の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor laser element which concerns on Embodiment 1 of this invention. 本発明の実施の形態1に係る半導体レーザ素子の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor laser element which concerns on Embodiment 1 of this invention. 本発明の実施の形態1に係る半導体レーザ素子の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor laser element which concerns on Embodiment 1 of this invention. 水素プラズマ発生機構を持つMOVPE装置の一例を示す断面図である。It is sectional drawing which shows an example of the MOVPE apparatus with a hydrogen plasma generation mechanism. 水素プラズマ発生機構を持つMOVPE装置の他の例を示す断面図である。MOVPE反応炉31内にアンテナ35が内挿されている。It is sectional drawing which shows the other example of the MOVPE apparatus with a hydrogen plasma generation mechanism. An antenna 35 is inserted in the MOVPE reactor 31. 本発明の実施の形態1に係る半導体レーザ素子の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor laser element which concerns on Embodiment 1 of this invention. 本発明の実施の形態1に係る半導体レーザ素子の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor laser element which concerns on Embodiment 1 of this invention. 本発明の実施の形態2に係る半導体レーザ素子の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor laser element concerning Embodiment 2 of this invention. 本発明の実施の形態2における埋込成長時の成長温度と各層の成長の時間推移を模式的に示した図である。It is the figure which showed typically the growth time at the time of the embedding growth in Embodiment 2 of this invention, and the time transition of the growth of each layer. 本発明の実施の形態3における埋込成長時の成長温度と各層の成長の時間推移を模式的に示した図である。It is the figure which showed typically the growth time at the time of the embedding growth in Embodiment 3 of this invention, and the time transition of the growth of each layer. AlInAsを各温度に昇温した場合のOとAlの結合状態の変化を示すXPS分析結果である。It is an XPS analysis result which shows the change of the bonding state of O and Al when AlInAs is heated to each temperature. 活性層を持つ半導体積層構造のメサの周囲をn/p/n/p型の半導体からなる埋め込み層で埋め込んだ半導体レーザ素子を示す断面図である。It is sectional drawing which shows the semiconductor laser element which embed | buried the circumference | surroundings of the mesa of the semiconductor laminated structure with an active layer with the embedding layer which consists of a n / p / n / p type semiconductor. メサから埋込層へ電流が流れる無効電流経路が形成された従来の半導体レーザ素子を示す断面図である。It is sectional drawing which shows the conventional semiconductor laser element in which the reactive current path | route into which an electric current flows from a mesa to a buried layer was formed.

符号の説明Explanation of symbols

11 p型InP基板(基板)
12 p型InPクラッド層(半導体積層構造)
13 AlGaInAs下光閉込層(半導体積層構造)
14 AlGaInAs―MQW活性層(半導体積層構造)
15 n型AlGaInAs上光閉込層(半導体積層構造)
16 n型InPクラッド層(半導体積層構造)
17 p型InP埋込層(埋め込み層)
17a p型InP第1埋込層(第1の埋め込み層)
17b p型InP第2埋込層(第2の埋め込み層)
18 n型InP電流ブロック層(埋め込み層)(第2の埋め込み層)
19 p型InP埋込層(埋め込み層)(第2の埋め込み層)
20 n型InP埋込層(埋め込み層)(第2の埋め込み層)
11 p-type InP substrate (substrate)
12 p-type InP cladding layer (semiconductor laminated structure)
13 AlGaInAs lower light confinement layer (semiconductor laminated structure)
14 AlGaInAs-MQW active layer (semiconductor laminated structure)
15 n-type AlGaInAs optical confinement layer (semiconductor laminated structure)
16 n-type InP cladding layer (semiconductor laminated structure)
17 p-type InP buried layer (buried layer)
17a p-type InP first buried layer (first buried layer)
17b p-type InP second buried layer (second buried layer)
18 n-type InP current blocking layer (buried layer) (second buried layer)
19 p-type InP buried layer (buried layer) (second buried layer)
20 n-type InP buried layer (buried layer) (second buried layer)

Claims (4)

基板上に、Alを含む半導体材料からなる活性層を持つ半導体積層構造を形成する工程と、
前記半導体積層構造をエッチングしてメサを形成する工程と、
水素プラズマを用いて前記メサの表面を清浄化させる工程と、
前記メサの表面を清浄化させた後に前記メサの表面を覆うように埋め込み層を形成する工程とを備えることを特徴とする半導体レーザ素子の製造方法。
Forming a semiconductor multilayer structure having an active layer made of a semiconductor material containing Al on a substrate;
Etching the semiconductor multilayer structure to form a mesa;
Cleaning the surface of the mesa with hydrogen plasma;
And a step of forming a buried layer so as to cover the surface of the mesa after cleaning the surface of the mesa.
前記埋め込み層をMOVPE法により形成することを特徴とする請求項1に記載の半導体レーザ素子の製造方法。   2. The method of manufacturing a semiconductor laser device according to claim 1, wherein the buried layer is formed by a MOVPE method. 前記埋め込み層を形成する工程は、
前記メサの表面を覆うように第1の埋め込み層を第1の成長温度で形成する工程と、
前記第1の埋め込み層の上に第2の埋め込み層を前記第1の成長温度よりも高い第2の成長温度で形成して前記メサの周囲を埋め込む工程とを有することを特徴とする請求項1又は2に記載の半導体レーザ素子の製造方法。
The step of forming the buried layer includes
Forming a first buried layer at a first growth temperature so as to cover the surface of the mesa;
Forming a second buried layer on the first buried layer at a second growth temperature higher than the first growth temperature and embedding the periphery of the mesa. A method for producing a semiconductor laser device according to 1 or 2.
前記メサの表面を清浄化させる工程は、
前記メサの側面の酸化層が強固なものに変化する臨界温度よりも低い温度において、前記水素プラズマを用いて前記メサの側面を清浄化させる第1清浄化工程と、
前記第1清浄化工程の後に、前記臨界温度よりも高い温度において、前記水素プラズマを用いて前記メサの側面を清浄化させる第2清浄化工程とを有することを特徴とする請求項1〜3の何れか1項に記載の半導体レーザ素子の製造方法。
The step of cleaning the surface of the mesa
A first cleaning step of cleaning the side surface of the mesa using the hydrogen plasma at a temperature lower than a critical temperature at which the oxide layer on the side surface of the mesa changes to a solid one;
The second cleaning step of cleaning the side surface of the mesa using the hydrogen plasma at a temperature higher than the critical temperature after the first cleaning step. The method for manufacturing a semiconductor laser device according to any one of the above.
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