JP2009049198A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

When forming an ohmic electrode on a silicon carbide substrate, an alloying heat treatment between a metal and silicon carbide is made unnecessary.
Phosphorus (P) is ion-implanted into a (0001) plane of a hexagonal single crystal silicon carbide substrate to form an amorphous layer. Next, the amorphous layer 12 is recrystallized into cubic single crystal n-type silicon carbide 13 by heat treatment. Next, the electrode 14 is formed by vapor-depositing nickel (Ni) on the upper surface of the n-type silicon carbide 13. The height of the Schottky barrier formed between the silicon carbide 13 and the electrode 14 is reduced, and an ohmic contact is realized between the electrode 14 and the silicon carbide 13 without using an alloying heat treatment.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device using silicon carbide and a method for manufacturing the same.

  Silicon carbide (SiC: silicon carbide) has a dielectric breakdown electric field of about 10 times, thermal conductivity of about 3 times, and electron saturation speed of about 2 times that of silicon. It is attracting attention as a semiconductor material for high-frequency devices. This silicon carbide is known to have many crystal structures such as cubic, hexagonal and orthorhombic, and the physical properties differ depending on the crystal structure. Currently, a hexagonal single crystal silicon carbide substrate is generally used as a semiconductor substrate, and devices having many structures have been developed.

  However, among the hexagonal single crystal silicon carbide, a material called 4H-SiC having a stacking period of 4 has a band gap of 3.26 eV, which is about three times larger than that of silicon. It is known that it is difficult to realize ohmic contact between them, and the following problems are known to occur.

  When a semiconductor and a metal are brought into contact with each other, if there is a difference between the work functions of each other, a contact potential difference (potential barrier) is generated on the contact surface. In particular, when the work function on the metal side is larger than the work function on the semiconductor side, this potential difference becomes a barrier (potential barrier) when electrons flow from the metal to the semiconductor. It is known that a semiconductor having a larger band gap has a lower work function. In fact, when nickel (Ni) is brought into contact with a hexagonal single crystal n-type silicon carbide substrate, the potential barrier becomes larger and the ohmic contact becomes smaller. It cannot be obtained and exhibits rectification characteristics. In a semiconductor device, ohmic contact is a metal / semiconductor junction characteristic that is indispensable for reducing power loss and realizing high-speed operation.

  In the formation of electrodes of silicon carbide devices, alloying treatment by heat treatment has been widely used to reduce this potential barrier, but since silicon carbide is thermally stable, in order to alloy with metal, Heat treatment at a high temperature close to 1000 ° C. is required (for example, see Non-Patent Document 1). As described above, when an electrode is formed on silicon carbide, a high temperature alloying heat treatment is required to realize ohmic contact, and various problems have arisen for manufacturing a semiconductor device.

  First, when manufacturing a Schottky diode, the ohmic electrode on the back surface must be formed in a process before forming the Schottky electrode on the front surface, and a clean silicon carbide surface is obtained before the Schottky electrode is formed. In order to protect the ohmic electrode formed on the back surface, a resist had to be applied to the surface before the hydrofluoric acid treatment. As described above, there has been a problem in that the resist coating and removal steps that are unnecessary in the production of a normal Schottky diode using silicon increase.

  Next, when manufacturing a metal / semiconductor junction FET (MESFET), if an alloying heat treatment is performed to form an ohmic electrode, the ohmic electrode is greatly collapsed from the alignment pattern. There has been a problem of deterioration. In particular, in the manufacturing process of a Schottky junction MESFET operated at a high frequency, the source electrode and the gate electrode are brought close to each other in order to reduce the source resistance of the device as much as possible. Therefore, the ohmic electrode is used as a mask alignment mark. However, since the alignment accuracy is poor, sometimes the gate electrode is applied to the source electrode region, and the drain current cannot be controlled by the gate electrode.

Next, in the manufacturing process of a DMOS (Double-diffused-MOS) FET, the ohmic electrode forming process is performed after the gate oxide film is formed. Therefore, the film quality of the gate oxide film is deteriorated by the heat treatment for forming the ohmic electrode, and the withstand voltage is increased. There was a problem that decreased. For example, S.M. In the manufacture of a silicon carbide MISFET using hafnium oxide (HfO ₂ ) as an insulating film announced by Hino (see Non-Patent Document 2), a heat treatment at 850 ° C. is applied to form an ohmic electrode on the back surface. In the electrode formation, alloy heat treatment is not performed in order to prevent changes in characteristics of the insulating film. Therefore, in this device, a large value of the electron channel mobility is obtained, but the problem remains that the on-resistance cannot be sufficiently reduced.

  Furthermore, when the ohmic electrode is formed by heat treatment, when the silicon carbide substrate and the metal undergo an alloying reaction, surplus carbon is deposited inside and on the surface of the silicided electrode. The carbon deposited on the surface further reduces the adhesion to the extraction electrode formed on the surface, and the carbon in the silicide may change its distribution during device use and affect the characteristics. Has been suggested (see Non-Patent Document 3).

Edited by Hiroyuki Matsunami, “Semiconductor SiC Technology and Applications”, Nikkan Kogyo Shimbun, 2003, 1st edition, pages 160-162. S. Hino, et al., "Low Temperature Deposition of HfO2 Gate Insulator on SiC by Metalorganic Chemical Vapor Deposition", Materials Science Forum, Vols. 527-529, (2006), pp. 1079-1082. Suzuki Tatsuhiro et al., “Improving electrode adhesion of Ni ohmic contacts”, 54th Applied Physics Related Conference Lecture Proceedings (Spring 2007, Aoyama Gakuin University), No.1, p.441, 28p-N-14 .

  As described above, when an ohmic electrode forming process that requires alloying is used in the manufacture of a silicon carbide semiconductor device, the manufacturing process is limited, man-hours are increased to avoid this, or heat treatment of the device is performed. There were problems such as a decrease in yield. Further, when the alloying reaction is used, there is a problem that adhesion with the upper electrode is lowered due to precipitation of excess carbon.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that eliminates the above-mentioned problems by eliminating the need for alloying heat treatment between a metal and silicon carbide when forming an electrode on a silicon carbide substrate. Is to provide.

In order to achieve the above object, a semiconductor device according to a first aspect of the present invention is a hexagonal single crystal whose surface is a (0001) plane or a (000-1) plane silicon carbide substrate, and the silicon carbide substrate. An n-type or p-type cubic single crystal silicon carbide region formed by recrystallizing the hexagonal single crystal on a part of the surface of the substrate, and deposited on the surface of the silicon single crystal region of the cubic single crystal. And an electrode.
A method for manufacturing a semiconductor device according to a second aspect of the present invention is a hexagonal single crystal, the surface of which is a (0001) plane or a (000-1) plane silicon carbide substrate, and is n-type or p-type at room temperature. Implanting impurity ions of a type to change at least a part of the hexagonal single crystal into an amorphous layer, and heat-treating the amorphous layer to form a silicon carbide region of an n-type or p-type cubic single crystal. And a step of depositing an electrode on the surface of the silicon carbide region of the cubic single crystal.

  According to the semiconductor device of the present invention, the electrode is deposited on the surface of the silicon carbide region of the n-type or p-type cubic single crystal formed on the hexagonal single crystal silicon carbide substrate. The height of the Schottky barrier between the first and second electrodes becomes low, and ohmic contact can be realized as it is by appropriately selecting the electrode material.

  In addition, according to the method for manufacturing a semiconductor device of the present invention, an alloying heat treatment for electrode formation is not required, the manufacturing process is simplified, a decrease in device yield due to the heat treatment can be prevented, and surplus carbon during the alloying heat treatment can be prevented. Due to the deposition, it is possible to avoid problems such as deterioration of electrode adhesion.

  For this reason, in the MESFET and its manufacture according to the present invention, the pattern of the ohmic electrode can be formed with high accuracy as the mask pattern is transferred, the alignment accuracy is improved in the next photolithography process, and the deterioration of device characteristics and yield are improved. However, there is an advantage that the on-resistance can be reduced. Furthermore, the DMOSFET and its manufacture have the advantages that there is no deterioration of the withstand voltage of the insulating film due to heat treatment, and that the on-resistance can be effectively reduced.

<Example 1>
FIG. 1 is a diagram showing a manufacturing process of a silicon carbide diode 10 of an embodiment to which the present invention is applied. First, n-type impurities are ion-implanted into the (0001) plane of a hexagonal single crystal silicon carbide substrate (here, 4H—SiC) 11 (FIG. 1A). Here, as the n-type impurity, phosphorus (P) is used as an ion species, and a multi-stage implantation is performed at room temperature so as to obtain a BOX-like profile with a total dose of 1.4 × 10 ¹⁶ / cm ² and a thickness of 150 nm. Do. Thereby, amorphous layer 12 is formed on the upper surface of silicon carbide substrate 11 (FIG. 1B). At this time, the dose is set to 1 × 10 ¹⁵ / cm ² or more so that an amorphous layer is always formed. If the dose is smaller than this, the amorphous layer 12 is not formed, and the effect of the present invention cannot be expected.

  Next, in order to recrystallize the amorphous layer 12 and activate the impurities, heat treatment is performed at 1700 ° C. for 10 minutes in an argon (Ar) atmosphere. During this heat treatment, the amorphous layer 12 changes its crystal structure to become a cubic n-type silicon carbide layer (n-3C-SiC) 13 (FIG. 1 (c)). At this time, if the heat treatment temperature is 700 ° C. or less, the temperature is too low for recrystallization and the treatment time becomes long, which is not practical. Moreover, if it is 1900 degreeC or more, since evaporation of silicon from the surface of the silicon carbide substrate 11 will become intense and surface roughness will arise, it is not suitable.

  Next, when nickel (Ni) is formed on the upper surface of the cubic n-type silicon carbide layer 13 formed in this manner by vapor deposition, an ohmic electrode 14 having a small contact resistance can be formed (FIG. 1 (d)). )).

  FIG. 2 shows a characteristic A as a result of evaluating the ohmic electrode 14 formed on the upper surface of the cubic n-type silicon carbide layer 13 as described above by the TLM method (Transmission Line Method). In addition, when phosphorus (P) is ion-implanted, the result of ion implantation under the same conditions while heating the hexagonal single-crystal silicon carbide substrate 11 to 500 ° C. is shown as characteristic B. When ion implantation is performed at 500 ° C., the implantation region does not become amorphous, so that a recrystallization process does not occur and the crystal structure is maintained as it is.

  As shown in FIG. 2, the contact made in the region where the crystal structure is changed from hexagonal to cubic by ion implantation at room temperature and then heat-treated can exhibit ohmic characteristics without being subjected to alloy heat treatment. You can see that On the other hand, in the sample implanted at 500 ° C., it is obvious that ohmic characteristics cannot be obtained as it is (when the alloy heat treatment is not performed).

  When ion implantation is performed on the (0001) plane of hexagonal single crystal silicon carbide, the part becomes amorphous, and the heat treatment is applied to this part to change the hexagonal crystal into a cubic crystal (M. Satoh, et.al. , "Characterization of Implanted Layer in (1-100) Oriented 4H- and 6H-SiC", Materials Science Forum Vols. 338-342, (2000) pp.905-908).

  The nickel (Ni) electrode becomes the ohmic electrode 14 because the height of the Schottky barrier formed by the cubic single crystal n-type silicon carbide layer 13 and nickel (Ni) is reduced. However, regarding this point, the paper (M. Satoh, et.al., "Evalution of Schottky Barrier Hight of Al, Ti, Au, and Ni Contacts to 3C-SiC", Materials Science Forum Vols. 527-529, ( 2006) pp.923-926).

As an impurity to be ion-implanted into the (0001) plane of hexagonal single crystal silicon carbide, nitrogen (N) or the like can be used in addition to phosphorus (P) in the case of n type, and boron ( B), aluminum (Al) and others can be used. When these ionic species are used, the dose is in a range where it becomes amorphous by normal ion implantation, and is about 1 × 10 ¹⁵ / cm ² to 2 × 10 ¹⁶ / cm ² . Further, the electrode metal is not limited to nickel (Ni), but aluminum (Al), titanium (Ti), gold (Au), copper (Cu), niobium (Nb), molybdenum (Mo), ruthenium ( If the work function is a metal having a work function of about 4.2 eV to 5.0 eV, such as (Ru), the height of the Schottky barrier is reduced, which can be implemented.

<Example 2>
FIG. 3 is a diagram showing a cross-sectional structure of a silicon carbide Schottky diode 20 according to an embodiment to which the present invention is applied. First, an epitaxial layer 22 having an impurity concentration of 1 × 10 ¹⁵ / cm ³ and a thickness of 10 μm is formed on the upper surface (0001) of a hexagonal single crystal n-type silicon carbide substrate (here, n-4H—SiC) 21 by CVD. Form by the method. The epitaxial layer 12 is a hexagonal single crystal.

  Next, a high-concentration n-type silicon carbide layer having a cubic crystal structure is formed on the back surface (000-1) of the silicon carbide substrate 21 by the same manufacturing method as that for forming the n-type silicon carbide layer 13 of Example 1. n-3C-SiC) 23.

  Next, titanium (Ti) or nickel (Ni) is formed as a Schottky electrode 24 on the epitaxial layer 22 by patterning. Finally, nickel (Ni) is deposited on the back surface to form the ohmic electrode 25, and the silicon carbide Schottky diode 20 is completed.

  Conventionally, in order to form the ohmic electrode 25 on the back surface, an alloying heat treatment is required. Therefore, the ohmic electrode 25 on the back surface has to be formed in a step before the Schottky electrode 24 is formed. Therefore, in order to obtain a clean silicon carbide surface before the formation of the Schottky electrode 24, it was necessary to perform hydrofluoric acid treatment. In order to do this, the ohmic electrode 25 formed on the back surface is protected. In addition, a resist had to be applied.

  In contrast, in this embodiment, since the alloying heat treatment for forming the ohmic electrode 25 is not required, the ohmic electrode 25 can be formed after the formation of the Schottky electrode 24, and the ohmic electrode 25 is protected. This eliminates the need for resist coating and a process for removing it.

<Example 3>
FIG. 4 is a diagram showing a cross-sectional structure of the MESFET 30 of the embodiment to which the present invention is applied. First, an n-type channel layer 32 is formed by ion implantation on the (0001) plane of a hexagonal single crystal silicon carbide substrate (here, 4H—SiC) 31. At this time, if the impurity ions are nitrogen (N), and implantation is performed at an acceleration voltage of 75 keV and a dose of 7.2 × 10 ¹² / cm ² , the maximum impurity concentration is 8 × 10 ¹⁷ / cm ³ and the thickness is 0.2 μm. A mold channel layer 32 can be formed. In this ion implantation, the silicon carbide substrate 31 is maintained in crystallinity. That is, it is a hexagonal single crystal.

  Next, using the same amorphization and recrystallization techniques as in Example 1, a cubic single crystal high-concentration n-type silicon carbide region (n-3C-SiC) 33 is formed as a source region and a drain region, On the upper surface, the source electrode 34S and the drain electrode 34D of ohmic contact are formed by depositing nickel (Ni) in the same manner as in the first embodiment. When the ohmic electrodes 34S and 34D are formed, a mark 34A for mask alignment (alignment) when forming the gate electrode is also formed at the same time.

  Next, in accordance with the mark 34A, the gate electrode is patterned by electron beam drawing, and subsequently, titanium (Ti) / platinum (Pt) / gold (Au) is deposited and lifted off as the material of the Schottky gate electrode 35. Thus, the MESFET 30 is completed by forming the Schottky gate electrode 35.

  The mark 34A is used when forming the pattern of the Schottky gate electrode 35, in order to form the distance between the gate electrode 35 and the source electrode 34S precisely and with good reproducibility, particularly in the production of a high-frequency MESFET. is there. When the alignment accuracy is lowered, a part of the gate electrode 35 overlaps with the region of the source electrode 34S, and the drain current cannot be modulated by the gate voltage. Conversely, the interval between the gate electrode 35 and the source electrode 34S is increased, and the parasitic source is increased. There is a risk that the resistance increases and the power gain of the high frequency characteristics is reduced.

  In the conventional method of forming an ohmic electrode using alloying heat treatment, the electrode shape of the mask alignment mark 34A is broken by the heat treatment step, and the problem of lowering alignment accuracy occurs. Then, since the shape of the mark 34A is not lost, it is possible to form a gate electrode with high alignment accuracy, and to improve the characteristics and yield of the MESFET.

<Example 4>
FIG. 5 is a diagram showing a cross-sectional structure of a DMOSFET 40 according to an embodiment to which the present invention is applied. First, a p-type region 42 is formed in a hexagonal single crystal n-type silicon carbide substrate (n-4H-SiC) 41. The p-type region 42 is formed by ion implantation of aluminum (Al) as an impurity so that the impurity concentration becomes 1 × 10 ¹⁷ / cm ³ . By this ion implantation, the p-type region 42 does not have an amorphous structure, and crystallinity is maintained. That is, it is a hexagonal single crystal.

Next, in order to form the source region 43, phosphorus (P) or nitrogen (N) is implanted so that the impurity concentration is about 1 × 10 ²⁰ / cm ³ . At this time, the crystal of the source region 43 has an amorphous structure. Further, in order to minimize the on-resistance of the DMOSFET, the same ion implantation is performed in order to form a similar drain region 44 on the back surface of the n-type silicon carbide substrate 41, so that the portion has an amorphous structure.

  Next, an activation heat treatment is performed at 1500 ° C. for 30 minutes. As a result, the impurities in the P-type region 42 are activated, and the hexagonal crystal is maintained without changing the crystal structure. On the other hand, the source region 43 and the drain region 44 having an amorphous structure change the crystal structure to cubic single crystal n-type silicon carbide by this heat treatment.

  Next, gate oxidation is performed on the upper surface of silicon carbide substrate 41. A 20 nm gate oxide film 45 is formed by wet oxidation at 1150 ° C. for 2 hours. Next, the gate electrode 46 is formed, and finally, the oxide film of the n-type source region 43 is removed to open the portion. Then, nickel (Ni) is vapor-deposited on the upper surface and the rear surface to form the source electrode 47 and the drain electrode 48 as ohmic electrodes, thereby completing the MOSFET. Reference numeral 49 denotes a channel region.

  In the conventional method using alloying heat treatment for forming the ohmic electrode, heat treatment at about 1000 ° C. for alloying must be performed after the gate oxide film 45 is formed, and this treatment damages the gate insulating film 45. There is a problem of lowering the withstand voltage. Further, if the electrode alloying process is performed before the formation of the gate oxide film 45, the silicon carbide substrate must be put in the oxidation furnace while the electrode is attached when the gate oxide film is formed. There is a problem that the film 45 is contaminated by metal ions.

  On the other hand, in this embodiment, since the alloying heat treatment is not required for forming the source electrode 47 and the drain electrode 48 as ohmic electrodes, problems such as characteristic changes and contamination of the insulating film can be avoided.

It is explanatory drawing which shows the manufacturing process of the diode of Example 1 of this invention. It is a VI characteristic figure between silicon carbide and an electrode. It is sectional drawing which shows the structure of the Schottky diode of Example 2 of this invention. It is sectional drawing which shows the structure of MESFET of Example 3 of this invention. It is sectional drawing which shows the structure of DMOSFET of Example 4 of this invention.

Explanation of symbols

10: diode, 11: hexagonal single crystal silicon carbide substrate, 12: n-type amorphous layer, 13: cubic single crystal n-type silicon carbide layer, 14: ohmic electrode, 20: Schottky diode, 21: hexagonal single crystal Crystalline n-type silicon carbide substrate, 22: epitaxial layer, 23: cubic single crystal n-type silicon carbide layer, 24: Schottky electrode, 25: ohmic electrode, 30: MISFET, 31: hexagonal single crystal silicon carbide substrate 32: n-type channel layer, 33: n-type silicon carbide layer of cubic single crystal, 34S: source electrode, 34D: drain electrode, 34A: mark, 35: gate electrode 40: DMOSFET, 41: hexagonal single crystal n-type silicon carbide substrate, 42: p-type region, 43: n-type source region of cubic single crystal, 44: n-type drain region of cubic single crystal, 45: gate oxide film, 4 : Gate electrode, 47: source electrode, 48: drain electrode, 49: channel region

Claims (2)

  A hexagonal single crystal having a (0001) or (000-1) plane silicon carbide substrate, and the hexagonal single crystal formed on a part of the surface of the silicon carbide substrate. A semiconductor device comprising: a silicon carbide region of an n-type or p-type cubic single crystal; and an electrode deposited on the surface of the silicon carbide region of the cubic single crystal. An n-type or p-type impurity ion is implanted into a surface of a silicon carbide substrate having a (0001) plane or a (000-1) plane at room temperature to form the hexagonal single crystal. Changing at least a part of the film into an amorphous layer;
Heat treating the amorphous layer to recrystallize into an n-type or p-type cubic single crystal silicon carbide region;
Depositing an electrode on the surface of the silicon carbide region of the cubic single crystal;
A method for manufacturing a semiconductor device, comprising:

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