JP2009043314A - Nonvolatile semiconductor memory device and control method of nonvolatile semiconductor memory device - Google Patents

Abstract

Charge / discharge current and noise generated during read access are reduced, and the operation of a NAND flash memory is stabilized.
A pair of selection gate electrodes 4, 6 and a plurality of floating gate electrodes 8 between the pair of selection gate electrodes 4, 6 and between each floating gate electrode 8 and the floating gate electrode 8 and the selection. A plurality of control gate electrodes 2 provided between the gate electrodes 4 and 6, respectively, and a first floating gate electrode 8 selected from the plurality of floating gate electrodes 8 during a first read access. A predetermined read voltage is marked on the pair of control gate electrodes 2 on both sides of the first floating gate electrode 2n (n is a natural number) from the first floating gate electrode 8 during the second read access following the first read access. The predetermined read power is applied to the pair of control gate electrodes 2 on both sides of the second floating gate electrode 8. Apply pressure.
[Selection] Figure 1

Description

  The present invention relates to a nonvolatile semiconductor memory device and a method for controlling the nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device including a pair of control gate electrodes located on both sides of a floating gate electrode and the nonvolatile semiconductor memory device. Relates to the control method.

  2. Description of the Related Art Conventionally, a so-called NAND flash memory is known as a nonvolatile semiconductor memory device that can be electrically rewritten and can be highly integrated.

  A memory cell of a conventional NAND flash memory has a stack gate structure in which a floating gate electrode for accumulating charges and a control gate electrode for controlling the voltage of the floating gate electrode are stacked.

  The memory cell stores data in a nonvolatile manner according to the charge accumulation state of the floating gate electrode. For example, in the case of realizing a binary storage system for storing binary data, a floating gate in which electrons are emitted from the channel with data “0” being higher than the threshold voltage of the floating gate electrode into which electrons are injected from the channel. A state lower than the threshold voltage of the electrode is defined as data “1”. It should be noted that a multi-value storage method for storing data of four or more values can be realized by further subdividing the threshold distribution.

  On the other hand, an improved NAND flash memory that realizes a lower write voltage, higher integration, and higher speed is known (Patent Document 1).

  The memory cell of the NAND flash memory of Patent Document 1 has a floating gate electrode sandwiched between a pair of control gate electrodes when a pair of control gate electrodes are positioned on both sides of the floating gate and the voltage of the pair of control gate electrodes changes. The voltage changes.

  In the write access of the NAND flash memory of Patent Document 1, binary or multivalued data is stored in a nonvolatile manner according to the relationship between the voltage of the floating gate electrode and the threshold voltage.

  In the read access of the NAND flash memory of Patent Document 1, an arbitrary floating gate electrode is selected at the first read access, and a floating gate electrode adjacent to the floating gate electrode is selected at the subsequent read access. These read accesses are continuously performed until the data read is completed.

  However, since adjacent floating gate electrodes are continuously selected, it is necessary to change the voltage of not only the selected floating gate electrode but also the control gate electrode that controls the unselected floating gate electrode.

As a result, the noise of the coupling and charging / discharging current affects the power supply line and the signal line (for example, bit line) by changing the voltage of a large number of control gate electrodes. There is a problem that becomes unstable.
JP 2005-101066 A

  An object of the present invention is to reduce the charge / discharge current and noise generated during read access and stabilize the operation of the NAND flash memory.

  According to the first aspect of the present invention, a semiconductor substrate, a pair of selection gate electrodes provided on the semiconductor substrate via a gate insulating film, and the semiconductor substrate between the pair of selection gate electrodes A plurality of floating gate electrodes provided via a gate insulating film, and a plurality of control gate electrodes provided between the floating gate electrodes and between the floating gate electrode and the selection gate electrode, respectively. A method for controlling a nonvolatile semiconductor memory device, wherein a predetermined voltage is applied to a pair of control gate electrodes positioned on both sides of a first floating gate electrode selected from the plurality of floating gate electrodes during a first read access. Applied to the first flow during a second read access following the first read access. The predetermined read voltage is applied to a pair of control gate electrodes located on both sides of the 2n (n is a natural number) second floating gate electrode from the scanning gate electrode, and the control of the nonvolatile semiconductor memory device A method is provided.

  According to the second aspect of the present invention, a semiconductor substrate, a pair of selection gate electrodes provided on the semiconductor substrate via a gate insulating film, and the semiconductor substrate between the pair of selection gate electrodes A plurality of floating gate electrodes provided via a gate insulating film, and a plurality of control gate electrodes provided between the floating gate electrodes and between the floating gate electrode and the selection gate electrode, respectively. A method for controlling a nonvolatile semiconductor memory device, wherein a voltage of a first floating gate electrode selected from among the plurality of floating gate electrodes changes during a first read access, and follows the first read access. During the second read access, the 2nth (n is a natural number) second from the first floating gate electrode. Control method for a nonvolatile semiconductor memory device characterized by voltage of the floating gate electrode is changed is provided.

  According to a third aspect of the present invention, a semiconductor substrate, a pair of selection gate electrodes provided on the semiconductor substrate via a gate insulating film, and a gate on the semiconductor substrate between the pair of selection gate electrodes Nonvolatile comprising: a plurality of floating gate electrodes provided via an insulating film; and a plurality of control gate electrodes provided between the floating gate electrodes and between the floating gate electrode and the selection gate electrode, respectively 2m-2 (m is a natural number) of physical addresses corresponding to a continuous first logical address, and 2m-1 of a physical address follows the first logical address. A nonvolatile memory comprising a memory portion having transistors arranged to correspond to consecutive second logical addresses Conductor storage device is provided.

  According to a fourth aspect of the present invention, a semiconductor substrate, a pair of selection gate electrodes provided on the semiconductor substrate via a gate insulating film, and a gate on the semiconductor substrate between the pair of selection gate electrodes Nonvolatile comprising: a plurality of floating gate electrodes provided via an insulating film; and a plurality of control gate electrodes provided between the floating gate electrodes and between the floating gate electrode and the selection gate electrode, respectively And a memory unit having transistors arranged so that each address of a physical address corresponds to a continuous logical address, and 2m-2 (m is a natural number) of a physical address of the memory unit Are converted into continuous first logical addresses, and 2m-1 addresses of the physical addresses of the memory units are respectively converted into the first logical addresses. An address conversion table storage unit for storing an address conversion table for conversion to a second logical address that is continuous following the logical address, and the floating gate electrode according to the address conversion table stored in the address conversion table storage unit There is provided a nonvolatile semiconductor memory device comprising: a control unit that applies a predetermined read voltage to a pair of control gate electrodes located on both sides.

  According to the present invention, it is possible to reduce the charge / discharge current and noise generated during read access and to stabilize the operation of the NAND flash memory.

  Embodiments of the present invention will be described below with reference to the drawings. The following examples are one embodiment of the present invention and do not limit the scope of the present invention.

(Basic structure)
First, the basic structure of a nonvolatile semiconductor memory device according to an embodiment of the present invention will be described.

  FIG. 1A is a schematic circuit configuration diagram of a nonvolatile semiconductor memory device according to an embodiment of the present invention, and FIG.

  As shown in FIG. 1B, the nonvolatile semiconductor memory device according to the embodiment of the present invention includes a p-type well 26 formed on the semiconductor substrate and a gate insulating film (not shown) on the well 26. A pair of provided selection gate electrodes 4 and 6, a plurality of floating gate electrodes (FG) 8 provided on a well 26 between the selection gate electrodes 4 and 6 via a gate insulating film (not shown), and each floating gate electrode A plurality of control gate electrodes (CG) 2 provided between the gate electrodes (FG) 8 and between the floating gate electrode (FG) 8 and the selection gate electrodes 4 and 6 via inter-electrode insulating films, respectively. Yes. The control gate electrode (CG) 2 is also provided on the well 26 via an insulating film (not shown).

  Control gate lines CG0 to CG8 are connected to each control gate electrode (CG) 2, and selection gate lines SGS and SGD are connected to the selection gate electrodes 4 and 6, respectively.

  In the well 26, an n-type bit line contact region 14, a source line contact region 16, and a plurality of diffusion layers 18 are provided. A bit line BL is wired in the bit line contact region 14. A source line SL is wired in the source line contact region 16. Each diffusion layer 18 is provided in a well 26 below each control gate electrode (CG) 2. The pair of select gate electrodes 4 and 6 and the plurality of floating gate electrodes (FG) 8 share the diffusion layer 18 and are arranged in series to form a NAND memory cell string (hereinafter referred to as “NAND string”).

  The NAND string includes a select gate transistor SG1 between the bit line BLk or BLk + 1, and one select gate line SGD is connected in parallel to the control gate lines CG0 to CG8. The NAND string includes a select gate transistor SG2 between the NAND line and the source line SL, and one select gate line SGS is connected in parallel to the control gate lines CG0 to CG8. Further, the NAND string is connected to the bit line BLk or BLk + 1 via the selection gate transistor SG1 connected adjacent to the control gate line CG8 and connected to the control gate line CG0. To the source line SL.

  Select gate lines SGS, SGD are wired to the gates of these select gate transistors SG1, SG2.

  As is clear from FIG. 1A, the two NAND strings are connected to different bit lines BLk and BLk + 1 via the bit line side select gate transistor SG1, and the bit line contacts CBk and CBk + 1 for each bit line. Have

  As shown in FIG. 1B, the bit line BL side of the NAND string is connected to the bit line contact region 14 via the selection gate line SGD connected to the selection gate 6 of the bit line side selection gate transistor SG1. The source line SL side of the NAND string is connected to the source line contact region 16 via the selection gate line SGS connected to the selection gate 4 of the source line side selection gate transistor SG2.

  A configuration including the source side selection gate transistor SG1 and the bit line side selection gate transistor SG2 in addition to the NAND string is referred to as a “NAND memory cell unit”.

  The circuit configuration shown in FIG. 1A shows two rows of NAND memory cell units, and the structure shown in FIG. 1B is the same as the circuit configuration shown in FIG. An apparatus having a cross-sectional structure schematically showing one NAND memory cell unit portion, and a schematic cross-sectional structure taken along line II in the planar pattern diagram shown in FIG. Represents.

  In the above example, there is one bit line side selection gate line SGD and one source side selection gate line SGS, but the embodiment of the present invention is not limited to this, and the bit line side selection gate line SGD is not limited thereto. There may be two or more, and there may be two or more source-side selection gate lines SGS.

  In the embodiment of the present invention, the number of floating gate electrodes (FG) and control gate electrodes (CG) may be any number as long as it is three or more.

  In the embodiment of the present invention, a dummy floating gate electrode may be provided between the control gate electrode (CG) at the extreme end and the selection gate electrodes 4 and 6.

(basic action)
Next, a basic operation of read access of the nonvolatile semiconductor memory device according to the example of the present invention will be described.

  Read access of the nonvolatile semiconductor memory device according to the embodiment of the present invention is continuously performed. Hereinafter, of the two read accesses that are successively performed, the first read access is referred to as a first read access, and the read access subsequent to the first read access is referred to as a second read access.

During the first read access, one of the plurality of floating gate electrodes (FG) 8 is selected as the first selected floating gate electrode (SFG1) and is located on both sides of the first selected floating gate electrode (SFG1). A predetermined read voltage V _t (for example, V _t = 0 V) is applied to each of a pair of control gate electrodes (CG) 2 (hereinafter referred to as “first selection control gate electrode (SCG1)”).

The voltage of the first selection floating gate electrode (SFG1) is an average value of the voltages of the pair of first selection control electrodes (SCG1). (In actuality, the value is obtained by multiplying the coupling ratio between CG and FG, but this value is used for simplification.) In this embodiment, it is applied to the two first selection control electrodes (SCG1). Since the predetermined read voltage V _t is equal, the voltage of the first selected floating gate electrode (SFG1) is also equal to the predetermined read voltage V _t (= 0V).

At this time, a read low voltage V _readL (for example, V _readL ) is alternately applied to control gate electrodes other than the first selected control gate electrode (SCG1) (hereinafter referred to as “first unselected control gate electrode (NSCG1)”). = 0V) and a read high voltage V _readH (for example, V _readH = 10V) are applied. As a result, the voltage of the floating gate electrodes other than the first selected floating gate electrode (SFG1) (hereinafter referred to as “first unselected floating gate (NSFG1)”) is 5V.

During the second read access, the 2nth (n is a natural number) floating gate electrode (FG) 8 from the first selected floating gate electrode (SFG1) is selected as the second selected floating gate electrode (SFG2). A predetermined read voltage V _t (for example, V _t = 0V) is applied to each of a pair of control gate electrodes (hereinafter referred to as “second selection control gate electrode (SCG2))” located on both sides of the selected floating gate electrode (SFG2). ) Is applied.

Similar to the read access of the first selected floating gate electrode (SFG1), the voltage of the second selected floating gate electrode (SFG2) is the average value of the voltage of the second selected control electrode (SCG2), and this embodiment In the embodiment, since the predetermined read voltage V _t applied to the two second selection control electrodes (SCG2) is equal, the voltage of the second selection floating gate electrode (SFG2) is also the predetermined read voltage V _t. (= 0V).

Further, read access to the first selected floating gate electrode (SFG1) is made to a control gate electrode other than the second selected control gate electrode (SCG2) (hereinafter referred to as “second unselected control gate electrode (NSCG2)”). Similarly to the time, a read low voltage V _readL (for example, V _readL = 0 V) and a read high voltage V _readH (for example, V _readH = 10 V) are applied alternately, and other than the second selected floating gate electrode (SFG2). The voltage of the floating gate electrode (hereinafter referred to as “second unselected floating gate (NSFG2)”) is 5V.

Non Each read access, the memory cells MC combination belongs predetermined read voltage V _t is applied selected control gate electrode (SCG) is the threshold voltage is determined, the different read voltages _V readL, V readH is applied together The memory cell MC to which the selected control gate electrode (NSFG) belongs is turned on regardless of the stored data.

  In the first and second read accesses, 2n-1 (n is a natural number) floating gate electrodes (FG) between the first selected floating gate electrode (SFG1) and the second selected floating gate electrode (SFG2). ) 8 exists.

  Next, Example 1 of the present invention will be described. Embodiment 1 of the present invention describes an example in which charge / discharge current and noise generated during read access are reduced using a circuit configuration of a nonvolatile semiconductor memory device.

  In the first embodiment of the present invention, the control gate electrodes (CG) 2 to which the control gate lines CG0 to CG8 to 8 are connected are referred to as control gate electrodes (CG0 to 8), respectively.

  FIG. 2 is a logical circuit configuration diagram (a) of the nonvolatile semiconductor memory device according to the first embodiment of the invention and a table (b) showing a relationship between a physical address and a logical address in read access.

  As shown in FIG. 2A, the nonvolatile semiconductor memory device according to the first embodiment of the present invention includes a plurality of NAND circuits corresponding to the plurality of control gate electrodes (CG) 2 and address lines. A memory unit including a plurality of transistors arranged so that the relationship shown in FIG. 2B is established with respect to the signals A0 to BA2 generated by decoding.

  As shown in FIG. 2B, the memory section of the nonvolatile semiconductor memory device according to the first embodiment of the present invention accesses every other physical address every time the logical address is incremented. That is, the physical address “2m-2 (m is a natural number)” corresponds to the logical address “0-3” (first logical address), and the physical address “2m-1” is the logical address “4”. Corresponds to “˜7” (second logical address).

  Here, an example in which the logical address “address 5” is accessed during the first read access and the logical address “address 6” is accessed during the second read access will be described.

  FIG. 3 is a conceptual diagram showing voltage transition of each control gate electrode (CG0-8) and each floating gate electrode (FG0-7) corresponding to FIG.

  During the first read access, the floating gate electrode (FG3) indicating the physical address “3” corresponding to the logical address “address 5” is selected as the first selected floating gate electrode (SFG1). As a result, the control gate electrodes (CG3, 4) located on both sides of the floating gate electrode (FG3) become the first selection control gate electrode (SCG1). Further, the floating gate electrodes (FG0-2, 4-7) serve as the first non-selected floating gate electrode (NSFG1), and the control gate electrodes (CG0-2, 5-8) serve as the first non-selected control gate electrode (NSFG1). NSCG1).

Subsequently, a predetermined read voltage V _t (= 0 V) is applied to each of the control gate electrodes (CG3, 4). As a result, the voltage of the floating gate electrode (FG3) becomes 0V.

At this time, the read low voltage V _readL (= 0 V) and the read high voltage V _readH (= 10 V) are alternately applied to the control gate electrodes (CG 0 to 2, 5 to 8). That is, the read high voltage VreadH (= 10 V) is applied to the control gate electrodes (CG0, CG2, CG5, CG7) which are the first non-selected control gate electrodes (NSCG1), and the first non-selected control gate electrodes ( A read low voltage VreadL (= 0 V) is applied to the control gate electrodes (CG1, CG6, CG8) which are NSCG1). As a result, the voltage of the floating gate electrodes (FG0-2, 4-7) which is the first non-selected floating gate electrode (NSFG1) is 5V.

  During the second read access, the floating gate electrode (FG5) indicating the physical address “5th address” corresponding to the logical address “6th address” is selected as the second selected floating gate electrode (SFG2). As a result, the control gate electrodes (CG5, 6) located on both sides of the floating gate electrode (FG5) become the second selection control gate electrode (SCG2). The floating gate electrodes (FG0 to 4, 6, and 7) serve as the second non-selected floating gate electrode (NSFG2), and the control gate electrodes (CG0 to 4, 7, and 8) serve as the second non-selected control gate electrode (NSFG2). NSCG2).

Subsequently, a predetermined read voltage V _t (= 0 V) is applied to each of the control gate electrodes (CG5, CG6). As a result, the voltage of the floating gate electrode (FG5) becomes 0V.

At this time, the read low voltage V _readL (= 0 V) and the read high voltage V _readH (= 10 V) are alternately applied to the control gate electrodes (CG 0 to 4, 7, 8). That is, the read high voltage VreadH (= 10 V) is applied to the control gate electrodes (CG0, CG2, CG4, CG7) which are the second non-selected control gate electrodes (NSCG1), and the second non-selected control gate electrodes (NS A read low voltage VreadL (= 0 V) is applied to the control gate electrodes (CG1, CG3, CG8) which are NSCG1). As a result, the voltage of the floating gate electrodes (FG0 to 4, 6, and 7) that are the second non-selected floating gate electrode (NSFG2) is 5V.

  As shown in FIG. 3, when the first read access and the second read access are compared, the voltages of the control gate electrodes (CG3 to CG6) that have become the first or second selection control gate electrodes (SCG1, 2). Only has changed. In other words, the voltages of the control gate electrodes (CG0 to 2, 7, 8) that have become the first and second non-selected control gate electrodes (NSCG1, 2) are maintained without change.

  FIG. 4 is a logical circuit configuration diagram (a) of a nonvolatile semiconductor memory device according to a modification of the first embodiment of the present invention and a table (b) showing a relationship between a physical address and a logical address in read access.

  As shown in FIG. 4A, the nonvolatile semiconductor memory device according to the modification of the first embodiment of the present invention includes a plurality of NAND circuits corresponding to the control gate electrode (CG) 2 and an address line. A memory unit including a plurality of transistors arranged so that the relationship shown in FIG. 4B is established with respect to the signals A0 to BA2 generated by predecoding.

  As shown in FIG. 4B, in the memory unit of the nonvolatile semiconductor memory device according to the modification of the first embodiment of the present invention, every time the logical address is incremented, the physical address is accessed every third address. It shows that.

  Here, an example in which the logical address “6” is accessed during the first read access and the logical address “7” is accessed during the second read access will be described.

  FIG. 5 is a conceptual diagram showing voltage transition of each control gate electrode (CG0-8) and each floating gate electrode (FG0-7) corresponding to FIG.

  First, in the first read access, the floating gate electrode (FG3) indicating the physical address “address 3” corresponding to the logical address “address 6” is selected as the first selected floating gate electrode (SFG1). As a result, the control gate electrodes (CG3, 4) located on both sides of the floating gate electrode (FG3) become the first selection control gate electrode (SCG1). Further, the floating gate electrodes (FG0-2, 4-7) serve as the first non-selected floating gate electrode (NSFG1), and the control gate electrodes (CG0-2, 5-8) serve as the first non-selected control gate electrode (NSFG1). NSCG1).

Subsequently, a predetermined read voltage V _t (= 0 V) is applied to each of the control gate electrodes (CG3, CG4). As a result, the voltage of the floating gate electrode (FG3) becomes 0V.

At this time, the read low voltage V _readL (= 0 V) and the read high voltage V _readH (= 10 V) are alternately applied to the control gate electrodes (CG 0 to 2, 5 to 8). As a result, the voltage of the floating gate electrodes (FG0 to 2, 4 to 7) becomes 5V.

  During the second read access, the floating gate electrode (FG7) indicating the physical address “7th address” corresponding to the logical address “7th address” is selected as the second selected floating gate electrode (SFG2). As a result, the control gate electrodes (CG7, 8) located on both sides of the floating gate electrode (FG7) become the second selection control gate electrode (SCG2). Further, the floating gate electrodes (FG0 to FG6) become the second non-selected floating gate electrode (NSFG2), and the control gate electrodes (CG0 to CG6) become the second non-selected control gate electrode (NSCG2).

Subsequently, a predetermined read voltage V _t (= 0 V) is applied to each of the control gate electrodes (CG7, CG8). As a result, the voltage of the floating gate electrode (FG7) becomes 0V.

At this time, the read low voltage V _readL (= 0 V) and the read high voltage V _readH (= 10 V) are alternately applied to the second non-selected control gate electrode (NSCG2). As a result, the voltage of the floating gate electrodes (FG0 to FG6) becomes 5V.

  As shown in FIG. 5, when the first read access and the second read access are compared, the control gate electrodes (CG3, 4, 7, 7) that become the first or second selection control gate electrodes (SCG1, 2) are obtained. Only the voltage of 8) and the voltage of the control gate electrodes (CG5, 6) located between the first and second selection control gate electrodes (SCG1, 2) are changed. In other words, the voltage of the control gate electrodes (CG0 to CG2) is maintained without change.

  According to the first embodiment of the present invention, the voltage is applied to the selected control gate electrode (SCG) so that only the voltage of the selected floating gate electrode (SFG) changes in successive read accesses. The charge / discharge current generated when a voltage is applied to (NSCG) can be reduced, and the operation of the nonvolatile semiconductor memory device can be stabilized.

  Further, according to the first embodiment of the present invention, noise generated by the charge / discharge current and the voltage change of the floating gate electrode (FG) 8 can be reduced, and the operation of the nonvolatile semiconductor memory device can be stabilized.

  Next, a second embodiment of the present invention will be described. The first embodiment of the present invention is an example using the circuit configuration of the nonvolatile semiconductor memory device, but the second embodiment of the present invention uses the address conversion table to reduce the charge / discharge current and noise generated during read access. This is an example. In addition, the description about the content similar to Example 1 of this invention is abbreviate | omitted.

  In Example 2 of the present invention, the control gate electrodes (CG) 2 to which the control gate lines CG0 to CG8 to 8 are connected are referred to as control gate electrodes (CG0 to 8), respectively.

  FIG. 6 is a logical circuit configuration diagram (a) of the nonvolatile semiconductor memory device according to the second embodiment of the present invention and a table (b) showing a relationship between a physical address and a logical address in read access.

  As shown in FIG. 6A, the nonvolatile semiconductor memory device according to Example 2 of the present invention pre-decodes a plurality of NAND circuits corresponding to the above-described control gate electrode (CG) 2 and address lines. A memory unit including a plurality of transistors arranged according to a predetermined standard with respect to the signals A0 to BA2 generated in this way is provided.

  As shown in FIG. 6B, the physical address of the memory unit 201 (FIG. 7) of the nonvolatile semiconductor memory device according to the second embodiment of the present invention is continuously accessed every time the logical address is incremented. The

  FIG. 7 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to Example 2 of the present invention.

  The nonvolatile semiconductor memory device according to the second embodiment of the present invention includes a memory unit 201 and a controller 202.

  The memory unit 201 has the above-described basic structure (FIGS. 1 and 2) and operates according to the above-described basic operation. The memory unit 201 has the above-described logic circuit configuration (FIG. 6).

  The controller 202 includes an address conversion table storage unit 2021 and a control unit 2022.

  The address conversion table storage unit 2021 stores a plurality of address conversion tables 2021A and 2021. The address conversion tables 2021A and 202B are information for converting a logical address into a physical address. For example, as shown in FIG. 2B or 4B, the physical address is changed every time the logical address is incremented. 2m-1 (m is a natural number) includes information indicating that access is made every other address.

The control unit 2022 refers to the address conversion table 2021A or B stored in the address conversion table storage unit 2021, converts the logical address into a physical address according to the information included in the address conversion table 2021A or B, and converts the converted physical address A predetermined read voltage V _t (for example, V _t = 0 V) is applied to the pair of control gate electrodes (CG) 2 located on both sides of the floating gate electrode (FG) 8 corresponding to the address.

  At the time of read access of the nonvolatile semiconductor memory device according to the second embodiment of the present invention, unlike the relationship between the physical address and the logical address shown in FIG. 6B, the information included in the address conversion table 2021A or B (that is, According to the relationship between the physical address and the logical address as shown in FIG. 2B or FIG. 4B), the floating gate electrode (FG0-7) and the control gate electrode (CG0) as shown in FIG. The voltage of ˜8) transitions.

  In the second embodiment of the present invention, the address conversion table storage unit 2021 may be provided outside the controller 202 or may be provided inside the memory unit 201.

  In the second embodiment of the present invention, the controller 202 may be provided inside the memory unit 201.

  According to the second embodiment of the present invention, a voltage is applied to the pair of control gate electrodes (CG) 2 with reference to the address conversion tables 2021A and 202B. Therefore, each time the logical address is incremented, the physical address is continuously increased. Even when a logic circuit indicating access is used, the same effect as in the first embodiment of the present invention can be obtained.

1A is a schematic circuit configuration diagram of a nonvolatile semiconductor memory device according to an embodiment of the present invention, and FIG. 2A is a logical circuit configuration diagram (a) of the nonvolatile semiconductor memory device according to the first embodiment of the invention, and FIG. 2B is a table (b) showing a relationship between a physical address and a logical address in read access. It is a conceptual diagram which shows the transition of the voltage of each control gate electrode (CG0-8) and each floating gate electrode (FG0-7) corresponding to FIG. FIG. 6 is a logical circuit configuration diagram (a) of a nonvolatile semiconductor memory device according to a modification of Example 1 of the present invention and a table (b) showing a relationship between a physical address and a logical address in read access. FIG. 5 is a conceptual diagram illustrating voltage transition of each control gate electrode (CG0 to 8) and each floating gate electrode (FG0 to 7) corresponding to FIG. 4. FIG. 7 is a logical circuit configuration diagram (a) of a nonvolatile semiconductor memory device according to Example 2 of the invention and a table (b) showing a relationship between a physical address and a logical address in read access. It is a block diagram which shows the structure of the non-volatile semiconductor memory device based on Example 2 of this invention.

Explanation of symbols

2 Control gate electrode (CG)
4, 6 Select gate electrode 8 Floating gate electrode (FG)
14 Bit line contact region 16 Source line contact region 18 Diffusion layer 26 Well 201 Memory unit 202 Controller 2021 Address conversion table storage unit 2021A, B Address conversion table 2022 Control unit

Claims (5)

A semiconductor substrate; a pair of select gate electrodes provided on the semiconductor substrate via a gate insulating film; and a plurality of gate electrodes provided on the semiconductor substrate between the pair of select gate electrodes. A control method for a nonvolatile semiconductor memory device, comprising: a floating gate electrode; and a plurality of control gate electrodes provided between the floating gate electrodes and between the floating gate electrode and the selection gate electrode, respectively. ,
During a first read access, a predetermined voltage is applied to a pair of control gate electrodes located on both sides of the first floating gate electrode selected from among the plurality of floating gate electrodes,
In a second read access subsequent to the first read access, the predetermined control gate electrodes are placed on the pair of control gate electrodes located on both sides of the 2n (n is a natural number) second floating gate electrode from the first floating gate electrode. A read voltage is applied to the nonvolatile semiconductor memory device.   2. The nonvolatile memory according to claim 1, wherein at the time of the second read access, the read voltage is applied to a pair of control gate electrodes positioned on both sides of the second floating gate electrode from the first floating gate electrode. Control method for conductive semiconductor memory device A semiconductor substrate; a pair of select gate electrodes provided on the semiconductor substrate via a gate insulating film; and a plurality of gate electrodes provided on the semiconductor substrate between the pair of select gate electrodes. A control method for a nonvolatile semiconductor memory device, comprising: a floating gate electrode; and a plurality of control gate electrodes provided between the floating gate electrodes and between the floating gate electrode and the selection gate electrode, respectively. ,
During the first read access, the voltage of the first floating gate electrode selected from the plurality of floating gate electrodes changes,
A non-volatile semiconductor, wherein a voltage of a 2nth (n is a natural number) second floating gate electrode from the first floating gate electrode changes during a second read access following the first read access. Storage device control method. A semiconductor substrate; a pair of select gate electrodes provided on the semiconductor substrate via a gate insulating film; and a plurality of gate electrodes provided on the semiconductor substrate between the pair of select gate electrodes. A non-volatile semiconductor memory device comprising: a floating gate electrode; and a plurality of control gate electrodes provided between each floating gate electrode and between the floating gate electrode and the selection gate electrode,
A second logical address in which physical addresses 2m-2 (m is a natural number) corresponds to a first logical address that continues, and 2m-1 addresses in a physical address follow each of the first logical addresses. A non-volatile semiconductor memory device comprising a memory portion having transistors arranged so as to correspond to the above. A semiconductor substrate; a pair of select gate electrodes provided on the semiconductor substrate via a gate insulating film; and a plurality of gate electrodes provided on the semiconductor substrate between the pair of select gate electrodes. A non-volatile semiconductor memory device comprising: a floating gate electrode; and a plurality of control gate electrodes provided between each floating gate electrode and between the floating gate electrode and the selection gate electrode,
A memory unit having transistors arranged so that each address of a physical address corresponds to a continuous logical address;
The 2m-2 (m is a natural number) address of the physical address of the memory unit is converted into a continuous first logical address, and the 2m-1 address of the physical address of the memory unit is respectively followed by the first logical address. An address conversion table storage unit for storing an address conversion table for converting to a second continuous logical address;
And a control unit that applies a predetermined read voltage to a pair of control gate electrodes located on both sides of the floating gate electrode in accordance with an address conversion table stored in the address conversion table storage unit. Semiconductor memory device.

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