JP2008311570A - Semiconductor device - Google Patents

Abstract

A wiring resource for signal wiring can be secured while suppressing a voltage drop of a power supply voltage and maintaining a stable operation of a semiconductor device.
A first power supply wiring 11 provided on an upper layer of a semiconductor chip, and a second power supply 11 provided on a substrate side of the first power supply wiring 11 and provided in a direction orthogonal to the first power supply wiring 11. Power supply wiring 12, and at least one wiring layer is provided between the first power supply wiring 11 and the second power supply wiring 12, and a first contact group 21 connecting the first power supply wiring 12 is provided. By providing, it is possible to secure a large number of wiring resources in the wiring layer provided between the power supply wirings 11 and 12, suppress a voltage drop of the power supply voltage, and maintain a stable operation of the semiconductor device.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device having a plurality of wiring layers, and more particularly to improvement of a power supply wiring structure of a semiconductor device.

  In a semiconductor device, a power supply current consumed when a circuit element is operated flows to a power supply wiring, and thus a power supply voltage drop and a ground potential rise occur. However, a malfunction of a circuit operation due to a power supply and ground potential fluctuation is not caused. In addition, it is necessary to sufficiently reduce the wiring resistance of the power supply wiring.

  In particular, due to the recent high integration and large scale of semiconductor devices, the wiring layers have become multi-layered, supplying a stable power supply voltage and reducing wiring area (necessary for arranging signal wiring). Power supply wiring design that secures a large wiring area) has become important.

  As a semiconductor device having a power supply wiring structure for supplying a stable power supply voltage and securing a large amount of wiring resources, there is one in which power is supplied to a circuit element from a mesh power supply wiring on the semiconductor device (for example, a patent). Reference 1).

  FIG. 4 is a three-dimensional representation of the positional relationship between the components of the power supply wiring structure of the conventional semiconductor device. As shown in the figure, the semiconductor device B includes a first power supply line 11, a mesh power supply line composed of a second power supply line 12, a first contact 21 connecting the first and second power supplies, a first and a second power supply line. A circuit element power supply line 13 formed below the second power supply line, a second contact 22 for connecting the circuit element power supply line and the mesh power supply line, and a power supply to the circuit element 30 It has become.

In the semiconductor device configured as described above, since the power supply wiring is configured in a mesh shape, the voltage drop of the power supply voltage is suppressed, and the stable operation of the semiconductor device can be maintained.
JP-A-5-335484 (page 2-3, FIG. 1)

  However, the conventional semiconductor device described above has the following problems.

  The mesh power supply wiring is often provided in the upper layer of the semiconductor device, and there are many wiring layers between the circuit element power supply wiring and the mesh power supply wiring. Therefore, when the intersection of the mesh power supply wiring and the circuit element power supply wiring is connected by the second contact 22, the plurality of wiring layers between the mesh power supply wiring and the circuit element power supply wiring A large number of contacts penetrating the wiring layer are disposed, and a very large amount of wiring resources (area necessary for arranging signal wirings) are consumed, resulting in a shortage of signal wiring resources. As a result, the area of the semiconductor device must be increased in order to make up for this shortage of wiring resources.

  The present invention has been made paying attention to the above-described problem, and has a power supply wiring structure that secures more wiring resources for signal wiring while maintaining a stable operation of the semiconductor device by suppressing a voltage drop of the power supply voltage. It is an object to provide a semiconductor device having the following.

  A semiconductor device according to the present invention is a semiconductor device having a plurality of wiring layers, and a plurality of first power supply wirings provided in the first wiring layer and parallel to each other, and closer to the substrate side than the first wiring layer. A plurality of second power supply wirings orthogonal to the first power supply wiring provided in the second wiring layer, and a first power supply wiring provided in a third wiring layer on the substrate side from the second wiring layer A plurality of third power supply wirings parallel to each other, and at least one layer between the first wiring layer and the second wiring layer and between the second wiring layer and the third wiring layer. A first contact group including one or more wiring layers and one or more contacts each having a wiring layer and connecting the first power supply wiring and the second power supply wiring; and the second power supply One or more wiring layers and one or more contacts connecting the wiring and the third power supply wiring to each other Those having a second contact group comprising.

  According to this configuration, the resources of the wiring layer are ensured between the first power supply wiring and the second power supply wiring, and stable power supply is possible.

  In the semiconductor device having the above structure, the number of wiring layers between the first wiring layer having the first power supply wiring and the second wiring layer having the second power supply wiring is an odd number, There is a mode in which the wiring direction of the first power supply wiring and the wiring direction of the second power supply wiring are orthogonal to each other. According to this configuration, the first power supply wiring and the second power supply wiring are configured to be orthogonal to each other regardless of the number of wiring layers and the priority wiring direction. The degree of freedom of the arrangement position of the first contact group for connecting the wiring is increased, and stable power supply is possible.

  Further, in the semiconductor device having the above structure, there is a mode in which the thickness of the first wiring layer having the first power supply wiring is larger than the thickness of the second wiring layer having the second power supply wiring.

  In the semiconductor device having the above-described structure, there is a mode in which a wiring width of the first power supply wiring is larger than a wiring width of the second power supply wiring.

  Further, in the semiconductor device having the above structure, there is an aspect in which a wiring interval of the first power supply wiring is smaller than a wiring interval of the second power supply wiring.

  Accordingly, stable power supply can be achieved by using the power supply wiring for the upper wiring having a small wiring resistance per unit length.

  In the semiconductor device having the above-described configuration, the number of contacts constituting the first contact group is smaller than the maximum number of contacts that can be arranged at a location where the first power supply wiring and the second power supply wiring intersect each other. There is a mode.

  In the semiconductor device having the above structure, the first wiring layer includes only the first power supply wiring.

  As a result, further wiring resources can be secured.

  Further, in the semiconductor device having the above structure, there is a mode in which the signal wiring is provided only in the wiring layer on the substrate side with respect to the first wiring layer. According to this configuration, it is possible to supply power stably by using the upper layer wiring having a smaller wiring resistance per unit length as the power source wiring than the wiring layer on the substrate side. Further, by using the wiring layer on the substrate side having a small upper limit of the wiring width only for the signal wiring, it is possible to efficiently use the wiring resources.

  According to the present invention, it is possible to secure a large amount of wiring resources for signal wiring while suppressing the voltage drop of the power supply voltage and maintaining the stable operation of the semiconductor device.

  Embodiments of a semiconductor device according to the present invention will be described below in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a perspective view showing a configuration of a semiconductor device A1 according to the first embodiment of the present invention. The semiconductor device A1 has a plurality of wiring layers, and includes a first power supply wiring 11, a second power supply wiring 12, a third power supply wiring 13, a first contact group 21, a second contact group 22, and circuit elements. 30, and one wiring layer is provided between the first power supply wiring 11 and the second power supply wiring 12.

  The first power supply wiring 11 is formed on the upper layer of the semiconductor device, and is a plurality of power supply wirings in a positional relationship parallel to each other at a predetermined interval.

  The second power supply wiring 12 is a projection shape of the first power supply wiring 11 and the second power supply wiring 12 as viewed from the uppermost layer side on the wiring layer below the wiring layer provided with the first power supply wiring 11. Are a plurality of power supply wires provided in directions orthogonal to each other, and the second power supply wires 12 are arranged in parallel to each other at a predetermined interval.

  The third power supply wiring 13 is a plurality of power supply wirings formed according to the arrangement of circuit elements 30 (for example, standard cells) formed in a wiring layer closer to the substrate than the second power supply wiring 12. A power supply voltage (or ground voltage) is supplied to the element 30.

  The first contact group 21 connects the first power supply wiring 11 and the second power supply wiring 12 at a position where they intersect.

  For the connection between the first power supply wiring 11 and the second power supply wiring 12, wiring such as a strap power supply is not used, and only the first contact group 21 is used for connection. The strap power supply wiring is a structure in which the VDD power supply wiring and the VSS power supply wiring are arranged in parallel in both the uppermost wiring layer and the lowermost wiring layer, and the VDD / VSS power supply wirings of both wiring layers are orthogonal to each other. It is.

  The second contact group 22 connects the second power supply wiring 12 and the third power supply wiring 13 at a position where they intersect.

  These power supply wirings may be used as VDD wiring for supplying the power supply voltage on the high potential side to the circuit element 30, or may be used as VSS wiring for supplying the power supply voltage on the low potential side.

  Further, the wiring width and wiring interval of the first power supply wiring 11 and the second power supply wiring 12 are determined according to the power consumption of the circuit element 30 such as a standard cell to which the power supply voltage is supplied.

  In the semiconductor device A1 configured as described above, the first power supply wiring 11 and the second power supply wiring 12 are connected only by the contact groups 21 and 22 without using a strap power supply or the like. Thus, the wiring resource of the wiring layer between the first power supply wiring 11 and the second power supply wiring 12 can be used for the signal wiring.

  In view of the ease of wiring, a configuration in which the wiring direction of the wiring layer immediately below or directly above the wiring direction of a certain wiring layer is considered to be perpendicular. However, in this embodiment, regardless of the number of wiring layers between the first power supply wiring 11 and the second power supply wiring 12, the first power supply wiring 11 and the second power supply wiring 12 are arranged in a perpendicular direction. Due to the configuration, the contact groups 21 and 22 can be arranged at the intersections of the first power supply wiring 11 and the second power supply wiring 12. When the first power supply wiring 11 and the second power supply wiring 12 are configured in parallel, the width and interval of the first power supply wiring 11 and the second power supply wiring 12 are considered in consideration of the arrangement of the contact groups 21 and 22. Need to be set. Therefore, the degree of freedom in power supply design is increased and power supply design is facilitated. If they cross each other, it is always possible to secure a rectangular crossing area in which the width of the first power supply wiring 11 and the width of the second power supply wiring 12 are two sides. If this is parallel instead of crossing, the crossing area of that size cannot always be secured.

  Although not shown, wiring other than the power supply wiring such as signal wiring is used for the wiring layer in which the first power supply wiring 11, the second power supply wiring 12, the third power supply wiring 13, and the like are provided. May be. On the other hand, the wiring layer constituting the first power supply wiring 11 may be configured to be used only for the power supply wiring, taking advantage of the fact that the wiring resistance per unit length is small.

(Embodiment 2)
FIG. 2 is a perspective view showing the configuration of the semiconductor device A2 according to the second embodiment of the present invention. In addition, about the component which has the function similar to Embodiment 1, the same code | symbol is attached | subjected and description is abbreviate | omitted.

  The semiconductor device A <b> 2 has a configuration in which the thickness of the wiring layer of the first power supply wiring 11 is thicker than that of the second power supply wiring 12 in order to further stabilize the power supply. In addition, the first power supply wiring 11 has a wider wiring width than the second power supply wiring 12. Further, the first power supply wiring 11 has a smaller wiring interval than the second power supply wiring 12. The wiring resistance is proportional to the wiring cross-sectional area, that is, the thickness and thickness.

  Also in the present embodiment, the projected shapes of the first power supply wiring 11 and the second power supply wiring 12 are provided in a direction perpendicular to each other, and the connection between the first power supply wiring 11 and the second power supply wiring 12 is performed. By using only the contact groups 21 and 22 without using a strap power supply, wiring resources in the wiring layer between the first power supply wiring 11 and the second power supply wiring 12 are secured, and stable power supply is possible. In addition, since only the first power supply wiring 11 is strengthened, the power supply can be made more stable without sacrificing the wiring resources of the wiring layers other than the first power supply wiring 11.

  Furthermore, in order to secure more signal wiring resources, the second power supply wiring 12 is optimal for the minimum wiring layer thickness, wiring width, and wiring interval necessary for supplying the power consumed by the circuit element 30. In this configuration, since the second power supply wiring resource is reduced, the size of the first contact group is reduced, and the wiring layer resource between the first power supply wiring and the second power supply wiring is reduced. Further, more wiring resources of the wiring layer constituting the second power supply wiring are secured.

(Embodiment 3)
FIG. 3A is a plan view showing the configuration of the semiconductor device A3 according to the third embodiment of the present invention. FIG. 3B is a plan view showing the difference from the first embodiment in the case of the first embodiment. Represented by

  In a semiconductor device, it is very difficult to supply uniform power to all circuit elements, and the amount of power supply varies depending on the location of circuit elements. For example, in a circuit element close to the power source point such as a power supply pad, the wiring resistance is reduced by reducing the wiring length of the power supply wiring, the voltage drop is small, and power that sufficiently satisfies the circuit operation is supplied to the circuit element. The In such a place where the power supply sufficiently satisfying the circuit operation is provided, the power supply wiring can be reduced.

  In the semiconductor device A3, the number of contacts forming the contact group 21 that connects the first power supply wiring 11 and the second power supply wiring 12 at the location where the power that satisfies the circuit operation is supplied is arranged at the intersecting location. Less than the maximum number of contacts possible. Thereby, it is possible to increase the wiring resources of the wiring layer between the first power supply wiring 11 and the second power supply wiring 12.

  Note that the first contact group 21 in FIG. 3B shows a contact group before the size change, and the first contact group 21 in FIG. 3A shows a contact group after the size change with a reduced size. . FIG. 3D shows the number of contacts constituting the first contact group 21 before the size change, and FIG. 3C shows the first contact group 21 after the size change. The number of contacts is illustrated.

(Embodiment 4)
In the semiconductor device shown in FIG. 1, it is possible to use wirings other than the power supply wiring (for example, signal wirings) for the wiring layer constituting the first power supply wiring 11, but generally in the upper layer of the chip. The wiring layer to be configured has severe restrictions on process manufacturing such as a minimum wiring width and a minimum wiring interval, and it is not preferable to use it for wirings other than power supply wiring. For example, when comparing the signal wiring resources per area of the wiring layer configured on the upper layer and the wiring layer configured on the substrate side, the wiring layer configured on the upper layer has the minimum wiring width and the minimum wiring interval as described above. Is larger than the wiring layer formed on the substrate side, so that the signal wiring resources per unit area are reduced. In this way, the wiring layer configured on the upper layer of the chip makes use of the feature that the wiring resistance per unit length is small, and only the power supply wiring is configured to provide stable power supply, so that the wiring configured on the substrate side The power supply wiring composed of layers can be reduced as much as possible, and signal wiring resources can be secured.

  The semiconductor device of the present invention has an effect of securing more wiring resources for signal wiring while suppressing the voltage drop of the power supply voltage and maintaining the stable operation of the semiconductor device, and has a plurality of wiring layers. It is useful as a device.

The perspective view which shows the structure of the semiconductor device in Embodiment 1 of this invention. The perspective view which shows the structure of the semiconductor device in Embodiment 2 of this invention. The top view which shows the structure of the semiconductor device in Embodiment 3 of this invention in comparison with Embodiment 1, and the top view which shows the structure of the contact group of the semiconductor device in Embodiment 3 in comparison with Embodiment 1. A perspective view showing a configuration of a conventional semiconductor device

Explanation of symbols

A1, A2, A3 Semiconductor device 11 First power supply wiring 12 Second power supply wiring 13 Third power supply wiring 21 First contact group 22 Second contact group 30 Circuit element

Claims (8)

  A semiconductor device having a plurality of wiring layers, which is provided in a plurality of first power supply wirings provided in parallel to each other provided in the first wiring layer and in a second wiring layer on the substrate side from the first wiring layer. A plurality of second power supply wirings orthogonal to the first power supply wiring provided, and a plurality of third power supply lines parallel to the first power supply wiring provided in the third wiring layer on the substrate side from the second wiring layer. Power wiring, and having at least one wiring layer between the first wiring layer and the second wiring layer and between the second wiring layer and the third wiring layer, A first contact group composed of one or more wiring layers and one or more contacts connecting the first power supply wiring and the second power supply wiring to each other; the second power supply wiring; and the third power supply A second contact group consisting of one or more wiring layers and one or more contacts connecting the wirings to each other; Example was a semiconductor device.   The number of wiring layers between the first wiring layer having the first power wiring and the second wiring layer having the second power wiring is an odd number, and the wiring of the first power wiring The semiconductor device according to claim 1, wherein a direction and a wiring direction of the second power supply wiring are orthogonal to each other.   3. The semiconductor device according to claim 1, wherein a thickness of the first wiring layer having the first power supply wiring is larger than a thickness of the second wiring layer having the second power supply wiring.   The semiconductor device according to claim 1, wherein a wiring width of the first power supply wiring is larger than a wiring width of the second power supply wiring.   The semiconductor device according to claim 1, wherein a wiring interval of the first power supply wiring is smaller than a wiring interval of the second power supply wiring.   6. The number of contacts constituting the first contact group is smaller than the maximum number of contacts that can be arranged at a location where the first power supply wiring and the second power supply wiring intersect each other. The semiconductor device according to any one of the above.   The semiconductor device according to claim 1, wherein the first wiring layer includes only the first power supply wiring.   8. The semiconductor device according to claim 1, wherein a signal wiring is provided only in a wiring layer closer to the substrate than the first wiring layer. 9.