JP2008310221A - Current output device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce an error in an output terminal voltage of a current output device. <P>SOLUTION: This current output device is provided with the first NMOS 2 with a source terminal connected to the ground VSS and for determining a constant current, the second NMOS 3 with a source terminal connected to a drain terminal of the first NMOS 2 and with a drain terminal connected to an output terminal IOUT, and a circuit 11 for imparting an ON/OFF control signal to a gate terminal of the second NMOS 3, and a drain voltage Vd of the first NMOS 2 is made to be lower than that of the output terminal IOUT, by a gate voltage of the second NMOS 3. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a current output device, for example, a current output device used for constant current driving of a display element of a light emitting display panel.

  An example of this type of current output device is disclosed in Patent Document 1.

JP 2006-184649 A

  The voltage at the output terminal of the current output device varies in a wide range in proportion to the power supply voltage. For this reason, the high withstand voltage current output device tends to cause an error in the output terminal voltage. This is because a high breakdown voltage is required for an element that outputs a constant current and a drive circuit thereof, and a high breakdown voltage element is a low breakdown voltage element if the drain-source current Ids is small and the same element size is the same. This is because it is necessary to set the gate voltage higher than that, so that the constant current characteristics in the saturation region deteriorate.

  The present invention aims to solve the above problems.

The present invention
A first NMOS transistor having a source terminal connected to the ground and passing a constant current;
A second NMOS transistor having a source terminal connected to the drain terminal of the first NMOS transistor and a drain terminal connected to the output terminal;
A circuit for providing an on / off control signal to the gate terminal of the second NMOS transistor,
A current output device is provided in which the drain voltage of the first NMOS transistor is made lower than the output terminal by the gate voltage of the second NMOS transistor.

  According to the present invention, an error in the output terminal voltage can be reduced, and an element that outputs a constant current and its drive circuit have a high breakdown voltage.

Embodiment 1 FIG.
FIG. 1 is a circuit diagram showing a current output device according to Embodiment 1 of the present invention. FIG. 2 shows the output characteristics of the current output device of FIG.

  The current output device shown in FIG. 1 has a buffer 11 that receives an on / off signal of a current input via a switch terminal SW, a drain terminal connected to the output terminal of the buffer 11, a source terminal and a gate terminal Is connected to a low-voltage power supply VDD, a p-channel MOS transistor (hereinafter referred to as “PMOS transistor” or simply “PMOS”) 5, a drain terminal connected to the output terminal of the buffer 11, and a source terminal and a gate terminal connected to the ground potential. N-channel MOS transistor (hereinafter referred to as “NMOS transistor” or simply “NMOS”) 4 connected to a node, that is, ground VSS, and differential amplification that receives the current determination voltage input to the voltage setting terminal VEL at the inverting input terminal A circuit 12, an NMOS 1 having a source terminal connected to the ground VSS, and a high voltage The resistor 14 connected between the power supply VDDH and the drain terminal of the NMOS 1, the NMOS 2 connected to the ground VSS, the source terminal connected to the drain terminal of the NMOS 2, and the drain terminal connected to the output terminal IOUT. The NMOS 3 includes a protective resistor 13 connected between the gate terminal of the NMOS 3 and the output terminal of the buffer 11.

In the above circuit, the PMOS 5 and the NMOS 4 are connected in series between the low voltage power supply VDD and the ground VSS, and the gate terminals are connected to the low voltage power supply VDD and the ground VSS, respectively. Is maintained and constitutes a voltage divider circuit.
The resistor 14 and the NMOS 1 are connected in series between the high voltage power supply VDDH and the ground VSS.
The NMOS 3 and NMOS 2 are connected in series between the output terminal IOUT and the ground VSS to constitute a circuit that outputs a constant current. The NMOS 3 performs a switching operation, and an element having a relatively large current capability is used. On the other hand, since the NMOS 2 performs a constant current operation, an element having a relatively small current capability and good saturation characteristics is used. . The fluctuation range of the drain voltage of the NMOS 3 is wide, and the fluctuation range of the drain voltage of the NMOS 2 is narrow.

NMOS 2 and NMOS 1 have their gate terminals connected to each other to form a current mirror circuit.
The differential amplifier circuit 12, the NMOS 1, and the resistor 14 constitute a reference voltage circuit that supplies the reference voltage VG1 to the output terminal of the differential amplifier circuit 12.
A low voltage logic circuit is connected to the switch terminal SW connected to the input terminal of the buffer 11, and a control signal is supplied from the logic circuit.
The buffer 11 and the protection resistor 13 supply an on / off control signal to the gate terminal of the NMOS 3 to configure a current switch circuit that turns on / off the output current.
On the other hand, an overvoltage protection circuit is configured by the protection resistor 13, the NMOS 4, and the PMOS 5.

  For example, a high-voltage positive power supply of 20V is input to the high-voltage power supply VDDH. A negative power supply (0 V) is input to the ground VSS. The low voltage power supply VDD supplies, for example, a voltage of 2.5V.

The voltage at the drain terminal of the NMOS 1 is input to the non-inverting input terminal of the differential amplifier circuit 12, and the output terminal of the differential amplifier circuit 12 is connected to the gate terminal of the NMOS 1 as the reference voltage VG1. It is configured. As a result, the current Iref flowing through the NMOS 1 and the resistor 14 is controlled by the set voltage VEL, and its value is
VDDH−VEL = Iref × REL (1)
It will satisfy. In the above formula (1), REL is the resistance value of the resistor 14. The current Iref that satisfies the above equation (1) is used as the reference current.

  When the switch terminal SW is “H”, the output of the buffer 11 is also “H” = VDD, and if the output terminal Iout) is connected to the power supply VDDH via the load LD, the NMOS 3 is turned on, and the NMOS 2 and the NMOS 3 Current flows. The gate voltage VG1 output from the differential amplifier circuit 12 is supplied as a reference voltage to the gate terminal of the NMOS 2, and the current flowing through the NMOS 2 has the same value as Iref.

Here, when the low voltage power supply is VDD, the amplification factor of NMOS3 is β, the source / gate voltage of NMOS3 is Vgs, and the threshold voltage of NMOS3 is Vth, the relationship between the current Iref and the source / gate voltage Vgs of NMOS3 is simply It is expressed by the following formula.
Iref = (β / 2) × (Vgs−Vth) ² (2)

The voltage Vd at the drain terminal of the NMOS 2 is
Vd = VDD−Vgs (3)
Given in. The above equation holds because the output (VDD level) of the buffer 11 is applied to the gate terminal of the NMOS 3 through the protective resistor 13.
Therefore, the voltage Vd applied to the drain terminal of the NMOS 2 is lower than the voltage of the output terminal IOUT, is a low voltage, becomes substantially constant, and current fluctuation can be suppressed. In other words, the Vds-Ids characteristic of the NMOS 2 has a slope, and the source / drain current Ids also changes with changes in Vds. However, by reducing Vds, the width of the current fluctuation is also reduced. Thus, the first embodiment can improve the constant current characteristics.

For example, when VDD = 2.5V and VDDH = 20V, the voltage at the drain terminal of the NMOS 3 (the voltage at the output terminal IOUT) varies in the range of 20V to 2.5− (Vth + ΔOv). Here, ΔOv is a drive voltage (overdrive voltage) corresponding to the output current.
The voltage Vd at the drain terminal of the NMOS 2 is the same as the voltage at the source terminal of the NMOS 3,
Vd = 2.5− (Vth + ΔOv) (4)
It becomes.
Since the NMOS 2 and the NMOS 3 are connected in series, the source / drain current of the NMOS 3 is equal to the source / drain current of the NMOS 2, and the constant current characteristic is improved by suppressing the source / drain voltage fluctuation of the NMOS 2.

  The gate voltage VG2 of the NMOS 3 may exceed VDD due to fluctuations in the voltage at the output terminal IOUT. However, a protective resistor 13 is inserted between the gate terminal of the NMOS 3 and the output terminal of the buffer 11, and the output terminal of the buffer 11 is maintained at a low voltage by a voltage dividing circuit composed of the PMOS 5 and the NMOS 4. Therefore, the high voltage is not transmitted to the low voltage logic circuit connected to the input terminal of the buffer 11, and the logic circuit is protected from the high voltage.

  In the current output device according to the first embodiment, since the fluctuation of the voltage Vd at the drain terminal of the NMOS 2 is suppressed, the constant current characteristics can be improved. In the first embodiment, the voltage of the drain terminal Vd of the NMOS 2 and the voltage of the differential amplifier circuit 12 that drives the NMOS 2 can be limited to a low voltage, so that the breakdown voltage of the element can be reduced and the layout area can be reduced. Can be reduced.

Embodiment 2. FIG.
FIG. 3 shows a current output apparatus according to the second embodiment of the present invention. FIG. 4 shows the output characteristics of the current output device of FIG.

  The current output device shown in FIG. 3 is generally the same as the current output device shown in FIG. 1 except that an NMOS 6 is inserted between the source terminal of the NMOS 1 and the ground VSS, and between the source terminal of the NMOS 2 and the ground VSS. NNMOS 7 is inserted. That is, the NMOS 6 has a source terminal connected to the ground VSS, and a drain terminal and a gate terminal connected to the source terminal of the NMOS 1. The NMOS 7 has a source terminal connected to the ground VSS, a drain terminal connected to the source terminal of the NMOS 2, and a gate terminal connected to the drain terminal of the NMOS 6, and performs a high impedance operation.

The source terminals of the NMOS 6 and the NMOS 7 are both connected to the ground VSS and the gate terminals are connected to each other to constitute a current mirror circuit.
NMOS 1 and NMOS 2 also constitute a current mirror circuit with their gate terminals connected to each other.
A circuit that outputs a constant current is configured by the NMOS 7, NMOS 2, and NMOS 3 connected in series.

The current Iref flowing through the resistor 14, NMOS1, NMOS6 is
VEL = Iref × REL (5)
It has the value which satisfy | fills. In the above equation (5), REL is the resistance value of the resistor 14. The gate voltage VG3 of the NMOS 6 becomes a value corresponding to the current Iref by the current Iref that satisfies the above formula (5), and this gate voltage VG3 is also applied to the NMOS 7 at the gate terminal.

Further, the gate voltage VG1 output from the differential amplifier circuit 12 is supplied to the NMOS 2, and the current flowing through the NMOS 2 has the same value as Iref.
The NMOS 7 performs a high impedance operation such that a constant current lref flows. The constant current of the NMOS 2 is negatively fed back by the NMOS 7 connected to the source terminal thereof and converges to the current Iref.

  In the second embodiment, as in the first embodiment, the voltage Vd at the drain terminal of the NMOS 2 is substantially constant. Thereby, the constant current characteristic can be improved also in the second embodiment (FIG. 4).

  In the second embodiment, the constant current circuit composed of NMOS1, NMOS2, NMOS6, and NMOS7 is less affected by the voltage Vd at the drain terminal of the NMOS2 than in the first embodiment. On the other hand, in the second embodiment, the voltage Vd at the drain terminal of the NMOS 2 varies by the overdrive voltage of the NMOS 3. Even when the driving capability of the NMOS 3 is reduced, the output current of the second embodiment can reduce the error (variation) corresponding to the overdrive voltage.

Embodiment 3 FIG.
FIG. 5 shows a current output apparatus according to Embodiment 3 of the present invention. The current output device shown in FIG. 5 is generally the same as that shown in FIG. 1, but the PMOS 5, NMOS 4 and protection resistor 13 in FIG. 1 are omitted, and the output of the buffer 11 is directly connected to the gate terminal of the NMOS 3. The NMOS is turned on / off by the output of the buffer 11.

  As the buffer 11, a high withstand voltage buffer composed of high withstand voltage elements is used. The high voltage buffer 11 is connected to a low voltage power supply VDD.

  A high voltage may be applied to the node VG2 connected to the NMOS 3 due to the influence of the NMOS 3. In that case, a current flows through the output terminal of the high voltage buffer 11 via the parasitic diode to the low voltage power supply VDD, and the current path acts as a protection circuit. This action prevents high voltage noise from flowing into the switch terminal SW connected to the input terminal of the high withstand voltage buffer 11, and thus protects the low voltage logic circuit.

  Also in the third embodiment, the voltage Vd applied to the drain terminal of the NMOS 2 is a low voltage, and fluctuations in current can be suppressed.

  In the third embodiment, the protection element can be omitted by using a high voltage buffer as the buffer 11. Therefore, the layout area can be reduced.

It is a circuit diagram which shows the current output device of Embodiment 1 of this invention. The output characteristic of the current output device of FIG. 1 is shown. It is a circuit diagram which shows the current output device of Embodiment 1 of this invention. The output characteristic of the current output device of FIG. 3 is shown. It is a circuit diagram which shows the current output device of Embodiment 1 of this invention.

Explanation of symbols

1, 2, 3, 4 NMOS, 5 PMOS, 11 buffer, 12 differential amplifier circuit, 13 protection resistor, 14 resistor, IOUT output terminal, SW switch terminal, VEL setting voltage.

Claims (4)

A first NMOS transistor having a source terminal connected to the ground and passing a constant current;
A second NMOS transistor having a source terminal connected to the drain terminal of the first NMOS transistor and a drain terminal connected to the output terminal;
A circuit for providing an on / off control signal to the gate terminal of the second NMOS transistor,
The current output device, wherein the drain voltage of the first NMOS transistor is made lower than the output terminal by the gate voltage of the second NMOS transistor. A reference voltage circuit for setting the output current value is further provided.
2. The current output device according to claim 1, wherein the first NMOS transistor performs an operation of receiving the output of the reference voltage circuit at a gate terminal thereof and causing the constant current to flow. 3. A circuit connected to a high voltage power supply for determining a reference voltage and supplying the reference voltage to the gate terminal of the first NMOS transistor;
The current output device according to claim 1, wherein the on / off control signal is lower than a voltage of the output terminal and a voltage of the high voltage power supply. A circuit that provides the on / off control signal includes: a buffer connected to a low-voltage power supply and a ground; an output terminal of the buffer circuit; and a resistor inserted between a gate terminal of the second NMOS transistor; 4. A first PMOS transistor connected between an output terminal of a buffer and the constant voltage power source, and a third NMOS transistor connected between the output terminal of the buffer and the ground. The current output device according to any one of the above.

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