JP2008304684A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce image quality unevenness in an active matrix type TFT liquid crystal display device.
A plurality of pixels arranged along one scanning signal line has a storage capacitor Cst1 of a pixel closer to the signal input end of the scanning signal line of two adjacent pixels, and the farther one Cst1 ≧ Cst2 when the pixel storage capacitor is Cst2, and Cst3> Cst4 when the pixel storage capacitor closest to the signal input terminal of the scanning signal line is Cst3 and the pixel storage capacitor farthest is Cst4. A plurality of pixels arranged along one video signal line has a storage capacity of Cst5 for a pixel closer to the signal input end of the video signal line among two adjacent pixels, and a pixel for a far pixel If Cst6 is Cst6, then Cst5 ≧ Cst6, and if Cst7 is the holding capacity of the pixel closest to the signal input end of the video signal line and Cst8 is the holding capacity of the farthest pixel, Cs A display device in which t7> Cst8.
[Selection] Figure 9 (b)

Description

  The present invention relates to a display device, and more particularly to a technique effective when applied to an active matrix liquid crystal display device in which TFT elements are arranged in a matrix.

  Conventional displays for televisions and personal computers (PCs) use, for example, an active matrix type liquid crystal display device. An active matrix type liquid crystal display device has a liquid crystal display panel in which liquid crystal is sealed between a pair of substrates, and one of the pair of substrates has a number of active elements (referred to as switching elements). Are also arranged in a matrix. In many cases, the active element in the liquid crystal display device is a TFT element, for example.

  The active matrix TFT liquid crystal display device is a liquid crystal display device that controls writing of a driving voltage to a pixel electrode (liquid crystal element) of each pixel constituting a display region by turning on / off a TFT element used as an active element. is there. At this time, each pixel includes a storage capacitor (auxiliary capacitor or storage capacitor) that holds the driving voltage written in the pixel electrode after the TFT element is turned off until the TFT element is turned on next time. May also be called).

  By the way, an active matrix type TFT liquid crystal display device has a substrate provided with a plurality of scanning signal lines and a plurality of video signal lines sterically intersecting with the plurality of scanning signal lines through an insulating layer. And a plurality of pixels are arranged in the extending direction of the scanning signal line and the extending direction of the video signal line. At this time, the gates of the TFT elements of a plurality of pixels arranged in the extending direction of the scanning signal line are connected to, for example, one common scanning signal line. Therefore, for example, when the display area is wide like a liquid crystal television and the length of one scanning signal line becomes long, the TFT element of the pixel close to the signal input end of the scanning signal line and the signal input due to the delay of the scanning signal Bias conditions are different from those of a TFT element of a pixel far from the end. Due to the difference in the bias conditions of the TFT elements, for example, a voltage called an unwritten voltage and a voltage called a feedthrough voltage in each pixel (pixel electrode) are different.

  To put it simply, the unwritten voltage and the feedthrough voltage can be determined by turning on the voltage of the gradation signal for a certain pixel of the video signal inputted to the video signal line and the gate of the TFT element of the certain pixel. This is a potential difference generated between the voltage actually written in the pixel electrode of the pixel during the period. When the unwritten voltage and the feedthrough voltage in each pixel are different, luminance unevenness, flicker, and the like become remarkable, and there is a problem that image quality unevenness in one display device (display panel) becomes remarkable.

  Therefore, in a recent active matrix type TFT liquid crystal display device, for example, for a plurality of pixels having TFT elements whose gates are connected to one common scanning signal line, the unwritten voltage or the like in each pixel is constant. As described above, a method of changing the size of the storage capacitor formed in each pixel (for example, a value S / d obtained by dividing the electrode area S by the distance d between the electrodes) has been proposed (for example, Patent Documents). 1 and Patent Document 2).

In the display devices described in Patent Document 1 and Patent Document 2, paying attention to the delay of the scanning signal input to the scanning signal line, for example, a TFT whose gate is connected to one common scanning signal line The plurality of pixels having elements are formed such that the storage capacitor becomes smaller as the distance from the signal input end of the scanning signal line becomes longer. That is, for example, in the configuration shown in FIG. 19, looking for a pixel having a TFT element in which the gate is connected to the scanning signal lines GL _1, the holding of the nearest pixel from the signal input terminal of the scan signal lines GL ₁ The relationship between the capacitance C2 ₁ , the holding capacitance C2 _{M of the} pixel farthest from the signal input end of the scanning signal line GL ₁ , and the size of the holding capacitance C2 _j of the pixel between the two pixels is C2 ₁ > C2 _j > C2 _M. Further, even if the gate is tried with all the pixels having a TFT element connected to the scanning signal lines GL _1, the scanning signal line GL largest storage capacitor C2 ₁ nearest pixel from the signal input terminal _1, the scanning signal The storage capacitor of the pixel whose distance from the signal input end of the line GL ₁ is longer is made smaller. FIG. 19 is a schematic circuit diagram showing an example of a schematic configuration of a conventional liquid crystal display panel. Further, in FIG. 19, the triangle mark at the left end of each scanning signal line GL ₁ , GL _i−1 , GL _i , GL _N−1 , GL _N indicates the signal input end of the scanning signal, and each video signal The triangles at the upper end of the lines DL ₁ , DL ₂ , DL _j , DL _{j + 1} , and DL _M indicate the video signal input ends.
Japanese Patent No. 3072984 JP 2002-072250 A

  Incidentally, in recent years, liquid crystal display devices (liquid crystal display panels) used for liquid crystal televisions have been further increased in area (larger screen) and higher definition. Therefore, the wiring resistance and the wiring capacity tend to increase, and not only the delay of the scanning signal in the scanning signal line but also the delay of the video signal in the video signal line increases. Furthermore, for example, in a liquid crystal display device driven at a high speed such as a double speed drive, each TFT element is required to perform a switching operation in a short time. Therefore, for example, when looking at each pixel having a TFT element whose drain is connected to one common video signal line, the unwritten voltage and signal input terminal of the pixel close to the signal input terminal of the video signal line. The difference from the unwritten voltage of a pixel far from the pixel tends to increase.

However, in the conventional display devices described in Patent Document 1 and Patent Document 2, for example, the storage capacitor C2 of each pixel having a TFT element whose drain is connected to one common video signal line is , Are formed to be the same size. That is, for example, in the configuration shown in FIG. 19, when viewed for each pixel having a TFT element in which the drain is connected to the video signal lines DL _1, the size of the storage capacitor of each pixel, the video signal lines DL _The same value C2 ₁ is set regardless of the distance from the signal input end of ₁ . Similarly, when viewing each pixel having a TFT element connected to another video signal line, for example, the video signal line DL _j , the size of the storage capacitor of each pixel is substantially the same value C2 _j . It is trying to become.

  Therefore, when the liquid crystal display panel has a large screen, high definition, or high speed driving, for example, a two-dimensional distribution (in-plane distribution) occurs in the difference in the unwritten voltage of each pixel. Therefore, it is difficult to prevent a phenomenon called luminance unevenness or flicker in a conventional display device having a configuration as described in Patent Document 1 or Patent Document 2, for example. There is a problem that the display quality in the panel) deteriorates.

  An object of the present invention is to provide a technique capable of improving the display quality of, for example, an active matrix TFT liquid crystal display device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of typical inventions among the inventions disclosed in the present application will be described as follows.

  (1) A plurality of scanning signal lines, a plurality of video signal lines sterically intersecting with the plurality of scanning signal lines, a plurality of TFT elements arranged in a matrix, and a matrix. And a display device comprising a display panel having a plurality of pixel electrodes connected to the source of the TFT element, wherein the display area of the display panel is connected to the TFT element and the source of the TFT element. Each of the TFT elements has a gate connected to one scanning signal line of the plurality of scanning signal lines, and a drain connected to the plurality of pixel electrodes. Connected to one of the video signal lines, each pixel electrode is connected to the video signal line and the scanning signal line to which the gate of the TFT element connected to the pixel electrode is connected. Different A storage capacitor is formed by the conductor layer, the pixel electrode, and the insulating layer interposed between the conductor layer, and one common scanning signal of the plurality of pixels constituting the display region A plurality of pixels each having a TFT element whose gate is connected to the line has the size of the storage capacitor formed in the pixel adjacent to the signal input end of the scanning signal line, of two adjacent pixels, Cst1 If the storage capacitor formed in the far pixel is Cst2, Cst1 ≧ Cst2, and the storage capacitor formed in the pixel closest to the signal input terminal of the scanning signal line is Cst3, where Cst4 is the size of the storage capacitor formed in the farthest pixel, Cst3> Cst4, and the pixel is connected to one common video signal line among the plurality of pixels constituting the display area. A plurality of pixels each having a TFT element to which IN is connected have a storage capacity Cst5, which is far from the pixel adjacent to the signal input end of the video signal line, of two adjacent pixels. When the size of the storage capacitor formed in the other pixel is Cst6, Cst5 ≧ Cst6 and the size of the storage capacitor formed in the pixel closest to the signal input end of the video signal line is Cst7, A display device in which Cst7> Cst8, where Cst8 is the size of the storage capacitor formed in the farthest pixel.

  (2) In the display device according to (1), a storage capacitor formed in a plurality of pixels each having a TFT element whose gate is connected to the one common scanning signal line includes two adjacent pixels. Of these, the area of the region where the pixel electrode and the conductor layer of the storage capacitor formed in the pixel closer to the signal input end of the scanning signal line overlap in plan view is formed in the far pixel. When the area of the region where the pixel electrode and the conductor layer of the storage capacitor overlap in plan view is S2, S1 ≧ S2 and the storage formed in the pixel closest to the signal input end of the scanning signal line. The area of the region where the pixel electrode of the capacitor and the conductor layer overlap in plan view is S3, and the area of the region where the pixel electrode of the storage capacitor formed in the farthest pixel and the conductor layer overlap in plan view is S4. Then, S3> S In a display device.

  (3) In the display device of (1) or (2), two storage capacitors are formed in a plurality of pixels each having a TFT element whose drain is connected to the one common video signal line. Of the adjacent pixels, the area of the region where the pixel electrode of the storage capacitor formed on the pixel closer to the signal input end of the video signal line and the conductor layer overlap in plan view is S5, and the farther pixel If the area of the region where the pixel electrode of the storage capacitor and the conductor layer overlap in plan view is defined as S6, S5 ≧ S6 and the pixel closest to the signal input end of the video signal line The area of the region where the pixel electrode and the conductor layer of the storage capacitor formed overlap in plan view is S7, and the area of the region of the storage capacitor formed in the farthest pixel and the conductor layer overlaps in plan view. Let the area be S8 If, S7> is S8 display device.

  (4) In the display device according to any one of (1) to (3), a storage capacitor formed in a plurality of pixels having TFT elements whose gates are connected to the one common scanning signal line is Depending on the distance from the signal input end of the scanning signal line, the difference in the size of the storage capacitor formed in two adjacent pixels changes, and the distance from the signal input end of the scanning signal line changes. A display device in which the difference in the size of the storage capacitor is smaller as the length is longer.

  (5) In the display device of any one of (1) to (3), a storage capacitor formed in a plurality of pixels having a TFT element whose gate is connected to the one common scanning signal line is Depending on the distance from the signal input end of the scanning signal line, the difference in the size of the storage capacitor formed in two adjacent pixels changes, and the distance from the signal input end of the scanning signal line changes. The change rate of the difference in the size of the storage capacitor formed in two adjacent pixels shorter than a certain distance is the size of the storage capacitor formed in two adjacent pixels longer than the certain distance. Display device larger than the rate of change of the difference.

  (6) In the display device according to (5), the certain distance is a distance between the signal input end of the scanning signal line and the TFT element of a pixel located farthest from the signal input end of the scanning signal line. A display device that is one-third of the distance to the position where the gate is connected.

  (7) In the display device according to any one of (1) to (6), a storage capacitor formed in a plurality of pixels having a TFT element whose drain is connected to the one common video signal line is Depending on the distance from the signal input end of the video signal line, the difference in the size of the storage capacitor formed in two adjacent pixels changes, and the distance from the signal input end of the video signal line changes. A display device in which the difference in the size of the storage capacitor is smaller as the length is longer.

  (8) In the display device according to any one of (1) to (6), a storage capacitor formed in a plurality of pixels having a TFT element having a drain connected to the one common video signal line is Depending on the distance from the signal input end of the video signal line, the difference in the size of the storage capacitor formed in two adjacent pixels changes, and the distance from the signal input end of the video signal line changes. The change rate of the difference in the size of the storage capacitor formed in two adjacent pixels shorter than a certain distance is the size of the storage capacitor formed in two adjacent pixels longer than the certain distance. Display device larger than the rate of change of the difference.

  (9) In the display device according to (8), the certain distance is a distance between the signal input end of the video signal line and a TFT element of a pixel farthest from the signal input end of the video signal line. A display device that is one-third of the distance to the position where the drain is connected.

  (10) In the display device according to any one of (1) to (9), a storage capacitor in each pixel constituting the display region is connected to a distance from a signal input end of the scanning signal line and the drain. A display device in which the thickness of the insulating layer varies depending on the distance from the signal input end of the video signal line.

  (11) The display device according to any one of (1) to (10), wherein the display panel is a liquid crystal display panel in which a liquid crystal material is sealed between a pair of substrates.

  According to the present invention, for example, when considering a plurality of pixels whose gates are connected to one common scanning signal line, the holding capacity of each pixel is equal to that of a pixel far from the signal input end of the scanning signal line. The smaller the holding capacity. Therefore, it is possible to reduce the difference in unwritten voltage and the difference in feedthrough voltage that occur between a plurality of pixels whose gates are connected to one common scanning signal line. Similarly, in the case of a plurality of pixels whose drains are connected to one common video signal line, the storage capacity of each pixel becomes smaller as the storage capacity of the pixel farther from the signal input end of the video signal line. . Therefore, it is possible to reduce the change in the unwritten voltage and the change in the feedthrough voltage that occur between a plurality of pixels whose drains are connected to one common video signal line. From these facts, the unwritten voltage and the feedthrough voltage of each pixel constituting the display area of one display device (display panel) can be made substantially uniform, and the display quality of the active matrix display device can be improved. it can.

  Further, according to the present invention, even when the thickness of the insulating layer in the storage capacitor of each pixel constituting the display region is changed, the change in the unwritten voltage and the change in the feedthrough voltage of each pixel can be reduced. Can do. Therefore, the display quality of the active matrix display device can be further improved.

Hereinafter, the present invention will be described in detail together with embodiments (examples) with reference to the drawings.
Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.

FIG. 1A is a schematic block diagram showing an example of a schematic configuration of a liquid crystal display device according to the present invention. FIG. 1B is a schematic circuit diagram illustrating an example of a circuit configuration of one pixel in the liquid crystal display panel illustrated in FIG.
FIG. 2A shows an example of the waveform of the scanning signal and the waveform of the video signal inputted to each TFT element of the pixel located at the four corners of the display area of the liquid crystal display panel shown in FIG. It is a schematic diagram shown. FIG. 2B is a schematic diagram for explaining the definitions of the unwritten voltage and the feedthrough voltage. FIG. 2C is a schematic diagram comparing the magnitudes of unwritten voltages in the two pixels SP1 and SP4 shown in FIG.
FIG. 3 is a schematic diagram showing an example of the distribution of the magnitude of the unwritten voltage in the display area of one conventional liquid crystal display panel.

  The present invention can be applied to, for example, an active matrix liquid crystal display device. As shown in FIG. 1A, for example, the active matrix type liquid crystal display device has a plurality of scanning signal lines GL extending long in the first direction (lateral direction) and long in the second direction (vertical direction). A liquid crystal display panel 1 having a plurality of video signal lines DL extending; a data driver 2 for inputting a video signal (sometimes referred to as gradation data) to the plurality of video signal lines DL of the liquid crystal display panel 1; A gate driver 3 for inputting a scanning signal to a plurality of scanning signal lines GL of the liquid crystal display panel 1, and a common voltage input circuit 4 for inputting a voltage signal Vcom of a common potential to a common electrode (not shown) of the liquid crystal display panel 1. Have

  In the display area DA of the liquid crystal display panel 1, TFT elements functioning as active elements (switching elements) are arranged in a matrix in the first direction and the second direction, for example. The display area DA is composed of a set of a plurality of pixels arranged in a matrix in the first direction and the second direction, and the area occupied by one pixel is, for example, two adjacent areas. Corresponds to a region surrounded by two scanning signal lines GL and two adjacent video signal lines DL.

Each pixel constituting the display region has a TFT element and a pixel electrode. For example, as shown in FIG. 1B, two adjacent scanning signal lines GL _n and GL _{n + 1} are adjacent to each other. The TFT element Tr included in the pixel in the region surrounded by the video signal lines DL _m and DL _{m + 1} has a gate connected to the scanning signal line GL _{n + 1} and a drain connected to the video signal line DL _m . The source of the TFT element Tr is connected to the pixel electrode PX included in the pixel.

  The liquid crystal display panel 1 is a display panel in which liquid crystal is sealed between a pair of substrates. The scanning signal line GL, the video signal line DL, the TFT element Tr, and the pixel electrode PX are included in the pair of substrates. It is formed on one substrate (hereinafter referred to as a TFT substrate).

  Further, the pixel electrode PX forms a pixel capacitor (sometimes referred to as a liquid crystal capacitor) C1 together with the common electrode CT and the liquid crystal LC. At this time, the common electrode CT may be formed on the TFT substrate, or may be formed on the other of the pair of substrates (hereinafter referred to as a counter substrate).

Furthermore, the pixel electrode PX, for example, the scanning signal lines _GL n of two adjacent, and _{GL n +} of the _one scanning signal line GL _n of better gate is not connected to the TFT elements Tr and the pixel electrodes PX, form a storage capacitor C2 together with the insulating layer PAS interposed overlapping area between the scanning signal line GL _n.

By the way, in a large liquid crystal display device such as a liquid crystal television among the liquid crystal display devices, not only the length of each scanning signal line GL in the extending direction (lateral direction) but also the extension of each video signal line DL. The length of the direction (longitudinal direction) has also become very long. For this reason, the delay amount of the scanning signal input to each scanning signal line GL and the delay amount of the video signal input to each video signal line DL are increased. A difference occurs in the waveform of the signal input to the element. At this time, the pixel SP1, SP2, SP3, SP4 located at the four corners of the display area DA shown in FIG. 1 (a), the waveform and the scanning signal _{V G} which is input to the gate of the TFT element of each pixel When the waveform of the video signal DATA input to the drain is examined, for example, it is as shown in FIG. Incidentally, in FIG. 2 (a), four pixels SP1, SP2, SP3, the waveform of the scanning signal _{V G} and the video signal DATA each pixel is actually input to the TFT elements having the SP4 shown in solid lines, each signal The ideal waveform (input waveform) is indicated by a dotted line.

The pixel SP1 located at the upper left corner of the display area DA is close to the signal input end of the scanning signal line GL and is also close to the signal input end of the video signal line DL. Therefore, as shown in the upper left of FIG. 2 (a), the waveform of the video signal DATA actually input to the waveform and the drain of the scanning signal V _G actually input to the gate of the TFT element of the pixel SP1, respectively ideal The waveform is close to a typical waveform (rectangle).

The pixel SP2 located at the upper right corner of the display area DA is far from the signal input end of the scanning signal line GL and close to the signal input end of the video signal line DL. Therefore, as shown in the upper right of FIG. 2A, the waveform of the video signal DATA actually input to the drain of the TFT element of the pixel SP2 is a waveform close to an ideal waveform (rectangular shape). actually waveform of the scanning signal V _G to be input is turned waveform dull than waveform input to the gate of the TFT element of the pixel SP1 delay due to the wiring resistance. That is, the waveform of the scanning signal V _G actually input to the gate of the TFT element of the pixel SP2, the scanning signal V _G changes when turned off from the change and on when turned on from off, the pixel SP1 It has become slower than the change in the scanning signal V _G which is input to the gate of the TFT element.

The pixel SP3 located at the lower left corner of the display area DA is close to the signal input end of the scanning signal line GL and far from the signal input end of the video signal line DL. Therefore, as shown in the lower left of FIG. 2 (a), although the waveform of the scanning signal V _G actually input to the gate of the TFT element of the pixel SP3 has a waveform close to the ideal waveform (rectangular), The waveform of the video signal DATA actually input to the drain is a waveform that is less than the waveform input to the drain of the TFT element of the pixel SP1 due to a delay due to the wiring resistance. That is, the waveform of the video signal DATA that is actually input to the drain of the TFT element of the pixel SP3 is that the change at the start position and the end position of the video signal DATA for the pixel SP3 is input to the drain of the TFT element of the pixel SP1. It is more gradual than the change in the video signal DATA.

The pixel SP4 located at the lower right corner of the display area DA is far from the signal input end of the scanning signal line GL and far from the signal input end of the video signal line DL. Therefore, as shown in the bottom right of FIG. 2 (a), the waveform and the waveform of the video signal DATA of the scan signal V _G actually input to the gate of the TFT element of the pixel SP4, pixel SP1 delay by the respective wiring resistance The waveform is less than the waveform actually input to the TFT element. That is, the waveform of the scanning signal V _G actually input to the gate of the TFT element of the pixel SP4, the scanning signal V _G changes when turned off from the change and on when turned on from off, the pixel SP1 It has become slower than the change in the scanning signal V _G which is input to the gate of the TFT element. Further, the waveform of the video signal DATA actually input to the drain of the TFT element of the pixel SP4 is such that the change at the start position and the end position of the video signal DATA for the pixel SP4 are input to the drain of the TFT element of the pixel SP1. It is more gradual than the change in the video signal DATA.

Although not shown, for example, a video signal that is actually input to the TFT element of each pixel whose gate is connected to the scanning signal line GL (GL ₁ ) closest to the signal input end of the video signal line DL. The waveform of DATA is substantially the same as the waveform of the video signal DATA actually input to the TFT element of the pixel SP1 and the TFT element of the pixel SP2. However, the waveform of the scanning signal V _G actually input to the gate of the TFT element of each of the pixels, as the distance from the signal input terminal of the scan signal lines GL (GL ₁₎ is long, the TFT element of the pixel SP1 It will change the waveform of the scanning signal V _G from the waveform of the scanning signal V _G which is input to the gate input to the gate of the TFT element of the pixel SP2. The same applies to the other scanning signal lines GL. When the TFT element is connected to one common scanning signal line GL, the video signal DATA input to the drain of each TFT element. of the waveform is similar for all the TFT elements, as the distance increases from the signal input terminal of the scan signal V _G is the waveform scanning signal line GL to be inputted to the gates of the TFT elements, the ideal rectangular The deviation (rounding) from the waveform increases.

Further, a drain, and when viewed with the TFT elements are connected to a common video signal line DL of a certain one, the waveform of the scanning signal V _G which is input to the gate of the TFT elements is approximately the same, each The deviation of the waveform of the video signal DATA input to the drain of the TFT element from the ideal rectangular waveform increases as the distance from the signal input end of the video signal line DL increases.

For the reasons described above, the waveform of the waveform and the video signal DATA of the scan signal V _G input is actually in the TFT element of each pixel in the display area DA of the liquid crystal display panel in combination, the two display areas DA throat Even if TFT elements are compared, they are different. The difference of the waveform and the video signal DATA of the waveform of the scanning signal V _G, the bias condition of the TFT element to charge the pixel capacitor formed in each pixel mean different things. A difference occurs between the unwritten voltage and the feedthrough voltage in each pixel due to the difference in the bias condition of the TFT element of each pixel.

Wherein the non-writing voltage, for example, as shown in (1) in FIG. 2 (b), the scanning signal V _G is turned on is input to the gate of the TFT element of a certain pixel, the video signal DATA for that pixel when written in the pixel electrode pX, a potential difference _{V L} of the voltage _{V px} and the image signal DATA of the pixel electrode pX at the time when the scanning signal _{V G} is switched from oN to oFF (time). The size of the non-writing voltage V _L, it is dull relationship of the waveform at the rising edge of the scanning signal V _G and the video signal DATA, the bias of the delay amount and the TFT element determined from the delay amount of the video signal DATA of the scan signal V _G It changes depending on the conditions V _gs and V _ds . At this time, the on-current of the delay (waveform rounding) the larger the TFT element of the scanning signal V _G and the video signal DATA falls, and pixels far from the signal input terminal of the scan signal lines GL, the video signal lines DL The pixel farther from the signal input end has a higher unwritten voltage V _L.

Also, the a feed-through voltage, for example, as shown in (2) in FIG. 2 (b), the scanning signal V _G which is input to the gate of the TFT element of a pixel is turned on, the video signal for the pixel DATA is the time written in the pixel electrode pX, the potential difference V between the voltage _{V px} of the pixel electrode pX in after switching the voltage _{V px} of the pixel electrode pX at the time when the scanning signal _{V G} is switched from oN to oFF (time) _FT . Feed-through voltage V _FT, when the fall of the scanning signal V _G, i.e. there is rounding a relationship waveform when the scanning signal V _G is switched from ON to OFF, the bias of the TFT element determined from the delay amount of the scanning signal V _{G Varies} depending on the condition V _gs . At this time, since the re-charging by the on-current of more TFT elements is larger delay amount of the scanning signal V _G (overcharging) increases, farther pixel from the signal input terminal of the scan signal lines GL, the feed-through voltage V _FT is smaller Become.

From the above, for example, for the two pixels SP1 and SP4 shown in FIG. 1A, the unwritten voltage ΔV among the changes in the unwritten voltage V _L and the feedthrough voltage V _FT generated in each pixel. For example, FIG. 2C shows the change in _L. Scanning signal lines pixel SP1 distance are both closest from the signal input end of the distance and the video signal lines DL from the signal input end of the GL is rise time of the waveform of the scanning signal V _G and the video signal DATA is input to the TFT element Are both sharp and the unwritten voltage V _L is small. On the other hand, the distance and the video signal lines together farthest pixel distance from the signal input end of the DL SP4 from the signal input end of the scanning signal lines GL, the rising edge of the scanning signal V _G and the video signal DATA is input to the TFT element , And the unwritten voltage V _L increases.

Further, in the display area DA as a whole, the distribution of the magnitude of the unwritten voltage _VL in each pixel is, for example, a distribution shown by a two-dot chain line in FIG. 3, and the signal input terminal of the scanning signal line And the distance from the signal input end of the video signal line are the smallest in the pixel SP1, and the unwritten voltage _VL increases in the pixel farthest from the pixel SP1.

Hereinafter, an example of a configuration example of such smaller liquid crystal display panel changes in non-writing voltage V _L and the feed-through voltage V _FT in each pixel.

  FIG. 4 is a schematic circuit diagram for explaining a schematic configuration of the liquid crystal display panel of Example 1 according to the present invention.

In the liquid crystal display panel of Example 1, as shown in FIG. 4, the storage capacitor C2 included in each pixel constituting the display area DA is distinguished by being expressed as C2 _{n, m} . Note that the subscript _n of C2 _{n, m} is one of integers 1, 2,..., I,..., N, and the TFT element connected to the pixel electrode PX of each storage capacitor. The scanning signal line GL _n to which the gate is connected is shown. Further, the subscript _m of C2 _{n, m} is one of integers 1, 2,..., J,..., M, and the TFT element connected to the pixel electrode PX of each storage capacitor. It shows the video signal line DL _m which drain is connected.

Further, in FIG. 4, the triangle mark at the left end of each of the scanning signal lines GL ₁ , GL _i−1 , GL _i , GL _N−1 , GL _N indicates that the signal input terminal of the scanning signal, and each video signal The triangles at the upper end of the lines DL ₁ , DL ₂ , DL _j , DL _{j + 1} , and DL _M indicate the video signal input ends.

In this case, for example, a storage capacitor of each pixel having a TFT element in which the gate is connected to the scanning signal lines GL _1, from the storage capacitor of the pixel in order of proximity to the signal input terminal of the scan signal lines GL _1, C2 _{1, 1 , C2 1,2, ..., C2 1} , j, ..., denoted _{C2 1, M.} That is, the gate is holding capacitor of each pixel having a TFT element connected to a common scanning signal line GL _n of a one, in order from closer to the signal input terminal of the scanning signal lines GL _n, C2 _{n, 1, C2 n, 2, ...} , C2 n, j, ..., C2 n, is expressed as _M.

In the liquid crystal display panel of the first embodiment, first, the storage capacitors (C2 _{n, 1} , C2 _{n, 2} ,...) Of the respective pixels having TFT elements whose gates are connected to one common scanning signal line GL _n . .., C2 _{n, j} ,..., C2 _{n, M} ) are set individually for each pixel, for example. At this time, the size of the storage capacitor (C2 _{n, 1} , C2 _{n, 2} ,..., C2 _{n, j} ,..., C2 _{n, M} ) of each pixel is, for example, the pixel having the shortest distance from the signal input end The holding capacitor C2 _{n, 1} is made the largest, and the holding capacitor is made smaller as the pixel has a longer distance from the signal input end.

At this time, each of the storage capacitor _{(C2 n, 1, C2 n} , 2, ..., C2 n, j, ..., C2 n, M) size of, for example, from the signal input end of the scanning signal lines GL _n distance longer pixel, the pixel electrode PX and the scanning signal line GL _n-1 is the area S of a region that overlaps in plan view, the insulating layer interposed between the pixel electrode PX and the scanning signal line GL _n-1 The value (S / d) divided by the thickness d is made small.

In this way, the switching capability of the TFT elements of pixels far from the signal input terminal of the scan signal line GL _n is improved. Therefore, for a plurality of pixels having TFT elements whose gates are connected to one common scanning signal line GL _n , the unwritten voltage of the pixel far from the signal input end of the scanning signal line GL _n and the signal input end Therefore, it is possible to reduce the difference from the unwritten voltage of the pixels close to. At this time, since the pixels far from the signal input terminal of the scan signal lines GL _n also reduces parasitic capacitance, and the feed-through voltage pixels far from the signal input terminal, also differences between the feed-through voltage of the pixel close to the signal input terminal Can be reduced.

In the liquid crystal display panel according to the first embodiment, the storage capacitors (C2 _{1, m} , C2 _{2, m} ,...) Of each pixel having TFT elements whose drains are connected to one common scanning signal line DL _m . The size of C2 _{i, m} ,..., C2 _{N, m} ) is also set individually for each pixel, for example. At this time, the holding capacity of each pixel _{(C2 1, m, C2 2} , m, ..., C2 i, m, ..., C2 N, m) the size of, for example, the nearest pixel the distance from the signal input terminal The holding capacitor C21 _{, m} is made the largest, and the holding capacitor is made smaller as the pixel has a longer distance from the signal input end.

Further, at this time, the size of each holding capacitor (C2 _{1, m} , C2 _{2, m} ,..., C2 _{i, m} ,..., C2 _{N, m} ) is, for example, from the signal input end of the video signal line DL _m . A value obtained by dividing the area S of the region where the pixel electrode PX and the scanning signal line GL overlap in plan view by the thickness of the insulating layer interposed between the pixel electrode PX and the scanning signal line GL as the pixel has a longer distance. To be smaller.

Thus, to improve the switching capacity of the TFT elements of pixels far from the signal input terminal of the video signal line DL _m. Therefore, for a plurality of pixels having a TFT element in which the drain is connected to a common video signal line DL _m of one, and a non-writing voltage of pixels far from the signal input terminal of the video signal line DL _m, the signal input terminal Therefore, it is possible to reduce the difference from the unwritten voltage of the pixels close to.

However, the waveform of the scanning signal drain is input to the gate of the TFT elements are connected to a common video signal line DL _m of one is almost the same waveform, from the signal input terminal of the video signal lines DL _m If the size of the storage capacitor is changed in accordance with the distance, the feedthrough voltage in each pixel may vary. Therefore, for each pixel having a TFT element in which the drain is connected to a common video signal line DL _m of one, for example, the size of the TFT element according to the size of the storage capacitor of each pixel (e.g., the channel width It is desirable to change the value obtained by dividing the channel length by the channel length so that the feedthrough voltage in each pixel becomes substantially constant.

FIG. 5A shows the relationship among the distance from the signal input end of one scanning signal line in the conventional liquid crystal display panel, the delay amount of the scanning signal, the unwritten voltage and the feedthrough voltage of each pixel. It is a schematic graph figure. FIG. 5B is a schematic graph illustrating an example of a method for setting a storage capacitor of each pixel having a TFT element connected to one common scanning signal line in the liquid crystal display panel according to the first embodiment.
FIG. 6A shows the relationship between the distance from the signal input end of one video signal line, the delay amount of the video signal, the unwritten voltage and the feedthrough voltage of each pixel in the conventional liquid crystal display panel. It is a schematic graph figure. FIG. 6B is a schematic graph showing an example of a method for setting a storage capacitor of each pixel having a TFT element connected to one common video signal line in the liquid crystal display panel of the first embodiment.

When the liquid crystal display panel of Example 1 focuses on a plurality of pixels having TFT elements whose gates are connected to one common scanning signal line GL _n , for example, the signal input of the scanning signal line GL _n as the holding capacity of the distance is long pixel from the end, the size (e.g., S / d) by such smaller, non at each pixel having a TFT element in which the gate is connected to the scanning signal line GL _n The write voltage V _L and the feedthrough voltage V _FT are made substantially the same.

Incidentally, one of the distance from the signal input terminal of the scan signal lines GL _n, examining the relationship between the delay amount of the scanning signal V _G which is input to the scanning signal lines GL _n, e.g., FIGS. 5 (a) It looks like the graph shown in. In the graph shown in FIG. 5A, the horizontal axis represents the relative distance LG _in from the signal input end of the scanning signal line GL _n . For example, the TFT of the pixel farthest from the signal input end and the signal input end The distance from the signal input end to each TFT element (pixel) is represented by setting the distance to the position where the gate of the element is connected to 1. Further, the graph shown in FIG. 5 (a), the delay amount Td of the vertical axis scanning signal V _G to the left, the delay amount toward the top increases, distortion of the waveform becomes large. In this case, the delay amount Td of the scanning signal lines GL _n, for example, by the relative distance _{LG in} from the signal input terminal as a boundary at near 0.3, the relative distance _{LG in} the (smaller shorter even 0.3 ) The change amount of the delay amount between the pixels is different from the change amount between the pixels longer than 0.3, and the change amount between the pixels having the relative distance LG _in shorter than 0.3 is larger.

Furthermore, the relationship between the relative distance LG _in from the signal input end of the scanning signal line GL _n and the delay amount Td indicates that the holding capacity of each pixel having a TFT element whose gate is connected to the scanning signal line GL _n is almost equal. When the relationship between the magnitude of the unwritten voltage V _{L and} the magnitude of the feedthrough voltage V _FT of each pixel in the case of the same magnitude is superimposed, for example, as shown in FIG. In the graph shown in FIG. 5A, the vertical axis on the right is the unwritten voltage V _L (or the feedthrough voltage V _FT ) of each pixel, and the voltages V _L and V _FT increase as it goes upward. Become. Thus, in the conventional general liquid crystal display panel, the unwritten voltage V _L increases as the relative distance LG _in from the signal input end of the scanning signal line GL _n increases (increases), and the feedthrough voltage V _FT increases. The value of becomes smaller. At this time, the change amount of the unwritten voltage V _L and the feedthrough voltage V _{FT is} the change amount between pixels whose relative distance LG _in is shorter (smaller) than 0.3, similarly to the delay amount Td of the scanning signal. Is bigger.

Therefore, the storage capacitor C2 _{n, m} (n is a constant, m = 1, 2,..., M) of each pixel having a TFT element whose gate is connected to one common scanning signal line GL _n is set. In some cases, the relationship between the distance (position) from the signal input end of the scanning signal line GL _n and the difference ΔC2 _{n, m} in the holding capacity of two adjacent pixels is shown in FIG. 5B, for example. It is desirable to use a graph like this. Incidentally, the graph shown in FIG. 5 (b), the horizontal axis indicates the subscript m of the video signal line DL _m to the drain of the TFT element is connected, m is from the signal input terminal of the scan signal lines GL _n .., M in order from the video signal line with the shortest distance. Further, in the graph shown in FIG. 5B, the vertical axis on the left is the size of each storage capacitor C2 _{n, m} , and the vertical axis on the right is the difference ΔC2 _{n, m} = (C2 _{n, m-} C2n _{, m-1} ). Further, as the vertical axis on the left side and the vertical axis on the right side increase, the respective values increase.

If there are M video signal lines DL intersecting one scanning signal line GL _n , the relative distance LG _in from the signal input end shown in FIG. 5A, the delay amount Td, and the unwritten voltage V _L , And the relationship with the feedthrough voltage V _FT , for example, with the pixel having a TFT element whose drain is connected to the video signal line DL _{M / 3} as a boundary, the drain is the video signal line DL _{1 to} DL _{M. /} variation .DELTA.C2 _n of the storage capacitor of each pixel in ₃ having a TFT element _{connected, m} is the having the TFT element in which the drain is connected to the video signal lines _{DL (M / 3) +1 ~DL} M The change amount ΔC2 of the storage capacitor in the pixel is set to be larger than _{n, m} . In this way, the unwritten voltage V _L and the feedthrough voltage V _FT of each pixel having a TFT element whose gate is connected to one common scanning signal line GL _n can be set to substantially the same value. . If M / 3 does not become an integer, it goes without saying that the change amount ΔC2 _{n, m} of the storage capacitor of each pixel may be changed with the integer number of video signal lines DL close to M / 3 as a boundary. .

Further, one and the distance from the signal input terminal of the video signal line DL _m, and examining the relationship between the delay amount of the video signal DATA input to the video signal line DL _m, for example, in FIGS. 6 (a) It looks like the graph shown. Incidentally, the graph shown in FIG. 6 (a), the horizontal axis indicates the relative distance LD _in from the signal input terminal of the video signal line DL _m, for example, a signal input end, farthest pixel of the TFT from the signal input terminal The distance from the signal input end to each TFT element (pixel) is represented by setting the distance to the position where the drain of the element is connected to 1. In the graph shown in FIG. 6A, the vertical axis on the left is the delay amount Td of the video signal DATA, and the delay amount increases as it goes upward, and the rounding of the waveform increases. In this case, the delay amount Td of the video signal line DL _m, for example, a relative distance _{LD in} from the signal input end in the boundary at near 0.3, the relative distance _{LD in} the (smaller shorter even 0.3 ) The change amount of the delay amount between the pixels is different from the change amount between the pixels longer than 0.3, and the change amount between the pixels having the relative distance LD _in shorter than 0.3 is larger.

Furthermore, the relationship between the relative distance LD _in from the signal input end of the video signal line DL _m and the delay amount Td indicates that the holding capacity of each pixel having a TFT element whose drain is connected to the video signal line DL _m is almost equal. When the relationship between the magnitude of the unwritten voltage V _{L and} the magnitude of the feedthrough voltage V _FT of each pixel in the case of the same magnitude is superimposed, for example, as shown in FIG. In the graph shown in FIG. 6A, the vertical axis on the right is the unwritten voltage V _L (or the feedthrough voltage V _FT ) of each pixel, and the voltages V _L and V _FT increase as it goes upward. Become. As described above, in the conventional general liquid crystal display panel, the unwritten voltage V _L increases as the relative distance LD _in from the signal input end of the video signal line DL _m increases (increases), but the feedthrough voltage V _L increases. The value of _FT is almost constant. At this time, the amount of change in the unwritten voltage _VL is larger in the amount of change between pixels whose relative distance LG _in is shorter (smaller) than 0.3, similarly to the delay amount Td of the video signal.

Therefore, a storage capacitor C2 _{n, m} (n = 1, 2,..., N, m is a constant) of each pixel having a TFT element whose drain is connected to one common video signal line DL _m is set. Sometimes, the relationship between the distance (position) from the signal input end of the video signal line DL _m and the difference ΔC2 _{n, m} between the holding capacities of two adjacent pixels, for example, in the graph shown in FIG. It is desirable to do so. In the graph shown in FIG. 6B, the horizontal axis is the subscript _n of the scanning signal line GL _n to which the gate of the TFT element is connected, and n is from the signal input end of the video signal line DL _m. , N in order from the scanning signal line having the shortest distance. In the graph shown in FIG. 6B, the vertical axis on the left is the size of each holding capacitor C _{n, m} , and the vertical axis on the right is the difference ΔC2 _{n, m} = (C2 _{n, m-} C2n _{-1, m} ). Further, as the vertical axis on the left side and the vertical axis on the right side increase, the respective values increase.

If the scanning signal lines GL crossing the one video signal line DL _m is an N present, the relative distance LD _in from the signal input end shown in FIG. 6 (a), the delay amount Td and non-writing voltage V _L reflecting the relationship between, for example, to a pixel having a TFT element in which the gate is connected to the scanning signal line GL N _{/ 3} as a boundary, and its gate connected to the scanning signal line _GL 1 ~GL N / ₃ the amount of change .DELTA.C2 _n storage capacitor in each pixel having a TFT _{element, m} is the amount of change storage capacitor in each pixel having a TFT element in which the gate is connected to the scanning signal line _{GL (n / 3) +1 ~GL} n ΔC2 is larger than _{n, m} . In this way, the unwritten voltage V _L of each pixel having a TFT element whose drain is connected to one common video signal line DL _m can be made substantially the same value. If N / 3 is not an integer, it goes without saying that the change amount ΔC2 _{n, m} of the storage capacitor of each pixel may be changed with the integer scanning signal line GL close to N / 3 as a boundary. .

In concept as shown in FIGS. 6 (a) and 6 (b), the holding capacitance of each pixel having a TFT element having a drain connected to a common video signal line DL _m of one C2 _{n, m} when setting the video signal line DL _m, it is necessary to consider the distance from the signal input terminal of the scan signal lines GL.

The size of the storage capacitor C2 of each pixel having a TFT element in which the gate is connected to a common scanning signal line GL _n of one, for example, become distribution (relationship) as shown in FIG. 5 (b) Need to be. That is, for example, in the liquid crystal display panel shown in FIG. 4, a storage capacitor C2 _{i, 1} of a pixel having a TFT element whose gate is connected to the scanning signal line GL _i and whose drain is the video signal line DL ₁ ; The gate is connected to the scanning signal line GL _i , the drain is connected to the video signal line DL _j , the size of the holding capacitor C2 _{i, j} of the pixel having the TFT element, the gate is connected to the scanning signal line GL _i , and the drain The relationship between the size of the storage capacitor C2 _{i, M} of the pixel having the TFT element that is the video signal line DL _M needs to follow the distribution shown in FIG. 5B. Therefore, when setting the storage capacitor C2 _{n, m} of the pixel having a TFT element having a drain connected to a common video signal line DL _m of one, for example, as shown in FIG. 6 (b), a drain storage capacitor of each pixel having a TFT element connected to the video signal lines DL _{1 C2 n, 1,} storage capacitor of each pixel having a TFT element in which the drain is connected to the video signal line DL _{j C2 n, j,} An image in which the holding capacitors C2 _{n and M of} each pixel having a TFT element whose drain is connected to the image signal line DL _M have different values and the distance from the signal input end of the scanning signal line GL is long. The storage capacity of the pixel having the TFT element whose drain is connected to the signal line is made smaller.

In the liquid crystal display panel according to the first embodiment, for a large number of pixels constituting the display area DA, for example, the size of the storage capacitor C2 of each pixel is set for each pixel by the method as described above. The magnitude of the unwritten voltage V _{L and} the magnitude of the feedthrough voltage V _FT in each pixel in the display area DA of the liquid crystal display panel can be made substantially equal, and uneven brightness and flicker can be reduced.

FIG. 7A is a schematic plan view showing a schematic configuration of the liquid crystal display panel. FIG.7 (b) is a schematic cross section in the AA 'line of Fig.7 (a).
FIG. 8A is a schematic plan view illustrating an example of a schematic configuration of one pixel in the TFT substrate of the liquid crystal display panel. FIG. 8B is a schematic cross-sectional view taken along the line BB ′ of FIG. FIG.8 (c) is a schematic cross section in the CC 'line of Fig.8 (a). FIG. 8D is a schematic cross-sectional view taken along the line DD ′ in FIG.
FIG. 9A is a schematic plan view illustrating an example of a storage capacitor of a pixel arranged along one scanning signal line in a TFT substrate to which the configuration of the first embodiment is applied. FIG. 9B is a schematic plan view illustrating an example of a storage capacitor of a pixel arranged along one video signal line in the TFT substrate to which the configuration of the first embodiment is applied.

  In the liquid crystal display panel 1 described in the first embodiment, for example, as shown in FIGS. 7A and 7B, a liquid crystal LC is sealed between a pair of substrates of a TFT substrate 101 and a counter substrate 102. It is. At this time, the TFT substrate 101 and the counter substrate 102 are bonded by, for example, a sealing material 103 provided in an annular shape outside the display area DA, and the liquid crystal LC is composed of the TFT substrate 101, the counter substrate 102, and the sealing material. It is sealed in a space surrounded by 103.

  As described above, the TFT substrate 101 includes a plurality of scanning signal lines GL, a plurality of video signal lines DL, a TFT element and a pixel electrode PX arranged in a matrix on the surface of an insulating substrate such as a glass substrate. It is the board | substrate provided. The counter substrate 102 is, for example, a substrate in which a light shielding film, a color filter, or the like that divides the display area DA for each pixel is provided on the surface of an insulating substrate such as a glass substrate.

  Further, when the liquid crystal display panel 1 is, for example, a vertical electric field driving method such as a VA method or a TN method, the common electrode CT is provided on the counter substrate 102. When the liquid crystal display panel 1 is a lateral electric field driving method such as an IPS method, the common electrode CT is provided on the TFT substrate 101.

  Further, when the liquid crystal display panel 1 is a transmissive or transflective type, for example, a pair of polarizing plates 104A and 104B are provided on the surfaces facing the outside of the TFT substrate 101 and the counter substrate 102. At this time, one or more retardation plates may be provided between the TFT substrate 101 and the polarizing plate 104A and between the counter substrate 102 and the polarizing plate 104B, respectively.

  When the liquid crystal display panel 1 is a reflection type, generally, the polarizing plate 104A and the retardation plate on the TFT substrate 101 side are unnecessary.

In the vertical electric field drive type liquid crystal display panel 1, the configuration of one pixel in the display area DA of the TFT substrate 101 is, for example, a configuration as shown in FIGS. 8 (a) to 8 (d). . At this time, a plurality of scanning signal lines GL including the scanning signal lines GL _n and GL _{n + 1} are first formed on the surface of the insulating substrate SUB such as a glass substrate. The scanning signal line GL is formed by etching a conductive film such as an aluminum film, for example.

Further, on the insulating substrate SUB and the scanning signal line GL, the semiconductor layer SC of the TFT element, the video signal lines DL _m , DL are provided via the first insulating layer PAS1 having a function as a gate insulating film of the TFT element. _A plurality of video signal lines DL including _{m + 1} , a drain electrode SD1 and a source electrode SD2 of the TFT element are formed. The first insulating layer PAS1 is formed, for example, by forming a silicon oxide film (SiO ₂ ). In the semiconductor layer SC, for example, after etching an amorphous silicon film, impurities are implanted to form a channel region, a drain region, and a source region. The video signal line DL, the drain electrode SD1, and the source electrode SD2 are formed by etching a conductor film such as an aluminum film, for example. At this time, the drain electrode SD1 is integrally formed with the video signal line DL, for example, as a part of the video signal line DL.

  Further, the pixel electrode PX is formed on the video signal line DL and the like via the second insulating layer PAS2. The pixel electrode PX is formed, for example, by etching a conductive film having a high light transmittance such as an ITO film. The pixel electrode PX is connected to the source electrode SD2 through the through hole TH.

At this time, the pixel electrode PX disposed in the region (pixel) surrounded by the two adjacent scanning signal lines GL _n and GL _{n + 1} and the two adjacent video signal lines DL _m and DL _{m + 1} is, for example, And a region overlapping with the scanning signal line GL _n different from the scanning signal line GL _{n + 1} to which the gate of the TFT element connected to the pixel electrode PX is connected in plan view. Then, a region where the pixel electrode PX and the scanning signal line GL _n overlap in plan (hereinafter, overlapped areas hereinafter) in, and the pixel electrode PX and the scanning signal lines GL and a pair of electrodes (upper electrode and lower electrode), A storage capacitor C2 is formed in which the first insulating layer PAS1 and the second insulating layer PAS2 interposed in the overlapping region are dielectric layers.

  Although omitted in FIGS. 8B to 8D, for example, an alignment film is formed on the pixel electrode PX.

When the configuration of one pixel of the TFT substrate 101 is the configuration shown in FIGS. 8A to 8D, for example, as described above, the size of the storage capacitor C2 of each pixel is individually set. In this case, the size of the storage capacitor (area of the overlapping region) of the pixel having the TFT element whose gate is connected to one scanning signal line GL _n is, for example, as shown in FIG. Become. FIG. 9A shows a pixel electrode in a region (pixel) surrounded by two adjacent scanning signal lines GL _n−1 , GL _n and two adjacent video signal lines DL _j , DL _{j + 1.} Pixels in a region (pixel) surrounded by the storage capacitor formed by PX _{n, j} and the two adjacent video signal lines DL _u and DL _{u + 1} adjacent to the two adjacent scanning signal lines GL _n−1 and GL _n Only the storage capacitor formed by the electrodes PX _{n, u} is shown. In addition, the four video signal lines DL _j , DL _{j + 1} , DL _u , and DL _{u + 1} shown in FIG. 9A are u> j + 1, and the video signal line DL _j is the scanning signal lines GL _n−1 , GL. _It is closest to the signal input terminal of _n .

In this way, the holding capacitor C2 _{n, m} of each pixel having a TFT element whose gate is connected to one common scanning signal line GL _n is represented by, for example, the relationship of the graph shown in FIG. when setting based, it is most widely area of the overlapping region of the distance from the signal input terminal of the scan signal line GL _n is the pixel electrode PX of the pixel closest to the scanning signal line GL _n-1, the scanning signal lines GL _n The area of the overlapping region between the pixel electrode PX and the scanning signal line GL _n-1 may be reduced as the distance from the signal input terminal increases.

Similarly, the size of the storage capacitor (area of the overlapping region) of the pixel having the TFT element whose drain is connected to one common video signal line GL _m is, for example, as shown in FIG. Become. FIG. 9B shows a pixel electrode in a region (pixel) surrounded by two adjacent scanning signal lines GL _i−1 and GL _i and two adjacent video signal lines DL _m and DL _{m + 1.} Pixels in a region (pixel) surrounded by the storage capacitor formed by PX _{i, m} and the two adjacent scanning signal lines GL _n−1 , GL _n and the two adjacent video signal lines DL _m , DL _{m + 1} Only the storage capacitor formed by the electrode PX _{n, m} is shown. In addition, the two scanning signal lines GL _i−1 and GL _n−1 shown in FIG. 9B are n−1> i, and the scanning signal line GL _i−1 is the video signal line DL _m , Close to the signal input end of DL _{m + 1} .

Thus, the drain storage capacitor C2 n of each pixel having a TFT element connected to a common video signal line DL _m of _one, the _m, for example, the relation of the graph shown in FIG. 6 (b) when setting based, the area of the overlapping region of the distance from the signal input terminal of the video signal line DL _m is the pixel electrode PX of the pixel closest to the scanning signal lines GL becomes widest, the signal input of the video signal lines DL _m The area of the overlapping region between the pixel electrode PX and the scanning signal line GL may be reduced as the distance from the end increases.

  In the example shown in FIGS. 9A and 9B, the extending direction (vertical direction) of the video signal line DL is changed when the area of the overlapping region of each pixel electrode PX and the scanning signal line GL is changed. However, the present invention is not limited to this, and it is needless to say that only the dimension in the extending direction (lateral direction) of the scanning signal line GL or both dimensions may be changed.

As described above, according to the liquid crystal display panel of the first embodiment, by setting the storage capacitor C2 of each pixel constituting the display area DA individually, the wiring delay of the scanning signal line GL and the video signal line DL are set. It is possible to reduce the difference in the unwritten voltage V _{L and} the difference in the feedthrough voltage V _FT of each pixel caused by the wiring delay. Therefore, for example, even in a large-screen liquid crystal display device such as a liquid crystal television, the occurrence of uneven brightness and flicker can be easily reduced, and the display quality can be easily improved.

  Further, when setting the storage capacitor of each pixel, for example, based on the area (electrode area) of the overlapping region of the pixel electrode and the scanning signal line in the storage capacitor of the pixel having the shortest distance from the signal input end, It is possible to reduce the electrode area of the TFT element and the storage capacitor that are far from the signal input end. Therefore, the aperture ratio of each pixel constituting the display area can be increased, and the liquid crystal transmittance (display luminance) can be increased.

  The configuration described in the first embodiment is not limited to a large-screen liquid crystal display panel used in a liquid crystal television or the like, and can be applied to, for example, a high-definition or high-speed liquid crystal display panel. For this reason, the configuration of the first embodiment can be applied to, for example, a small and medium-sized liquid crystal display panel used for a display such as a notebook PC or a mobile phone terminal.

  FIG. 10A is a schematic block diagram showing a schematic configuration of a first modification of the liquid crystal display device according to the present invention. FIG. 10B shows a storage capacitor of a pixel having a TFT element connected to one common video signal line when the configuration of the first embodiment is applied to the liquid crystal display panel shown in FIG. It is a schematic graph which shows an example of the setting method.

In the first embodiment, for example, as shown in FIGS. 1A and 4, the signal input ends of the video signal lines DL are provided above the liquid crystal display panel 1 (display area DA). In the example, for N scanning signal lines GL, GL ₁ ,..., GL _i ,... GL _N are set in order from the upper scanning signal line having a short distance from the signal input end of the video signal line DL. .

However, in recent liquid crystal display devices, as shown in FIG. 10A, for example, signal input ends of the video signal lines DL are provided below the liquid crystal display panel 1 (display area DA). There is also a liquid crystal display device. In this case, assuming that the N scanning signal lines GL are GL ₁ ,..., GL _i ,... GL _{N in} order from the scanning signal line on the uppermost side of the display area DA, the distance from the signal input end of the video signal line DL. There shortest of is the scanning signal line GL _N.

As described above, when the scanning signal line GL _N at the lowermost side of the display area DA becomes the scanning signal line GL having the shortest distance from the signal input end of the video signal line DL, the common video signal having one drain is used. The difference (change amount) ΔC2 _{n, m} in the holding capacitance C2 _{n, m of} each pixel having a TFT element connected to the signal line DL _m and the holding capacitance of two adjacent pixels is, for example, FIG. Needless to say, the graph shown in FIG. In the graph shown in FIG. 10B, the horizontal axis is the subscript _n of the scanning signal line GL _n to which the gate of the TFT element of each pixel is connected, and n is the signal of the video signal line DL _m . .., N in order from the scanning signal line farthest from the input end. In the graph shown in FIG. 10B, the vertical axis on the left is the size of the storage capacitor C2 _{n, m} of each pixel, and the vertical axis on the right is the change amount ΔC2 _{n, m} = (C2 _{n, m} -C2 _{n-1, m} ). Further, as the vertical axis on the left side and the vertical axis on the right side increase, the respective values increase.

  FIG. 11A is a schematic block diagram showing a schematic configuration of a second modification of the liquid crystal display device according to the present invention. FIG. 11B shows an example of the relationship between the position of one scanning signal line and the delay amount of the scanning signal when the configuration of the first embodiment is applied to the liquid crystal display panel shown in FIG. An example of the relationship between the position of one scanning signal line and the unwritten voltage of a pixel having a TFT element connected to one common scanning signal line, and the TFT element connected to one common scanning signal line It is a schematic graph which shows an example of the setting method of the storage capacity of the pixel which has.

In the first embodiment, for example, as shown in FIGS. 1A and 4, the signal input ends of the scanning signal lines GL are provided on the left side of the liquid crystal display panel 1 (display area DA). As an example, for M video signal lines DL, DL ₁ ,..., DL _j ,... DL _M are set in order from the left video signal line having a short distance from the signal input end of the scanning signal line GL. .

However, in recent liquid crystal display devices, as shown in FIG. 11A, for example, signal input terminals of the scanning signal lines GL are provided on both the left side and the right side of the liquid crystal display panel 1 (display area DA). There is also a liquid crystal display device. In this case, assuming that the M video signal lines DL are DL ₁ ,..., DL _j ,... DL _{M in} order from the leftmost video signal line in the display area DA, the distance from the signal input end of the scanning signal line GL. The shortest video signal line DL is, for example, two video signal lines DL ₁ and DL _M formed on the outermost side. The video signal line DL having the longest distance from the signal input end of the scanning signal line GL is the video signal line DL formed near the middle between the two video signal lines DL ₁ and DL _M formed on the outermost side. Become _u .

In this case, first delay amount Td of the scanning signal V _G which is input to the scanning signal line GL _n of this is, for example, will change as shown in the lower graph of FIG. 11 (b), the outermost formation The delay amount becomes the largest at a position where the video signal line DL _u formed near the middle of the two video signal lines DL ₁ and DL _M intersects or in the vicinity thereof. Therefore, the unwritten voltage V _L in each pixel having a TFT element whose gate is connected to one common scanning signal line GL _n also changes as shown in the central graph of FIG. Therefore, in the case of the liquid crystal display panel 1 that both ends of the one scanning signal line GL _n to the signal input terminal, each pixel having a TFT element in which the gate is connected to a common scanning signal line GL _n of one Needless to say, the holding capacitor C2 _{n, m} may be set based on the change shown in the upper graph of FIG. 11B, for example. Note that the three graphs shown in FIG. 11 (b), the horizontal axis indicates the subscript m of the video signal line DL _m to the drain of the TFT element is connected, m is the left side of the scanning signal lines GL _n .., M in order from the video signal line closest to the signal input end. Also, the vertical axis on the left side of the three graphs shown in FIG. 11B is, in order from the bottom, the delay amount Td of the scanning signal, the unwritten voltage V _L , and the size of the storage capacitor C2 _{n, m} of each pixel. It is. Each vertical axis on the left increases as it goes upward.

  That is, in the liquid crystal display panel according to the first embodiment, each pixel has a storage capacitor according to the position of the signal input end of the scanning signal line GL and the position of the signal input end of the video signal line DL with respect to the display area DA of the TFT substrate 101. Should be set. Accordingly, the position of the signal input end of the scanning signal line GL and the position of the signal input end of the video signal line DL with respect to the display area DA of the TFT substrate 101 are shown in FIG. 4 (FIG. 1A), FIG. Of course, the configuration described in the first embodiment can be applied even if the positional relationship is not as shown in FIG.

12A to 12D are schematic views for explaining an example of a schematic configuration of the TFT substrate of Example 2 according to the present invention.
FIG. 12A is a schematic plan view showing an example of the configuration of the insulating substrate immediately after forming the first insulating layer. FIG. 12B is a schematic cross-sectional view illustrating an example of a cross-sectional configuration taken along the line EE ′ of FIG. FIG. 12C is a schematic cross-sectional view illustrating an example of a cross-sectional configuration of the storage capacitors of the two pixels SP5 and SP6 illustrated in FIG. FIG. 12D shows an example of the relationship between the position of one scanning signal line and the delay amount of the scanning signal in the liquid crystal display panel of Embodiment 2, the position of one scanning signal line and one common scanning. Schematic showing an example of a relationship with an unwritten voltage of a pixel having a TFT element connected to a signal line, and an example of a method for setting a storage capacitor of a pixel having a TFT element connected to one common scanning signal line FIG.
FIG. 12C is a cross-sectional view in the y direction of the portion where the storage capacitors of the two pixels SP5 and SP6 are formed, and each corresponds to the cross-sectional view shown in FIG.

  In Example 2, the configuration of one pixel is exemplified by the TFT substrate 101 having the configuration shown in FIGS. 8A to 8D, and the TFT substrate 101 capable of further improving display quality is used. The configuration will be described.

  When the TFT substrate 101 having the configuration of one pixel shown in FIGS. 8A to 8C is manufactured, first, a plurality of scanning signal lines GL are formed on the surface of an insulating substrate SUB such as a glass substrate. Form. Next, a first insulating layer PAS1 having a function as a gate insulating film of each TFT element is formed. Next, the semiconductor layer SC is formed. Next, the video signal line DL (including the drain electrode SD1) and the source electrode SD2 are formed. Next, a second insulating layer PAS2 is formed. Finally, the pixel electrode PX is formed.

  In the conventional manufacturing method of the TFT substrate 101, for example, the area of the overlapping region between the pixel electrode PX and the scanning signal line GL of each pixel is generally the insulating layer (first layer) interposed between each pixel electrode and the scanning signal line. The first insulating layer PAS1 and the second insulating layer PAS2) are set on the assumption that the thickness is uniform. That is, when the TFT substrate 101 having the configuration described in the first embodiment is manufactured according to the conventional manufacturing method, the size of the region overlapping with the scanning signal line of each pixel electrode PX when viewed in plan is generally the scanning signal line. It may be set on the assumption that the thickness of the first insulating layer PAS1 and the second insulating layer PAS2 on the GL is uniform.

  However, regarding the insulating substrate SUB formed up to the first insulating layer PAS1, a cross section in the y direction (cross section taken along the line EE ′) passing through the pixels SP5 and SP6 shown in FIG. For example, as shown in FIG. 12B, the first insulating layer PAS1 is formed so as to monotonously increase from one end SBy1 of both ends in the y direction toward the other end SBy2. There may be.

When the film thickness in the y direction of the first insulating layer PAS1 changes, for example, as shown in FIG. 12B, the film thickness in the y direction of the second insulating layer PAS2 changes similarly. I often do. Therefore, the cross-sectional shape of the storage capacitor of the pixel SP5 and the cross-sectional shape of the storage capacitor of the pixel SP6 are as shown in FIG. 12C, for example. That is, the film thickness PASD _i-1 of the insulating layer (first insulating layer PAS1 and second insulating layer PAS2) in the storage capacitor forming portion of the pixel SP5 is equal to the film thickness PASD of the insulating layer in the storage capacitor forming portion of the pixel SP6. It is thinner than _v-1 .

At this time, regarding the film thickness of the insulating layer of the storage capacitor of each pixel having the TFT element whose drain is connected to one common video signal line DL, the film thickness PASD _L assumed at the time of design and actually relationship between the thickness pasd _R of the formed insulating layer, for example, when have a relationship as shown in the lower graph of FIG. 12 (d), the storage capacitor is assumed at the time of designing in the respective pixels The relationship between (C2 _{n, m} ) _L and the actual storage capacity (C2 _{n, m} ) _R is, for example, as shown in the center graph of FIG. That is, as the distance from the signal input end of the video signal line DL is longer, the actual storage capacity is smaller than the storage capacity assumed at the time of design.

Therefore, in such a case, for example, as shown in the upper graph of FIG. 12D, the overlapping area (SGP _{n, m} ) _L of each storage capacitor assumed at the time of design is set to the storage of each pixel. The overlapping area (SGP _{n, m} ) _R reflecting the film thickness PASD _R of the insulating layer of the capacitor forming portion is corrected.

In the three graphs shown in FIG. 12D, the horizontal axis is the subscript _n of the scanning signal line GL _n to which the gate of the TFT element of each pixel is connected, and n is the scanning signal line GL _n. .., N in order from the video signal line closest to the signal input terminal. Further, the vertical axis on the left side of the three graphs shown in FIG. 12D is, in order from the bottom, the film thickness PASD of the insulating layer of the storage capacitor forming portion, the size of the storage capacitor C2, and the pixel electrode and the scanning signal line. Is the area SGP of the overlapping region. Each vertical axis on the left increases as it goes upward.

As described above, the area (dimension) of the overlapping region between the pixel electrode and the scanning signal line of each pixel is changed in accordance with the change in the film thickness of the actually formed first insulating layer PAS1 and second insulating layer PAS2. By correcting, it is possible to reduce the difference between the storage capacitor at the time of design and the actually formed storage capacitor due to the change in the film thickness of the insulating layer. Therefore, the change in the unwritten voltage _VL in each pixel can be further reduced.

  The change in the film thickness of the first insulating layer PAS1 and the film thickness of the second insulating layer PAS2 is very rarely distributed randomly for each TFT substrate 101, for example. Can be classified into several patterns. Hereinafter, an example of a manufacturing method of the TFT substrate 101 and a film thickness distribution pattern (trend) of the first insulating layer PAS1 and the second insulating layer PAS2 will be described.

  FIG. 13A is a schematic plan view showing the film thickness distribution of the insulating film when two TFT substrates are cut out from one mother glass. FIG. 13B is a schematic plan view showing the film thickness distribution of the insulating film when four TFT substrates are cut out from one mother glass. FIG. 13C is a schematic plan view showing the film thickness distribution of the insulating film when six TFT substrates are cut out from one mother glass. FIG. 13D is a schematic diagram showing the film thickness distribution of the insulating film when 15 TFT substrates are cut out from one mother glass.

  At present, the TFT substrate 101 used in the liquid crystal display panel 1 is formed, for example, by forming a plurality of TFT substrates at once using a single large-area glass substrate (mother glass), and then forming each TFT substrate from the mother glass. The TFT substrate 101 is manufactured by a method called multiple chamfering.

  In the case of so-called two-chamfering, in which two TFT substrates 101 are cut out from one mother glass, for example, as shown in FIG. 13A, the TFT substrate is placed in each of the regions 501 and 502 of one mother glass 5. 101 is formed. Then, after forming the TFT substrate 101 in each of the regions 501 and 502, the regions 501 and 502 are cut out from the mother glass 5 to obtain two TFT substrates 101.

  In the case of such two-chamfering, an insulating film for forming the first insulating layer PAS1 and the second insulating layer PAS2 in each of the regions 501 and 502 of the mother glass 5 is generally formed on the entire surface of the mother glass 5. (Film formation). At this time, the film thickness distribution of the insulating film formed on the entire surface of the mother glass 5 is represented by, for example, a concentric circle centered on the center P of the mother glass 5 as shown by a two-dot chain line in FIG. The distribution is such that the center P and its vicinity are the thickest and gradually become thinner as the distance from the center P increases. This is because the insulating film is formed by, for example, a plasma CVD method.

  In the case of so-called four-chamfering, in which four TFT substrates 101 are cut out from one mother glass, for example, as shown in FIG. 13B, regions 511, 512, 513, and 514 of one mother glass 5 are formed. A TFT substrate 101 is formed on each. Then, after forming the TFT substrate 101 in each of the regions 511 to 514, the TFT substrates 101 are obtained by cutting the regions 511 to 514 from the mother glass 5.

  In the case of such four-chamfering as well, the insulating film for forming the first insulating layer PAS1 and the second insulating layer PAS2 in each of the regions 511 to 514 of the mother glass 5 is generally formed on the entire surface of the mother glass 5. It is formed. Also at this time, the film thickness distribution of the insulating film formed on the entire surface of the mother glass 5 is, for example, a concentric circle centered on the center P of the mother glass 5 as shown by a two-dot chain line in FIG. The distribution is such that the center P and its vicinity are the thickest and gradually become thinner as the distance from the center P increases.

  In the case of so-called six chamfering, in which six TFT substrates 101 are cut out from one mother glass, for example, as shown in FIG. 13C, areas 521, 522, 523, 524 of one mother glass 5 are used. A TFT substrate 101 is formed on each of 525 and 526. Then, after the TFT substrate 101 is formed in each of the regions 521 to 526, the regions 521 to 526 are cut out from the mother glass 5 to obtain six TFT substrates 101.

  Also in the case of such 6 chamfering, for example, the insulating film for forming the first insulating layer PAS1 and the second insulating layer PAS2 in each of the regions 521 to 526 of the mother glass 5 is generally made of the mother glass 5. It is formed on the entire surface. Also at this time, the film thickness distribution of the insulating film formed on the entire surface of the mother glass 5 is, for example, a concentric circle centered on the center P of the mother glass 5 as shown by a two-dot chain line in FIG. The distribution is such that the center P and its vicinity are the thickest and gradually become thinner as the distance from the center P increases.

  In the case of so-called 15 chamfering, in which 15 TFT substrates 1 are cut out from one mother glass, for example, as shown in FIG. 13D, areas 531, 532, 533, and 534 of one mother glass 5 are used. The TFT substrate 101 is formed on each of 535, 536, 537, 538, 539, 540, 541, 542, 543, 544, and 545. Then, after forming the TFT substrate 101 in each of the regions 531 to 545, the regions 531 to 545 are cut out from the mother glass 5 to obtain 15 TFT element substrates 101.

  Also in the case of such 15 chamfering, for example, the insulating film for forming the first insulating layer PAS1 and the second insulating layer PAS2 in each of the regions 531 to 545 of the mother glass 5 is generally the same as the mother glass 5. It is formed on the entire surface. Also at this time, the film thickness distribution of the insulating film formed on the entire surface of the mother glass 5 is, for example, a concentric circle centered on the center P of the mother glass 5 as shown by a two-dot chain line in FIG. The distribution is such that the center P and its vicinity are the thickest and gradually become thinner as the distance from the center P increases.

  Here, as shown in FIGS. 13A to 13D, the film thickness distribution of the insulating film on one mother glass 5 and each region cut out from the mother glass 5, that is, one TFT substrate 101 are shown. When the relationship with the film thickness distribution of the insulating film in the region where is formed, the relationship is classified into the following four patterns.

  The first pattern of the relationship between the thickness distribution of the insulating film on one mother glass 5 and the thickness distribution of the insulating film in the region where one TFT substrate 101 is formed is the x-direction of the insulating film. In this pattern, the film thickness and the film thickness in the y direction change as shown in regions 501 and 502 shown in FIG. 13A and regions 537 and 539 shown in FIG. The relationship between this first pattern and the thickness of the insulating layer in the storage capacitor forming portion of each pixel formed in the display area of one TFT substrate 101 will be described with reference to FIG.

  FIG. 14 is a schematic plan view for explaining an example of the relationship between the first pattern of the film thickness distribution of the insulating film and the thickness of the insulating layer in the storage capacitor forming portion of each pixel.

In describing the relationship between the first pattern of the thickness distribution of the insulating film and the thickness of the insulating layer in the storage capacitor forming portion of each pixel, as shown in FIG. An example of the TFT substrate formed in 501 is given. In FIG. 14, GL ₁ and GL _N indicate scanning signal lines arranged on the outermost side of the display area, and DL ₁ and DL _M indicate video signal lines arranged on the outermost side of the display area. Show. Further, a plurality of scanning signal lines (not shown) are arranged between the two scanning signal lines GL ₁ and GL _N. Further, between the two video signal lines DL ₁ and DL _M , a video signal line DL _u positioned approximately in the middle thereof and a plurality of video signal lines (not shown) are arranged.

At this time, the film thickness of the first thickness and the second insulating layer PAS2 insulating layer PAS1 in on the scanning signal line GL _N, for example, to intersect the scanning signal lines GL _N and the video signal line DL _u is It becomes thickest at or near the point where it is, and it becomes thinner as the distance from the intersecting point becomes longer. Therefore, the insulating layer in the storage capacitor forming portion of each pixel having the TFT element whose gate is connected to the scanning signal line GL _N is, for example, the pixel of the pixel having the TFT element whose drain is connected to the video signal line DL _u . insulating layer is thickest in the storage capacitor forming portion, pixel drain has a TFT element pixel or drain is connected to the video signal line DL _M having a TFT element connected to the video signal lines DL ₁ or a, The insulating layer in the storage capacitor forming portion of both pixels is the thinnest.

Further, the thickness of the first insulating layer PAS1 and the second thickness of the insulating layer PAS2 under the video signal line DL _u, for example, the scanning signal lines GL ₁ and the video signal line DL _u intersect From the point, the thickness increases monotonously toward the point where the scanning signal line GL _N and the video signal line DL _u intersect. Therefore, the insulating layer in the storage capacitor forming portion of each pixel having a TFT element whose drain is connected to the video signal line DL _u is, for example, a pixel having a TFT element whose gate is connected to the scanning signal line GL ₁ . insulating layer is thinnest in the storage capacitor forming portion, an insulating layer is thickest in the storage capacitor formed of the pixel having a TFT element in which the gate is connected to the scanning signal line GL _N.

Therefore, the TFT substrate 101 formed in the region 501 of the mother glass 5 has a film thickness of the insulating layer in the storage capacitor forming portion of each pixel. For example, the gate is connected to the scanning signal line GL _N and the drain is the video signal line. The insulating layer in the storage capacitor forming portion of the pixel having the TFT element connected to DL _u is thickest, and the insulating layer in the storage capacitor forming portion of the pixel having a long distance from the pixel is thinner. Therefore, the change in the film thickness of the insulating layer in the storage capacitor forming portion of each pixel, the position of the signal input end of each scanning signal line GL in the TFT substrate 101 formed in the region 501, and the position of each video signal line DL By setting the area of the overlapping region of each pixel electrode and the scanning signal line individually based on the relationship with the position of the signal input end, the magnitude of the unwritten voltage V _L of each pixel and the feedthrough voltage V The size of the _FT can be made substantially the same.

In the above description with reference to FIG. 14, the TFT substrate formed in the region 501 of the mother glass 5 in the case of two chamfering is taken as an example, but the TFT substrate formed in the other region 502 is also in the region. By setting the area of the overlapping region of each pixel electrode and the scanning signal line individually in the same way as the TFT substrate 501, the magnitude of the unwritten voltage V _{L and} the magnitude of the feedthrough voltage V _FT of each pixel are set. Can be made approximately the same size. In addition, regarding the TFT substrate formed in the regions 537 and 539 in the case of 15 chamfering shown in FIG. 13D, the area of the overlapping region of each pixel electrode and the scanning signal line is considered in the same way as the TFT substrate in the region 501. Are set individually, the magnitude of the unwritten voltage _{VL and} the magnitude of the feedthrough voltage _VFT of each pixel can be made substantially the same.

  The second pattern of the relationship between the film thickness distribution of the insulating film on one mother glass 5 and the film thickness distribution of the insulating film in the region where one TFT substrate 101 is formed is the x-direction of the insulating film. The pattern in which the film thickness and the film thickness in the y direction change as in the regions 522, 525 shown in FIG. 13C and the regions 532, 535, 541, 544 shown in FIG. 13D, respectively. It is. The relationship between this second pattern and the insulating layer in the storage capacitor forming portion of each pixel formed in the display area of one TFT substrate 101 will be described with reference to FIG.

  FIG. 15 is a schematic plan view for explaining an example of the relationship between the second pattern of the thickness distribution of the insulating film and the thickness of the insulating layer in the storage capacitor forming portion of each pixel.

In explaining the relationship between the second pattern of the thickness distribution of the insulating film and the thickness of the insulating layer in the storage capacitor forming portion of each pixel, as shown in FIG. The TFT substrate formed in 522 is taken as an example. In FIG. 15, GL ₁ and GL _N indicate scanning signal lines arranged on the outermost side of the display area, and DL ₁ and DL _M indicate video signal lines arranged on the outermost side of the display area. Show. In addition, between the two scanning signal lines GL ₁ and GL _N , a scanning signal line GL _v located approximately in the middle of them and a plurality of scanning signal lines (not shown) are arranged. Also, a plurality of video signal lines (not shown) are arranged between the two video signal lines DL ₁ and DL _M.

At this time, the first thickness and the second thickness of the insulating layer PAS2 insulating layer PAS1 in on the scanning signal line GL _v, for example, to intersect the scanning signal lines GL _v and the video signal line DL ₁ is from the point it is, toward a point where the scanning signal line GL _v and the video signal line DL _M intersect, become monotonically larger. Therefore, the insulating layer in the storage capacitor forming part of the pixels having a TFT element in which the gate is connected to the scanning signal line GL _v, for example, a drain of the pixel having a TFT element connected to the video signal lines DL ₁ insulating layer is thinnest in the storage capacitor forming portion, a drain insulating layer becomes thickest in the storage capacitor formed of the pixel having a TFT element connected to the video signal line DL _M.

The first thickness and the second thickness of the insulating layer PAS2 insulating layer PAS1 under the video signal line DL _M is, for example, the scanning signal line GL _v and the video signal line DL _M intersect It becomes the thickest at or near the point and becomes thinner as the distance from the intersecting point becomes longer. Therefore, the insulating layer in the storage capacitor forming part of the pixels having a TFT element in which the drain is connected to the video signal line DL _M, for example, a pixel having a TFT element in which the gate is connected to the scan signal line GL _v insulating layer is thickest in the storage capacitor forming portion, a pixel having a TFT element having a gate a pixel or a gate having a TFT element connected to the scanning signal line GL ₁ is connected to the scan signal line GL _N or a, The insulating layer in the storage capacitor forming portion of both pixels is the thinnest.

Accordingly, the TFT substrate 101 which is formed in the region 522 of the mother glass 5, the thickness of the insulating layer in the storage capacitor forming part of each pixel, for example, a gate connected to the scanning signal line GL _v, drain the video signal lines The insulating layer in the storage capacitor forming portion of the pixel having the TFT element connected to the DL _M is the thickest, and the insulating layer in the storage capacitor forming portion of the pixel having a long distance from the TFT element is thinner. Therefore, the change in the thickness of the insulating layer in the storage capacitor forming portion of each pixel, the position of the signal input end of each scanning signal line GL in the TFT substrate 101 formed in the region 522, and the position of each video signal line DL Based on the relationship with the position of the signal input end, the overlapping area between each pixel electrode and the scanning signal line is individually set, so that the magnitude of the unwritten voltage _{VL and} the magnitude of the feedthrough voltage _VFT of each pixel are set. Can be made approximately the same size.

In the above description along FIG. 15, the TFT substrate formed in the region 522 of the mother glass 5 in the case of 6 chamfering is taken as an example, but the TFT substrate formed in the other region 525 is also in the region. By setting the area of the overlapping region of each pixel electrode and the scanning signal line individually in the same way as the TFT substrate 522, the magnitude of the unwritten voltage _{VL and} the magnitude of the feedthrough voltage _VFT of each pixel are set. Can be made approximately the same size. Further, with respect to the TFT substrate formed in the regions 532, 535, 541, and 544 in the case of 15 chamfering shown in FIG. 13D, each pixel electrode and the scanning signal line are connected in the same way as the TFT substrate in the region 522. By setting the area of the overlapping region individually, the magnitude of the unwritten voltage _{VL and} the magnitude of the feedthrough voltage _VFT of each pixel can be made substantially the same.

  The third pattern of the relationship between the film thickness distribution of the insulating film on one mother glass 5 and the film thickness distribution of the insulating film in the region where one TFT substrate 101 is formed is the x-direction of the insulating film. The film thickness and the film thickness in the y direction are as shown in regions 511, 512, 513, 514 shown in FIG. 13B, regions 521, 523, 524, 526 shown in FIG. 13C, and FIG. It is a pattern that changes as shown in the regions 531, 533, 534, 536, 540, 542, 543, and 545. The relationship between the third pattern and the insulating layer in the storage capacitor forming portion of each pixel formed in the display area of one TFT substrate 101 will be described with reference to FIG.

  FIG. 16 is a schematic plan view for explaining an example of the relationship between the third pattern of the film thickness distribution of the insulating film and the thickness of the insulating layer in the storage capacitor forming portion of each pixel.

In describing the relationship between the third pattern of the thickness distribution of the insulating film and the thickness of the insulating layer in the storage capacitor forming portion of each pixel, as shown in FIG. The TFT substrate formed in 511 is taken as an example. In FIG. 16, GL ₁ and GL _N indicate scanning signal lines arranged on the outermost side of the display area, and DL ₁ and DL _M indicate video signal lines arranged on the outermost side of the display area. Show. A plurality of scanning signal lines (not shown) are arranged between the two scanning signal lines GL ₁ and GL _N , and between the two video signal lines DL ₁ and DL _M , A plurality of video signal lines (not shown) are arranged.

At this time, the first thickness and the second thickness of the insulating layer PAS2 insulating layer PAS1 in on the scanning signal line GL _N, for example, to intersect the scanning signal lines GL _N and the video signal line DL ₁ is From the point where the scanning signal line GL _N and the video signal line DL _M intersect, the thickness increases monotonously. Therefore, the insulating layer in the storage capacitor forming part of the pixels having a TFT element in which the gate is connected to the scanning signal line GL _N, for example, a drain of the pixel having a TFT element connected to the video signal lines DL ₁ insulating layer is thinnest in the storage capacitor forming portion, a drain insulating layer becomes thickest in the storage capacitor formed of the pixel having a TFT element connected to the video signal line DL _M.

The first thickness and the second thickness of the insulating layer PAS2 insulating layer PAS1 under the video signal line DL _M is, for example, the scanning signal lines GL ₁ and the video signal line DL _M intersect From the point, the thickness increases monotonously toward the point where the scanning signal line GL _N and the video signal line DL _M intersect. Therefore, the insulating layer in the storage capacitor forming portion of each pixel having a TFT element whose drain is connected to the video signal line DL _M is, for example, a pixel having a TFT element whose gate is connected to the scanning signal line GL ₁ . insulating layer is thinnest in the storage capacitor forming portion, an insulating layer is thickest in the storage capacitor formed of the pixel having a TFT element in which the gate is connected to the scanning signal line GL _N.

Therefore, the TFT substrate 101 formed in the region 511 of the mother glass 5 has a film thickness of the insulating layer in the storage capacitor forming portion of each pixel. For example, the gate is connected to the scanning signal line GL _N and the drain is the video signal line. The insulating layer in the storage capacitor forming portion of the pixel having the TFT element connected to the DL _M is the thickest, and the insulating layer in the storage capacitor forming portion of the pixel having a long distance from the pixel is thinner. Therefore, the change in the thickness of the insulating layer in the storage capacitor forming portion of each pixel, the position of the signal input end of each scanning signal line GL in the TFT substrate 101 formed in the region 511, and the position of each video signal line DL By setting the area of the overlapping region of each pixel electrode and the scanning signal line individually based on the relationship with the position of the signal input end, the magnitude of the unwritten voltage V _L of each pixel and the feedthrough voltage V The size of the _FT can be made substantially the same.

In the above description along FIG. 16, the TFT substrate formed in the region 511 of the mother glass 5 in the case of four chamfering is taken as an example, but the TFT element substrate formed in the other three regions 512 to 514. In the same manner as the TFT substrate in the region 511, by setting the area of the overlapping region of each pixel electrode and the scanning signal line individually, the magnitude of the unwritten voltage _VL of each pixel and the feedthrough voltage are set. The size of _VFT can be made substantially the same. Further, the TFT substrate formed in the regions 521, 523, 524, and 526 in the case of 6 chamfering shown in FIG. 13C, and the regions 532, 535, 541, and 544 in the case of 15 chamfering shown in FIG. For the TFT substrate formed in the same manner, the size of the unwritten voltage V _L of each pixel can be set by individually setting the area of the overlapping region of each pixel electrode and the scanning signal line in the same way as the TFT substrate in the region 511. And the magnitude of the feedthrough voltage _VFT can be made substantially the same.

  The fourth pattern of the relationship between the film thickness distribution of the insulating film on one mother glass 5 and the film thickness distribution of the insulating film in the region where one TFT substrate 101 is formed is the x-direction of the insulating film. In this pattern, the film thickness and the film thickness in the y direction change as in the region 538 shown in FIG. The relationship between the fourth pattern and the thickness of the insulating layer in the storage capacitor forming portion of each pixel formed in the display area of one TFT substrate 101 will be described with reference to FIG.

  FIG. 17 is a schematic plan view for explaining an example of the relationship between the fourth pattern of the film thickness distribution of the insulating film and the thickness of the insulating layer in the storage capacitor forming portion of each pixel.

In explaining the relationship between the fourth pattern of the thickness distribution of the insulating film and the thickness of the insulating layer in the storage capacitor forming portion of each pixel, as shown in FIG. The TFT substrate formed on 538 is taken as an example. In FIG. 17, GL ₁ and GL _N indicate scanning signal lines arranged on the outermost side of the display area, and DL ₁ and DL _M indicate video signal lines arranged on the outermost side of the display area. Show. In addition, between the two scanning signal lines GL ₁ and GL _N , a scanning signal line GL _v located approximately in the middle of them and a plurality of scanning signal lines (not shown) are arranged. Further, between the two video signal lines DL ₁ and DL _M , a video signal line DL _u positioned approximately in the middle thereof and a plurality of video signal lines (not shown) are arranged.

At this time, the first thickness and the second thickness of the insulating layer PAS2 insulating layer PAS1 in on the scanning signal line GL _v, for example, to intersect with the scanning signal line GL _v and the video signal line DL _u is It becomes thickest at or near the point where it is, and it becomes thinner as the distance from the intersecting point becomes longer. Therefore, the insulating layer in the storage capacitor forming part of the pixels having a TFT element in which the gate is connected to the scanning signal line GL _v, for example, a drain of the pixel having a TFT element connected to the video signal line DL _u insulating layer is thickest in the storage capacitor forming portion, pixel drain has a TFT element pixel or drain is connected to the video signal line DL _M having a TFT element connected to the video signal lines DL ₁ or a, The insulating layer in the storage capacitor forming portion of both pixels is the thinnest.

The first thickness and the second thickness of the insulating layer PAS2 insulating layer PAS1 under the video signal line DL _u, for example, the scanning signal line GL _v and the video signal line DL _u intersect It becomes the thickest at or near the point and becomes thinner as the distance from the intersecting point becomes longer. Therefore, the insulating layer in the storage capacitor forming part of the pixels having a TFT element in which the drain is connected to the video signal line DL _u, for example, a pixel having a TFT element in which the gate is connected to the scan signal line GL _v insulating layer is thickest in the storage capacitor forming portion, a pixel having a TFT element having a gate a pixel or a gate having a TFT element connected to the scanning signal line GL ₁ is connected to the scan signal line GL _N or a, The insulating layer in the storage capacitor forming portion of both pixels is the thinnest.

Accordingly, the TFT substrate 101 which is formed in the region 538 of the mother glass 5, the thickness of the insulating layer in the storage capacitor forming part of each pixel, for example, a gate connected to the scanning signal line GL _v, drain the video signal lines The insulating layer in the storage capacitor forming portion of the pixel having the TFT element connected to DL _u is thickest, and the insulating layer in the storage capacitor forming portion of the pixel having a long distance from the pixel is thinner. Therefore, the change in the thickness of the insulating layer in the storage capacitor forming portion of each pixel, the position of the signal input end of each scanning signal line GL in the TFT substrate 101 formed in the region 538, and the position of each video signal line DL By setting the area of the overlapping region of each pixel electrode and the scanning signal line individually based on the relationship with the position of the signal input end, the magnitude of the unwritten voltage V _L of each pixel and the feedthrough voltage V The size of the _FT can be made substantially the same.

In the above description along FIG. 16, the TFT element substrate formed in the region 538 of the mother glass 5 in the case of 15 chamfering is mentioned, but not limited to 15 chamfering, for example, 3 vertical surfaces × 3 horizontal surfaces In the case of the nine chamfering, the TFT element substrate formed in the central region is also set by individually setting the area of the overlapping region of each pixel electrode and the scanning signal line in the same way as the TFT substrate in the region 538. The magnitude of the unwritten voltage V _{L and} the magnitude of the feedthrough voltage V _FT of each pixel can be made substantially the same.

  The present invention has been specifically described above based on the above-described embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. is there.

  For example, in the first and second embodiments, the configuration of one pixel is exemplified by the TFT substrate 101 having the configuration shown in FIGS. 8A to 8D, but the present invention is not limited to this. Of course, the configuration of one pixel can be applied to another configuration.

  FIG. 18 is a schematic plan view showing another example of the schematic configuration of one pixel on the TFT substrate of the liquid crystal display panel.

In the TFT substrate 101 of the liquid crystal display panel 1, the storage capacitor formed in each pixel includes a pixel electrode PX, a scanning signal line to which a video signal line and a gate of a TFT element connected to the pixel electrode are connected. Need only be formed of different conductor layers and an insulating layer interposed between the pixel electrode and the conductor layer. Therefore, for example, as shown in FIG. 18, a conductor layer STL different from the scanning signal line GL (GL _n , GL _{n + 1} ) is provided, and a storage capacitor C2 is formed in the overlapping region of the conductive layer STL and the pixel electrode PX. Of course, you may do. At this time, the conductive layer STL is formed, for example, between every two adjacent scanning signal lines in the step of forming the scanning signal line GL. At this time, the conductive layer STL formed between two adjacent scanning signal lines is connected (short-circuited) outside the display region so as to have the same potential as the counter electrode CT.

  Moreover, in the said Example 1 and the said Example 2, although the TFT substrate 1 of the liquid crystal display device (liquid crystal display panel) was mentioned as an example, this invention is applied not only to a liquid crystal display device but to other display devices. It is also possible. That is, if the display device has a configuration equivalent to that of the TFT substrate 101 as shown in FIGS. 8A to 8D and has a display panel for displaying images and images with the same operation principle. By applying the present invention, luminance unevenness and flicker can be reduced, and display quality can be improved. As such a display device, for example, there is a display device having a self-luminous display panel using an organic EL (ElectroLuminescence).

It is a schematic block diagram which shows an example of schematic structure of the liquid crystal display device concerning this invention. FIG. 2 is a schematic circuit diagram illustrating an example of a circuit configuration of one pixel in the liquid crystal display panel illustrated in FIG. FIG. 2 is a schematic diagram illustrating an example of a waveform of a scanning signal and a waveform of a video signal input to each TFT element of a pixel located at four corners of the display area of the liquid crystal display panel illustrated in FIG. It is a schematic diagram for demonstrating the definition of an unwritten voltage and a feedthrough voltage. FIG. 3 is a schematic diagram comparing the magnitudes of unwritten voltages in two pixels SP1 and SP4 shown in FIG. It is a schematic diagram which shows an example of distribution of the magnitude | size of the unwritten voltage in the display area of one conventional liquid crystal display panel. It is a schematic circuit diagram for demonstrating schematic structure of the liquid crystal display panel of Example 1 by this invention. It is a schematic graph which shows the relationship between the distance from the signal input end of one scanning signal line in the conventional liquid crystal display panel, the delay amount of a scanning signal, and the unwritten voltage and feedthrough voltage of each pixel. 6 is a schematic graph illustrating an example of a method for setting a storage capacitor of each pixel having a TFT element connected to one common scanning signal line in the liquid crystal display panel of Example 1. FIG. It is a schematic graph which shows the relationship between the distance from the signal input end of one video signal line in the conventional liquid crystal display panel, the delay amount of a video signal, the unwritten voltage and feedthrough voltage of each pixel. 6 is a schematic graph illustrating an example of a method for setting a storage capacitor of each pixel having a TFT element connected to one common video signal line in the liquid crystal display panel of Embodiment 1. FIG. It is a model top view which shows schematic structure of a liquid crystal display panel. It is a schematic cross section in the A-A 'line of Fig.7 (a). It is a schematic plan view which shows an example of schematic structure of one pixel in the TFT substrate of a liquid crystal display panel. It is a schematic cross section in the B-B 'line of Fig.8 (a). It is a schematic cross section in the C-C 'line of Fig.8 (a). It is a schematic cross section in the D-D 'line of Fig.8 (a). 6 is a schematic plan view illustrating an example of a storage capacitor of a pixel arranged along one scanning signal line in a TFT substrate to which the configuration of Example 1 is applied. FIG. 6 is a schematic plan view illustrating an example of a storage capacitor of a pixel arranged along one video signal line in a TFT substrate to which the configuration of Example 1 is applied. FIG. It is a schematic block diagram which shows schematic structure of the 1st modification of the liquid crystal display device concerning this invention. FIG. 10 is a schematic diagram illustrating an example of a method for setting a storage capacitor of a pixel having a TFT element connected to one common video signal line when the configuration of the first embodiment is applied to the liquid crystal display panel illustrated in FIG. FIG. It is a schematic block diagram which shows schematic structure of the 2nd modification of the liquid crystal display device concerning this invention. An example of the relationship between the position of one scanning signal line and the delay amount of the scanning signal when the configuration of the first embodiment is applied to the liquid crystal display panel shown in FIG. 11A, the position of one scanning signal line And an unwritten voltage of a pixel having a TFT element connected to one common scanning signal line, and a storage capacitor of a pixel having a TFT element connected to one common scanning signal line It is a schematic graph which shows an example of the setting method. It is a schematic plan view which shows an example of a structure of the insulated substrate immediately after forming a 1st insulating layer. It is a schematic cross section which shows an example of the cross-sectional structure in the EE 'line of Fig.12 (a). FIG. 13 is a schematic cross-sectional view illustrating an example of a cross-sectional configuration of a storage capacitor of two pixels SP5 and SP6 illustrated in FIG. An example of the relationship between the position of one scanning signal line and the delay amount of the scanning signal in the liquid crystal display panel of Embodiment 2 TFT connected to the position of one scanning signal line and one common scanning signal line It is a schematic graph which shows an example of the relationship with the unwritten voltage of the pixel which has an element, and an example of the setting method of the storage capacity of the pixel which has a TFT element connected to one common scanning signal line. It is a schematic plan view which shows the film thickness distribution of the insulating film in the case of cutting out two TFT substrates from one mother glass. It is a schematic plan view which shows the film thickness distribution of the insulating film in the case of cutting out four TFT substrates from one mother glass. It is a schematic plan view which shows the film thickness distribution of the insulating film in the case of cutting out six TFT substrates from one mother glass. It is a schematic diagram which shows the film thickness distribution of the insulating film in the case of cutting out 15 TFT substrates from one mother glass. It is a schematic plan view for explaining an example of the relationship between the first pattern of the film thickness distribution of the insulating film and the thickness of the insulating layer in the storage capacitor forming portion of each pixel. It is a schematic plan view for explaining an example of the relationship between the second pattern of the film thickness distribution of the insulating film and the thickness of the insulating layer in the storage capacitor forming portion of each pixel. It is a schematic plan view for explaining an example of the relationship between the third pattern of the thickness distribution of the insulating film and the thickness of the insulating layer in the storage capacitor forming portion of each pixel. It is a schematic plan view for explaining an example of the relationship between the fourth pattern of the film thickness distribution of the insulating film and the thickness of the insulating layer in the storage capacitor forming portion of each pixel. It is a schematic plan view which shows another example of schematic structure of one pixel in the TFT substrate of a liquid crystal display panel. It is a schematic circuit diagram which shows an example of schematic structure of the conventional liquid crystal display panel.

Explanation of symbols

1 ... liquid crystal display panel 101 ... TFT substrate 102 ... facing substrate 103 ... sealing material 104A, 104B ... polarizer SUB ... glass substrate _{GL, GL n, GL n +} 1, GL 1, GL i-1, GL i, GL v, GL _N−1 , GL _N ... Scanning signal line DL, DL _m , DL _{m + 1} , DL ₁ , DL ₂ , DL _j , DL _{j + 1} , DL _u , DL _M ... Video signal line SD1 ... drain electrode SD2 ... source electrode SC ... semiconductor Layer PX ... Pixel electrode LC ... Liquid crystal CT ... Common electrode PAS1 ... First insulating layer PAS2 ... Second insulating layer DA ... Display area C1 ... Pixel capacitance C2, C2 _1,1 , C2 _{1, j} , C21 _{, M} , C2 _{i, 1} , C2 _{i, j} , C2 _{i, M} , C2 _{N, 1} , C2 _{N, j} , C2 _{N, M} ... Holding capacitor Tr... TFT element PX1, PX2, PX3, PX 4, PX5, PX6 ... Pixel 2 ... Data driver 3 ... Gate driver 4 ... Common voltage input circuit 5 ... Mother glass

Claims (11)

A plurality of scanning signal lines, a plurality of video signal lines three-dimensionally intersecting with the plurality of scanning signal lines, a plurality of TFT elements arranged in a matrix, and a matrix. A display device comprising a display panel having a plurality of pixel electrodes connected to a source of the TFT element,
The display area of the display panel is composed of a set of a plurality of pixels each having a TFT element and a pixel electrode connected to the source of the TFT element.
Each TFT element has a gate connected to one scanning signal line of the plurality of scanning signal lines, and a drain connected to one video signal line of the plurality of video signal lines. And
Each pixel electrode includes a conductor layer different from the scanning signal line to which the gate of the TFT element connected to the video signal line and the pixel electrode is connected, and an insulation interposed between the pixel electrode and the conductor layer. A storage capacity is formed by the layers,
Among the plurality of pixels constituting the display region, a plurality of pixels having a TFT element whose gate is connected to a certain common scanning signal line is the scanning of the two adjacent pixels. When the size of the storage capacitor formed in the pixel closer to the signal input end of the signal line is Cst1, and the size of the storage capacitor formed in the farther pixel is Cst2, Cst1 ≧ Cst2, and When the size of the storage capacitor formed in the pixel closest to the signal input terminal of the scanning signal line is Cst3 and the size of the storage capacitor formed in the pixel farthest is Cst4, Cst3> Cst4,
Among the plurality of pixels constituting the display region, a plurality of pixels having a TFT element whose drain is connected to a certain common video signal line is the image of the two adjacent pixels. When the size of the storage capacitor formed in the pixel closer to the signal input terminal of the signal line is Cst5 and the size of the storage capacitor formed in the farther pixel is Cst6, Cst5 ≧ Cst6 and Cst7> Cst8, where Cst7 is the size of the storage capacitor formed in the pixel closest to the signal input end of the video signal line and Cst8 is the size of the storage capacitor formed in the farthest pixel. Display device.   A storage capacitor formed in a plurality of pixels each having a TFT element whose gate is connected to the one common scanning signal line is connected to a signal input terminal of the scanning signal line of two adjacent pixels. The area of the region where the pixel electrode of the storage capacitor formed in the near pixel and the conductor layer overlap in plan view is S1, and the pixel electrode of the storage capacitor formed in the far pixel and the conductor layer are Assuming that the area of the overlapping region in the plane is S2, S1 ≧ S2, and the pixel electrode of the storage capacitor formed in the pixel closest to the signal input end of the scanning signal line and the conductor layer are planar. S3> S4, where S3 is the area of the overlapping region, and S4 is the area of the overlapping region of the pixel electrode of the storage capacitor formed in the farthest pixel and the conductor layer in plan view. Claim 1 Of the display device.   A storage capacitor formed in a plurality of pixels each having a TFT element whose drain is connected to the one common video signal line is connected to a signal input terminal of the video signal line of two adjacent pixels. The area of the region where the pixel electrode of the storage capacitor formed in the near pixel and the conductor layer overlap in plan view is S5, and the pixel electrode of the storage capacitor formed in the far pixel and the conductor layer are Assuming that the area of the overlapping region in a plane is S6, S5 ≧ S6, and the pixel electrode of the storage capacitor formed in the pixel closest to the signal input end of the video signal line and the conductor layer are planar. S7> S8, where S7 is the area of the overlapping region, and S8 is the area of the overlapping region of the pixel electrode of the storage capacitor formed in the farthest pixel and the conductor layer in plan view. Claim 1 The display device according to claim 2. A storage capacitor formed in a plurality of pixels each having a TFT element whose gate is connected to the one common scanning signal line has two storage capacitors according to the distance from the signal input end of the scanning signal line. The difference in the size of the storage capacitor formed in the adjacent pixel changes,
4. The display device according to claim 1, wherein the larger the distance from the signal input end of the scanning signal line, the smaller the difference in the size of the storage capacitor. 5. A storage capacitor formed in a plurality of pixels each having a TFT element whose gate is connected to the one common scanning signal line has two storage capacitors according to the distance from the signal input end of the scanning signal line. The difference in the size of the storage capacitor formed in the adjacent pixel changes,
The change rate of the difference between the storage capacitor sizes formed in two adjacent pixels shorter than a certain distance from the signal input end of the scanning signal line is longer than the certain distance. 4. The display device according to claim 1, wherein the display device has a change rate larger than a change rate of a difference in size of a storage capacitor formed in two adjacent pixels. 5.   The certain distance is a distance 3 from the signal input end of the scanning signal line to the position where the gate of the TFT element of the pixel located farthest from the signal input end of the scanning signal line is connected. The display device according to claim 5, wherein the distance is a fraction of a minute. A storage capacitor formed in a plurality of pixels each having a TFT element whose drain is connected to the one common video signal line has two storage capacitors according to the distance from the signal input end of the video signal line. The difference in the size of the storage capacitor formed in the adjacent pixel changes,
7. The display device according to claim 1, wherein the difference in the size of the storage capacitor is smaller as the distance of the video signal line from the signal input end is longer. A storage capacitor formed in a plurality of pixels each having a TFT element whose drain is connected to the one common video signal line has two storage capacitors according to the distance from the signal input end of the video signal line. The difference in the size of the storage capacitor formed in the adjacent pixel changes,
The change rate of the difference in the size of the storage capacitor formed in two adjacent pixels shorter than a certain distance from the signal input end of the video signal line is longer than the certain distance 2 7. The display device according to claim 1, wherein the display device has a change rate larger than a change rate of a difference in size of a storage capacitor formed in two adjacent pixels.   The certain distance is a distance 3 from the signal input end of the video signal line to the position where the drain of the TFT element of the pixel located farthest from the signal input end of the video signal line is connected. The display device according to claim 8, wherein the distance is a fraction of a distance.   The storage capacitor in each pixel constituting the display region has a capacitance of the insulating layer according to the distance from the signal input end of the scanning signal line and the distance from the signal input end of the video signal line to which the drain is connected. The display device according to claim 1, wherein the thicknesses are different.   The display device according to any one of claims 1 to 10, wherein the display panel is a liquid crystal display panel in which a liquid crystal material is sealed between a pair of substrates.

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