JP2008301287A - D / A converter circuit and liquid crystal driving device - Google Patents

Abstract

When a digital signal for switching the most significant bit (MSB) is input, the value of the digital signal changes from (1000... 000) to (0111... 111) and vice versa. Provided is a D / A converter circuit capable of suppressing the occurrence of a large glitch when changing.
An R-2R ladder resistor network 1 including a plurality of shunt resistors corresponding to each bit of an input digital signal, and a current path in the R-2R ladder resistor network 1 are switched based on the digital signal. A switch circuit S0-S9 corresponding to each bit for generating an analog voltage corresponding to the value of the digital signal at one end of the shunt resistor R19 corresponding to the most significant bit of the R-2R resistor network, The R-2R resistor network 1 has a capacitor C1 connected between the shunt resistor R19 corresponding to the most significant bit and the ground.
[Selection] Figure 1

Description

  The present invention relates to a D / A converter circuit and a liquid crystal driving device, and particularly suppresses the occurrence of glitches during DA conversion in an R-2R D / A converter circuit that converts an input digital signal into an analog signal. And a liquid crystal driving device using such a D / A converter circuit.

  Conventionally, an R-2R D / A converter circuit is a D / A converter that selects a gradation display voltage in accordance with gradation display data in a liquid crystal driving device such as a source driver circuit that drives a liquid crystal display unit. It is used as a circuit.

  Such an R-2R D / A converter circuit is generally well known, and FIG. 6 shows a specific circuit configuration of a 10-bit R-2R D / A converter circuit.

  The R-2R D / A converter circuit 200 corresponds to digital input nodes T0 to T9 to which data of each bit D0 to D9 (hereinafter also referred to as bit data) of a digital signal is input and each bit D0 to D9. And a pair of unit resistors (hereinafter simply referred to as resistors) R0a to R9a and R0b to R9b. In this D / A converter circuit 200, switch circuits S0 to S9 corresponding to the respective bits D0 to D9 of the digital signal are provided, and each switch circuit corresponds to the shunt resistor R10 to R19 corresponding to each bit data. Is configured to switch the potential at one end to either a power supply potential or a ground potential.

  Further, series resistors R0 and R00 are connected in series between the other end of the shunt resistor R10 corresponding to the least significant bit D0 and the ground. A series resistor R1 is connected between the other end of the shunt resistor R10 corresponding to the least significant bit D0 and the other end of the shunt resistor R11 corresponding to the next bit (second bit) D1. . Similarly, the other ends of the shunt resistors R11 to R18 corresponding to the respective bits from the second bit D1 to the bit D8 one bit lower than the most significant bit, and the respective bits from the third bit D2 to the most significant bit D9. Series resistors R2 to R9 are respectively connected between the other ends of the shunt resistors R12 to R19 corresponding to. Here, the resistors R0a to R9a and R0b to R9b and the series resistors R00 and R0 to R9 constituting the shunt resistors R10 to R19 constitute an R-2R resistor network 10, and the resistance value of each resistor is R Therefore, the resistance value of the shunt resistor consisting of a pair of series-connected resistors is 2R.

  The switch circuits S0 to S9 constitute a current path switching circuit 20 that switches a current path in the R-2R resistor network 10 based on the input digital signal. The R-2R resistor network 10 corresponds to the most significant bit D9 by switching the current path in the R-2R ladder resistor network 10 by the switch circuits S0 to S9 based on the input digital signal. An analog voltage corresponding to the value of the digital signal is generated at the other end (hereinafter also referred to as an analog output node) Nout of the shunt resistor R19.

  The operational amplifier 2 is connected to the output node Nout of the R-2R ladder resistor network 10, and the output signal of the operational amplifier 2 is output as an analog signal from the R-2R D / A converter circuit 200.

  FIG. 7 shows a specific circuit configuration of the switch circuit.

  For example, the switch circuit Sn corresponding to the nth bit of the digital signal is formed by connecting the PchMOS transistor 3a and the NchMOS transistor 4b in series between the power supply and the ground, and inverts the data of the corresponding bit. And a second inverter circuit 5b that inverts the output of the first inverter circuit 5a, in which a PchMOS transistor 3b and an NchMOS transistor 4b are connected in series between the power source and the ground. Each inverter circuit has a CMOS circuit configuration.

  Next, the operation will be described.

  In the D / A converter circuit 200 having such a configuration, when the data of each bit D0 to D9 of the digital signal is input to the digital input nodes T0 to T9, the switch circuits S0 to S9 change the value of each bit data. Accordingly, the potential at one end of the shunt resistors R10 to R19 is switched to a high level (VDD) or a low level (GND).

  For example, when the value of the input 10-bit digital signal (hereinafter also referred to as a digital input code) is (1000000000), one end of the shunt resistor R19 of the most significant bit is set to High level by the switch circuit S9, and the One ends of the shunt resistors R18 to R10 of bits other than the upper bits are set to the low level by the switch circuits S8 to S0. In this case, the resistance value between the power supply and the output node Nout is the resistance value (2R) by the shunt resistor R19 corresponding to the most significant bit, and the resistance between the output node Nout and the ground is R -2R resistance value (2R) due to resistances other than the shunt resistance R19 in the resistance network. Accordingly, 1 / 2VDD is output as the analog voltage DAOUT to the output node Nout of the R-2R resistor network 10, and this is output from the output terminal Tout of the D / A converter circuit as the analog signal AVOUT via the operational amplifier 2.

  When the value of the input 10-bit digital signal (digital input code) is (11000000), one end of the shunt resistor R9a of the most significant bit D9 and the shunt resistor R18 of the bit D8 that is one bit lower than the most significant bit Are switched to High level by the switch circuits S9 to S8, and one end of the other shunt resistors R17 to R10 is set to Low level by the switch circuits S7 to S0. As a result, the analog voltage DAOUT corresponding to the digital input code is output to the output node Nout of the R-2R resistor network 10 in the same manner as described above, and this is output as the analog signal AVOUT via the operational amplifier 2 in the D / A converter circuit. Output from the output terminal Tout.

  As described above, in the D / A converter circuit 200, a predetermined level among the levels obtained by dividing the power supply voltage VDD by 1024 (10 bits) according to the digital input code is output as the analog data (analog signal) VOUT.

  By the way, in the D / A converter circuit, when the digital input code changes, spike-like noise called a glitch that should not be generated appears in the converted analog signal.

  As this spike noise, the value of the most significant bit (MSB) is usually switched, that is, the digital input code is switched from (1000... 000) to (0111... 111) and vice versa. The largest thing occurs where is done.

  This is a switch circuit corresponding to a skew between bits at an input node to which a digital input code is inputted, a skew between bits at a node inside the D / A converter, and a bit within each D / A converter. It is known that this occurs due to a difference in ON and OFF times.

  For example, a switch circuit that switches the potential of one end of a shunt resistor corresponding to each bit in the R-2R resistor network 10 to either a high level or a low level according to an input digital signal is shown in FIG. In the case of a CMOS circuit configuration, it is necessary to make the ON resistances of the PchMOS transistor and the NchMOS transistor as small as possible and to make the ON resistance uniform for all bits. If this is not uniform, a skew occurs between the bits, or a time difference occurs when switching between the High level and the Low level, and a glitch occurs.

  A countermeasure for such a problem is disclosed in Patent Document 1, for example.

  As disclosed in Patent Document 1, in order to make the ON resistance of a MOS transistor ideally small enough to be ignored, it is necessary to increase the channel width of the MOS transistor, that is, to configure a transistor with a large area. However, this impairs the high integration and increases the gate capacitance of the MOS transistor, thereby impairing the speeding up of the changeover switch.

  Therefore, in this document, as a glitch reduction method, all the MOS transistors that switch the R-2R resistor network except the MOS transistor corresponding to the most significant bit MSB are connected to the gates of all the bit data stages. There is disclosed a circuit in which dummy gates are provided so as to have the same capacity, the ON / OFF speeds of all bits are made uniform, and glitches are reduced.

  However, in such a method disclosed in the literature, manufacturing variations of transistors are unavoidable, and a switching circuit composed of MOS transistors has a switching noise due to a through current due to simultaneous switching of a PchMOS transistor and an NchMOS transistor. A distortion occurs in the waveform for switching the -2R resistor network, which causes the skew between all bits and the ON / OFF speeds of the switch circuits corresponding to all the bits to become non-uniform, thereby causing a glitch.

Further, as described above, such an R-2R D / A converter circuit is used as a D / A converter circuit that selects a gradation display voltage in accordance with gradation display data in a source driver circuit. However, when such a liquid crystal driving device is used, the above-described waveform distortion may deteriorate the liquid crystal display quality.
JP-A-10-28056

  As described above, in the conventional D / A converter circuit, since it is difficult to switch the R-2R resistor network in an ideal state, when a digital signal for switching the most significant bit (MSB) is input, When the value of the digital signal, that is, the digital input code changes from (1000... 000) to (0111... 111) and vice versa, it is inevitable that the largest glitch occurs. .

  The present invention has been made to solve the above-described conventional problems. When a digital signal in which the most significant bit (MSB) is switched is input, the present invention is significant when the value of the most significant bit of the digital signal changes. It is an object of the present invention to obtain a D / A converter circuit capable of suppressing the occurrence of glitches and a liquid crystal driving device using the same.

  A D / A converter circuit according to the present invention is a D / A converter circuit that converts an input digital signal into an analog signal, and includes an R-2R ladder resistor including a plurality of resistors corresponding to each bit of the digital signal. And a current path switching circuit for switching a current path in the R-2R ladder resistor network so that an analog potential corresponding to the digital signal is generated at an output end of the R-2R ladder resistor network, The -2R ladder resistor network has a capacitor connected to a resistor corresponding to the most significant bit of the digital signal, thereby achieving the above object.

  In the present invention, the resistor corresponding to each bit of the digital signal is a shunt resistor composed of a pair of resistors connected in series, and the capacitor is connected to a resistance connection point in the shunt resistor corresponding to the most significant bit of the digital signal. It is preferable that they are connected.

  In the present invention, it is preferable that the pair of series-connected resistors constituting the shunt resistor have the same resistance value.

  In the present invention, the current path switching circuit includes a plurality of switch circuits corresponding to each bit of the digital signal, and each switch circuit connects one end of a shunt resistor corresponding to each bit of the digital signal to the digital signal. It is preferable to connect to either a power supply or ground according to each bit data of the signal.

  In the present invention, the switch circuit is formed by connecting a first conductivity type transistor and a second conductivity type transistor in series between a power supply and a ground, and a first inverter circuit that inverts corresponding bit data; It is preferable to have a second inverter circuit in which a first conductivity type transistor and a second conductivity type transistor are connected in series between the power source and the ground and invert the output of the first inverter circuit.

  In the present invention, it is preferable to have a capacitor connected to a resistance connection point in a shunt resistor corresponding to at least one bit other than the most significant bit of the digital signal.

  In the present invention, it is preferable that a capacitor is connected to a resistance connection point in the shunt resistor corresponding to the bit one bit lower than the most significant bit of the digital signal.

  In the present invention, the capacitor preferably uses a gate capacitance of a MOS transistor.

  In the present invention, the capacitor is preferably an MIM capacitor in which metal layers used for manufacturing an LSI are arranged on both sides of an insulating layer.

  In the present invention, the capacitor is preferably a capacitor having a polysilicon layer disposed on both sides of an insulating layer.

  The liquid crystal drive device according to the present invention is a liquid crystal drive device for driving a liquid crystal display unit, and as a drive circuit for supplying a drive voltage to the liquid crystal display unit based on a digital image signal, the D / D of the present invention described above. An A converter circuit is provided, thereby achieving the above object.

  With the above configuration, the operation of the present invention will be described below.

  In the present invention, an R-2R ladder resistor network including a plurality of resistors corresponding to each bit of the digital signal, and an analog voltage corresponding to the digital signal is generated at the output end of the R-2R ladder resistor network. Since the R-2R ladder resistor network includes a capacitor connected to a resistor corresponding to the most significant bit of the digital signal, the most significant bit (MSB) is switched. When a signal is input, the value corresponding to the most significant bit changes when the value of the digital signal changes from (1000... 000) to (0111... 111) and vice versa. Even if the current flowing through the capacitor changes, the capacitor connected to the resistor can alleviate the change in voltage due to this change in current. That.

  As a result, it is possible to suppress occurrence of a large glitch when the value of the digital signal changes from (1000... 000) to (0111... 111) and vice versa.

  In the present invention, the resistor corresponding to each bit of the digital signal is a shunt resistor comprising a pair of resistors connected in series, and the capacitor is connected to the resistor in the shunt resistor corresponding to the most significant bit of the digital signal. Since it is connected to the point, a CR filter is formed by the capacitor and the resistance of the R-2R resistor network, and glitch suppression can be effectively performed.

  In the present invention, not only a capacitor is connected to the connection point of the shunt resistor corresponding to the most significant bit of the digital signal but also the resistance of the shunt resistor corresponding to at least one bit other than the most significant bit. Since a capacitor is connected to the connection point, when a digital signal that switches bits other than the most significant bit (MSB) is input, the current flowing in the resistor corresponding to the bit changes when the value of the bit changes. Even so, the capacitor connected to this resistor can alleviate the change in voltage due to this change in current.

  According to the present invention, since the R-2R ladder resistor network constituting the D / A converter circuit has a capacitor connected to a resistor corresponding to the most significant bit of the digital signal, the most significant bit (MSB) When a digital signal to be switched is input to the D / A converter circuit, it is possible to suppress the occurrence of a large glitch when the value of the most significant bit of the digital signal changes.

  Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1)
FIG. 1 is a diagram for explaining a D / A converter circuit according to Embodiment 1 of the present invention, and shows a specific circuit configuration of a 10-bit R-2R D / A converter circuit.

  The D / A converter circuit 100 according to the first embodiment includes a part of the shunt resistor R19 corresponding to the most significant bit of the input digital signal in the R-2R resistor network 10 constituting the conventional D / A converter circuit. A capacitor C1 is connected to the ground.

  That is, the R-2R D / A converter circuit 100 according to the first embodiment inputs the data (hereinafter also referred to as bit data) of each bit D0 to D9 of the digital signal, as in the conventional D / A converter circuit 200. Digital input nodes T0 to T9 and shunt resistors R10 to R19 corresponding to each bit data. These shunt resistors 10 to R19 include a pair of series-connected resistors R0a to R9a and R0b to R9b. Also in this D / A converter circuit 100, switch circuits S0 to S9 corresponding to the respective bits D0 to D9 of the digital signal are provided, and each switch circuit has a corresponding shunt resistor in accordance with each bit data. Is configured to switch the potential at one end to either a power supply voltage or a ground potential. That is, the switch circuits S0 to S9 for switching the input nodes T0 to T9 corresponding to the respective bits between the high level and the low level are constituted by inverter circuits having a CMOS configuration as shown in FIG. When the data of bit Dn (n = 0 to 9) is at a high level (VDD), DOUTn (n = 0 to 9) is output at a high level, and each bit Dn (n = 0 to 9) of the input digital signal is output. When the data is at the low level (GND), the buffer circuit outputs the low level (GND).

  In the D / A converter circuit 100 of the first embodiment, the capacitor C1 is connected between the connection point of the pair of resistors R9a and R9b in the shunt resistor R19 corresponding to the most significant bit D9 and the ground. . Therefore, in the first embodiment, the resistors R0a to R9a and R0b to R9b, the series resistors R00, R0 to R9, and the capacitor C1 that constitute the shunt resistor constitute the R-2R resistor network 1, The resistance value of the resistor is R, and therefore the resistance value of the shunt resistor is 2R.

  Here, the capacitance value of the capacitor C1 is a capacitance value of about several hundreds of fF, and can be sufficiently created by the gate capacitance of the MOS transistor. Therefore, here, the capacitor C1 uses the gate capacitance of a MOS transistor. However, various types of capacitors can be used. For example, MIM (Metal-Insulated-Metal using a capacitance between metal wirings, in which metal layers used for manufacturing LSIs are arranged on both sides of an insulating layer. ) A capacitor having a structure, or a double polycapacitor using a capacitance between polysilicon wirings, in which a polysilicon layer is arranged on both sides of an insulating layer, may be used.

  The other configurations in the D / A converter circuit 100 of the first embodiment are the same as those in the conventional D / A converter circuit 200.

  Next, the operation will be described.

  When the digital signal is input to the D / A converter circuit 100, the D / A converter circuit 100 switches the corresponding switch circuits S0 to S9 according to the data of the bits D0 to D9 of the digital signal, The R-2R resistor network 1 is driven. Thereby, in the R-2R resistor network 1, a current path corresponding to the digital input code is formed, and an analog voltage corresponding to the value of the digital signal is generated at the output node Nout. This analog voltage is output as the DA conversion output AVOUT of the D / A converter circuit 100 via the operational amplifier 2 at the subsequent stage of the R-2R resistor network 1.

  Here, when a digital signal for switching the most significant bit (MSB) is input, when the digital input code changes from 511 (0111111111) to 512 (1000000000), the switch circuit S9 connects one end of the shunt resistor R19 to the ground potential. Switching from (Low level) to the power supply potential (High level), the other switch circuits S0 to S8 switch one end of the shunt resistors R10 to R18 from the power supply potential (High level) to the ground potential (Low level). On the other hand, when the digital input code changes from 512 (1000000000) to 511 (0111111111), the switch circuit S9 switches one end of the shunt resistor R19 from the power supply potential (High level) to the ground potential (Low level). The switch circuits S0 to S8 switch one end of the shunt resistors R10 to R18 from the ground potential (Low level) to the power supply potential (High level).

  FIG. 2 is a simulation of the occurrence of glitches at the time of switching the digital input code as described above under the following conditions. That is, the resistance value of each resistor constituting the 10-bit R-2R resistor network is R = 60 KΩ, the drive frequency of the D / A converter circuit is 3 MHz, and the power supply voltage is VDD = 5V.

  FIG. 2 shows a simulation of the state of occurrence of a glitch when the value of the capacitor C1 connected to the resistance connection point of the shunt resistor R19 is changed with the vertical axis representing voltage (v) and the horizontal axis representing time (usec). Is shown.

  Here, the value of the capacitor is sequentially changed to 0 fF, 50 fF, 100 fF, 150 fF, 175 fF, and 200 fF. It can be seen that at 100 fF, it is possible to suppress the glitch to about 1/2 before inserting the capacitor.

  As described above, according to the first embodiment, the capacitor C1 is connected between the resistance connection point of the shunt resistor R19 that is included in the R-2R resistor network 1 and driven by the data of the most significant bit (MSB) D9 and the ground. Therefore, when a digital signal that switches the most significant bit (MSB) is input, the value of the digital signal changes from (1000... 000) to (0111... 111). When the current flowing through the shunt resistor corresponding to the most significant bit changes, the change in voltage due to the change in current is alleviated by the capacitor connected to the shunt resistor. As a result, it is possible to suppress the occurrence of a large glitch when a digital input code for switching the most significant bit (MSB) is input.

  In this embodiment, since the capacitor C1 is connected to the connection point of the pair of resistors R9a and R9b in the shunt resistor corresponding to the most significant bit of the digital signal, the CR due to the capacitor C1 and the resistance of the R-2R resistor network is used. A filter is formed, and glitch suppression can be effectively performed.

In the first embodiment, the capacitor C1 is inserted between the connection point of the pair of resistors R9a and R9b constituting the shunt resistor R19 and the ground, but this capacitor C1 is the resistance of the resistor R9a in the shunt resistor R19. It may be inserted between one end on the side opposite to the connection point with R9b and the ground, or between one end on the side opposite to the connection point with the resistor R9a of the resistor R9b in the shunt resistor R19 and the ground.
(Embodiment 2)
FIG. 3 is a diagram for explaining a D / A converter circuit according to Embodiment 2 of the present invention, and shows a specific circuit configuration of a 10-bit R-2R D / A converter circuit.

  The D / A converter circuit 100a according to the second embodiment has a bit lower than the most significant bit of the input digital signal in the R-2R resistor network 1 constituting the D / A converter circuit 100 of the first embodiment. A capacitor C2 is further connected between a part of the corresponding shunt resistor R18 and the ground.

  That is, in the D / A converter circuit 100a of the second embodiment, the capacitor C1 is connected between the connection point of the pair of resistors R9a and R9b of the shunt resistor R19 corresponding to the most significant bit D9 and the most significant bit. A capacitor C2 is connected between the connection point of the pair of resistors R8a and R8b of the shunt resistor R18 corresponding to the bit D8 that is one level below and the ground. Therefore, in the second embodiment, the resistors R0a to R9a and R0b to R9b, the series resistors R00, R0 to R9, and the capacitors C1 and C2 constituting the shunt resistors R10 to R19 constitute the R-2R resistor network 1a. The resistance value of each resistor is R, and therefore the resistance value of the shunt resistor is 2R. The other configurations in the D / A converter circuit 100a of the second embodiment are the same as those in the conventional D / A converter circuit 200.

  Next, the operation will be described.

  Also in the D / A converter circuit 100a of the second embodiment, when a digital signal is input to the D / A converter circuit 100a, the D / A converter circuit 100a responds to the data of each bit D0 to D9 of the digital signal. Accordingly, the corresponding switch circuits S0 to S9 drive the R-2R resistor network 1a. As a result, an analog voltage corresponding to the value of the digital signal is generated at the output node Nout of the R-2R resistor network 1a, and this analog voltage is output from the DA conversion output of the D / A converter circuit 100 via the operational amplifier 2. Output as AVOUT.

  Here, when a digital signal in which data of one bit lower than the most significant bit (MSB) is switched is input, when the digital input code changes from 255 (0011111111) to 256 (0100000000000), the switch circuit S8 One end of the shunt resistor R18 is switched from the ground potential (Low level) to the power supply potential (High level), and the switch circuits S0 to S7 switch one end of the shunt resistors R10 to R17 from the power supply potential (High level) to the ground potential (Low level). Switch. At this time, switching of the switch circuit S9 is not performed, and one end of the shunt resistor R19 remains at the ground potential. On the other hand, when the digital input code changes from 256 (0100000000000) to 255 (0011111111), the switch circuit S8 switches one end of the shunt resistor R18 from the power supply potential (High level) to the ground potential (Low level), and the switch circuit S0. To S7 switch one end of the shunt resistors R10 to R17 from the ground potential (Low level) to the power supply potential (High level). Also at this time, switching of the switch circuit S9 is not performed, and one end of the shunt resistor R19 remains at the ground potential.

  FIG. 4 shows a simulation result of the occurrence of glitches at the time of switching the digital input code as described above (switching between 255 and 256), as in the first embodiment.

  However, in the simulation shown in FIG. 4, the value of the capacitor C1 corresponding to the most significant bit is fixed to 150 fF, and the value of the capacitor C2 corresponding to the bit immediately below the most significant bit is set to 0 fF, 50 fF, 100 fF, and 150 fF. 175 fF and 200 fF are sequentially changed. It can be seen that at 100 fF, the glitch can be suppressed to about ½ or less before the capacitor is inserted.

  Further, when a digital signal in which data of the bit one bit lower than the most significant bit (MSB) is switched is input, when the digital input code changes from 767 (1011111111) to 768 (1100000), the switch circuit S8 is shunted. One end of the resistor R18 is switched from the ground potential (Low level) to the power supply potential (High level), and the switch circuits S0 to S7 switch one end of the shunt resistors R10 to R17 from the power supply potential to the ground potential. At this time, switching of the switch circuit S9 is not performed, and one end of the shunt resistor R19 remains at the power supply potential. On the other hand, when the digital input code changes from 768 (11100000000) to 767 (1011111111), the switch circuit S8 switches one end of the shunt resistor R18 from the power supply potential (High level) to the ground potential (Low level), and the switch circuit S0. To S7 switch one end of the shunt resistors R10 to R17 from the ground potential (Low level) to the power supply potential (High level). Also at this time, switching of the switch circuit S9 is not performed, and one end of the shunt resistor R19 remains at the power supply potential.

  FIG. 5 shows a simulation of the occurrence of glitches at the time of switching the digital input code as described above (switching between 767 and 768), as in the first embodiment.

  However, in the simulation shown in FIG. 5, the value of the capacitor C1 corresponding to the most significant bit is fixed to 150 fF, and the value of the capacitor C2 corresponding to the bit immediately below the most significant bit is set to 0 fF, 50 fF, 100 fF, and 150 fF. 175 fF and 200 fF are sequentially changed. It can be seen that at 100 fF, the glitch can be suppressed to about ½ or less before the capacitor C2 is inserted.

  Thus, by inserting both the capacitor C1 and the capacitor C2 into the R-2R resistor network, a CR filter is formed by these capacitors and the resistance R of the R-2R resistor network, the glitch is filtered, and the glitch is suppressed. An effect is obtained.

  As described above, in the second embodiment, the capacitor C1 is inserted between the resistance connection point of the shunt resistor R19 corresponding to the most significant bit and the ground, and the shunt resistor R18 corresponding to the bit one bit lower than the most significant bit. Since the capacitor C2 is inserted between the resistance connection point and the ground, it is possible to further suppress the generation amount of glitches.

  In the above embodiment, in the R-2R resistor network, the shunt resistor corresponding to the most significant bit is connected to the capacitor C1, or the shunt resistor corresponding to the most significant bit and the bit one bit lower than the most significant bit. Although the capacitors C1 and C2 are connected to both of the corresponding shunt resistors, among the shunt resistors corresponding to the bits other than the most significant bit, the shunt resistor connecting the capacitor is two lower than the most significant bit. Any shunt resistor corresponding to a bit between the bit and the least significant bit may be used. The connection of such a capacitor means that in addition to the shunt resistor corresponding to the most significant bit, whether the capacitor is added to the shunt resistor corresponding to any bit other than the most significant bit depends on the resistance value of R-2R or What is necessary is just to determine suitably according to the drive capability of the switch which drives R-2R resistance network.

  Although not specifically described in the first and second embodiments, the liquid crystal driving device using the D / A converter circuit of the first and second embodiments includes a liquid crystal display device such as a mobile phone device or a personal computer. It can be used with electronic information devices such as computers.

  For example, an electronic information device according to a further embodiment of the present invention uses at least one of the D / A converter circuits of the above-described first and second embodiments of the present invention, and a liquid crystal display constituting the electronic information device. The liquid crystal driving device for driving the unit includes at least one of the D / A converter circuits of the first and second embodiments of the present invention described above. By using the D / A converter circuit in a liquid crystal driving device that drives a liquid crystal display unit of such an electronic information device, the quality of a display image can be improved.

  Needless to say, the D / A converter circuit of the present invention can also be used in a semiconductor LSI other than the liquid crystal driving device.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments of the present invention. It is understood that the patent documents cited in the present specification should be incorporated by reference into the present specification in the same manner as the content itself is specifically described in the present specification.

  The present invention relates to an R-2R type D / A converter circuit for converting an input digital signal into an analog signal, and an R-2R resistor network in the field of a liquid crystal driving device using such a D / A converter circuit. By connecting a capacitor to the shunt resistor driven by the most significant bit (MSB) data, it is possible to suppress the occurrence of glitches during DA conversion.

FIG. 1 is a diagram illustrating a D / A converter circuit according to Embodiment 1 of the present invention. FIG. 2 is a diagram for explaining the analog output waveform of the D / A converter circuit of the first embodiment, and the waveform when the digital input code changes from 511 (0111111111) to 512 (1000000000) and vice versa. The waveform when a change occurs is shown. FIG. 3 is a diagram illustrating a D / A converter circuit according to Embodiment 2 of the present invention. FIG. 4 is a diagram for explaining an analog output waveform of the D / A converter circuit according to the second embodiment. The waveform when the digital input code changes from 255 (0011111111) to 256 (01000000) and vice versa. The waveform when a change occurs is shown. FIG. 5 is a diagram for explaining an analog output waveform of the D / A converter circuit according to the second embodiment. The waveform when the digital input code changes from 767 (1011111111) to 768 (11100000000) and vice versa. The waveform when a change occurs is shown. FIG. 6 is a diagram illustrating a conventional R-2R D / A converter circuit. FIG. 7 is a diagram showing a configuration of a conventional D / A converter circuit and a switch circuit constituting the D / A converter circuit according to Embodiments 1 and 2 of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,1a R-2R resistance network 2 Operational amplifier 3a, 3b PchMOS transistor 4a, 4b NchMOS transistor 5a, 5b 1st, 2nd inverter circuit 20 Current path switching circuit 100, 100a R-2R system D / A converter circuit C1, C2 capacitor Nout output node R1-R9 series resistance R10-R19 shunt resistance R0a-R9a, R0b-R9b resistance S0-S9, Sn switch circuit T0-T9 input node Tout output terminal

Claims (11)

A D / A converter circuit for converting an input digital signal into an analog signal,
An R-2R ladder resistor network including a plurality of resistors corresponding to each bit of the digital signal;
A current path switching circuit that switches a current path in the R-2R ladder resistor network so that an analog voltage corresponding to the digital signal is generated at an output terminal of the R-2R ladder resistor network;
The R-2R ladder resistor network is a D / A converter circuit having a capacitor connected to a resistor corresponding to the most significant bit of the digital signal. The resistor corresponding to each bit of the digital signal is a shunt resistor consisting of a pair of resistors connected in series,
The D / A converter circuit according to claim 1, wherein the capacitor is connected to a resistance connection point in a shunt resistor corresponding to the most significant bit of the digital signal.   3. The D / A converter circuit according to claim 2, wherein the pair of series-connected resistors constituting the shunt resistor have the same resistance value. The current path switching circuit includes a plurality of switch circuits corresponding to each bit of the digital signal,
4. The D / D according to claim 2, wherein each switch circuit connects one end of a shunt resistor corresponding to each bit of the digital signal to either a power supply or ground according to each bit data of the digital signal. A converter circuit.   The switch circuit is formed by connecting a first conductivity type transistor and a second conductivity type transistor in series between a power source and a ground, a first inverter circuit for inverting the corresponding bit data, a power source and a ground, 5. A D / A according to claim 4, further comprising: a second inverter circuit configured by connecting a first conductivity type transistor and a second conductivity type transistor in series, and inverting an output of the first inverter circuit. Converter circuit.   4. The D / A converter circuit according to claim 2, further comprising a capacitor connected to a resistance connection point in a shunt resistor corresponding to at least one bit other than the most significant bit of the digital signal.   The D / A converter circuit according to claim 6, wherein a capacitor is connected to a resistance connection point in a shunt resistor corresponding to a bit one bit lower than the most significant bit of the digital signal.   8. The D / A converter circuit according to claim 1, wherein the capacitor uses a gate capacitance of a MOS transistor.   8. The D / A converter circuit according to claim 1, wherein the capacitor is a MIM capacitor in which metal layers used for manufacturing an LSI are arranged on both sides of an insulating layer.   8. The D / A converter circuit according to claim 1, wherein the capacitor is a capacitor in which a polysilicon layer is disposed on both sides of an insulating layer. A liquid crystal driving device for driving a liquid crystal display unit,
11. A liquid crystal driving device having the D / A converter circuit according to claim 1 as a driving circuit for supplying a driving voltage to the liquid crystal display unit based on a digital image signal.

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