JP2008235699A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

An object of the present invention is to provide a highly reliable semiconductor device and a method for manufacturing the same, which can effectively suppress the occurrence of peeling between a pad and a resin in a flip chip connecting portion.
A first resin layer is formed on a semiconductor chip, a wiring is formed on the first resin layer, and is electrically connected to an electrode of the semiconductor chip. Of these, the first wiring layer 13a, which is a high-purity copper layer, is formed on the first resin layer 12 without sputtering with a dissimilar metal, and the second wiring layer 13b is formed by copper electroplating. To do. After the wiring 13 is formed, heat treatment is performed at a temperature of 200 ° C. or higher. Solder balls 15 serving as bumps for flip chip connection are formed on flip chip pads 14 included in the wiring 13.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device and a manufacturing method thereof in which a flip chip connecting portion excellent in reliability can be obtained.

  Semiconductor elements such as LSI (Large Scale Integrated Circuit) are formed on the surface of a semiconductor chip or wafer made of silicon or the like. These semiconductor chips and the like are subjected to a heat cycle of heating / cooling by, for example, melting of solder in a flip chip connection, a heat cycle test, and heat generation from the semiconductor element.

  At this time, thermal stress is generated at the connection portion between the semiconductor chip and the mounting substrate due to the difference in thermal expansion coefficient between different materials used respectively. For example, many substrates on which semiconductor elements are mounted are made of an organic material such as a resin or a composite material such as FR-4 having a resin or the like as a constituent material. Its thermal expansion coefficient (linear expansion coefficient) is 10 to several tens of ppm / K, which is considerably larger than about 4 ppm / K of silicon. This thermal stress acts on, for example, the pad-resin interface of the flip chip connecting portion, and when the thermal stress increases, peeling at the interface is caused.

  As a method of relieving such thermal stress, various studies have been conventionally made on providing a semiconductor device with a structure that relieves stress. For example, Patent Document 1 discloses a structure in which a resin layer is provided between a semiconductor chip and electrodes such as bumps. FIG. 3 is a cross-sectional view showing a conventional semiconductor device of Patent Document 1. In FIG.

  As shown in FIG. 3, a passivation film 103 is formed on the semiconductor element 101, and a first resin layer 104 is further formed. The wiring 106 is formed so that a part thereof is on the first resin layer 104, and is electrically connected to the semiconductor element electrode unit 102 through the passivation film 103 and the opening 108 provided in the first resin layer 104. It is connected. Further, the wiring 106 is formed so that a plurality of plane portions form a predetermined angle 109 with each other in accordance with the shape of the opening 108. The package electrode 107 is formed on the planar portion of the wiring 106 formed on the first resin layer 104. The second resin layer 105 is formed so as to cover the wiring 106 and the like except for a part of the package electrode 107. The conventional semiconductor device configured in this manner mainly includes resin because the first resin layer 104, the second resin layer 105, and the wiring 106 are appropriately deformed with respect to the thermal cycle applied to the semiconductor device. It is intended to relieve the thermal stress generated due to the difference in thermal expansion coefficient between the layer and the semiconductor chip.

JP 2000-323628 A

  However, the conventional semiconductor device described above has the following problems. Thermal distortion of the semiconductor device due to heating / cooling increases in proportion to the distance from the center of the semiconductor chip. For this reason, when the semiconductor chip is large, the semiconductor chip and the resin layer and the like cause a large displacement of about several tens to 100 μm in terms of calculation at the end of the semiconductor chip. If the displacement, in other words, the stress becomes large, the stress cannot be alleviated by the above-described stress relaxation structure alone. Therefore, between the pad and the resin (between the wiring 106 and the first resin layer 104 in FIG. 3). ) Has a problem that peeling occurs.

  This peeling between the pad and the resin does not directly cause an electrical disconnection, but when peeling occurs between the pad and the resin after filling with the underfill resin, a closed space is formed there. This closed space causes cracks in the resin layer or the like during the subsequent heat treatment when soldering, for example, the semiconductor chip to the substrate. In particular, moisture is accumulated in this closed space in a high humidity state, and cracks may be generated in the substrate or the like due to stress generated by the moisture being vaporized by the subsequent heat treatment. Furthermore, the generated peeling progresses with time due to the application of a thermal cycle, which causes a decrease in the reliability of the semiconductor element. In addition, these peeling and closed spaces are observed by SAT (Scan Acoustic Tomograph).

  On the other hand, when a wiring or pad is formed on a resin such as polyimide, in order to prevent peeling between the resin and the wiring or pad, chromium (Cr) or titanium (Ti) or the like is provided between the wiring or pad and the resin layer. A method of interposing an adhesive metal is known. However, for example, chromium is not preferable from the viewpoint of environmental load and the like, and titanium has a problem that the adhesive strength is reduced by a curing process of a resin layer provided on the upper layer of the wiring or the pad or a heating process such as soldering.

  The present invention has been made in view of such a problem, and can effectively suppress the occurrence of peeling between the wiring or pad of the flip chip connecting portion and the resin, and has excellent reliability. And it aims at providing the manufacturing method.

  A semiconductor device according to the present invention includes a semiconductor chip, a first resin layer formed on the semiconductor chip, and at least a part of the first resin layer formed on the first resin layer and provided on the semiconductor chip. A plurality of layers of wirings that are electrically connected to the electrodes of the first layer and the surface of the wirings formed on the first resin layer, either directly or via a pad, are flip-chip connected to the outside. And the first and second wiring layers are composed mainly of copper in order from the side in contact with the first resin layer in the plurality of wiring layers, and the first wiring layer Is formed without interposing a layer mainly containing a metal other than copper between the first resin layer, and the purity of copper is higher than that of the second wiring layer. To do.

  In the present invention, the wiring formed on the first resin layer formed on the semiconductor chip is composed of a plurality of layers including the first and second wiring layers mainly composed of copper. Further, the first wiring layer having a high copper purity is formed on the first resin layer without using a layer mainly composed of a different metal. Thereby, the adhesive strength between the dissimilar metal layer used for the seed layer and the first resin layer is not lowered by the heat treatment during the manufacturing process of the semiconductor device. For this reason, it is possible to prevent the wiring (including the pad) and the first resin layer from being peeled off, and to obtain a semiconductor device having a highly reliable flip chip connecting portion. Further, by forming a structure that relaxes thermal stress and the like by the first wiring layer and the first resin layer, the occurrence of peeling can be more effectively prevented. Furthermore, by providing the second wiring layer having a copper purity lower than that of the first resin layer, the wiring layer can be formed more efficiently while obtaining the effect on the adhesive strength. In the present specification, “having copper as a main component” means that the ratio (purity) of a copper element in a material is 50% by mass or more, and is formed by electroplating or electroless plating of copper. Including material that can.

  In this case, the first wiring layer may be formed by a sputtering method, and the second wiring layer may be formed by a plating method.

  Further, it is preferable that the first resin layer and the first wiring layer are heat-treated at a temperature of 200 ° C. or higher after the formation of the first wiring layer. Thereby, since the adhesive strength between the first wiring layer and the first resin layer can be further increased, the reliability of the semiconductor device can be further improved.

  Furthermore, the first resin layer can contain a polyimide resin as a main component.

  Furthermore, you may have the 2nd resin layer formed so that at least one part of the said wiring might be covered. In this case, the second resin layer can contain a polyimide resin as a main component.

  The method for manufacturing a semiconductor device according to the present invention includes a step of forming a first resin layer on a semiconductor chip, and first and second wirings containing copper as a main component in order from the side in contact with the first resin layer. Forming a plurality of wiring layers including a layer so that a part of the wiring is formed on the first resin layer and electrically connected to a first electrode provided on the semiconductor chip; Forming a second electrode directly or via a pad on the surface of the wiring formed on the first resin layer, the first wiring layer being the first resin layer. Without interposing a layer containing a metal other than copper as a main component, the purity of copper is higher than that of the second wiring layer, and the first resin layer and A heat treatment is performed at a temperature of 200 ° C. or higher after forming the first wiring layer.

  In this case, the first wiring layer may be formed by a sputtering method, and the second wiring layer may be formed by a plating method. Thereby, a high purity copper layer reflecting the copper purity of the sputtering target can be formed as the first wiring layer. Further, since the sputtering is performed in a vacuum, the first wiring layer can be formed without forming a copper oxide film that causes a decrease in adhesive strength. Furthermore, by forming the second wiring layer by a plating method, it is possible to efficiently form the wiring layer while obtaining the effect of adhesive strength.

  Furthermore, it is good also as having the process of forming a 2nd resin layer so that a part of said wiring may be covered, and the curing process with respect to the said 2nd resin layer. In this case, the heat treatment can be performed by a curing process for the second resin layer. Thereby, in order to raise the adhesive strength of a 1st semiconductor layer and a 1st resin layer, an adhesive strength can be raised efficiently, without providing another heat processing process.

  ADVANTAGE OF THE INVENTION According to this invention, generation | occurrence | production of peeling between the wiring or pad of a flip chip connection part, and resin can be suppressed effectively, and the semiconductor device excellent in reliability is obtained.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. First, a first embodiment of the present invention will be described. FIG. 1A is a cross-sectional view showing the semiconductor device according to the first embodiment, and FIG. 1B is a plan view showing the wiring 13 and the flip chip pad 14. FIG. 1 is an enlarged view of only one of a plurality of flip chip connecting portions formed between the semiconductor chip and the substrate.

  As shown in FIG. 1, a first resin layer 12 is formed on the surface of the semiconductor chip 11. For example, a polyimide resin is used as the first resin layer 12. A wiring 13 is formed on the surface of the first resin layer 12 and its opening. The wiring 13 is formed so that a plurality of plane portions form a predetermined angle with each other in accordance with the shape of the opening provided in the first resin layer 12, and is electrically connected to an electrode of the semiconductor chip 11 (not shown). Has been. The first resin layer 12 and the wiring 13 constitute a so-called stress relaxation structure which will be described later. A part of the plane portion formed on the surface of the first resin layer 12 in the wiring 13 is a flip chip pad 14. On the flip chip pad 14, there are provided solder balls 15 to be bumps when flip chip connecting to a substrate (not shown).

  The wiring 13 is configured by laminating a first wiring layer 13a and a second wiring layer 13b, which are mainly composed of copper and have different copper purity. Among these, the 1st wiring layer 13a which contact | connects the 1st resin layer 12 has a copper purity higher than the 2nd wiring layer 13b formed on it. In addition, after the wiring 13 is formed on the first resin layer 12, heat treatment is performed at a temperature of 200 ° C. or higher.

  As described above, a heating / cooling thermal cycle is applied to a semiconductor device for various reasons during manufacturing, testing, and use. At this time, thermal stress is generated based on the difference in thermal expansion coefficient between the semiconductor chip or the silicon substrate or the like and the resin or the like. When this thermal stress increases, for example, peeling occurs between the wiring 13 (and flip chip pad 14) shown in FIG. 1 and the first resin layer 12, and the peeling progresses with time, and the reliability of the semiconductor device is increased. Cause a decline in sex.

  In normal flip chip connection, since the flip chip pad 14 is formed directly on the chip 11, the thermal stress caused by the difference in thermal expansion coefficient between the flip chip connected substrate and the chip is directly applied to the semiconductor chip. Applied. However, in the stress relaxation structure shown in FIG. 1, the wiring 13 is provided between the electrode (solder ball 15) such as a bump flip-chip connected to the electrode on the substrate side and the electrode provided on the semiconductor chip 11. Yes. Since the wiring 13 has a plurality of plane portions having a predetermined angle, the thermal stress due to the thermal cycle applied to the semiconductor device is alleviated when the wiring 13 is appropriately deformed. In addition, since the first resin layer 12 is provided between the flip chip connecting portion including the wiring 13 and the semiconductor chip 11, the first resin layer 12 is appropriately deformed due to thermal strain. Also relieves stress. Thereby, since the stress applied to the semiconductor chip 11 becomes small, it is possible to prevent the semiconductor chip 11 and the like from being broken. This is particularly effective when a low-k (low dielectric constant) material having a relatively low mechanical strength is used for a semiconductor chip or the like. In addition to the polyimide resin, various types can be used as the first resin layer 12. From the viewpoint that the resin is easily deformed by stress, a resin having a low elastic modulus is desirable, but from the viewpoint of efficiently dispersing thermal strain and suppressing the influence on the semiconductor chip 11, a resin having a slightly high elastic modulus. Is desirable.

  However, when the thermal strain increases, for example, when the chip is large, even if the stress relaxation structure shown in FIG. 1 is provided, peeling or the like may occur between the wiring or pad and the resin layer. In a conventional semiconductor device, for example, when a wiring or a pad is formed by an additive method, Ti or the like is first formed as a seed layer on a resin layer, and then a copper wiring layer is formed by plating or the like. As described above, when Ti or the like is interposed between the copper and the resin layer, the adhesive strength between the Ti and the resin layer is reduced by heating in the subsequent process. For this reason, it is thought that there was a case where the effect of the stress relaxation structure could not be sufficiently exhibited.

  In the semiconductor device of the present embodiment, the first wiring layer 13a having a high copper purity is formed by sputtering without interposing a dissimilar metal layer such as Ti on the surface of the resin layer. A second wiring layer 13b mainly composed of copper is formed thereon by electroplating. As a result, the adhesive strength with the first resin layer 12 does not decrease due to the heat treatment during the manufacturing process of the semiconductor device as in the case where the dissimilar metal layer is provided. Furthermore, by performing heat treatment at a temperature of 200 ° C. or higher, the adhesive strength between the first wiring layer 13a and the first resin layer 12 can be increased. This is based on the experimental result that the adhesive strength between the copper layer and the resin layer is increased by performing the heat treatment at a temperature of 200 ° C. or higher. In addition, the details of the mechanism by which the adhesive strength is improved at such a high temperature are not clear. For example, with respect to a polyimide resin (including a polymer having a polyimide bond) used as the first resin layer 12, the polyimide polar group (such as a carboxylic acid group and an amide group) and copper undergo some reaction upon heating. It is considered that the adhesive strength increases. In this embodiment, copper is oxidized at the interface between the first wiring layer 13a and the first resin layer 12 in order to perform heat treatment after the wiring 13 is formed on the first resin layer 12. There is nothing. This is considered to contribute to the improvement of the adhesive strength by heat treatment. Note that it is not desirable that the copper on the side not in contact with the resin layer is oxidized, so that the heat treatment after the formation of the wiring 13 is preferably performed under a condition in which an oxidation reaction such as a nitrogen atmosphere hardly occurs.

  Such an effect of improving the adhesive strength is considered to be greater when the copper purity of the wiring layer in contact with the resin layer is higher. For this reason, it is preferable to form the first wiring layer 13a having a high copper purity by sputtering. As for the heat treatment temperature, the higher the temperature, the higher the adhesive strength. More specifically, when the temperature of the heat treatment is lower than 200 ° C., the adhesive strength is hardly improved. On the other hand, when the heat treatment temperature is 200 ° C. or higher, the adhesive strength increases as the temperature rises. When the temperature of the heat treatment is 250 ° C. or higher, and further 300 ° C. or higher, the adhesive strength can be further increased.

  Further, as will be described later, the wiring 13 has a two-layer structure of a first wiring layer 13a by sputtering and a second wiring layer 13b by plating or the like, so that copper can be efficiently obtained while obtaining the effect of improving the adhesive strength. The wiring layer can be formed. As described above, according to the present embodiment, the adhesive strength between the copper wiring layer and the resin layer can be effectively improved, and the flip chip is more reliable by being used in combination with the stress relaxation structure. A semiconductor device having a connection portion can be obtained.

  In addition, in this embodiment shown in FIG. 1, although an example of what is called a stress relaxation structure is shown, this invention is not limited to this. For example, the wiring shape may be formed in a curved or corrugated shape, and other known stress relaxation structures may be applied. In addition, according to the present invention, the present invention may be applied to a wiring structure that is not configured as a stress relaxation structure because it has high adhesive strength in the relationship between the wiring layer and the resin layer.

  In the present embodiment shown in FIG. 1, the wiring 13 has a two-layer structure of a first wiring layer 13a and a second wiring layer 13b. However, the wiring 13 can also be configured as a multilayer structure.

  Furthermore, in this embodiment shown in FIG. 1, the solder ball 15 is configured as a flip-chip connection bump, but the present invention is not limited to this. For example, a bump such as a printed bump or a gold bump may be used.

  A method for manufacturing the semiconductor device of this embodiment shown in FIG. 1 will be described below. First, as shown in FIG. 1A, the first resin layer 12 is formed on the semiconductor chip 11. At this time, an opening is formed by photolithography or the like so that the electrode of the semiconductor chip 11 (not shown) is exposed. The opening has a tapered shape such that the planar portions of the wiring 13 formed in a later process form a predetermined obtuse angle, for example.

  Next, the wiring 13 for electrically connecting the electrode of the semiconductor chip 11 and the solder ball 15 formed in a later process is formed. Here, first, the first wiring layer 13a is formed by sputtering copper. At this time, since sputtering is performed in a vacuum, a high-purity copper layer reflecting the copper purity of the sputtering target can be formed, and a copper oxide film that causes a decrease in adhesive strength with the resin layer is not generated. . Thereafter, a copper layer to be the second wiring layer 13b is further formed by electrolytic plating, and the wiring 13 is formed by etching. The wiring 13 is formed so as to include a flip chip pad 14 as shown in FIG.

  Next, heat treatment is performed on the semiconductor device formed up to the wiring 13 at a temperature of, for example, 200 ° C. or higher. Thereby, the adhesive strength between the 1st resin layer 12 and the 1st wiring layer 13a which is a high purity copper layer becomes high. The heat treatment may also serve as a heat treatment for a resin layer (not shown), for example. Further, the temperature during the heat treatment is preferably higher than 200 ° C. for the purpose of increasing the adhesive strength between the first resin layer 12 and the first wiring layer 13a, for example, 250 ° C., more preferably 300 ° C. or more. .

  Next, solder balls 15 are formed on the flip chip pad 14. The solder balls 15 become bumps when they are flip-chip connected to the electrodes on the mounting board side. Thereby, the semiconductor device shown in FIG. 1 is obtained.

  Next, a second embodiment of the present invention will be described. FIG. 2 is a configuration diagram showing the semiconductor device of the second embodiment. 2 is the same as that of the first embodiment except for the matters described below. In FIG. 2, the same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 2, in the semiconductor device of this embodiment, a second resin layer 16 is formed so as to cover the first resin layer 12 and the wiring 13. A flip chip pad 14 is formed on the wiring 13 through an opening provided in the second resin layer 16. The solder ball 15 is formed on the flip chip pad 14. As the second resin layer 16, for example, a polyimide resin is used. Other configurations are the same as those in the first embodiment.

  The second resin layer 16 that is the upper resin layer has an effect of protecting the wiring from the outside, and also functions as a solder resist that prevents the solder from adhering to other portions than the necessary portion of the pad portion. It is. The second resin layer 16 is formed by performing a curing (thermosetting) process after spin coating or dry film lamination, and this curing process corresponds to the heat treatment described above. For example, in the case of polyimide of the second resin layer 16, the curing process is usually performed at a temperature of 250 ° C. or higher. Further, depending on the type of polyimide, heat treatment at 300 ° C. or higher may be required. Thereby, the adhesive strength between the first wiring layer 13a and the first resin layer 12 can be improved, and a highly reliable semiconductor device can be obtained as in the first embodiment.

  The present invention can be suitably used for, for example, a semiconductor device having a semiconductor chip mounted on a substrate by flip chip connection.

(A) is sectional drawing which shows the semiconductor device which concerns on the 1st Embodiment of this invention, (b) is a top view which shows the wiring 13 and the flip-chip pad 14. In FIG. (A) is sectional drawing which shows the semiconductor device which concerns on the 2nd Embodiment of this invention, (b) is a top view which shows the wiring 13 and the flip-chip pad 14. In FIG. It is sectional drawing which shows the conventional semiconductor device.

Explanation of symbols

11; Semiconductor chip 12; First resin layer 13; Wiring 14; Flip chip pad 15; Solder ball 16; Second resin layer 101; Semiconductor element 102; Semiconductor element electrode portion 103; Passivation film 104; Layer 105; second resin layer 106; wiring 107; package electrode 108; opening 109; predetermined angle

Claims (12)

A semiconductor chip, a first resin layer formed on the semiconductor chip, and at least part of the semiconductor chip is electrically connected to a first electrode provided on the semiconductor chip formed on the first resin layer. And a second electrode formed on the surface of the wiring formed on the first resin layer directly or via a pad and flip-chip connected to the outside. The first and second wiring layers are both composed mainly of copper in order from the side in contact with the first resin layer in the plurality of layers of wiring, and the first wiring layer is formed of the first resin layer. A semiconductor device, characterized in that the copper layer has a higher purity than that of the second wiring layer, with a layer containing a metal other than copper as a main component interposed therebetween. The semiconductor device according to claim 1, wherein the first wiring layer is formed by a sputtering method, and the second wiring layer is formed by a plating method. 3. The semiconductor device according to claim 1, wherein the first resin layer and the first wiring layer are heat-treated at a temperature of 200 ° C. or higher after the formation of the first wiring layer. The semiconductor device according to claim 1, wherein the first resin layer contains a polyimide resin as a main component. 5. The semiconductor device according to claim 1, further comprising a second resin layer formed so as to cover at least a part of the wiring. 6. The semiconductor device according to claim 5, wherein the second resin layer contains a polyimide resin as a main component. A step of forming a first resin layer on a semiconductor chip, and a plurality of wiring layers including first and second wiring layers mainly composed of copper in order from the side in contact with the first resin layer. Forming a portion on the first resin layer so as to be electrically connected to a first electrode provided on the semiconductor chip, and forming the portion on the first resin layer Forming a second electrode directly on the surface of the wiring or via a pad, and a metal other than copper as a main component between the first wiring layer and the first resin layer The copper purity is higher than the copper purity of the second wiring layer without any intervening layer, and 200 ° C. after the first resin layer and the first wiring layer are formed. A method for manufacturing a semiconductor device, wherein heat treatment is performed at the above temperature. The method of manufacturing a semiconductor device according to claim 7, wherein the first wiring layer is formed by a sputtering method, and the second wiring layer is formed by a plating method. The method for manufacturing a semiconductor device according to claim 7, wherein the first resin layer contains a polyimide resin as a main component. 10. The method according to claim 7, further comprising a step of forming a second resin layer so as to cover a part of the wiring, and a curing step for the second resin layer. The manufacturing method of the semiconductor device as described in 2 .. The method of manufacturing a semiconductor device according to claim 10, wherein the heat treatment is performed by a curing process for the second resin layer. The method of manufacturing a semiconductor device according to claim 10, wherein the second resin layer contains a polyimide resin as a main component.

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