JP2008234110A - Semiconductor integrated circuit design method and design apparatus therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve stable power supply to raise reliability of operation. <P>SOLUTION: A chip is designed by referring to layout data (S11). Power consumption of a memory cell of the chip and a peripheral circuit part which are designed assuming that voltage drop does not occur are calculated (S12). Placement of the memory cell on the chip to which direct power source is supplied from an electrode part is determined so as to satisfy a reference value of a voltage drop (S13) by referring to the reference values of the power consumption and the voltage drop. After that, placement of the peripheral circuit part is similarly determined (S14) so as to satisfy the reference value of the voltage drop. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for designing a semiconductor integrated circuit, and more particularly to a method for designing a semiconductor integrated circuit in which a memory cell is mounted.

  The power supply wiring of a semiconductor integrated circuit usually has a net-like or similar wiring structure, and I / O (Input / Output) cells of the semiconductor integrated circuit are arranged on the outer periphery of the chip and are connected to external electrodes. The power supplied via the I / O cell is supplied to a power supply wiring network that spreads in a mesh pattern inside. Accordingly, power is supplied to a memory cell such as a RAM (Random Access Memory) disposed in the semiconductor integrated circuit and a peripheral circuit section through the power supply wiring network. For the placement of memory cells, peripheral circuit portions, etc., a method of automatically performing layout and placement (P & R: Place and Route) of layout data based on a circuit diagram is often used.

  However, due to current consumption at each point inside the semiconductor integrated circuit, a voltage drop in the power supply wiring network increases toward the center of the chip. That is, the voltage on the power supply wiring network is high in the peripheral part of the semiconductor integrated circuit, and the voltage on the power supply wiring is lowered toward the center. For example, when a RAM whose operation is compensated up to 0.9V is arranged as a memory cell at the center of the chip, and 1.0V is applied from an external electrode, a margin drop occurs when a voltage drop is greater than 0.1V. Will end up.

In order to reduce the voltage drop at the center portion of the chip, voltage is directly supplied from the power ring at the outer peripheral portion of the chip to the power ring provided at the center portion of the chip (for example, see Patent Document 1). )) And other methods.
JP 2004-273844 A

  However, since Patent Document 1 automatically arranges memory cells and peripheral circuit portions by P & R, there is a problem that the memory cells are affected by voltage drop by the peripheral circuit portions.

  Specifically, if a peripheral circuit portion with a large consumption electrode is automatically placed in the vicinity of the memory cell due to the placement and routing, a voltage drop occurs due to this peripheral circuit portion, and the memory cell may be affected by the voltage drop. Increases sex.

  The present invention has been made in view of these points, and an object of the present invention is to provide a semiconductor integrated circuit design method and a design apparatus that realize stable power supply and improved operation reliability.

  In the present invention, in order to solve the above-described problem, in a method for designing a semiconductor integrated circuit in which memory cells are mounted, as shown in FIG. 1, a layout data storage means for storing layout data is referred to directly from an electrode portion. A chip composed of a memory cell to be supplied with power and a peripheral circuit unit is designed (S11), and the power consumption of the memory cell and the peripheral circuit unit is calculated assuming that no voltage drop occurs. It is stored in the storage means (S12), and it is determined whether or not the memory cell satisfies the reference value with reference to the voltage drop reference value of the memory cell stored in the voltage drop reference value storage means and the power consumption of the memory cell. If the reference value is not satisfied, the layout data of the memory cell is changed until the memory cell satisfies the reference value (S13). The peripheral circuit unit determines whether or not the peripheral circuit unit satisfies the reference value of the peripheral circuit unit with reference to the reference value of the peripheral circuit unit and the power consumption of the peripheral circuit unit further stored by the drop reference value storage unit. If the reference value of the peripheral circuit portion is not satisfied, the layout data of the peripheral circuit portion is changed until the reference value of the peripheral circuit portion is satisfied (S14).

  According to such a semiconductor integrated circuit design method, the chip is designed with reference to the layout data, and the power consumption of the memory cell and the peripheral circuit portion of the chip designed as having no voltage drop is calculated. Referring to the power consumption and the voltage drop reference value, the arrangement of the memory cells on the chip to which power is directly supplied from the electrode unit is determined so as to satisfy the voltage drop reference value, and then the peripheral The arrangement of the circuit unit is determined so as to satisfy the reference value of the voltage drop.

  According to the present invention, in order to solve the above problems, in a semiconductor integrated circuit design apparatus in which a memory cell is mounted, layout data storage means for storing layout data, power consumption data storage means for storing power consumption, Voltage drop reference value storage means for storing a voltage drop reference value for the memory cell and peripheral circuit section, and a layout for designing a chip composed of the memory cell and the peripheral circuit section with reference to the layout data storage means Refer to design means, power consumption calculation means for calculating the power consumption of the memory cell and the peripheral circuit section in which the voltage drop does not occur, the voltage drop reference value storage means, and the power consumption data storage means. Whether the memory cell or the peripheral circuit portion satisfies the reference value of the voltage drop A power supply wiring network determination means for determining whether or not the reference value is satisfied, the analysis result of the power supply wiring network determination means is referred to, and the layout of the memory cell or the peripheral circuit section until the reference value is satisfied There is provided a design apparatus for a semiconductor integrated circuit, comprising layout changing means for updating data.

  According to such a semiconductor integrated circuit design apparatus, the power consumption of the memory cell and the peripheral circuit portion of the chip designed as a chip designed with no voltage drop is calculated with reference to the layout data. Referring to the power consumption and the voltage drop reference value, the arrangement of the memory cells on the chip to which power is directly supplied from the electrode section is determined so as to satisfy the voltage drop reference value, and then the peripheral A chip determined so that the arrangement of the circuit portion satisfies the reference value of the voltage drop is formed.

  In the present invention, the chip is designed with reference to the layout data, the power consumption of the memory cell and the peripheral circuit portion of the chip designed as a voltage drop is not calculated, and the reference value of the power consumption and the voltage drop Referring to the above, the memory cell arrangement on the chip to which power is directly supplied from the electrode section is determined so as to satisfy the voltage drop reference value, and then the peripheral circuit section arrangement is similarly set to the voltage drop reference value. It was decided to satisfy. This makes it possible to suppress voltage drops that occur along the center of the chip for memory cells that are directly powered from the electrodes. Even when voltage drops occur, voltage drops can be achieved by changing the memory cell position and wiring. Can be suppressed. After determining the position and wiring of the memory cell, the voltage drop can be suppressed in the same manner for the peripheral circuit portion. Therefore, it is possible to realize a semiconductor integrated circuit in which power can be stably supplied to the chip and operation reliability is improved.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments.
First, a description will be given of a conventional form considered in the process leading to the present invention, and an outline and an embodiment of the present invention will be sequentially described.

FIG. 12 is a schematic diagram of a conventional design flow.
The design flow 500 is roughly divided into three steps after the start of design: a layout design step (S501), a power consumption calculation step (S502), and a macro cell arrangement determination step (S503). Hereinafter, each step will be described.

[Step S501] In a layout design process, a chip composed of a memory cell and a macro cell such as a peripheral circuit section is designed with reference to layout data.
[Step S502] In the power consumption calculation process, assuming that no voltage drop occurs in the chip designed in step S501, the power consumption of the macro cell is calculated and listed.

  [Step S503] In the macro cell placement determination step, the chip designed in Step S501 is referred to with reference to the power consumption calculated and listed in Step S502 and the preset reference value of the macro cell voltage drop. It is analyzed and determined whether or not the voltage drop of the macro cell that constitutes satisfies a reference value.

  When the voltage drop of the macro cell does not satisfy the reference value, the layout data regarding the macro cell is changed and the layout design is performed according to the changed layout data until the voltage drop of the macro cell satisfies the reference value. Then, the position of the macro cell on the chip, the wiring, etc. are automatically determined.

A chip was designed by such a design flow 500, but in reality, a desired chip could not be obtained and a voltage drop occurred.
FIG. 13 is a schematic diagram of a chip according to a conventional design flow, and FIG. 14 is a schematic diagram of a power supply wiring network according to a conventional design flow.

  As shown in FIG. 13, the chip 510 is provided with electrodes 511 at the four corners, and the memory cell 512 is installed at a substantially central portion of the chip 510 according to the design flow 500. Note that the description of the peripheral circuit section is omitted.

  In the design flow 500, the macro cell is automatically arranged in consideration of voltage drop. However, as shown in FIG. 13, the memory cell 512 may be arranged at the center of the chip 510. In this case, the memory cell A voltage drop occurs at 512.

  Further, as shown in FIG. 14, the power supply network 510a is a schematic diagram of the power supply network of the chip 510, in which the memory cell 512 and the peripheral circuit portions 513a and 513b are arranged in parallel between the electrode VDD511a and the electrode VSS511b. They are connected via a wiring resistor 514.

  As shown in FIG. 14, when the design cell 500 automatically arranges the memory cells 512 and the macro cells of the peripheral circuit units 513a and 513b, if the power consumption of the peripheral circuit unit 513b is large, the peripheral circuit unit 513b drops the voltage. Occurs, which affects the memory cell 512.

The outline of the present invention will be described below with respect to such a design flow.
FIG. 1 is a schematic diagram of the design flow of the present invention.
The design flow 10 is roughly divided into four steps after the start of design: a layout design step (S11), a power consumption calculation step (S12), a memory cell placement determination step (S13), and a peripheral circuit portion placement determination step (S14). It is constituted by. Hereinafter, each step will be described.

[Step S11] In the layout design process, referring to the layout data, a chip composed of a memory cell directly supplied with power from the electrode and a peripheral circuit portion is designed.
[Step S12] In the power consumption calculation process, assuming that no voltage drop occurs in the chip designed in step S11, the power consumption of the memory cell and the peripheral circuit section is calculated and listed.

  [Step S13] In the memory cell arrangement determination step, the voltage drop of the memory cell is determined by referring to the power consumption calculated and listed in step S12 and the preset reference value of the voltage drop of the memory cell. Whether or not satisfies the reference value.

  If the reference value is not satisfied, the layout data relating to the memory cell is changed and the layout design is performed according to the changed layout data until the voltage drop of the memory cell satisfies the reference value. Then, the position of the memory cell on the chip, the wiring from the electrode, the number of wirings, and the like are automatically determined.

  [Step S14] In the peripheral circuit portion arrangement determination step, when the memory cell satisfies the reference value in step S13, the power consumption calculated and listed in step S12 and the preset peripheral circuit With reference to the reference value of the voltage drop of the part, it is analyzed and determined whether or not the voltage drop of the peripheral circuit part satisfies the reference value of the peripheral circuit part.

  When the voltage drop of the peripheral circuit unit does not satisfy the reference value, the layout data regarding the peripheral circuit unit is changed and the layout design is performed according to the changed layout data until the voltage drop of the peripheral circuit unit satisfies the reference value. Then, the position and wiring of the peripheral circuit portion on the chip are automatically determined. When the voltage drop of the peripheral circuit portion satisfies the reference value, a chip that satisfies the reference value of the voltage drop of the memory cell and the peripheral circuit portion is designed.

  As described above, in the design flow 10 of the present invention, the placement and routing are determined in consideration of the voltage drop for each of the memory cell that is a macro cell on the chip and the peripheral circuit unit, that is, power is directly supplied from the electrode. After determining the position and wiring of the memory cell in consideration of the voltage drop, the position and wiring of the peripheral circuit portion are similarly determined. For this reason, the voltage drop that occurs along the center of the chip can be suppressed with respect to the memory cell that is directly supplied with power from the electrode. Even if a voltage drop occurs, the voltage drop can be reduced by changing the position and wiring of the memory cell. Can be suppressed. After determining the position and wiring of the memory cell, the voltage drop can be suppressed in the same manner for the peripheral circuit portion. Therefore, it is possible to realize a semiconductor integrated circuit in which power can be stably supplied to the chip and operation reliability is improved.

Based on the outline of the present invention, embodiments will be described below.
In the first embodiment, an example has been described in which layout data related to the number of wirings of a RAM is changed in order to satisfy a voltage drop reference value of a RAM installed as a memory cell.

FIG. 2 is a diagram showing a hardware configuration of a semiconductor integrated circuit design apparatus according to the present invention.
The semiconductor integrated circuit design apparatus 100 is controlled by a CPU (Central Processing Unit) 101 as a whole. A RAM 102, a hard disk drive (HDD: Hard Disk Drive) 103, a graphic processing device 104, and an input interface 105 are connected to the CPU 101 via a bus 106.

  The RAM 102 temporarily stores at least part of an OS (Operating System) program and application programs to be executed by the CPU 101. The RAM 102 stores various data necessary for processing by the CPU 101. The HDD 103 stores an OS program and application programs.

A monitor 21 is connected to the graphic processing device 104. The graphic processing device 104 displays an image on the screen of the monitor 21 in accordance with a command from the CPU 101.
A keyboard 22 and a mouse 23 are connected to the input interface 105. The input interface 105 transmits a signal sent from the keyboard 22 or the mouse 23 to the CPU 101 via the bus 106.

With the hardware configuration as described above, the processing functions of the present embodiment can be realized.
Next, the module configuration of the semiconductor integrated circuit design apparatus 100 will be described.

FIG. 3 is a block diagram showing functions of the semiconductor integrated circuit design apparatus of the present invention.
A semiconductor integrated circuit design apparatus 100 includes a layout data storage unit 110, a power consumption data storage unit 120, a voltage drop reference value storage unit 130, a chip file storage unit 140, a layout design unit 150, a power consumption calculation unit 160, and an arrangement determination unit. In addition, the arrangement determining unit 170 includes a power wiring network analysis unit 170a and a power wiring network determination unit 170b. The layout design unit 150 can accept an input from the developer through the keyboard 22 and the mouse 23. Further, the layout design unit 150 and the arrangement determination unit 170 can display the final processing result on the screen of the monitor 21.

The layout data storage unit 110 stores layout data. The layout data can be set as appropriate according to the design specifications of the desired semiconductor integrated circuit.
The power consumption data storage unit 120 stores the listed power consumption.

  The voltage drop reference value storage unit 130 stores reference values for voltage drops in the RAM and the peripheral circuit unit. Each reference value can be set as appropriate according to the design specifications of a desired semiconductor integrated circuit.

The chip file storage unit 140 stores the finally designed chip as a file.
The layout design unit 150 refers to the layout data storage unit 110 to design a chip having a RAM and a peripheral circuit unit.

  The power consumption calculation unit 160 calculates the power consumption of the RAM and the peripheral circuit unit on the assumption that a voltage drop does not occur in the chip designed by the layout design unit 150, lists it, and stores it in the power consumption data storage unit 120. To do.

  The placement determining unit 170 determines whether or not the voltage drop of the RAM or the peripheral circuit unit satisfies the reference value. If not, the layout determining unit 170 changes the layout data until the RAM or the peripheral circuit unit satisfies the reference value of the voltage drop. When the voltage drop of the RAM and the peripheral circuit section satisfies the reference value, the chip design is completed. In addition, each element of the arrangement | positioning determination part 170 is demonstrated below.

The power supply network analysis unit 170a refers to the power consumption data storage unit 120 and analyzes a voltage drop in the RAM or the peripheral circuit unit.
The power supply wiring network determination unit 170b refers to the analysis result of the power supply wiring network analysis unit 170a and the voltage drop reference value storage unit 130, and determines whether or not the reference value of the RAM or the peripheral circuit unit is satisfied.

When the RAM or the peripheral circuit unit does not satisfy the voltage drop reference value, the layout design unit 150 changes the layout data regarding the RAM or the peripheral circuit unit.
Next, processing performed by such a semiconductor integrated circuit design apparatus will be described using a design flow.

FIG. 4 is a design flow showing a processing procedure of the semiconductor integrated circuit design apparatus of the present invention.
Processing performed by the semiconductor integrated circuit design apparatus 100 will be described using the design flow 20.

  [Step S21] The layout design unit 150 refers to the layout data storage unit 110 to design a chip having a RAM and a peripheral circuit unit. At this time, the RAM wiring is designed so that power is directly supplied from the electrodes.

  [Step S22] The power consumption calculation unit 160 calculates the power consumption of the RAM and the peripheral circuit unit on the assumption that a voltage drop does not occur in the chip designed in step S21, lists the power consumption, and stores the power consumption data storage unit 120. To store. Further, when the layout data is changed in steps S26 and S29 described later, the power consumption is calculated again accordingly, and the calculation result is similarly stored in the power consumption data storage unit 120.

  [Step S23] The power supply wiring network determination unit 170b proceeds to step S24 without performing the determination in the first process. Then, in the second and subsequent processes, it is determined whether or not the RAM voltage drop satisfies the RAM reference value by referring to the determination result of the first step S25. The process proceeds to S24, and if satisfied, the process proceeds to Step S27. Similarly, when the process of step S23 is performed for the third time, the determination result of step S25 for the second time is referred to, and the determination result of step S25 is sequentially referred to.

[Step S24] The power supply wiring network analysis unit 170a refers to the power consumption data storage unit 120 and analyzes the power supply wiring network of the RAM.
[Step S25] The power supply wiring network determination unit 170b refers to the voltage drop reference value storage unit 130 and the analysis result in step S24 to determine again whether or not the RAM voltage drop satisfies the RAM reference value. . If the RAM does not satisfy the reference value, the process proceeds to step S26, and if it does, the process proceeds to step S27.

  [Step S26] When the RAM does not satisfy the reference value, the layout design unit 150 refers to the analysis result of Step S24 and changes the layout data regarding the number of wirings to the RAM.

  [Step S27] When the RAM satisfies the reference value, the power supply wiring network determination unit 170b refers to the result of the power supply wiring network analysis in Step S28 and the voltage drop reference value storage unit 130, and the voltage drop of the peripheral circuit unit is detected. It is determined whether or not the reference value of the peripheral circuit unit is satisfied. If the peripheral circuit portion does not satisfy the reference value, the process proceeds to step S29, and if satisfied, the design ends.

[Step S28] The power supply wiring network analyzing unit 170a refers to the power consumption data storage unit 120 and analyzes the power supply wiring network of the peripheral circuit unit.
[Step S29] The power supply wiring network analysis unit 170a refers to the analysis result of step S28 and changes the layout data regarding the arrangement of the peripheral circuit unit and the like.

With the design flow 20 described above, a chip that satisfies the voltage drop reference values of the RAM and the peripheral circuit section is designed.
A chip designed by such processing and its power supply wiring network will be described below.

FIG. 5 is a schematic diagram of a chip in the first embodiment, and FIG. 6 is a schematic diagram of a power supply wiring network in the first embodiment.
As shown in FIG. 5, the chip 200 is provided with electrodes 201 at four corners and a RAM 202 at almost the center of the chip 200, and the RAM 202 is directly supplied with power from the electrode 201 via the wiring 203 by the design flow 20. The number of wirings 203 is set so that the voltage drop of the RAM 202 satisfies the reference value. In FIG. 5, the peripheral circuit portion is not shown.

  Further, as shown in FIG. 6, the power supply wiring network 200a is a schematic diagram of the power supply wiring network of the chip 200, and the peripheral circuit portions 205a and 205b are connected via the wiring resistance 204 between the electrode VDD 201a and the electrode VSS 201b. It is connected. Since the RAM 202 is directly wired to the electrode VDD 201a and the electrode VSS 201b in parallel with the peripheral circuit portions 205a and 205b, power is reliably supplied regardless of voltage drop due to power consumption of the peripheral circuit portions 205a and 205b. Is done.

Next, a second embodiment will be described.
In the second embodiment, a RAM is arranged as a memory cell as in the first embodiment, and in order to satisfy the RAM voltage drop reference value, in addition to the number of RAM wirings, the wiring width is increased. In this example, the layout data involved is changed. In the second embodiment, it is assumed that the semiconductor integrated circuit design apparatus 100 is used in the same manner as in the first embodiment. Therefore, unless otherwise specified, the same components as those in the first embodiment will be described using the same reference numerals.

  In the second embodiment, in order for the RAM to satisfy the voltage drop reference value, the layout data related to the wiring width is changed in addition to the number of RAM wirings. For example, when the layout data is changed for the first time and the number of wirings is changed to two but the RAM does not satisfy the reference value, the wiring width is changed from 1 grid to 2 when the layout data is changed for the second time. The layout data related to the number of wirings and the wiring width is changed in step S26 of the design flow 20 so as to change to the grid so as to satisfy the reference value of the voltage drop of the RAM.

FIG. 7 is a schematic diagram of a chip in the second embodiment.
According to this chip 210, it can be seen that the number of wirings 203a is reduced from five to three as compared with the chip 200 of FIG. 5, but the wiring width is increased. In this way, the same effects as those of the first embodiment can be obtained.

Next, a third embodiment will be described.
In the first and second embodiments, power is directly supplied from the electrodes to the RAM. However, in the third embodiment, the electrodes for supplying power to the RAM and the peripheral circuit unit are separated and the RAM is divided. A case where a dedicated electrode is provided will be described as an example.

  In order to provide a dedicated electrode for the RAM, it can be set to perform desired wiring for the RAM in the “layout design” in step S21 of the design flow 20. Hereinafter, an example of a chip provided with an electrode dedicated to RAM will be described.

FIG. 8 is a schematic diagram of a chip according to the third embodiment.
In the chip 220, the electrodes 201 are installed at the four corners, and the RAM 202 is installed at almost the center of the chip 220. The RAM 202 is directly supplied from the electrode 201 a provided separately from the electrode 201 via the wiring 203 b according to the design flow 20. Is supplied, and the number of wirings 203b is set so that the voltage drop satisfies the reference value. In FIG. 8, the description of the peripheral circuit portion is omitted.

Hereinafter, a power supply wiring network provided with an electrode dedicated to RAM will be described.
FIG. 9 is a schematic diagram of a power supply wiring network in the third embodiment.
The power supply wiring network 220a is a schematic diagram of the power supply wiring network of the chip 220, and the peripheral circuit portions 205a and 205b are connected between the electrode VDD1221a and the electrode VSS1221b via a wiring resistance 224. Since the RAM 202 is directly connected to the newly provided electrode VDD 2221c and the electrode VSS 1221b separately from the electrode VDD 1221a, the power can be reliably supplied regardless of the voltage drop due to the power consumption of the peripheral circuit portions 205a and 205b. Supplied.

FIG. 10 is a schematic diagram of another power supply wiring network in the third embodiment.
The power supply wiring network 220b is a power supply wiring network different from the power supply wiring network 220a, and the peripheral circuit portions 205a and 205b are connected between the electrode VDD1221a and the electrode VSS1221b via a wiring resistor 224. The RAM 202 is connected between a separately provided electrode VDD 2221c and electrode VSS 2221d via a wiring resistor 224, and is directly supplied with power. For this reason, the power is reliably supplied regardless of the voltage drop due to the power consumption of the peripheral circuit portions 205a and 205b.

A fourth embodiment will be described.
In the first to third embodiments, the flow of the design flow is in the order of determining the RAM wiring and determining the peripheral circuit wiring. On the other hand, in the fourth embodiment, a case where the wiring determination order of the RAM and the peripheral circuit unit is switched will be described as an example.

FIG. 11 is a design flow showing a processing procedure of the semiconductor integrated circuit design apparatus according to the fourth embodiment.
In the flow of FIG. 11, the same step numbers as in FIG. 4 are used. However, “power supply network determination (RAM)” is step S25, “first power supply network determination (peripheral circuit)” is step S28, and “second power supply network determination (peripheral circuit)” is step S28a. .

  In the design flow 30, processing related to the wiring determination of the peripheral circuit section is performed first, and then processing related to the wiring determination of the RAM is performed, and this flow can also obtain the same effects as those of the embodiments already described. it can.

  As described above, in the present invention, a RAM to which power is directly supplied from an electrode can reduce a voltage drop that occurs along the center of the chip, and even if a voltage drop occurs, a voltage can be reduced by changing the position and wiring of the RAM. Drops can be suppressed. After the RAM position and wiring are determined, the voltage drop can be suppressed in the same manner for the peripheral circuit portion. Therefore, it is possible to realize a semiconductor integrated circuit in which power can be stably supplied to the chip and operation reliability is improved.

It is a schematic diagram of the design flow of this invention. It is a figure which shows the hardware constitutions of the design apparatus of the semiconductor integrated circuit of this invention. It is a block diagram which shows the function of the design apparatus of the semiconductor integrated circuit of this invention. It is a design flow which shows the process sequence of the design apparatus of the semiconductor integrated circuit of this invention. It is a mimetic diagram of a chip in a 1st embodiment. It is a power supply wiring network schematic diagram in a 1st embodiment. It is a mimetic diagram of a chip in a 2nd embodiment. It is a schematic diagram of the chip | tip in 3rd Embodiment. It is a power supply wiring network schematic diagram in 3rd Embodiment. It is the other power supply wiring network schematic diagram in 3rd Embodiment. It is a design flow which shows the process sequence of the design apparatus of the semiconductor integrated circuit in 4th Embodiment. It is a schematic diagram of the conventional design flow. It is the model of the chip | tip by the conventional design flow. It is a power supply wiring network schematic diagram by the conventional design flow.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor integrated circuit design apparatus 110 Layout data memory | storage part 120 Power consumption data memory | storage part 130 Voltage drop reference value memory | storage part 140 Chip file memory | storage part 150 Layout design part 160 Power consumption calculation part 170 Placement determination part 170a Power supply wiring network determination part 170b Power supply network analysis unit

Claims (6)

In a design method of a semiconductor integrated circuit in which a memory cell is mounted,
With reference to the layout data storage means for storing the layout data, a chip composed of the memory cell that is directly supplied with power from the electrode portion and the peripheral circuit portion is designed,
Calculate the power consumption of the memory cell and the peripheral circuit section as no voltage drop occurs, and store the power consumption in the power consumption data storage means,
Determining whether or not the memory cell satisfies the reference value by referring to the voltage drop reference value of the memory cell stored by the voltage drop reference value storage means and the power consumption of the memory cell;
If the reference value is not satisfied, the layout data of the memory cell is changed until the memory cell satisfies the reference value,
When the reference value is satisfied, the peripheral circuit unit refers to the reference value of the peripheral circuit unit further stored by the voltage drop reference value storage unit and the power consumption of the peripheral circuit unit, and the peripheral circuit unit Whether or not the reference value is satisfied,
When the reference value of the peripheral circuit portion is not satisfied, the layout data of the peripheral circuit portion is changed until the reference value of the peripheral circuit portion is satisfied.   2. The method of designing a semiconductor integrated circuit according to claim 1, wherein the layout data relating to the number of wirings of the memory cell is changed.   3. The method of designing a semiconductor integrated circuit according to claim 2, wherein the layout data relating to a wiring width is changed in addition to the number of wirings of the memory cell.   4. The method for designing a semiconductor integrated circuit according to claim 1, wherein the electrode portion that supplies power to the memory cell and the peripheral circuit portion is separately designed.   5. The method for designing a semiconductor integrated circuit according to claim 1, wherein the voltage drop determination and the power supply wiring network analysis are performed before the memory cell for the peripheral circuit unit. 6. In a semiconductor integrated circuit design apparatus equipped with a memory cell,
Layout data storage means for storing layout data;
Power consumption data storage means for storing power consumption;
Voltage drop reference value storage means for storing a voltage drop reference value of the memory cell and the peripheral circuit unit;
Layout design means for designing a chip composed of the memory cell and the peripheral circuit section with reference to the layout data storage means;
A power consumption calculating means for calculating the power consumption of the memory cell and the peripheral circuit section that the voltage drop does not occur;
Power wiring network determination means for determining whether the memory cell or the peripheral circuit unit satisfies the reference value of the voltage drop with reference to the voltage drop reference value storage means and the power consumption data storage means;
If the reference value is not satisfied, referring to the analysis result of the power wiring network determination means, layout changing means for updating the layout data of the memory cell or the peripheral circuit unit until the reference value is satisfied;
An apparatus for designing a semiconductor integrated circuit, comprising:

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