JP2008228128A - Radio reception circuit and input interference wave reduction circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compact input interference wave reduction circuit for reducing interference waves over a wide frequency region and to provide a compact radio reception circuit provided with the input interference wave reduction circuit. <P>SOLUTION: Reception signals are supplied to the gate of a transistor Q1, the transistor Q1 is connected to transistors QA-QD, and four amplifiers are constituted of the transistors Q1 and QA-QD. Adjustment circuits 13A-13D are respectively connected to the transistors QA-QD, the adjustment circuits 13A-13D are LC resonance circuits, and the resonance frequency is adjusted by adjustment signals and fine adjustment signals. Selection signals select the amplifier to be used from the four amplifiers, the gain frequency of the selected amplifier is determined corresponding to the resonance frequency of the corresponding adjustment circuit (13A-13D), and signals amplified by the selected amplifier are outputted. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a radio reception circuit and an input interference wave reduction circuit, and more particularly to a radio reception circuit and an input interference wave reduction circuit used in a system in which a plurality of radio channels to which different frequencies are assigned are set.

  In general, a wireless receiver has a function of selectively extracting a radio wave (hereinafter referred to as a desired wave) having a frequency corresponding to a channel requested by a user. For example, a television receiver or a radio receiver has a function of extracting a desired wave. In order to extract the desired wave, it is necessary to remove radio waves having frequencies other than the desired wave (hereinafter, interference waves).

  FIG. 9 is a diagram illustrating an example of a conventional wireless reception circuit. In FIG. 9, the received signal received via the antenna (ANT) includes signals of various frequencies. This received signal passes through an attenuator (ATT) 501 and a low noise amplifier 502 and is then supplied to a band pass filter (BPF) 503. The bandpass filter 503 passes a signal having a frequency indicated by the control signal. That is, the band pass filter 503 passes the frequency band of the desired wave. The PLL frequency synthesizer 504 outputs an oscillation signal having a frequency necessary for generating a target intermediate frequency, and the mixer 505 down-converts (or up-converts) the reception signal using the oscillation signal. The signal processing circuit 506 then reproduces the desired wave by converting the intermediate frequency signal into a baseband frequency signal and then demodulating it.

  In the receiving circuit having the above-described configuration, the band-pass filter 503 and the PLL frequency synthesizer 504 operate in cooperation with each other in order to select a channel designated by the user as a desired wave. That is, the pass frequency band of the band pass filter 503 and the oscillation frequency output from the PLL frequency synthesizer 504 change in conjunction with each other.

  In order to realize the above operation, the bandpass filter 503 includes an LC circuit, and the PLL frequency synthesizer 504 includes a resonance circuit. Then, the pass frequency band / oscillation frequency is adjusted by changing the capacitance values of the capacitance components constituting the LC circuit and the resonance circuit. Here, in a broadcasting system that provides a large number of channels, the channels are arranged over a wide frequency range. Therefore, in order to receive these many channels, it is necessary to greatly change the above-described pass frequency band / oscillation frequency. For this purpose, the capacitance values of the capacitance components constituting the resonance circuit and the LC circuit vary greatly. There is a need.

  However, an element that can greatly change the capacitance value basically increases in size. For example, in the receiving circuit shown in FIG. 9, the bandpass filter 503 includes a varactor 507 and the PLL frequency synthesizer 504 includes a varactor 508 as variable capacitance elements. Then, the capacitance values of the varactors 507 and 508 are adjusted by a common control signal. However, since the varactors 507 and 508 are large in size, they are provided as external elements (that is, external components). Therefore, downsizing of the receiving circuit has been hindered.

As one of the techniques for solving this problem, Patent Document 1 describes a PLL frequency synthesizer that can obtain an oscillation frequency over a wide frequency range without providing external components. This PLL frequency synthesizer includes a plurality of switched capacitor voltage controlled oscillation circuits. Each switched capacitor voltage controlled oscillator circuit includes a plurality of tuning switched capacitors, inductors, and variable capacitors. A desired oscillation frequency is obtained by selecting a switched capacitor voltage controlled oscillator circuit, selecting a switched capacitor for tuning, and adjusting a variable capacitor.
JP 2004-120215 A

  However, when the technique described in Patent Document 1 is introduced into the wireless reception circuit shown in FIG. 9, a varactor 507 for controlling the pass frequency band of the bandpass filter 503 is configured by an external element, and the oscillation frequency of the PLL frequency synthesizer 504 is controlled. Since the varactor to be configured is an internal element, it is difficult to control the pass frequency band of the bandpass filter 503 and the oscillation frequency of the PLL frequency synthesizer 504 in conjunction with each other. For this reason, there is a possibility that the reception sensitivity of the desired wave is deteriorated. In addition, a configuration for realizing a bandpass filter capable of greatly changing the pass frequency band without an external component has not been proposed. If the size of the band-pass filter as the input interference wave reducing circuit can be reduced, the radio receiving circuit can be further reduced in size.

  An object of the present invention is to reduce the size of an input jamming wave reduction circuit that can reduce jamming waves over a wide frequency range, and to reduce the size of a radio reception circuit including such an input jamming wave reduction circuit.

  A radio reception circuit of the present invention is a radio reception circuit including an input interference wave reduction circuit and a frequency conversion circuit, wherein the input interference wave reduction circuit amplifies a reception signal and has a plurality of amplifiers having different pass frequency regions. And a first selection means for selecting an amplifier to be used from among the plurality of amplifiers, wherein the frequency conversion circuit includes a plurality of voltage controlled oscillators having different oscillation frequency ranges from each other, and the plurality of voltage controlled oscillators. Second selection means for selecting a voltage controlled oscillator to be used from the output, and an oscillation signal obtained by using the output signal of the voltage controlled oscillator selected by the second selection means is output from the input disturbance wave reducing circuit. A mixer for multiplying the signal is provided. The second selection unit selects a voltage controlled oscillator in response to a channel selection request, and the first selection unit selects a corresponding amplifier according to a selection signal representing a selection result by the second selection unit. To do.

  Here, the “oscillation frequency region” in the present invention refers to the frequency range of the oscillation frequency that can be selected by one voltage-controlled oscillator, and the “pass frequency region” means the center of the pass frequency that can be selected by one amplifier. Refers to the frequency range of frequencies.

  In the radio reception circuit having the above-described configuration, a wide frequency region is covered using a plurality of amplifiers, so that the pass frequency region to be covered by each amplifier becomes narrow. Accordingly, since it is not necessary to change the pass characteristics of each amplifier greatly, the pass characteristics required by an element that can be formed on a semiconductor chip can be obtained, and no external parts are required, so that the size of the radio receiving circuit is small Can be achieved. In addition, since the amplifier to be used is selected from the plurality of amplifiers according to the selection result of selecting the voltage control oscillator to be used, the input interference wave reduction circuit and the frequency conversion circuit can be controlled in conjunction with each other. Therefore, the interference wave can be surely removed, and variation in frequency characteristics between the input interference wave reduction circuit and the frequency conversion circuit is reduced, so that the desired wave can be received with high accuracy.

  In the wireless reception circuit, each of the plurality of amplifiers may include an LC circuit including an inductor and a capacitor, and a pass frequency region may be determined based on an inductor value and a capacitance value of the LC circuit.

  In the wireless reception circuit, the LC circuit includes a plurality of capacitors, and the plurality of voltage controlled oscillators each include an adjustment circuit for selecting an oscillation frequency from the oscillation frequency region, The amplifier selected by the first selection means is selected by selecting a capacitor to be connected to the inductor according to the adjustment signal representing the adjustment result in the previous adjustment circuit included in the voltage controlled oscillator selected by the second selection means. A pass frequency band may be selected from the pass frequency region.

  In this case, the LC circuit included in the amplifier selected by the first selection unit has a pass frequency band according to the adjustment signal representing the selection result in the adjustment circuit included in the voltage controlled oscillator selected by the second selection unit. select. In this configuration, it is possible to select the pass frequency band in the input jamming wave reduction circuit and the oscillation frequency in the frequency conversion circuit, and more reliably remove the jamming wave. Further, since the pass frequency band is selected according to the selection result of the oscillation frequency, variation in frequency characteristics between the input interference wave reducing circuit and the frequency converting circuit is reduced, so that the desired wave can be received with higher accuracy.

  In the wireless reception circuit, the LC circuit includes first fine adjustment means for finely adjusting a pass frequency band, and the adjustment circuit includes second fine adjustment means for finely adjusting an oscillation frequency. May be. In this case, the first fine adjustment unit finely adjusts the pass frequency band in accordance with a fine adjustment signal representing a result of the fine adjustment in the second fine adjustment unit. In this configuration, since the pass frequency band and the oscillation frequency can be further finely adjusted, the interference wave can be more reliably removed. Further, since the pass frequency is finely adjusted according to the result of fine adjustment of the oscillation frequency, variation in frequency characteristics between the input interference wave reducing circuit and the frequency converting circuit is reduced, and the desired wave can be received with higher accuracy.

The first fine adjustment unit may be a varactor that changes a capacitance value of the LC circuit.
The input interference wave reducing circuit of the present invention has a plurality of amplifiers and a selection means for selecting an amplifier to be used from among the plurality of amplifiers in response to a channel selection request, and the plurality of amplifiers are respectively An LC circuit composed of an inductor and a capacitor is provided. According to this configuration, since the gain frequency region to be covered by each amplifier is narrow, it is not necessary to greatly change the gain characteristics of each amplifier. Therefore, gain characteristics required by an LC circuit that is small enough to be formed on a semiconductor chip can be obtained, and no external parts are required.

  In the input interference wave reducing circuit, the LC circuit may include a plurality of the capacitors and select a capacitor to be connected to the inductor. Further, the LC circuit may include a varactor for finely adjusting the capacitance value.

  ADVANTAGE OF THE INVENTION According to this invention, size reduction of the input interference wave reduction circuit which can reduce an interference wave over a wide frequency range, and size reduction of a radio | wireless receiving circuit provided with such an input interference wave reduction circuit can be achieved.

FIG. 1 is a diagram illustrating a configuration of a wireless reception circuit according to an embodiment of the present invention.
The radio reception circuit 1 includes an antenna ANT, an input interference wave reduction circuit 2 that amplifies a reception signal from the antenna ANT and outputs only a signal within the pass frequency band among the amplified signals, and an input interference A frequency conversion circuit 4 for converting the output signal from the wave reduction circuit 2 from a high frequency signal to an intermediate frequency signal, and a feedback for monitoring the amplitude of the intermediate frequency signal obtained by the frequency conversion circuit 4 and stabilizing the amplitude at a predetermined level. The AGC circuit 8 that performs control and a signal processing circuit (not shown) that reproduces a desired wave by converting and demodulating the intermediate frequency signal obtained by the frequency conversion circuit 4 into a baseband frequency signal. In FIG. 1, functions that are not highly relevant to the present invention are omitted.

  The radio reception circuit 1 of the embodiment is used in a system in which a plurality of radio channels to which different frequencies are assigned are set. That is, the radio reception circuit 1 is not particularly limited, but is used as a television broadcast receiver or a radio broadcast receiver, for example.

  In FIG. 1, the radio reception circuit 1 operates in response to a channel selection request. The channel selection request is a signal that designates a channel to be received by the wireless reception circuit 1, and is input by the user. This channel selection request is given to the PLL frequency synthesizer 6 provided in the frequency conversion circuit 4. In the following description, a channel designated by a channel selection request may be referred to as a “request channel”.

  As will be described in detail later, the input interference wave reduction circuit 2 includes a plurality of amplifiers 3A to 3D provided in parallel, and selects an amplifier to be used in accordance with a selection signal generated by the PLL frequency synthesizer 6. Then, a pass frequency region is selected, and a pass frequency band to be used is selected and adjusted from within the pass frequency region of the selected amplifier according to the adjustment signal and the fine adjustment signal.

  The amplifiers 3A to 3D amplify the received signal received using the antenna ANT. In this embodiment, each operates as a low noise amplifier (LNA). The amplifiers 3A to 3D have LC circuits, which will be described in detail later. The LC circuit has a filter function for outputting, as an output signal, only a signal within the pass frequency band determined by the inductor value and the capacitance value among the amplified signals.

  Here, for example, when the amplifier 3A is selected, only the signal in the pass frequency region of the LC circuit included in the amplifier 3A is output as the output signal of the amplifier 3A. Therefore, the interference wave for the request channel can be removed.

  The frequency conversion circuit 4 converts the signal from which the interference wave is removed by the input interference wave reduction circuit 2 from a high frequency signal to an intermediate frequency signal. At this time, the frequency conversion circuit 4 generates an oscillation signal having a frequency necessary for generating a target intermediate frequency signal, and performs frequency conversion using the oscillation signal.

  The frequency conversion circuit 4 includes a PLL frequency synthesizer 6 including a plurality of voltage controlled oscillators 5A to 5D having different oscillation frequency regions, and a mixer 7. When the frequency conversion circuit 4 selects a voltage controlled oscillator to be used from the voltage controlled oscillators 5A to 5D, the PLL frequency synthesizer 6 generates an oscillation signal using the output of the voltage controlled oscillator to generate a mixer 7 To give. Then, the mixer 7 performs frequency conversion by multiplying the output signal of the input interference wave reducing circuit 2 by the oscillation signal. Thereby, a target intermediate frequency signal is generated. Each of the voltage controlled oscillators 5A to 5D includes an adjustment circuit that selects an oscillation frequency from within the oscillation frequency region, which will be described in detail later.

  The AGC circuit 8 monitors the amplitude of the intermediate frequency signal obtained by the frequency conversion circuit 4 and performs feedback control for stabilizing the amplitude at a predetermined level. In this feedback control, a gain control signal is generated and applied to the amplifiers 3A to 3D. The gains of the amplifiers 3A to 3D are controlled by this gain control signal.

Next, the PLL frequency synthesizer 6 will be described with reference to FIG.
The PLL frequency synthesizer 6 includes a VCO circuit 5 including voltage control oscillators 5A to 5D, a frequency dividing circuit 51, a phase comparator 52, a charge pump 53, a loop filter LPF 54, a lock detection circuit 55, a control circuit 56, and a frequency dividing ratio signal. The generation circuit 57 is configured.

  The frequency division ratio signal generation circuit 57 generates a frequency division ratio signal corresponding to the channel selection request input by the user, and outputs this frequency division ratio signal to the frequency division circuit 51. The frequency dividing circuit 51 divides the output signal from the VCO circuit 5 according to the frequency division ratio signal. The phase comparator 52 outputs a phase difference signal representing the phase difference between the phase of the output signal from the frequency dividing circuit 51 and the phase of the reference signal. The charge pump 53 generates a current corresponding to the phase difference signal. The loop filter 54 generates a fine adjustment signal to be given to the VCO circuit 5 by changing the output signal of the charge pump 53 to a voltage.

  The lock detection circuit 55 monitors the output signal of the phase comparator 52 and determines whether the phase of the output signal of the frequency dividing circuit 51 and the phase of the reference signal input to the phase comparator 52 are substantially the same. The control circuit 56 until the lock detection circuit 55 detects that the phase of the output signal of the frequency divider circuit 51 and the phase of the reference signal input to the phase comparator 52 are substantially the same (hereinafter, locked). Sequentially, a selection signal for selecting a voltage controlled oscillator to be used from among the voltage controlled oscillators 5A to 5D constituting the VCO circuit 5, and an adjustment for selecting an oscillation frequency to be used from within the oscillation frequency region of the selected voltage controlled oscillator Generate and switch signals.

  As shown in FIG. 3, the VCO circuit 5 includes voltage controlled oscillators 5A to 5D, a selection circuit (second selection means) 33, and a selector 34. The voltage controlled oscillators 5A to 5D each select an oscillation frequency. An adjustment circuit 31 and a fine adjustment unit (second fine adjustment means) 32 are provided.

  The selection circuit 33 selects the corresponding voltage controlled oscillator (5A to 5D) according to the selection signal generated by the control circuit 56. The adjustment circuit 31 selects an oscillation frequency to be used from the oscillation frequency region of the voltage controlled oscillator selected by the selection circuit 33 according to the adjustment signal generated by the control circuit 56. The fine adjustment unit 32 performs fine adjustment of the oscillation frequency selected by the selection circuit 33 and the adjustment circuit 31 in accordance with the fine adjustment signal given through the low-pass filter 54 shown in FIG. The selector 34 outputs an oscillation signal of the selected voltage controlled oscillator. This oscillation signal is given to the mixer 7.

  The voltage controlled oscillators 5A to 5D are not particularly limited, but may have a configuration equivalent to the voltage controlled oscillator described in Patent Document 1 (Japanese Patent Application Laid-Open No. 2004-120215), for example. In this case, the selection signal, the adjustment signal, and the fine adjustment signal of the embodiment correspond to the selection control signal, the switched capacitor control signal, and the control voltage described in Patent Document 1, respectively. The adjustment circuit 31 corresponds to the tuning switched capacitors 24 to 27, and the fine adjustment unit 32 corresponds to the variable capacitors C1 and C2.

  The operation of the PLL frequency synthesizer 6 configured as described above will be described with reference to FIGS. In the following description, it is assumed that the VCO circuit 5 of this embodiment is provided with a selection signal for selecting the voltage controlled oscillator 5A and an adjustment signal for selecting the frequency characteristic a1 shown in FIG. 4 as an initial state. .

  The PLL frequency synthesizer 6 oscillates with a frequency necessary for generating a target intermediate frequency when a frequency division ratio signal generated in response to a channel selection request from a user is input to the frequency dividing circuit 51. Generate a signal. When the frequency division ratio signal is input, the frequency dividing circuit 51 divides the free run frequency signal of the VCO circuit 5A, which is the output signal of the VCO circuit 5, and outputs it to the phase comparator 52. The phase comparator 52 that has received the output signal of the frequency dividing circuit 51 outputs a phase difference signal that represents the phase difference between the output signal from the frequency dividing circuit 51 and the reference signal. It is converted into a fine adjustment signal via the filter 54 and input to the fine adjustment circuit 32 of the voltage control circuits 5A to 5D. Then, the VCO circuit 5 converts this fine adjustment signal into a frequency signal and outputs it to the frequency dividing circuit. Thereafter, the above procedure is repeated for a predetermined time.

  As a result, if the PLL system is locked, thereafter, the control circuit 56 fixes the selection signal and the adjustment signal, and the fine adjustment signal is stabilized. On the other hand, if the PLL system does not lock even after a certain period of time has elapsed, the same PLL operation is performed after switching the adjustment signal so as to obtain the frequency characteristic a2.

  Thereafter, similarly, the above procedure is repeated in order from the lowest frequency of the frequency characteristics shown in FIG. 4 while switching the selection signal and the adjustment signal until the PLL system is locked. For example, in order to output the frequency f1 in response to the channel selection request, a selection signal for selecting the voltage controlled oscillator 5A and an adjustment signal for obtaining the frequency characteristic a2 are generated. In order to output the frequency f2, a selection signal for selecting the voltage controlled oscillator 5B and an adjustment signal for obtaining the frequency characteristic b3 are generated. When the PLL system is locked, the PLL frequency synthesizer 6 outputs the selection signal, adjustment signal, and fine adjustment signal at the time of locking to the input interference wave reduction circuit 2 as shown in FIG.

Next, the input interference wave reduction circuit 2 will be described in detail with reference to FIGS. 3, 5, 6, and 7. FIG.
The input jamming wave reduction circuit 2 includes amplifiers 3A to 3D, a selector 14, and a selection circuit 12. As illustrated in FIG. 6, the selection circuit 12 includes switches 21 </ b> A to 21 </ b> D and 22 </ b> A to 22 </ b> D.

  A gain control signal is given to the input side terminals of the switches 21A to 21D. The gain control signal is a feedback signal for keeping the loop gain constant when the input is excessive, and is generated by the AGC circuit 8 shown in FIG. Output side terminals of the respective switches 21A to 21D are grounded via the switches 22A to 22D, respectively. The switches 21A to 21D and 22A to 22D are not particularly limited, but are, for example, MOS transistors. The switches 21A to 21D are controlled by selection signals a1 to d1, respectively. The switches 22A to 22D are controlled by inverted signals of the selection signals a1 to d1, respectively. Then, selection signals a2 to d2 are output from the output-side terminals of the switches 21A to 21D and input to the gates of the transistors QA to QD of the amplifiers 3A to 3D.

  The selection signals a1 to d1 are selection signals generated in the PLL frequency synthesizer 6, and are selection signals when the PLL frequency synthesizer 6 is locked. In this embodiment, each is a binary signal.

  The amplifiers 3A to 3D include transistors QA to QD (first transistor), a transistor Q1 (second transistor), a current source 11, and LC circuits 13A to 13D. The drains of the transistors QA to QD are LC circuits 13A to 13D. The sources of the transistors QA to QD are connected to the drain of the transistor Q1, the current source 11 is connected to the source of the transistor Q1, and the reception signal is input to the gate of the transistor Q1.

  The amplifier 3A includes transistors Q1 and QA, a current source 11, and an adjustment circuit 13A. Similarly, the amplifier 3B includes transistors Q1 and QB, a current source 11, and an adjustment circuit 13B. The amplifier 3C includes transistors Q1 and QC, the current source 11, and an adjustment circuit 13C, and the amplifier 3D includes transistors Q1, Q1, It is comprised by QD, the current source 11, and the adjustment circuit 13D. That is, the transistor Q1 and the current source 11 are shared by the amplifiers 3A to 3D.

  Output signals (selection signals a2 to d2) of the selection circuit 12 are input to the gates of the transistors QA to QD of the amplifiers 3A to 3D configured as described above, and a reception signal is input to the transistors Q1 of the amplifiers 3A to 3D. Entered.

  As shown in FIG. 7, the LC circuits 13A to 13D include an inductor L, capacitors C1 to C4, and a varactor (first fine adjustment means) 23 controlled by a fine adjustment signal generated in the PLL frequency synthesizer 6. The switches SW1 to SW4 are controlled by adjustment signals generated in the PLL frequency synthesizer 6, and the basic configurations are the same. However, the constants of the LC circuits are different from each other so that the pass frequency regions of the LC circuits 13A to 13D are different. In the present embodiment, by appropriately determining the inductor value of the inductor L of each of the LC circuits 13A to 13D, the pass frequency regions of the LC circuits 13A to 13D are set to be different as shown in FIG. . The capacitors C1 to C4 are connected in parallel to the inductor L via switches SW1 to SW4, respectively.

An adjustment signal and a fine adjustment signal are input to the LC circuits 13A to 13D configured as described above.
The adjustment signal is a signal that determines ON / OFF of the switches SW1 to SW4. This adjustment signal is an adjustment signal generated in the PLL frequency synthesizer 6 and is an adjustment signal when the PLL frequency synthesizer 6 is locked. In the present embodiment, any one of the switches SW1 to SW4 is controlled to be in an ON state. In this case, the capacitors C1 to C4 need to have different capacities. The adjustment signal may control one or more of the switches SW1 to SW4 to be in an ON state. In this case, the capacities of the capacitors C1 to C4 may be the same or different from each other.

  The fine adjustment signal is a voltage signal. That is, the voltage applied to the varactor 23 is changed by the fine adjustment signal, and the capacitance value of the varactor 23 is adjusted according to the voltage. This fine adjustment signal is a fine adjustment signal generated in the PLL frequency synthesizer 6 and is a fine adjustment signal when the PLL frequency synthesizer 6 is locked. The selector 14 selects a corresponding signal according to the selection signals a1 to d1 described above. Here, for example, if “1” is generated as the selection signal a1 and “0” is generated as the selection signals b1, c1, and d1, respectively, the selector 14 outputs the signal output from the drain of the transistor QA. select. That is, the signal amplified by the amplifier 3A is selected.

  In the present embodiment, the inductor L, the capacitors C1 to C4, the switches SW1 to SW4, and the varactor 23 are formed on the semiconductor chip. Further, the circuit configuration shown in FIG. 7 is one example, and other circuit configurations may be employed. For example, a capacitor may be provided between the varactor 23 and the inductor L. Further, a plurality of inductors having different inductances may be provided, and the corresponding inductor may be selected using the adjustment signal.

Next, the operation of the input interference wave reducing circuit 2 will be described with reference to FIGS.
The input interference wave reduction circuit 2 amplifies the reception signal received by the antenna ANT, and outputs only the signal in the pass frequency band determined by the inductor value and the capacitance value of the LC circuits 13A to 13D among the amplified signals as an output signal. Output.

  The pass frequency band is obtained by selecting the corresponding amplifier (3A to 3D) according to the given selection signal, and selecting and adjusting the pass frequency band according to the adjustment signal and the fine adjustment signal from within the pass frequency region of the selected amplifier. Confirmed.

  The selection signal is a selection signal when the PLL frequency synthesizer 6 is locked (selection result of the voltage controlled oscillator), and the adjustment signal is a selection signal when the PLL frequency synthesizer 6 is locked (result of selection of the oscillation frequency). The fine adjustment signal is a fine adjustment signal (result of fine adjustment of the oscillation frequency) when the PLL frequency synthesizer 6 is locked. Therefore, the operation of selecting the amplifier to be used in the input jamming wave reduction circuit 2 is linked to the operation of selecting the voltage controlled oscillator to be used in the frequency conversion circuit 4, and the operation of the amplifier selected in the input jamming wave reduction circuit 2 is performed. The operation of selecting the pass frequency band from the pass frequency region is linked to the operation of selecting the oscillation frequency from the oscillation frequency region of the voltage controlled oscillator selected by the frequency conversion circuit 4. The operation for finely adjusting the pass frequency band selected in the input interference wave reducing circuit 2 is linked to the operation for finely adjusting the oscillation frequency selected in the frequency conversion circuit 4.

  Here, a method of determining the pass frequency band will be described in detail. In the present embodiment, the switch C1 of the LC circuit 13A is a switch for selecting the pass frequency band a1 shown in FIG. 8, and the switches C2 to C4 of the LC circuit 13A are respectively pass frequency bands a2 to a2 shown in FIG. This is a switch for selecting a4.

  For example, when the frequency corresponding to the requested channel is “f3” shown in FIG. 8, a selection signal for selecting the amplifier 3A is given to the selection circuit 12, and the adjustment is made so that the pass frequency band a1 is selected. A signal is applied to the LC circuits 13A to 13D.

  Specifically, “1” is given as the selection signal a1, and “0” is given as the selection signals b1 to d1, respectively. In this case, the switch 21A is turned on and the switch 22A is turned off. Then, a “gain control signal” is output as the selection signal a2. Therefore, the transistor QA is driven by the selection signal a2 (that is, the gain control signal). On the other hand, the switches 21B to 21D are turned OFF and the switches 22B to 22D are turned ON. Then, “zero” is output as the selection signals b2 to d2. Therefore, all of the transistors QB to QD hold the OFF state.

  Further, “1” is given as the adjustment signal to the switch C1 of the LC circuit 13A, and “0” is given as the adjustment signal to the switches C2 to C4. Then, the switch C1 is turned on and the switches C2 to C4 are turned off. Therefore, an LC circuit including the inductor L, the capacitor C1, and the varactor 23 is configured, and “1 / 2π√L (C1 + C5)” that is the center frequency of the pass frequency band a1 is obtained.

  Then, the pass frequency band is determined by changing the capacitance value C5 using the fine adjustment signal so that the center frequency of the pass frequency band a1 becomes the frequency of “f3”. The “capacitance value C5” in “½π√L (C1 + C5)” described above is the capacitance value of the varactor 23.

  By determining the pass frequency band as described above, the input interference wave reducing circuit 2 outputs only the signal within the determined pass frequency band among the received signals amplified by the selected amplifier. Therefore, the interference wave is removed by the input interference wave reduction circuit 2.

In this embodiment, the following effects can be obtained.
(1) The amplifiers 3 </ b> A to 3 </ b> D of the above embodiment have a configuration having an LC circuit. Therefore, it is possible to amplify the received signal and output only the signal within the pass frequency band determined by the inductor value and the capacitance value of the LC circuit as the output signal of the input interference wave reducing circuit. That is, the amplifiers 3A to 3D realize both an amplification function (low-noise amplifier 502 in FIG. 9) and a band-pass filter function (band-pass filter 503 in FIG. 9). Furthermore, if a plurality of amplifiers are realized with the configuration shown in FIG. 5, the increase in input capacitance is reduced, so that deterioration of frequency characteristics can be suppressed.

  (2) The input interference wave reducing circuit 2 of the above embodiment is composed of a plurality of amplifiers. Therefore, since a wide pass frequency region is covered using a plurality of amplifiers, the pass frequency region to be covered by each amplifier is narrowed, and it is not necessary to change the pass characteristics of each amplifier greatly, so that it can be formed on a semiconductor chip. The required pass characteristic can be obtained with a certain degree of element. That is, according to the configuration of the embodiment, the interference wave can be effectively removed over a wide frequency region without providing an external component as shown in FIG.

  (3) According to the radio reception circuit 1 of the above embodiment, the selection signal for selecting the amplifier (3A to 3D) to be used in the input interference wave reduction circuit 2 and the voltage controlled oscillator (to be used in the frequency conversion circuit 4) The selection signal for selecting 5A to 5D) is the same signal. Further, the adjustment signal for selecting the capacitors (C1 to C4) for determining the pass frequency band in the input interference wave reduction circuit 2 and the adjustment signal for selecting the oscillation frequency in the frequency conversion circuit 4 are the same signal. . Further, the fine adjustment signal for finely adjusting the pass frequency band in the input interference wave reducing circuit 2 and the fine adjustment signal for finely adjusting the oscillation frequency in the frequency conversion circuit 4 are the same signal. That is, the selection signal, adjustment signal, and fine adjustment signal generated to determine the frequency of the oscillation signal in the PLL frequency synthesizer 6 are commonly used in the input interference wave reduction circuit 2 and the frequency conversion circuit 4. Therefore, since the process for removing the interference wave for the request channel can be linked, the request channel can be reproduced with high accuracy.

The embodiment is not limited to the above, and may be embodied as follows, for example.
In the above-described embodiment, the interference waves are reduced by using a plurality of amplifiers 3A to 3D provided in parallel. However, each of the amplifiers 3A to 3D has a configuration in which a plurality of amplifiers are provided in multiple stages. Also good. In this case, a control signal (that is, a selection signal, an adjustment signal, a fine adjustment signal) may be given to each stage of the amplifier, or a control signal may be given to a part of the amplifiers. .

  In the above-described embodiment, the pass frequency band is finely adjusted using the varactor 23. However, the varactor 23 is not necessarily provided in a radio reception circuit that does not require fine adjustment. That is, the pass frequency band may be obtained only by selecting the amplifiers 3A to 3D and selecting the capacitors C1 to C4.

  In the above embodiment, it is determined whether or not to lock in order from the lowest frequency. However, the present invention is not limited to this, and it may be determined whether or not to lock in order from the highest frequency. It may be determined whether or not to lock.

  In the radio reception circuit 1 having the above-described configuration, an attenuator (ATT) may be provided before the input interference wave reduction circuit 2. An amplifier may be provided between the input interference wave reducing circuit 2 and the frequency conversion circuit 4. Further, an IF amplifier and / or a fixed band-pass filter for amplifying the intermediate frequency signal may be provided at the subsequent stage of the frequency conversion circuit 4.

In the above embodiment, the configuration includes four amplifiers and four voltage controlled oscillators, but the number of these is not particularly limited.
In the above embodiment, the frequency conversion circuit 4 converts the high frequency signal into the intermediate frequency signal, but the present invention is not limited to this. That is, the frequency conversion circuit 4 may convert the received signal into a baseband frequency signal or may up-convert the received signal.

It is a figure which shows the structure of the radio | wireless receiving circuit concerning embodiment of this invention. It is a figure which shows the structure of a PLL frequency synthesizer. It is a figure which shows the structure of the VCO circuit with which a PLL frequency synthesizer is provided. It is a figure explaining operation | movement of a PLL frequency synthesizer. It is a figure which shows the structure of an input jamming wave reduction circuit. It is an Example of the selection circuit with which an input disturbance wave reduction circuit is provided. It is an Example of the adjustment circuit with which an input disturbance wave reduction circuit is provided. It is a figure explaining operation | movement of an input jamming wave reduction circuit. It is a figure which shows an example of the conventional radio | wireless receiving circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Radio reception circuit 2 Input interference wave reduction circuit 3A-3D Amplifier 4 Frequency conversion circuit 5 VCO circuit 5A-5D Voltage control oscillator 6 PLL frequency synthesizer 7 Mixer 8 AGC circuit 11 Current source 12 Selection circuit 13A-13D Adjustment circuit 14 Selector 23 Varactor 31 Adjustment unit 32 Fine adjustment unit 33 Selection circuit 34 Selector 56 Control circuit

Claims (8)

A radio reception circuit including an input disturbance wave reduction circuit and a frequency conversion circuit,
The input interference wave reducing circuit includes a plurality of amplifiers that amplify a received signal and have different pass frequency regions, and a first selection unit that selects an amplifier to be used from the plurality of amplifiers,
The frequency conversion circuit includes a plurality of voltage controlled oscillators having different oscillation frequency ranges, a second selecting unit that selects a voltage controlled oscillator to be used from the plurality of voltage controlled oscillators, and the second selecting unit. A mixer that multiplies the output signal of the input interference wave reduction circuit by an oscillation signal obtained by using the output signal of the selected voltage controlled oscillator;
The second selection means selects a voltage controlled oscillator according to a channel selection request,
The radio receiving circuit, wherein the first selection unit selects a corresponding amplifier according to a selection signal representing a selection result by the second selection unit. Each of the plurality of amplifiers includes an LC circuit including an inductor and a capacitor,
The radio reception circuit according to claim 1, wherein the pass frequency region is determined by an inductor value and a capacitance value of the LC circuit. The LC circuit includes a plurality of the capacitors,
Each of the plurality of voltage controlled oscillators includes an adjustment circuit for selecting an oscillation frequency from the oscillation frequency region,
The amplifier selected by the first selection unit is selected by selecting a capacitor to be connected to the inductor in accordance with an adjustment signal representing an adjustment result in the adjustment circuit included in the voltage control oscillator selected by the second selection unit. The radio reception circuit according to claim 2, wherein a pass frequency band to be used is selected from a pass frequency region. The LC circuit includes first fine adjustment means for finely adjusting the pass frequency band,
The adjustment circuit includes second fine adjustment means for finely adjusting the oscillation frequency,
The said 1st fine adjustment means fine-adjusts the said pass frequency band according to the fine adjustment signal showing the result of the fine adjustment in the said 2nd fine adjustment means. The Claim 2 or Claim 3 characterized by the above-mentioned. Wireless receiver circuit. The wireless reception circuit according to claim 4, wherein the first fine adjustment means is a varactor that changes a capacitance value of the LC circuit. A plurality of amplifiers;
Selecting means for selecting an amplifier to be used from the plurality of amplifiers in response to a channel selection request;
An input jamming wave reduction circuit comprising:
Each of the plurality of amplifiers includes an LC circuit including an inductor and a capacitor. The input interference wave reduction circuit according to claim 6, wherein the LC circuit includes a plurality of the capacitors and selects a capacitor to be connected to the inductor. The input interference wave reducing circuit according to claim 7, wherein the LC circuit includes a varactor for finely adjusting a capacitance value.

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