JP2008228021A - Solid-state imaging device and imaging device - Google Patents

Abstract

An appropriate signal output level is ensured by correcting a decrease in signal output level accompanying a read time difference caused by a focal plane method.
A bias voltage applied to a read transistor can be variably adjusted for each pixel row by an applied voltage generation circuit, and an applied voltage level in each pixel row is slow to read from a pixel row that is read quickly. It is controlled so as to gradually decrease as it goes to the pixel row. Therefore, by appropriately adjusting the voltage applied to the read transistor 12 in each pixel row, the capacitance of the photodiode in each pixel row is changed, and the decrease in the accumulated electrons in each photodiode is offset, resulting in a time difference in read timing. It is possible to absorb an error in the output level of the pixel signal and obtain a uniform output over the entire screen.
[Selection] Figure 3

Description

  The present invention relates to a solid-state imaging device and an imaging device that sequentially scan pixels that are two-dimensionally arranged as in a CMOS image sensor in the pixel column direction in units of pixel rows, and read signals from the pixels.

In recent years, amplification-type solid-state imaging devices represented by CMOS image sensors have been actively developed, and are used in various camera devices and mobile phones.
In general, a CMOS image sensor is provided with an imaging region composed of a pixel array portion in which a plurality of pixels including photodiodes are arranged in a two-dimensional direction on a single semiconductor substrate, and a peripheral circuit region formed outside the imaging region. It is a thing.

  In the imaging region, a signal charge corresponding to the amount of received light is generated for each pixel of the pixel array unit, and a photodiode to be accumulated and a readout transistor that reads the signal charge of the photodiode to an FD (floating diffusion) unit (Transfer gate), an amplification transistor that generates a pixel signal corresponding to the potential of the FD, a selection transistor that selects a pixel that outputs the pixel signal, and various pixel transistors such as a reset transistor that resets the FD, The signal charge detected by the pixel photodiode is converted into a pixel signal by driving each pixel transistor, and output from a signal line provided for each pixel column.

Further, in the peripheral circuit region, a drive control circuit that controls reading of pixel signals by supplying various control pulses to the pixel array unit, a signal processing circuit that performs various signal processing on the read pixel signals, A power supply control circuit for generating a drive power supply is provided.
A laminated film such as an insulating film, a transistor driving electrode film, a wiring film, and a light shielding film is sequentially formed on the semiconductor substrate, and a color filter, a microlens, and the like are further formed through a planarization film.
In such a CMOS image sensor, the signal charge accumulated in the photodiode of each pixel is converted into a pixel signal for each pixel by driving each pixel transistor, and this is output for each pixel column and is output to the signal processing circuit in the subsequent stage. Send, noise removal, signal processing, etc., and output.

As the photodiode, for example, a photodiode having an HAD structure in which an N-type ion region is provided in a P-type well region formed in an upper layer of a silicon substrate and a P-type ion region is provided on the surface thereof is employed. .
The read transistor is arranged in a state where one of the source / drain regions is shared with the photodiode region, and the FD portion is shared by the source / drain region of the read transistor, the source / drain region of the reset transistor, and the FD portion. It is formed with a structure.
When the signal charge is read from the photodiode, the reading transistor is turned on, the signal charge of the photodiode is transferred to the FD portion, and the potential fluctuation of the FD portion due to this is detected by the amplification transistor and converted into a pixel signal. . When resetting the signal charge, the reset transistor is turned on to connect the FD portion to the power supply potential.

By the way, in the CMOS image sensor as described above, all pixels are exposed collectively by operations such as various shutters, signal charges are accumulated in the photodiodes of each pixel, and then the pixel array unit is sequentially scanned in units of pixel rows. Then, the readout transistor of each pixel is turned on to read out the signal charge and output from the amplification transistor to the vertical signal line provided for each pixel column.
Such a characteristic operation of the CMOS image sensor is sometimes called a so-called focal plane method or focal plane reading. Therefore, in the following explanation, the term “focal plane” is used for explanation.
(For example, see Patent Document 1)
JP 2004-140479 A

However, in the conventional CMOS image sensor employing the focal plane method, there is a time difference from the first row readout period to the last row readout period of the pixel array unit.
For example, it is assumed that a focal plane read operation is performed after exposure of the pixel array unit is performed for a predetermined period using a mechanical shutter, a flashlight, or the like.
FIG. 6 is an explanatory diagram showing the readout operation in this case, and shows the operation of starting the readout from the first row of the pixel array section after the vertical blanking period and sequentially executing the readout until the last row. Yes.

By the way, in such an operation, when the photodiode is saturated during the exposure period, the charge accumulated in the photodiode gradually leaks to the floating diffusion part or the substrate deep part side from the end of exposure to the readout period of each row. It will follow.
Due to the time difference between the reading of the first row and the reading of the last row, the amount of leakage of the photodiodes of the first row is small, and the amount of leakage of the photodiodes increases as approaching the last row.
For this reason, when the exposure period and the readout period are provided independently using a mechanical shutter or the like, there is a problem that the signal output level decreases as it approaches the last line as compared to the signal output level of the first line.

FIG. 7 is an explanatory diagram showing the operation in this case, and shows how the signal output level gradually decreases as it advances from the first row to the last row.
Such a phenomenon is a problem that particularly occurs in a digital still camera that captures a still image with a large number of pixels.

  Therefore, the present invention corrects a decrease in the signal output level caused by the read time difference caused by the focal plane method, can ensure an appropriate signal output level, and can obtain an accurate imaging signal, and an imaging An object is to provide an apparatus.

  In order to achieve the above object, a solid-state imaging device of the present invention includes a pixel array unit in which a plurality of pixels each including a photoelectric conversion unit and a readout gate are arranged in a two-dimensional array, and photoelectric conversion of each pixel in the pixel array unit. And a shutter unit that simultaneously performs signal charge accumulation operation according to a predetermined exposure period, and scans each pixel that accumulates the signal charge in a pixel column direction in a pixel row unit, and reads out a gate for each pixel row. Scanning means for sequentially reading signal charges accumulated in the photoelectric conversion unit of each pixel by controlling on / off of the pixel, and applying to the readout gate in response to a decrease in the accumulated charge level occurring during the signal charge readout period. Voltage control means for variably controlling the voltage to be applied.

  Moreover, the imaging device of the present invention includes an imaging unit using a solid-state imaging device, a control unit that controls the imaging unit, and an operation unit that operates the imaging unit. A signal charge accumulation operation is simultaneously performed for a pixel array unit in which a plurality of pixels including a conversion unit and a readout gate are arranged in a two-dimensional array and a photoelectric conversion unit of each pixel of the pixel array unit with a predetermined exposure period. Each pixel row in which the signal charge is stored is scanned in the pixel column direction, and the readout gate is sequentially turned on / off for each pixel row and stored in the photoelectric conversion unit of each pixel. Scanning means for sequentially reading out signal charges, and voltage control means for variably controlling the voltage applied to the readout gate in response to a decrease in the accumulated charge level generated during the period of reading out the signal charges. To.

  According to the solid-state imaging device and the imaging device of the present invention, it is possible to prevent a decrease in output from the first row to the last row caused by leakage of signal charges from the photoelectric conversion unit when an object is imaged by the focal plane method. Therefore, uniform output can be obtained over the entire screen, and the image quality can be improved.

FIG. 1 is a plan view showing a specific example of a solid-state imaging device in an embodiment of the present invention, and shows an example of a CMOS image sensor. FIG. 2 is a circuit diagram showing a circuit configuration in a pixel of the solid-state imaging device shown in FIG.
As shown in FIG. 1, the solid-state imaging device of the present embodiment includes a pixel array unit 20 that forms an imaging region by a plurality of pixels 16 arranged in a two-dimensional direction, and each pixel of the pixel array unit 20 is arranged in the vertical direction. A vertical scanning circuit 21 that scans and controls a pixel signal reading operation, a load MOS transistor circuit 24 that controls a vertical signal line 28 led from each pixel column of the pixel array unit 20, and a pixel array unit 20 A CDS circuit 26 that takes in pixel signals read from each pixel column and removes noise by correlated double sampling processing, a horizontal selection transistor circuit 26 that outputs pixel signals of the CDS circuit 26 to a horizontal signal line 27, A horizontal scanning circuit 22 for sequentially selecting the horizontal selection transistor circuit 26 in the horizontal direction and controlling the output of the pixel signal.
The pixel signal output to the horizontal signal line 27 is transmitted to the subsequent circuit through the buffer amplifier.

Further, as shown in FIG. 2, each pixel 16 includes a photodiode (PD) 1 that photoelectrically converts incident light, and a floating diffusion (FD) based on a transfer pulse (ΦTRG) of the photoelectrically converted electric signal. A read transistor (TG) 12 transferred to the unit 3; a reset transistor (RST) 14 that resets the potential of the FD unit 3 to the power supply voltage VDD based on a reset pulse (ΦRST); It has an amplification transistor (AMP) 13 that converts it into a current signal, and a selection transistor 15 that connects the output of the amplification transistor 13 to a vertical signal line 28 based on the selection signal (ΦSEL).
Therefore, in the vicinity of the pixel 16, a vertical signal line 28, a power supply line 23, and the like are wired in the vertical direction, and a readout line 17, a reset line 18, a selection line 19, and the like are wired in the horizontal direction.

FIG. 3 is an explanatory diagram showing the relationship between the change in the applied voltage of the readout transistor and the change in the capacitance of the photodiode with respect to the focal plane readout operation of the pixel array section.
FIG. 3A schematically shows the arrangement of the pixel array unit 20, the vertical scanning circuit 21, and the horizontal scanning circuit 22.
In this example, the bias voltage applied to the read transistor (read gate) 12 (that is, the applied voltage when the read gate is off) can be variably adjusted for each pixel row by the applied voltage generation circuit (voltage control means) 30. Thus, as shown in FIG. 3B, the applied voltage level in each pixel row is controlled so as to gradually decrease from the pixel row with early readout to the pixel row with late readout.

Then, due to such a change in the voltage applied to the readout transistor, the apparent capacitance of the photodiode is gradually increased from a pixel row with fast readout to a pixel row with slow readout as shown in FIG. Going bigger.
On the other hand, since the electrons accumulated in the photodiode gradually leak with the passage of time from the exposure operation, the electrons gradually decrease from the pixel row that is read quickly to the pixel row that is read slowly.

  Therefore, in this embodiment, by appropriately adjusting the voltage applied to the read transistor 12 in each pixel row, the capacitance of the photodiode in each pixel row is changed, and the decrease in accumulated electrons in each photodiode is offset. It is possible to absorb an error in the output level of the pixel signal due to a time difference in readout timing and obtain a uniform output over the entire screen.

The voltage applied to the readout transistor can be controlled by, for example, a level shifter using a charge pump circuit or the like provided for each pixel row.
FIG. 4 is a circuit diagram showing a configuration example of a charge pump circuit that can be used in the applied voltage generation circuit in this embodiment.
This charge pump circuit includes an oscillation circuit 301, an amplifier 302, switches SW1 to SW4, voltage dividing resistors (output voltage setting unit 307) R1, R2, a pump capacitor (pump capacity) C _P , an output capacitor C _OUT , and an inverter 303. , A phase compensation circuit 304, a control circuit 305, a reference voltage source 306, and the like.

First, the control circuit 305 generates a pulse signal based on the frequency signal from the oscillation circuit 301, supplies the pulse signal to the switches SW1 and SW3, and sends the inverted pulse signal to the switches SW2 and SW4 via the inverter 303. Supply.
This switching operation, the capacitor _{C P} pump is charged by the power supply voltage via a switch SW1, SW3, the charge voltage is supplied to the output capacitor _{C OUT} via the switch SW2. In the output capacitor C _OUT, the output of capacitor C _P pump smoothes and outputs a voltage output VOUT.
The voltage output VOUT from the output capacitor C _OUT is divided by resistors R 1 and R 2 and input to the amplifier 302. The amplifier 302 supplies an error signal between the divided voltage and the reference voltage to the control circuit 305, and the control circuit 305 generates an output voltage control signal corresponding to the error signal and supplies the output voltage control signal to the switch SW4. Control.

By providing such a level shifter by the charge pump circuit for each pixel row and supplying it as the applied voltage of the read transistor for each pixel row, the operation as shown in FIG. 3 can be obtained.
Such a level shifter for the read transistor is also used in a conventional CMOS image sensor for the purpose of optimizing the level of the transfer pulse, for example, and the temperature of the read transistor is compensated by such a level shifter. Various configurations have also been proposed.
Therefore, by using such a level shifter, it can be used as means for adjusting the applied voltage level at the time of off described in the present embodiment, and can be realized without significant hardware changes. .
Also, other configurations can be used as the applied voltage generating circuit, and it is needless to say that the applied voltage generating circuit is not limited to the above example of the charge pump circuit.

With the configuration as in the present embodiment as described above, it is possible to prevent a decrease in output from the first line to the last line caused by leakage of electrons from the photodiode when capturing a still image using a mechanical shutter or the like.
Therefore, for example, even when a still image is captured by a multi-pixel still camera using a mechanical shutter or the like, a uniform output can be obtained on the entire screen, and a high-quality still camera can be provided. Note that the functions realized in this embodiment are applicable not only to a still camera but also to a video camera.

  The specific embodiments of the solid-state imaging device according to the present invention have been described above, but the present invention can be further modified in various ways. For example, in the above embodiment, the description is given on the assumption that four transistors (reading, reset, amplification, and selection) are provided in one pixel. For example, a three-transistor configuration in which the selection transistor is omitted, A five-transistor configuration having two transistors for row selection and column selection has also been proposed, and the present invention can be applied to any method.

  The solid-state imaging device is not limited to an image sensor or the like configured on one chip, and may be a module in which an imaging unit, a signal processing unit, and an optical system are packaged together. Moreover, the apparatus utilized for a camera system or a mobile telephone device may be used. In the present invention, a configuration having a CMOS image sensor function alone is called a solid-state imaging device, and the solid-state imaging device and other elements (control circuit, operation unit, display unit, data storage function, communication function, etc.) An integrated configuration is referred to as an imaging device.

Hereinafter, a specific example of an imaging apparatus to which the present invention is applied will be described.
FIG. 5 is a block diagram showing a configuration example of a camera apparatus using the CMOS image sensor of this example.
In FIG. 5, an imaging unit 410 performs imaging of a subject using, for example, the CMOS image sensor shown in FIG. 1, and outputs an imaging signal to a system control unit 420 mounted on the main board.
That is, the imaging unit 410 performs processing such as AGC (automatic gain control), OB (optical black) clamping, CDS (correlated double sampling), A / D conversion on the output signal of the above-described CMOS image sensor, and performs digital processing. An imaging signal is generated and output.

In this example, an example in which an imaging signal is converted into a digital signal and output to the system control unit 420 in the imaging unit 410 is shown. However, an analog imaging signal is sent from the imaging unit 410 to the system control unit 420, and the system The control unit 420 may convert to a digital signal.
In addition, various methods have been conventionally provided for specific control operations, signal processing, and the like in the imaging unit 410, and of course, there is no particular limitation in the imaging apparatus of the present invention.

  The imaging optical system 400 includes a zoom lens 401 and a diaphragm mechanism 402 disposed in a lens barrel, and forms a subject image on the light receiving unit of the CMOS image sensor. Under the control of the drive control unit 430 based on this, each part is mechanically driven to perform control such as autofocus.

The system control unit 420 includes a CPU 421, a ROM 422, a RAM 423, a DSP 424, an external interface 425, and the like.
The CPU 421 uses the ROM 422 and the RAM 423 to send instructions to each part of the camera apparatus and controls the entire system.
The DSP 424 performs various signal processing on the imaging signal from the imaging unit 410 to generate a still image or moving image video signal (for example, a YUV signal) in a predetermined format.
The external interface 425 is provided with various encoders and D / A converters, and with external elements (in this example, the display 430, the memory medium 440, and the operation panel unit 450) connected to the system control unit 420. Various control signals and data are exchanged.

The display 430 is a small display such as a liquid crystal panel incorporated in the camera apparatus, and displays a captured image. In addition to the small display device incorporated in such a camera device, it is of course possible to transmit the image data to an external large display device for display.
The memory medium 440 can appropriately store images taken on, for example, various memory cards, and can replace the memory medium with the memory medium controller 441, for example. As the memory medium 440, in addition to various memory cards, a disk medium using magnetism or light can be used.
The operation panel unit 450 is provided with input keys for the user to give various instructions when performing a shooting operation with the camera apparatus. The CPU 421 monitors an input signal from the operation panel unit 450, Various operation controls are executed based on the input contents.

  By applying the solid-state imaging device of the present invention to such a camera device, a high-quality imaging device can be provided. In the above configuration, unit devices and unit modules as system components, a combination method, a set size, and the like can be appropriately selected based on the actual state of commercialization and the like. The device shall include a wide variety of variations.

In the solid-state imaging device and imaging device of the present invention, the imaging target (subject) is not limited to a general image such as a person or a landscape, but a special fine image pattern such as a counterfeit bill detector or a fingerprint detector. It can also be applied to.
The apparatus configuration in this case is not the general camera apparatus shown in FIG. 5, but further includes a special imaging optical system and a signal processing system including pattern analysis. In this case as well, the operational effects of the present invention are included. This makes it possible to realize accurate image detection.
Furthermore, when configuring a remote system such as telemedicine, security monitoring, personal authentication, etc., it is also possible to configure the device configuration including a communication module connected to the network as described above, and a wide range of applications can be realized. It is.

It is a top view which shows the specific example of the solid-state imaging device in the Example of this invention. FIG. 2 is a circuit diagram showing a circuit configuration in a pixel of the solid-state imaging device shown in FIG. 1. It is explanatory drawing which shows the relationship between the change of the applied voltage of the read transistor with respect to the focal plane read-out operation | movement of a pixel array part, and the capacitance change of a photodiode. FIG. 4 is a circuit diagram showing an example of a charge pump circuit that can be used in the CMOS image sensor shown in FIG. 3. It is a block diagram which shows the structural example of the camera apparatus in the other Example of this invention. It is explanatory drawing which shows the focal plane read-out operation | movement of a CMOS image sensor. It is explanatory drawing which shows the reduction | decrease in the output signal level in the conventional CMOS image sensor.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Photodiode, 3 ... FD part, 12 ... Read-out transistor, 13 ... Amplification transistor, 14 ... Reset transistor, 15 ... Selection transistor, 16 ... Pixel, 20 ... Pixel array part, 21 ... ... vertical scanning circuit, 22 ... horizontal scanning circuit, 30 ... applied voltage generation circuit.

Claims (6)

A pixel array unit in which a plurality of pixels each including a photoelectric conversion unit and a readout gate are arranged in a two-dimensional array;
Shutter means for causing the photoelectric conversion units of the respective pixels of the pixel array unit to perform signal charge accumulation operation all at once in a predetermined exposure period;
Each pixel in which the signal charge is accumulated is scanned in the pixel column direction in units of pixel rows, and the signal charge accumulated in the photoelectric conversion unit of each pixel is sequentially read out by sequentially controlling the on / off of the readout gate for each pixel row. Scanning means;
Voltage control means for variably controlling the voltage applied to the readout gate in response to a decrease in the accumulated charge level that occurs during the readout period of the signal charge;
A solid-state imaging device.   2. The solid-state imaging device according to claim 1, wherein the voltage control unit gradually decreases the voltage applied to the read gate in response to a decrease in the accumulated charge level that occurs during a period in which the signal charge is read.   2. The solid-state imaging device according to claim 1, wherein the voltage control means is a charge pump. An imaging unit using a solid-state imaging device, a control unit that controls the imaging unit, and an operation unit that operates the imaging unit,
The solid-state imaging device
A pixel array unit in which a plurality of pixels each including a photoelectric conversion unit and a readout gate are arranged in a two-dimensional array;
Shutter means for causing the photoelectric conversion units of the respective pixels of the pixel array unit to perform signal charge accumulation operation all at once in a predetermined exposure period;
Each pixel in which the signal charge is accumulated is scanned in the pixel column direction in units of pixel rows, and the signal charge accumulated in the photoelectric conversion unit of each pixel is sequentially read out by sequentially controlling the on / off of the readout gate for each pixel row. Scanning means;
Voltage control means for variably controlling the voltage applied to the readout gate in response to a decrease in the accumulated charge level that occurs during the readout period of the signal charge;
An imaging device comprising:   5. The image pickup apparatus according to claim 4, wherein the voltage control unit gradually decreases the voltage applied to the read gate in response to a decrease in the accumulated charge level that occurs during a period in which the signal charge is read.   5. The imaging apparatus according to claim 4, wherein the voltage control means is a charge pump.

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