JP2008227037A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

To provide a semiconductor device including a transistor having a recess channel structure having a structure suitable for mass production even when high integration and fine structure of a semiconductor device typified by a DRAM or the like progress.
A selective epitaxial silicon layer grown on a part of a surface of a semiconductor silicon substrate; and a source region and a drain region corresponding to a gate electrode;
The source region is formed in a surface region of the semiconductor silicon substrate;
The semiconductor device, wherein the drain region includes the selective epitaxial silicon layer and an asymmetric transistor having a recess channel structure formed in a surface region of the semiconductor silicon substrate below the selective epitaxial silicon layer.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including an asymmetric transistor having a recessed channel structure and a manufacturing method thereof.

2. Description of the Related Art Conventionally, many field effect transistors have been adopted as memory cell transistors mounted on semiconductor devices typified by DRAM (Dynamic Random Access Memory). This field effect transistor has a source / drain region formed in a surface region of a semiconductor silicon substrate, a gate insulating film formed on the semiconductor silicon substrate, and a gate electrode formed through the gate insulating film. Is.
As knowledge about the source / drain regions formed in the surface region of the semiconductor silicon substrate, by forming the source region of the memory cell transistor deeply, it is possible to suppress the occurrence of junction leakage current, and to maintain DRAM data, etc. It is known that the refresh characteristics and the like can be improved.

On the other hand, when mass-producing semiconductor devices typified by a DRAM or the like, the source / drain regions are simultaneously formed by an ion implantation process for the surface region of the semiconductor silicon substrate. For this reason, when the ion implantation energy in the ion implantation step is increased, the N-type impurity such as implanted phosphorus spreads in the channel direction, and the memory cell transistor characteristics such as the short channel effect are deteriorated.
In order to prevent this short channel effect or the like, it is necessary to secure a distance between the source region and the drain region, that is, a channel length of the memory cell transistor at a certain level or more.

However, if the channel length is secured above a certain level, there is a limit to miniaturization of the memory cell transistor itself, which causes a problem that it is difficult to achieve high integration and fine structure of the semiconductor device.
In order to cope with this problem, a memory cell transistor 230 shown in FIG. 14 has been proposed.
Specifically, as shown in FIG. 14, a semiconductor device including a memory cell transistor 230 in which the depth of the source region 2 provided in the semiconductor silicon substrate 1 is formed deeper than the depth of the drain region 3 is mounted. It has been proposed (Patent Document 1).
JP 2000-353792 A

However, in the case of the memory cell transistor 230 shown in FIG. 14, it is necessary to separately perform ion implantation processes for the source region 2 and the drain region 3 in the process of manufacturing the memory cell transistor 230.
At this time, in order to make the depth of the drain region 3 shallower than the depth of the source region 2, it is necessary to reduce the ion implantation amount to the source region 2, but the ion implantation amount to the source region 2 is constant. If the value is lower than, problems such as failure of the memory cell transistor to operate normally occur.
Even if the ion implantation amount does not fall below a certain amount, if a small amount of ion implantation is performed, the implantation amount is likely to vary due to the influence of the manufacturing environment as compared with the case where a large amount of ion implantation is performed. There is a problem.
Further, with the high integration and fine structure of the semiconductor device, it is not easy to accurately control the amount ratio of ion implantation to the source region and the drain region, and the manufacturing conditions for manufacturing the semiconductor device are not easy. There were problems in mass production, such as narrowing the selection range.

  An object of the present invention is to easily and accurately set the amount ratio of ion implantation with respect to the source region and the drain region even when the semiconductor device represented by a DRAM or the like is highly integrated and finely structured. An object of the present invention is to provide a semiconductor device including a transistor having a recess channel structure having a structure suitable for mass production that can be controlled, and a method for manufacturing the semiconductor device.

  As a result of intensive studies to solve the above problems, the present inventor, among semiconductor devices including a transistor having a recess channel structure, one of the source region and the drain region corresponding to the transistor having the recess channel structure. A semiconductor device including a transistor having a recess channel structure in which a selective epitaxial silicon layer is formed on the drain region side and the drain region is formed in the selective epitaxial silicon layer or the like is suitable for the purpose of the present invention. The headline and the present invention were completed.

That is, the present invention
[1] a semiconductor silicon substrate;
A selective epitaxial silicon layer grown on a part of the surface of the semiconductor silicon substrate;
A recess formed in the semiconductor silicon substrate;
A gate insulating film formed in contact with the recess;
A gate electrode formed in contact with the gate insulating film;
And at least a source region and a drain region including a pair of N-type diffusion layers corresponding to the gate electrode,
The source region is formed in a surface region of the semiconductor silicon substrate;
The drain region is formed in a surface region of the semiconductor silicon substrate below the selective epitaxial silicon layer and the selective epitaxial silicon layer,
An asymmetric transistor having a recessed channel structure;
A semiconductor device including the above is provided.

The present invention also provides:
[2] The depth of the source region with respect to the surface of the semiconductor silicon substrate;
The semiconductor device including an asymmetric transistor having a recess channel structure according to the above [1], wherein the depth of the drain region with respect to the surface of the selective epitaxial silicon layer is substantially equal. Is.

The present invention also provides
[3] A step (1) of forming a recess in the semiconductor silicon substrate.
A step (2) of forming a gate insulating film in contact with the recess;
Forming a gate electrode in contact with the gate insulating film (3);
A step (4) of growing a selective epitaxial silicon layer on the surface of one of the semiconductor silicon substrates separated by the recess by a selective epitaxial growth method; and
Of the semiconductor silicon substrates separated by the recess,
The selective epitaxial silicon layer grown on the surface of the semiconductor silicon substrate on one side;
The surface region of the semiconductor silicon substrate on the other side;
(5) forming a drain region and a source region by implanting N-type impurities into both
The present invention provides a method of manufacturing a semiconductor device including an asymmetric transistor having a recess channel structure.

The present invention also provides:
[4] After forming an insulating film on the upper surface of the semiconductor silicon, the upper surface of the gate electrode and the side surface of the gate electrode, an opening is formed in the insulating film at a position where the selective epitaxial silicon layer is formed, and then the step ( 4)
Subsequently, the step (5) is performed after an opening is formed in the insulating film at a position where the source region is formed. The asymmetric type having a recess channel structure according to the above [3] A method for manufacturing a semiconductor device including a transistor is provided.

The present invention also provides:
[5] A semiconductor device including an asymmetric transistor having a recessed channel structure obtained by the manufacturing method according to [3] or [4] is provided.

The present invention also provides:
[6] An electronic apparatus including a semiconductor device including an asymmetric transistor having a recessed channel structure according to any one of [1], [2], and [5] is provided.

  According to the present invention, the amount ratio of ion implantation with respect to the source region and the drain region can be easily and accurately even when high integration and fine structure of a semiconductor device typified by a DRAM or the like has progressed. A semiconductor device including a transistor having a recessed channel structure suitable for mass production, which can be controlled, and a manufacturing method thereof can be provided.

The semiconductor device of the present invention will be described below with reference to the drawings.
FIG. 1 is a schematic cross-sectional view of an essential part illustrating an embodiment of a semiconductor device of the present invention.
As illustrated in FIG. 1, an element isolation film 30 is formed on the surface region 20 of the semiconductor silicon substrate 1.
Here, the surface region of the semiconductor silicon substrate 1 refers to an active region in the vicinity of the surface of the semiconductor silicon substrate 1 for forming a semiconductor element such as an asymmetric transistor having a recess channel structure, or for partitioning these semiconductor elements. It means an inactive region near the surface of the semiconductor silicon substrate 1.
The semiconductor silicon substrate 1 is made of single crystal silicon containing p-type impurities such as boron, and is available as a commercial product.

An asymmetric transistor 200 having a recessed channel structure is formed on the semiconductor silicon substrate 1.
The asymmetric transistor 200 having the recess channel structure is formed by forming a recess 100 formed in the semiconductor silicon substrate 1, a gate insulating film 5 provided in contact with the recess 100, and a contact with the gate insulating film 5. A gate electrode 6 is provided.

The gate insulating film 5 is made of silicon oxide or the like.
The gate electrode 6 is made of polysilicon 60 containing a p-type impurity such as boron or an N-type impurity such as phosphorus, a metal 62 such as tungsten, or the like.
An insulating film 64 made of silicon nitride or the like is formed on the gate electrode 6. A side wall 66 made of silicon nitride or the like is formed in contact with the gate electrode 6, and the gate electrode 6 is insulated from the cell contact 70 and the bit contact 72. Reference numeral 74 denotes an interlayer insulating film made of silicon oxide or the like.
Further, upper structures (not shown) such as capacitors and bit lines are formed above the cell contacts 70 and the bit contacts 72.

A selective epitaxial silicon layer 40 is grown on a part of the surface of the semiconductor silicon substrate 1.
A source region 2 and a drain region 3 including a pair of N-type diffusion layers corresponding to the gate electrode are formed on both sides of the gate electrode 6. The drain region 3 includes the selective epitaxial silicon layer 40 and the drain region 3. It is formed in the surface region 20 of the semiconductor silicon substrate 1 below the selective epitaxial silicon layer 40.
The source region 2 is formed in the surface region 20 of the semiconductor silicon substrate 1.

As described above, in the asymmetric transistor 200 having a recess channel structure used in the present invention, the selective epitaxial silicon layer 40 is formed at a position corresponding to the drain region 3 in the semiconductor silicon substrate 1. Since the selective epitaxial silicon layer 40 is not formed at a position corresponding to the source region 2, it has an asymmetric structure as a whole.
With this asymmetric structure, the asymmetric transistor 200 having the recess channel structure can alleviate the influence of the junction electric field in the source region.
As a result, when the asymmetric transistor 200 having a recessed channel structure is applied to a DRAM, the refresh characteristics can be improved.
Further, by having the asymmetric structure and the recess 100, the asymmetric transistor 200 having the recess channel structure has a large distance between the source region 2 and the drain region 3, that is, a channel length. Therefore, short channel effects such as deterioration of subthreshold characteristics can be suppressed as compared with the case where the selective epitaxial silicon layer 40 does not exist.

  The semiconductor device of the present invention can be used for applications such as DRAM (Dynamic Random Access Memory), and can be suitably used for various electronic devices such as computers and communication devices in the electronic / electric field.

  EXAMPLES Next, although this invention is demonstrated in detail based on an Example, this invention is not limited at all by these Examples.

FIG. 2 is a process sectional view for explaining the semiconductor device manufacturing method according to the first embodiment of the present invention.
As shown in FIG. 2, an element isolation film 30 made of silicon oxide having a width of 200 nm and a depth of 250 nm is formed on a predetermined surface region 20 of the p-type semiconductor silicon substrate 1.

Subsequently, an insulating film 50 made of silicon nitride is formed on the surface of the p-type semiconductor silicon substrate 1.
The insulating film 50 made of silicon nitride is usually deposited using a low pressure CVD method. By using dichlorosilane and ammonia as source gases, the insulating film 50 made of silicon nitride can be formed.

Next, a photoresist layer is formed on the surface of the insulating film 50 made of silicon nitride.
A photoresist pattern 52 is formed on the photoresist layer by forming an opening pattern by a known lithography method. Then, using the photoresist pattern 52 as a mask, an opening 54 is formed in the insulating film 50 made of silicon nitride.

FIG. 3 is a process sectional view for explaining a process of forming a recess at a predetermined position of the p-type semiconductor silicon substrate 1. The meaning of each reference symbol is the same as in the case of FIG.
The p-type semiconductor silicon substrate 1 can be etched by a plasma etching method using, for example, a gas containing at least chlorine gas, using the previously formed photoresist pattern 52 and the insulating film 50 made of silicon nitride as a mask.
The photoresist pattern 52 often disappears during the etching, and in this case, the insulating film 50 made of silicon nitride under the photoresist pattern 52 serves as an etching mask.
If the photoresist pattern 52 remains after etching, the photoresist pattern 52 can be removed by an ashing process.
By this step, a recess 100 having a depth of 150 nm can be formed at a predetermined position of the p-type semiconductor silicon substrate 1.

FIG. 4 is a process sectional view for explaining a process of forming a gate insulating film and a gate electrode inside the recess.
First, following the step shown in FIG. 3, the resist is removed, and then the insulating film 50 made of silicon nitride is removed by etching with hot phosphoric acid. Subsequently, a gate insulating film 5 made of silicon oxide or the like is formed in contact with the inside of the recess 100. The gate insulating film 5 has a thickness of 7 nm.
Subsequently, a polysilicon 60 having a thickness of 80 nm is deposited in the recess 100.

The polysilicon 60 is usually deposited using a low pressure CVD apparatus. In addition to monosilane as a source gas, phosphine (PH ₃ ) is simultaneously supplied to cause the polysilicon 60 to contain phosphorus as an impurity.
The polysilicon 60 formed at a temperature of 580 [deg.] C. or more is in a polycrystalline state and exhibits conductivity because it is sufficiently doped with phosphorus (P).

Subsequently, a metal layer 62 is formed by depositing tungsten having a thickness of 50 nm on the polysilicon 60 by a process such as MOCVD, and an insulating film 64 made of silicon nitride having a thickness of 30 nm is further formed thereon.
The insulating film 64 made of silicon nitride can be formed by a low pressure CVD method or the like, similar to the case of the insulating film 50 made of silicon nitride described above.

FIG. 5 is a process cross-sectional view for explaining a process of forming a gate electrode included in an asymmetric transistor having a recessed channel structure on the p-type semiconductor silicon substrate 1.
Unnecessary portions of the insulating film 64 made of silicon nitride, the polysilicon 60, and the metal layer 62 can be removed through the same processes as the known lithography process and etching process described above. In this way, the structure shown in FIG. 5 can be obtained.
The polysilicon 60 and the metal layer 62 function as gate electrodes included in an asymmetric transistor having a recessed channel structure.
A polysilicon 61 and a metal layer 63 are also formed on the upper surface of the element isolation region 30.
In this embodiment, the width of the gate electrode in the cross section shown in FIG. 5 is 100 nm, and the distance between the gate electrodes is 100 nm.

FIG. 6 is a process sectional view for explaining a process of forming an insulating film 66 made of silicon nitride on the entire p-type semiconductor silicon substrate 1.
As shown in FIG. 6, an insulating film 66 made of silicon nitride is deposited on the entire p-type semiconductor silicon substrate 1.
The insulating film 66 made of silicon nitride can be formed by a low-pressure CVD method or the like, as in the case of the insulating film 50 made of silicon nitride described above.
Thus, by depositing the insulating film 66 made of silicon nitride on the entire p-type semiconductor silicon substrate 1, it is possible to prevent the selective epitaxial silicon layer from growing other than the necessary position.

FIG. 7 is a process sectional view for explaining a process of forming an opening for growing a selective epitaxial silicon layer at a predetermined position of the p-type semiconductor silicon substrate 1.
A photoresist layer is formed on the surface of the insulating film 66 made of silicon nitride.
An opening pattern is formed on the photoresist layer by a known lithography method to form a photoresist pattern 56. Using the photoresist pattern 56 as a mask, the insulating film 66 made of silicon nitride is formed by anisotropic etching. Opening 54 is formed.
By this step, the insulating film 66 made of silicon nitride at a predetermined position can be removed, and the surface of the p-type semiconductor silicon substrate 1 can be exposed.
Subsequently, if the photoresist pattern 56 remains after anisotropic etching, the photoresist pattern 56 can be removed by an ashing process.

FIG. 8 is a process sectional view for explaining a process of growing a selective epitaxial silicon layer on the p-type semiconductor silicon substrate 1.
A selective epitaxial silicon layer 40 is grown by a selective epitaxial growth method at a predetermined position on the surface of the p-type semiconductor silicon substrate 1 exposed in the previous step.
The selective epitaxial growth method is performed, for example, by carrying out the conditions of a temperature of 800 ° C. and a pressure of 20 Torr while supplying a mixed gas of dichlorosilane gas at a rate of 100 ml / min and hydrogen chloride gas at a rate of 50 ml / min. The epitaxial silicon layer 40 can be grown on the p-type semiconductor silicon substrate 1 to a height of 80 nm.
The height for growing the selective epitaxial silicon layer 40 can be appropriately selected according to the design policy of the transistor to be formed. A transistor having a large source / drain asymmetry is formed as the height is high, and a transistor having a small source / drain asymmetry is formed as the height is low.
As the normally assumed height, about 5 to 100 nm is conceivable.
In this embodiment, the height of the selective epitaxial silicon layer 40 is 80 nm.
When the height is high, the refresh characteristics of the obtained semiconductor device such as DRAM are improved, and when the height is low, the threshold voltage during operation of the obtained semiconductor device such as DRAM is stabilized.

FIG. 9 is a process sectional view for explaining a process for manufacturing the semiconductor device of the present invention.
After the formation of the selective epitaxial silicon layer 40, the entire insulating films 64 and 66 made of silicon nitride are etched back.
By this etch-back, as shown in FIG. 9, an insulating film 64 made of silicon nitride having a thickness of 150 nm and a sidewall made of silicon nitride 66 having a thickness of 30 nm can be formed on the metal layer 62. .

Subsequently, an N-type impurity such as phosphorus is ion-implanted with an acceleration energy of 60 keV as an implantation amount of 1 × 10 ¹³ / cm ² , so that the open portion of the surface of the p-type semiconductor silicon substrate 1 and the selective epitaxial silicon The surface of the layer 40 can be doped with phosphorus to form the drain region 3 and the source region 2 shown in FIG. 9, respectively.
The source region 2 is formed in the surface region 20 of the p-type semiconductor silicon substrate 1, and the junction depth from the surface of the p-type semiconductor silicon substrate is about 120 nm.
The drain region 3 is formed in the surface region 20 of the p-type semiconductor silicon substrate 1 below the selective epitaxial silicon layer 40 and the selective epitaxial silicon layer 40.
Here, the film thickness of the selective epitaxial silicon is 80 nm. The junction depth from the surface of the selective epitaxial silicon layer 40 is 120 nm, and the junction depth of the drain region 3 from the surface of the p-type semiconductor silicon substrate is about 40 nm.
Thus, the junction depth of the source region 2 with respect to the surface of the p-type semiconductor silicon substrate 1 of the asymmetric transistor having a recess channel structure included in the semiconductor device obtained by this embodiment, and the selective epitaxial silicon The junction depth of the drain region 3 with respect to the surface of the layer 40 is substantially the same.

  Further, as shown in FIG. 1, by forming a cell contact 70, a bit contact 72, an interlayer insulating film 74, and an upper wiring structure such as a capacitor, a bit line, and a plate electrode (not shown) by a known method. A semiconductor device including the asymmetric transistor 200 having a recess channel structure can be manufactured as a DRAM.

10 and 11 are process cross-sectional views for explaining a modification of the process of the first embodiment.
In the case of Example 1, ion implantation was performed after the entire insulating film 66 made of silicon nitride was etched back. In the case of Example 2, the insulation made of silicon nitride was performed after ion implantation was performed. The difference is that the entire film 66 is etched back.
Specifically, it is as follows.
If the photoresist pattern 56 remains after the step shown in FIG. 8 of the first embodiment, the photoresist pattern 56 is removed by an ashing step.
Next, the insulating film 66 made of silicon nitride at a position corresponding to the opening 54 shown in FIG. 10 is removed by a known lithography process and anisotropic etching process, and the surface of the p-type semiconductor silicon substrate 1 is exposed. .
Next, the insulating film 66 made of silicon nitride at a position corresponding to the opening 54 shown in FIG. 10 is removed by a known lithography process and anisotropic etching process, and the surface of the p-type semiconductor silicon substrate 1 is exposed. .
Subsequently, as shown in FIG. 11, N-type impurities such as phosphorus are ion-implanted with an acceleration energy of 60 keV at an implantation amount of 1 × 10 ¹³ / cm ² , thereby opening the surface of the p-type semiconductor silicon substrate 1. The drain region 3 and the source region 2 can be formed by doping the portion thus formed and the surface of the selective epitaxial silicon layer 40 with phosphorus.
Subsequently, the entire insulating films 64 and 66 made of silicon nitride are etched back.
Next, the semiconductor device including the asymmetric transistor 200 having the recess channel structure can be manufactured as a DRAM through the same process as that of the first embodiment described above.

[Comparative Example 1]
FIG. 12 is a schematic cross-sectional view of a main part of a semiconductor device including a symmetric transistor 210 having a recess channel structure manufactured by the same process as in the first embodiment except that the selective epitaxial silicon layer 40 is not formed. .
The meaning of each reference symbol is the same as in FIG.
In the case of Comparative Example 1, the acceleration energy of ions of N-type impurities such as phosphorus is increased so that the source region 2 and the drain region 3 are half the depth of the recess 100 with respect to the surface of the p-type semiconductor silicon substrate. Formed deeper than.
As a result, since the PN junction of the source region can be set deeply, the depletion layer can be relaxed without contacting the surface of the p-type semiconductor silicon substrate 1, and the junction leakage current can be reduced. Can do.
However, since the distance between the source region 2 and the drain region 3, that is, the channel length is shortened, a short channel effect such as deterioration of subthreshold characteristics was observed in the semiconductor device obtained in Comparative Example 1.

[Comparative Example 2]
FIG. 13 is a schematic cross-sectional view of a main part of a semiconductor device including a symmetric transistor 220 having a recess channel structure manufactured by the same process as in the first embodiment except that the selective epitaxial silicon layer 40 is not formed. . The meaning of each reference symbol is the same as in the case of FIG.
In the case of Comparative Example 2, the acceleration energy of ions of N-type impurities such as phosphorus is reduced, so that the source region 2 and the drain region 3 are half the depth of the recess 100 with respect to the surface of the p-type semiconductor silicon substrate. Formed shallower.
As a result, a sufficient distance between the source region 2 and the drain region 3, that is, a channel length can be secured, so that a short channel effect such as deterioration of subthreshold characteristics can be reduced in the semiconductor device obtained in Comparative Example 2. Can do.
However, the PN junction of the source region cannot be formed deeply.
For this reason, since the depletion layer is in contact with the surface of the p-type semiconductor silicon substrate 1, it becomes difficult to relax the electric field, and the junction leakage current increases, so that the refresh characteristics of the semiconductor device obtained in Comparative Example 2 are observed to deteriorate. It was done.

It is a typical principal part sectional view which illustrated one embodiment of a semiconductor device of the present invention. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device which is the 1st embodiment of this invention. It is process sectional drawing for demonstrating the process of forming a recess in the predetermined position of a semiconductor silicon substrate. It is process sectional drawing for demonstrating the process of forming a gate insulating film and a gate electrode inside a recess. It is process sectional drawing for demonstrating the process of forming a gate electrode on a p-type semiconductor silicon substrate. It is process sectional drawing for demonstrating the process of forming the insulating film which consists of silicon nitrides on the whole p-type semiconductor silicon substrate. It is process sectional drawing for demonstrating the process of forming the opening part for making a selective epitaxial silicon layer grow in the predetermined position of a p-type semiconductor silicon substrate. It is process sectional drawing for demonstrating the process of growing a selective epitaxial silicon layer on a p-type semiconductor silicon substrate. It is process sectional drawing for demonstrating the process of manufacturing the semiconductor device of this invention. FIG. 10 is a process cross-sectional view for explaining a modification of the process of the first embodiment. FIG. 10 is a process cross-sectional view for explaining a modification of the process of the first embodiment. It is a typical principal part sectional view of a semiconductor device containing symmetrical transistor 210 which has a recess channel structure (comparative example 1). It is a typical principal part sectional view of a semiconductor device containing symmetrical transistor 210 which has a recess channel structure (comparative example 2). It is a typical principal part sectional view of a semiconductor device containing a conventional memory cell transistor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor silicon substrate 2 Source region 3 Drain region 5 Gate insulating film 6 Gate electrode 20 Surface region 30 Element isolation film 40 Selective epitaxial silicon layer 50, 52, 64, 66 Insulating film made of silicon nitride 54 Opening 56 Photoresist pattern 60 , 61 Polysilicon 62, 63 Metal such as tungsten 70 Cell contact 72 Bit contact 74 Interlayer insulating film 100 Recess 200 Asymmetric transistor having a recess channel structure 210, 220 Symmetric transistor having a recess channel structure 230 Conventional memory cell transistor

Claims (6)

A semiconductor silicon substrate;
A selective epitaxial silicon layer grown on a part of the surface of the semiconductor silicon substrate;
A recess formed in the semiconductor silicon substrate;
A gate insulating film formed in contact with the recess;
A gate electrode formed in contact with the gate insulating film;
And at least a source region and a drain region including a pair of N-type diffusion layers corresponding to the gate electrode,
The source region is formed in a surface region of the semiconductor silicon substrate;
The drain region is formed in a surface region of the semiconductor silicon substrate below the selective epitaxial silicon layer and the selective epitaxial silicon layer,
An asymmetric transistor having a recessed channel structure;
A semiconductor device including: The depth of the source region relative to the surface of the semiconductor silicon substrate;
2. The semiconductor device including an asymmetric transistor having a recessed channel structure according to claim 1, wherein a depth of the drain region with respect to a surface of the selective epitaxial silicon layer is substantially equal. Forming a recess in the semiconductor silicon substrate (1);
A step (2) of forming a gate insulating film in contact with the recess;
Forming a gate electrode in contact with the gate insulating film (3);
A step (4) of growing a selective epitaxial silicon layer on the surface of one of the semiconductor silicon substrates separated by the recess by a selective epitaxial growth method; and
Of the semiconductor silicon substrates separated by the recess,
The selective epitaxial silicon layer grown on the surface of the semiconductor silicon substrate on one side;
The surface region of the semiconductor silicon substrate on the other side;
(5) forming a drain region and a source region by implanting N-type impurities into both
A method of manufacturing a semiconductor device including an asymmetric transistor having a recess channel structure, comprising: After forming an insulating film on the upper surface of the semiconductor silicon, the upper surface of the gate electrode, and the side surface of the gate electrode, an opening is formed in the insulating film at a position where the selective epitaxial silicon layer is formed, and then the step (4) is performed. Done
4. The asymmetric transistor having a recessed channel structure according to claim 3, wherein the step (5) is performed after an opening is formed in the insulating film at a position where the source region is formed. A method of manufacturing a semiconductor device including:   A semiconductor device including an asymmetric transistor having a recessed channel structure obtained by the manufacturing method according to claim 3. An electronic device on which a semiconductor device including an asymmetric transistor having a recess channel structure according to claim 1 is mounted.

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