JP2008224743A - Data driving method and apparatus for liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal panel driving method and apparatus for driving a liquid crystal panel having five color sub-pixels in one pixel.
A liquid crystal panel driving method according to the present invention is a liquid crystal panel driving method in which a plurality of first color sub-pixels arranged at the center of a pixel are spaced apart at a predetermined interval. And applying the first color data to the adjacent first color sub-pixels by short-circuiting the adjacent first color sub-pixels, and disposing at one end of the central portion within the one pixel. Applying the second color data to the plurality of second color sub-pixels, and applying the second color data to the plurality of third color sub-pixels disposed at the other end of the central portion in the one pixel. The method includes the step of applying data of three colors.
[Selection] Figure 7B

Description

  The present invention relates to a liquid crystal panel, and more particularly to a liquid crystal panel driving method for driving a liquid crystal panel having five color sub-pixels in one pixel, a driving apparatus therefor, and a liquid crystal display apparatus therefor.

  A liquid crystal display usually displays an image by adjusting the light transmittance of a liquid crystal cell according to a video signal. An active matrix type liquid crystal display device in which a switching element is formed for each liquid crystal cell is suitable for displaying a moving image. As a switching element used in an active matrix type liquid crystal display device, a thin film transistor (hereinafter referred to as “TFT”) is used.

  FIG. 1 is a block diagram of a general liquid crystal display device.

  Referring to FIG. 1, a driving device of a liquid crystal display device includes a digital video card (1) for converting analog video data into digital video data, and a data line (DL) of a liquid crystal panel (6). A data driver (3) for supplying video data to a gate driver, a gate driver (5) for sequentially driving the gate lines (GL) of the liquid crystal panel (6), and a data driver (3) And a timing controller (2) for controlling the gate driver (5).

  In the liquid crystal panel (6), liquid crystal is injected between two glass substrates, and a gate line (GL) and a data line (DL) are formed on the lower glass substrate so as to be orthogonal to each other. A TFT for selectively supplying an image input from the data line (DL) to the liquid crystal cell (Clc) is formed at the intersection of the gate line (GL) and the data line (DL). For this reason, the gate terminal of the TFT is connected to the gate line (GL), and the source terminal of the TFT is connected to the data line (DL). The TFT drain terminal is connected to the pixel electrode of the liquid crystal cell (Clc).

  The digital video card (1) converts the analog input image signal into a digital image signal suitable for the liquid crystal panel (6), and detects a synchronization signal included in the image signal.

  The timing controller (2) supplies red (R), green (G) and blue (B) digital video data from the digital video card (1) to the data driver (3). The timing controller (2) uses a horizontal / vertical synchronizing signal (H, V) input from the digital video card (1), a dot clock (Dclk), a gate start pulse (Gsp), etc. The data driver (3) and the gate driver (5) are timing-controlled by generating the data and the gate control signal. A data control signal such as a dot clock (Dclk) is supplied to the data driver (3), while a gate control signal such as a gate start pulse (Gsp) is supplied to the gate driver (5).

  The gate driver (5) includes a shift register (not shown) that sequentially generates a scan pulse in response to a gate start pulse (Gsp) input from the timing controller (2), and a voltage of the scan pulse. Is constituted by a level shift (not shown) for shifting to a level suitable for driving the liquid crystal cell (Clc). In response to the scan pulse input from the gate driver (5), video data on the data line (DL) is supplied to the pixel electrode of the liquid crystal cell (Clc) by the TFT.

  A dot clock (Dclk) is input to the data driver (3) together with digital video data of red (R), green (G) and blue (B) from the timing controller (2). The data driver (3) latches red (R), green (G) and blue (B) digital video data in synchronization with a dot clock (Dclk), and then latches the latched data with a gamma voltage ( Vγ) is corrected. The data driver (3) converts the data corrected by the gamma voltage (Vγ) into analog data and supplies it to the data line (DL) line by line.

  FIG. 2 is a diagram showing in detail the relationship between the pixel and the TFT structure of the liquid crystal display device of FIG.

  Referring to FIG. 2, the pixel of the liquid crystal display device is configured in a region partitioned by four data lines (DL1 to DL4) and two gate lines (GL1, GL2). Then, one pixel electrode (12a) is installed in a region surrounded by the gate lines (GL1, GL2) and the data lines (DL1, DL2), and this region becomes one pixel. One pixel electrode (12b) is installed in a region surrounded by the lines (GL1, GL2) and the data lines (DL2, DL3), and this region becomes one pixel, and the gate lines (GL1, GL2) One pixel electrode (12c) is provided in a region surrounded by the data lines (DL3, DL4), and this region becomes one pixel. These three pixels constitute one pixel (16) and a TFT (14) as a switching element on each side of each pixel electrode (12).

  In addition, a color filter (R, G, B) is installed on a different substrate facing the transparent substrate on which the pixel electrode is formed. In this embodiment, the left side of one pixel shown in FIG. As shown in FIG. 3, an R color filter is disposed at a position facing the pixel electrode (12a) at the stage, and a G color filter is disposed at a position facing the pixel electrode (12b) at the right stage, as shown in FIG. B color filters are respectively arranged at positions facing (12c).

  In order to display the VGA specification in this form, 640 data lines (DL) and 480 gate lines (GL) are provided, so 307200 pixels are formed on one screen.

  FIG. 3 is a diagram showing the arrangement state of the RGB color filters by the conventional liquid crystal display device shown in FIG. 1 by the connection state of the gate driver (5) and the data driver (3).

  Referring to FIG. 3, the liquid crystal display device receives 6-bus input signals (Re, Ge, Be, Ro, Go, Bo) and receives the first to nth data lines (DL1 to DLn) in synchronization with the data clock. ) Is output.

  The R signal is output to the first data line (DL1) through the data driver (3), the G signal is output to the second data line (DL2) through the data driver (3), and the B signal is output from the data driver. The data is output to the third data line (DL3) through (3). The signal repeats as a set of three outputs.

  At this time, the B signal is output to the first data line (DL1) through the data driver (3) by the line arrangement through the data driver (3), and the G signal is supplied to the second data through the data driver (3). The B signal is output to the third data line (DL3) through the data driver (3).

  A liquid crystal panel driven by a conventional liquid crystal display device employs a dot inversion method as shown in FIGS. 4A and 4B. As shown in FIGS. 4A and 4B, the dot inversion type liquid crystal panel driving method has opposite polarity data alternately in adjacent liquid crystal cells for each column line and row line on the liquid crystal panel. A signal is supplied and the polarity of the data signal supplied to all liquid crystal cells on the liquid crystal panel is reversed for each frame. In other words, when the video signal for each frame is displayed in the dot inversion method, as shown in FIG. 4A, as the liquid crystal cell on the left side of the row line moves from the liquid crystal cell on the right side, The data signal is supplied to the liquid crystal cell on the liquid crystal panel so that the positive polarity (+) and the negative polarity (−) appear alternately as the liquid crystal cell moves from the bottom to the bottom. When the video signal of the next frame is displayed, as shown in FIG. 4B, the polarity of the data signal supplied to each liquid crystal cell is inverted with respect to the polarity of the immediately preceding frame.

  However, the conventional method for driving a liquid crystal panel having a stripe type pixel has a limit in further improving the color purity or the quality of a moving image.

  Accordingly, an object of the present invention is to provide a driving method of a liquid crystal panel having a structure in which five color sub-pixels are arranged in one pixel, a driving device thereof, and a liquid crystal display device thereof.

  In order to achieve the above object, a method of driving a liquid crystal panel according to the present invention includes a plurality of pixels including a plurality of sub-pixels having switching elements, a data driver and a gate driver, and the data via each of the switching elements. In the method of driving a liquid crystal panel of a liquid crystal display device comprising a plurality of data lines connected to a driver and a plurality of gate lines connected to the gate driver via each of the switching elements, the plurality of pixels In one of the pixels, the first color sub-pixel arranged in the center of the one pixel is short-circuited to the first color sub-pixel of the other one pixel, and the other one pixel Applying the first color data to the first color sub-pixel through the first color sub-pixel, and a plurality of end portions surrounding the central portion of the one pixel; A step of applying the second color data to the second color sub-pixel disposed at at least one end, and a third color sub-pixel disposed at at least one of the plurality of end portions. Applying a third color data to the pixel, wherein the first color is any one of red, blue and green, and the second color is from the red, blue and green to the first color. One of two colors excluding one color is provided, and the third color is one color obtained by removing the first color and the second color from red, blue, and green.

  At this time, the step of applying the second color data includes the step of applying the data to the second color sub-pixels disposed diagonally opposite the first color sub-pixel in the one pixel. It is characterized by including.

  The step of applying the third color data includes the step of applying data to the third color sub-pixels disposed in the one pixel so as to face each other diagonally with the first color sub-pixel as the center. It is characterized by.

  A liquid crystal panel driving device according to the present invention is a device for driving a liquid crystal panel in which pixels including a large number of sub-pixels are arranged in a matrix, and a signal selection means for selectively inputting red, green, and blue data to the sub-pixels. A control signal generation unit that generates a control signal for controlling the signal selection unit using a horizontal synchronization signal and a dot clock that are input from the outside; and the data output by the signal selection unit is applied to the sub-pixel. And a liquid crystal panel for displaying an image.

  In the present invention, the signal selection means supplies first signal selection means for alternately supplying red data and green data according to the control signal when the liquid crystal panel is driven, and supplies blue data at predetermined intervals. And second signal selection means.

  The control signal generating means in the present invention uses the dot clock to generate a first control signal that applies a control signal for supplying the green data at a predetermined cycle, and uses the horizontal synchronization signal to And a second control signal generating means for applying a control signal to the signal selecting means and the first control signal generating means.

[Action]
By applying the liquid crystal display device driving method and the driving device according to the present invention to a liquid crystal display device having a structure in which five sub-pixels are arranged in one pixel, the color purity in the image quality is improved, and a moving image is obtained. The display quality can be improved, such as displaying the outline naturally. Further, when a liquid crystal display device having such a sub-pixel arrangement structure is driven using the driving method and driving device of the present invention which is a new driving method, it is similar to the conventional dot inversion method. It is also possible to reduce the effect of flicker to reverse the polarity of the data to form.

  As described above, the liquid crystal display device driving method and the driving device according to the present invention are applied to a liquid crystal display device having a structure in which five sub-pixels are arranged in one pixel, whereby the color purity in the image quality is achieved. Display quality can be improved, for example, by displaying contours naturally in moving images. Further, when a liquid crystal display device having such a sub-pixel arrangement structure is driven using the driving method and driving device of the present invention which is a new driving method, it is similar to the conventional dot inversion method. It is also possible to reduce the effect of flicker to reverse the polarity of the data to form.

  Hereinafter, a preferred embodiment of the present invention will be described with reference to FIGS.

  FIG. 5 is a block diagram of a general liquid crystal display device.

  Referring to FIG. 5, the driving device of the liquid crystal display device includes a digital video card (21) for converting analog video data into digital video data, and a data line (DL) of the liquid crystal panel (26). A data driver (23) for supplying video data to the gate, a gate driver (25) for sequentially driving the gate lines (GL) of the liquid crystal panel (26), and a data driver (23) And a timing controller (22) for controlling the gate driver (25).

  Liquid crystal is injected between the two glass substrates of the liquid crystal panel (26), and a gate line (GL) and a data line (DL) are formed on the glass substrate below the substrate so as to be orthogonal to each other. A TFT for selectively supplying an image input from the data line (DL) to the liquid crystal cell (Clc) is formed at the intersection of the gate line (GL) and the data line (DL). A gate terminal of the TFT is connected to the gate line (GL), and a source terminal of the TET is connected to the data line (DL). The TFT drain terminal is connected to the pixel electrode of the liquid crystal cell (Clc).

  The digital video card (21) converts an analog input image signal into a digital image signal suitable for the liquid crystal panel (26), and detects a synchronization signal included in the image signal.

  The timing controller (22) supplies red (R), green (G) and blue (B) digital video data from the digital video card (21) to the data driver (23). The timing controller (22) uses the horizontal / vertical synchronization signals (H, V) input from the digital video card (1) and data such as a dot clock (Dclk) and a gate start pulse ( Gsp) and other gate control signals are generated to control the timing of the data driver (23) and the gate driver (25). A data control signal such as a dot clock (Dclk) is supplied to the data driver (23), and a gate control signal such as a gate start pulse (Gsp) is supplied to the gate driver (25).

  The gate driver (25) is a shift register that sequentially generates scan pulses in response to the gate start pulse (Gsp) input from the timing controller (22), and the voltage of the scan pulse is supplied to the liquid crystal cell. It is constituted by a level shift for shifting to a level suitable for driving. In response to the scan pulse input from the gate driver (25), the video data on the data line (DL) is supplied to the pixel electrode of the liquid crystal cell (Clc) by the TFT.

  A dot clock (Dclk) is input to the data driver (23) together with red (R), green (G), and blue (B) digital video data from the timing controller (22). The data driver 23 latches red (R), green (G), and blue (B) digital video data in synchronization with the dot clock (Dclk), and then converts the latched data to a gamma voltage. Correct by (Vr). The data driver (3) converts the data corrected by the gamma voltage (Vr) into analog data and supplies it to the data line (DL) line by line.

  6A and 6B are diagrams illustrating the pixel structure of the liquid crystal panel according to the first and second embodiments of the present invention and the input of data to the pixel.

  Referring to FIGS. 6A and 6B, the pixels of the liquid crystal panel are composed of five different color sub-pixels arranged in one pixel.

  The pixel (27) has a regular square shape, and the pixel (27) includes a sub-pixel (30) having a rhombus-shaped B color filter disposed in the center of the regular square pixel (27); A sub-pixel (28a, 28b) having an R-color filter at each of the upper left and lower-right ends centered on a sub-pixel (30) having a B color filter, and a sub-pixel (30) having a B color filter Sub-pixels (29a, 29b) having respective G color filters are provided at the upper left and lower right ends at the center.

  FIG. 6A shows that four sub-pixels and one B sub-pixel (30) are located between two gate lines, and alternate between every two pixels in the lower gate line (GL2) and the upper gate line (GL1). 6B, the B sub-pixel (30) in FIG. 6B is located between the two gate lines, and is alternately arranged for each pixel on the lower gate line (GL4) and the upper gate line (GL3). The structure connected to is shown. Thus, the B sub-pixel (31) displays a color on only two pixels based on four pixels.

  Further, the driving method of the liquid crystal panel having five color subpixels in one pixel is different from the conventional method in which the data enable signal is periodically applied to the R, G, and B data signals. When the R data signal is input once for each gate line (GL) to the data bus and the G data bus, the G data signal is alternately input next. At this time, the B data signal is input twice to the B data bus while the R and G data signals are input four times.

  A driving method of the present invention, which is a new driving method for driving a liquid crystal panel having the sub-pixel arrangement structure shown in FIGS. 6A and 6B using a conventional data driver, will be described below.

<First Embodiment>
7A and 7B are diagrams schematically showing the pixel structure shown in FIG. 6A and the connection state of wiring for driving the liquid crystal panel to the data driver.

  Referring to FIGS. 7A and 7B, the liquid crystal display device receives 6-bus input signals (Re, Ge, Be, Ro, Go, Bo) and receives the first to Nth data lines (in synchronization with the data clock). DL1 to DLN).

  In the present invention, the second and fifth output terminals of a set of twelve output terminals connected to the data driver (23) are used without being connected to the data line (DL).

  The eighth and eleventh output terminals from the subsequent data driver (23) are normally connected to the data line (DL) and driven so as to output B subpixel data.

  Such a connection method is applied to the Nth output terminal.

  FIG. 8 is a diagram showing in detail a data pulse generator included in the data driver (23) for outputting data to the liquid crystal panel having the sub-pixel arrangement structure shown in FIG. 7B.

  Referring to FIG. 8, the data pulse generator includes first to fourth multiplexers (R1 to DL3) that selectively input color data (R, G, B) to data lines (DL1 to DL3) through a timing controller (22). MUX1-MUX4), first and third D-flip flops (31, 33), first D-flip flop (31) and fourth multiplexer (MUX 4) according to control signals (Dclk, Hsync) from the timing controller (22) And a second D-flip-flop (32) connected between the two.

  As shown in FIG. 9A, the first multiplexer (MUX1) inputs odd data to the data lines (DL1 to DL3) and generates the nth horizontal synchronization signal (Hsync) in the nth horizontal period. R data (R1a to R4a) to be output to the first data line (DL1), then even data is supplied to the data lines (DL1 to DL3), and the (n + 1) th horizontal synchronization signal (Hsync) is generated. In the (n + 1) th horizontal period, the input G data (G1b to G4b) is output to the first data line (DL1) as shown in FIG. 9B. In the nth horizontal period, the second multiplexer (MUX2) outputs the G data (G1a to G4a) input as shown in FIG. 9A to the second data line (DL2), and then (n + 1) In the second horizontal period, the R data (R1b to R4b) input as shown in FIG. 9B is output to the second data line (DL2). The third multiplexer (MUX3) outputs the B data (B3a, B4a) input as shown in FIG. 9A to the third data line (DL3) as shown in FIG. 9A in the nth horizontal period, and then the (n + 1) In the) th horizontal period, the B data (B1b, B2b) input as shown in FIG. 9B is output to the third data line (DL3). The fourth multiplexer (MUX4) supplies a control signal for controlling the third multiplexer (MUX3). Note that the fourth multiplexer (MUX4) can be replaced with a three-state buffer or a control switch.

  The first and second D-flip-flops (31, 32) are connected in series to generate a dot clock (Dclk) divided by 4 and supply the dot clock (Dclk) divided by 4 to the fourth multiplexer (MUX4). To do. At this time, the dot clock (Dclk) divided by four has a frequency corresponding to a quarter of the dot clock (Dclk) input to the first D-flip-flop (31). This is because the dot clock (Dclk) from the timing controller (22) is input to the clock terminal (CLK) of the first D-flip flop (31), and the output terminals (Q, ¬Q of the first D-flip flop (31)). ) Is input to the input terminal (D) of the first D-flip flop (31) and from the non-inverting output terminal (Q) of the first D-flip flop (31). Is output to the clock terminal (CLK) of the second D-flip flop (32), and then the output signal from the inverting output terminal (¬Q) of the second D-flip flop (32) is the second D-flip flop. By being input to the input terminal (D) of (31), it is generated as an output signal from the non-inverting output terminal (Q) of the second D-flip flop (32).

  The third D-flip-flop (33) divides the horizontal synchronization signal (Hsync) by 2, and controls the first, second, and fourth multiplexers (MUX1, MUX2, MUX4). Supply to the terminal. At this time, the horizontal synchronizing signal divided by two has a frequency corresponding to one half of the horizontal synchronizing signal (Hsync) from the timing controller (22). This is because the horizontal synchronization signal (Hsync) from the timing controller (22) is input to the clock terminal (CLK) of the third D-flip flop (33), and the inverted output terminal (¬Q ) Is input to the input terminal (D) of the third D-flip flop (33), and is generated as an output signal from the non-inverting output terminal (Q) of the third D-flip flop (33). The

  In this way, the first multiplexer (MUX1) outputs R data (R1a to R4a) in the nth horizontal period according to the horizontal synchronizing signal divided by two from the third D-flip flop (33). Then, G data (G1b to G4b) are output in the (n + 1) th horizontal period. The second multiplexer (MUX2) outputs G data (G1a to G4a) in the nth horizontal period, and then outputs R data (R1b to R4b) in the (n + 1) th horizontal period. The third multiplexer (MUX3) outputs B data (B3a, B4a) in the nth horizontal period according to the dot clock divided by 4 from the fourth multiplexer (MUX4), and then the (n + 1) th The B data (B1a, B2a) is output in the horizontal period.

  9A and 9B are diagrams for explaining output of odd-numbered color data and even-numbered color data to the data line through the driving device shown in FIG.

  Referring to FIGS. 9A and 9B, in the driving method of the liquid crystal display device according to the first embodiment of the present invention, in order to drive a liquid crystal panel (26) having five color sub-pixels in one pixel, R is used. Via the data bus, the G data bus, and the B data bus, R data and G data are alternately supplied to the data line every horizontal period, and different B data are alternately supplied to the data lines.

Second Embodiment
10A and 10B are diagrams schematically showing the pixel structure shown in FIG. 6B and the connection state of the data driver for driving the liquid crystal panel of the wiring.

  Referring to FIGS. 10A and 10B, the liquid crystal display device receives the 6-bus input signals (Re, Ge, Be, Ro, Go, Bo) shown in FIGS. 7A and 7B as inputs and synchronizes with the data clock. Unlike the method, the 6 bus system input signals (Re, Ge, Be, Ro, Go, Bo) are input and the outputs are supplied to the 1st to Nth data lines (DL1 to DLN).

  In the present invention, twelve output terminals connected to the data driver (23) are used without connecting the second and eighth output terminals of the set of output terminals to the data line (DL).

  Subsequent fifth and eleventh output terminals from the data driver (23) are normally connected to the data line (DL) and output B data.

  The above connection method is applied to the Nth output terminal.

  FIG. 11 is a detailed diagram illustrating a data pulse generator for generating data in a pixel as shown in FIG. 10B.

  Referring to FIG. 11, the data pulse generator included in the data driver (23) controls the selective output of pixel data to the data lines (DL1 to DL3) through the timing controller (22) as described above. The first to fourth multiplexers (MUX1 to MUX4) and the fourth and fifth D-flip-flops (34, 35) that are controlled by receiving a control signal from the timing controller (22).

  The first multiplexer (MUX1) outputs R data (R1a to R4a) input as shown in FIG. 12A in the nth horizontal period in which the nth horizontal synchronization signal (Hsync) is generated, and then In the (n + 1) th horizontal period in which the (n + 1) th horizontal synchronization signal (Hsync) is generated, the G data (G1a to G4a) input as shown in FIG. 12B are output. The second multiplexer (MUX2) outputs the G data (G1a to G4a) input as shown in FIG. 12A in the nth horizontal period, and then in the (n + 1) th horizontal period, R data (R1b to R4b) input as shown in 12B is output. The third multiplexer (MUX3) outputs the B data (B2a, B4a) input as shown in FIG. 12A in the nth horizontal period, and then in the (n + 1) th horizontal period, The B data (B1b, B3b) input as shown in 12B is output. The fourth multiplexer (MUX4) receives the dot clock divided by two from the fourth D-flip flop (34) in response to the horizontal synchronizing signal divided by two from the fifth D-flip flop (35). MUX3) is supplied to the control terminal to control the third multiplexer (MUX3).

  The fourth D-flip flop (34) divides the dot clock (Dclk) from the timing controller (22) by 2, and supplies the dot clock divided by 2 to the fourth multiplexer (MUX4). The fifth D-flip flop (35) divides the horizontal synchronizing signal (Hsync) from the timing controller (22) by 2, and the divided horizontal synchronizing signal is divided into first, second and fourth multiplexers (MUX1, MUX2, MUX4) are supplied to the control terminals to control the first, second and fourth multiplexers (MUX1, MUX2, MUX4).

  At this time, the dot clock (Dclk) from the timing controller (22) is input to the clock terminal (CLK) of the fourth D-flip flop (34), and the inverted output terminal (¬Q) of the fourth D-flip flop (34). ) Is input to the input terminal (D) of the fourth D-flip flop (34). The output signal from the non-inverting output terminal (Q) of the fourth D-flip flop (34) is input to the input terminal of the fourth multiplexer (MUX4). The output of the fourth multiplexer (MUX4) is input to the control terminal of the third multiplexer (MUX3). Further, the horizontal synchronization signal (Hsync) from the timing controller (22) is input to the clock terminal (CLK) of the fifth D-flip flop (35), and the inverted output terminal (¬Q) of the fifth D-flip flop (35). ) Is input to the input terminal (D) of the fifth D-flip flop (35). The output signal from the non-inverting output terminal (Q) of the fifth D-flip flop (35) is input to the control terminals of the first, second and fourth multiplexers (MUX1, MUX2, MUX4).

  The horizontal synchronization signal (Hsync) from the timing controller (22) is divided by two by the fifth D-flip flop (35), and is output as an output signal from the non-inverting output terminal (Q) of the fifth D-flip flop (35). Is done.

  Further, the dot clock (Dclk) from the timing controller (22) is divided by two by the fourth D-flip flop (34), and output from the non-inverting output terminal (Q) of the fourth D-flip flop (34). And output to the input terminal of the fourth multiplexer (MUX4).

  In this way, the first multiplexer (MUX1) receives the R data (R1a to R4a) in the nth horizontal period according to the output of the non-inverting output terminal (Q) of the fifth D-flip flop (35). Then, G data (G1b to G4b) is output in the (n + 1) th horizontal period. The second multiplexer (MUX2) outputs G data (G1a to G4a) in the nth horizontal period according to the output of the non-inverting output terminal (Q) of the fifth D-flip flop (35), and then R data (R1b to R4b) is output in the (n + 1) th horizontal period. The third multiplexer (MUX3) outputs B data (B2a, B4a) in the nth horizontal period in accordance with the output of the fourth multiplexer (MUX4), and then outputs B data in the (n + 1) th horizontal period. Data (B1b, B3b) is output.

  12A and 12B show odd-numbered and even-numbered color data output to the data lines (DL1 to DL3) through the data driver by the driving device shown in FIG.

  Referring to FIGS. 12A and 12B, in the liquid crystal display device driving method according to this embodiment, as described in FIGS. 9A and 9B shown as the first embodiment, five sub-pixels are provided in one pixel. In order to drive a liquid crystal panel having pixels, R data and G data are alternately switched and B data different from each other alternately for each horizontal period via the R data bus, G data bus, and B data bus. Supply to the data line.

  6A to 12B, a part of the output terminals of the conventional data driver is disconnected, and the B subpixel included in one pixel is identical to the B subpixel included in another pixel. An embodiment is shown in which B data is supplied in a time-sharing manner via the B data bus.

  In order to drive the liquid crystal panel configured in such a pixel form, a new form of data driver may be manufactured and used.

  Specifically, a normal data driver outputs 3 sub-pixel color sub-pixels, and thus has 3 times as many output channels as 384 channels. In the present invention, in the process of generating 6 color sub-pixels. Since the output unit of the color sub-pixel (B color sub-pixel) is shorted, the output terminal from the data driver needs only 5 times as many as 320 channels. Thus, a pixel can be driven by driving a data driver having five times the number of channels.

  13A and 13B show polarities of data signals supplied to the pixels of the liquid crystal panel when the liquid crystal panel having the sub-pixel arrangement structure shown in FIGS. 6A and 6B is driven by the driving method of the present invention. It is drawing which illustrated this pattern. FIG. 13A shows the polarity of data applied to each pixel in the nth frame period, and FIG. 13B shows the polarity of data applied to each pixel in the (n + 1) th frame period.

  Referring to FIGS. 13A and 13B, pixels are arranged in a matrix form with a rhombus of a regular square inscribed therein.

  In the first pixel shown in FIG. 13A, the upper left and upper right polarities are positive (+) adjacent to the central rhombus B data, and the lower left and lower right polarities are negative ( -) At this time, the polarity of the central B data is positive (+).

  In the second pixel, adjacent to the central rhombus B data, the upper left and upper right polarities are negative (−), and the lower left and lower right polarities are positive (−). At this time, the polarity of B data at the center is negative (-).

  In the third pixel, adjacent to the central rhombus B data, the upper left and upper right polarities are positive (+), and the lower left and lower right polarities are negative (-). At this time, the polarity of the central B data is positive (+).

  In the fourth pixel, the upper left and upper right polarities are negative (−) adjacent to the central rhombus B data, and the lower left and lower right polarities are positive (+). At this time, the polarity of B data at the center is negative (-).

  In the first pixel in FIG. 13B, the polarities in the upper left and upper right are negative (−) and the polarities in the lower left and lower right are positive (+) adjacent to the central rhombus B data. Tinged. At this time, the polarity of B data at the center is negative (-).

  In the second pixel, adjacent to the central rhombus B data, the upper left and upper right polarities are positive (+), and the lower left and lower right polarities are negative (-). At this time, the polarity of the central B data is positive (+).

  In the third pixel, adjacent to the central rhombus B data, the upper left and upper right polarities are negative (−), and the lower left and lower right polarities are positive (+). At this time, the polarity of B data at the center is negative (-).

  In the fourth pixel, adjacent to the central rhombus B data, the upper left and upper right polarities are positive (+), and the lower left and lower right polarities are negative (-). At this time, the polarity of the central B data is positive (+).

  The polarity pattern of the data signal supplied to the pixels of the liquid crystal panel according to the present invention by the above method has voltage charging polarity for each sub-pixel through all the panels by alternately repeating FIGS. 13A and 13B.

  It will be understood by those skilled in the art that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should be determined not only by the contents described in the detailed description of the specification but also by the claims.

FIG. 1 is a block diagram showing a general liquid crystal display device. FIG. 2 is a detailed diagram showing the relationship between the pixel and the TFT structure of the liquid crystal display device of FIG. FIG. 3 is a diagram illustrating an arrangement state of RGB color filters according to the prior art of the liquid crystal display device shown in FIG. 1 and a connection state of gate drivers and data drivers. FIG. 4A is a diagram illustrating a conventional dot inversion method. FIG. 4B illustrates a conventional dot inversion method. FIG. 5 is a block diagram showing a liquid crystal display device according to the present invention. FIG. 6A illustrates a pixel structure of the liquid crystal panel according to the first and second embodiments of the present invention and data input to the pixel. FIG. 6B illustrates a pixel structure of the liquid crystal panel according to the first and second embodiments of the present invention and data input to the pixel. FIG. 7A is a diagram illustrating a connection state of a data driver for driving the liquid crystal panel having the pixel structure and the wiring illustrated in FIG. 6A. FIG. 7B illustrates a connection state of a data driver for driving the liquid crystal panel having the pixel structure and the wiring illustrated in FIG. 6A. FIG. 8 is a detailed diagram illustrating a data pulse generator for outputting data to a pixel as shown in FIGS. 7A and 7B. FIG. 9A illustrates the output of odd and even color data to the data line through the driving apparatus of FIG. FIG. 9B illustrates the output of odd and even color data to the data line through the driving device of FIG. FIG. 10A schematically shows a connection state of a data driver for driving the liquid crystal panel having the pixel structure and wiring shown in FIG. 6B. FIG. 10B schematically shows a connection state of a data driver for driving the liquid crystal panel having the pixel structure and the wiring shown in FIG. 6B. FIG. 11 is a detailed diagram illustrating a data pulse generator for outputting data to a pixel as shown in FIGS. 10A and 10B. FIG. 12A is a diagram illustrating the output of the odd and even color data to the data line through the data driver through the driver in FIG. FIG. 12B is a diagram illustrating the output of the odd and even color data to the data line through the data driver through the driver in FIG. FIG. 13A illustrates a polarity pattern of a data signal supplied to a pixel of a liquid crystal panel by the method of driving the liquid crystal panel illustrated in FIGS. 6A and 6B. FIG. 13B is a diagram illustrating a polarity pattern of a data signal supplied to a pixel of a liquid crystal panel by the method of driving the liquid crystal panel illustrated in FIGS. 6A and 6B.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 2: Digital video card 2, 22: Timing controller 3, 23: Data driver 5, 25: Gate driver 6, 26: Liquid crystal panel 12a, 12b, 12c: Pixel electrode 14: TFT
16: Pixel 27: Pixel 28: Sub-pixel having R color filter 29: Sub-pixel having G color filter 30: Sub-pixel having B color filter 31, 32, 33, 34, 35: D flip-flop

Claims (13)

A plurality of pixels including a plurality of sub-pixels having a switching element, a data driver and a gate driver, a plurality of data lines connected to the data driver via each of the switching elements, and each of the switching elements In a method for driving a liquid crystal panel of a liquid crystal display device comprising a plurality of gate lines connected to the gate driver,
In one pixel of the plurality of pixels, the first color sub-pixel disposed in the center of the one pixel is short-circuited to the first color sub-pixel of the other pixel, Applying the first color data to the first color sub-pixel through the first color sub-pixel of one pixel;
Applying the second color data to the second color sub-pixels disposed at at least one of the plurality of ends surrounding the central portion of the one pixel;
Applying a third color data to a third color sub-pixel disposed at at least one of the plurality of ends,
The first color is any one of red, blue, and green, and the second color is any one of two colors obtained by removing the first color from red, blue, and green, The method of driving a liquid crystal panel, wherein the third color is one color obtained by removing the first color and the second color from red, blue, and green.   In the step of applying the second color data, the data is applied to the second color sub-pixels arranged opposite to each other in the diagonal direction around the first color sub-pixel arranged in the one pixel. 2. The method of driving a liquid crystal panel according to claim 1, further comprising steps.   In the step of applying the third color data, the data is applied to the third color sub-pixels arranged opposite to each other diagonally about the first color sub-pixel arranged in the one pixel. 2. The method of driving a liquid crystal panel according to claim 1, further comprising steps.   3. The method of driving a liquid crystal panel according to claim 2, further comprising the step of applying data signals having opposite polarities to the sub-pixels of the second color arranged opposite to each other in the diagonal direction.   4. The method of driving a liquid crystal panel according to claim 3, further comprising the step of applying data signals having mutually reversed polarities to the sub-pixels of the third color arranged opposite to each other in the diagonal direction.   In each of the plurality of pixels, the method includes a step of applying data signals having opposite polarities to each other at a predetermined interval to a first color sub-pixel disposed in a central portion of each pixel. The method for driving a liquid crystal panel according to claim 1.   In an apparatus for driving a liquid crystal panel in which pixels including a plurality of sub-pixels are arranged in a matrix form, signal selection means for selectively inputting red, green and blue data to the sub-pixels, and horizontal synchronization input from the outside A control signal generating means for generating a control signal for controlling the signal selecting means using a signal and a dot clock; and a liquid crystal for displaying an image by applying the data output by the signal selecting means to the plurality of sub-pixels. A liquid crystal panel drive device comprising a panel.   The signal selection means includes first signal selection means for alternately supplying red data and green data by the control signal when driving the liquid crystal panel, and second signal selection means for supplying blue data at a predetermined cycle. The liquid crystal panel drive device according to claim 7, further comprising:   The control signal generating means applies a control signal for supplying the green data at a predetermined cycle using the dot clock, and the signal selecting means using the horizontal synchronization signal. 8. The liquid crystal panel driving device according to claim 7, further comprising second control signal generating means for applying a control signal to the first control signal generating means.   A pixel including first to fifth sub-pixels having a switching element, a data driver and a gate driver, a plurality of data lines connected to the data driver via each switching element, and each switching element A plurality of gate lines connected to the gate driver, the first and second sub-pixels being connected to the first data line, and the third sub-pixel being connected to the second data line. The fourth and fifth sub-pixels are connected to a third data line, and the switching element of the third sub-pixel is a switching element of a third sub-pixel in an adjacent pixel having five sub-pixels. A liquid crystal display device connected to   A pixel having first to fifth sub-pixels having a switching element; a second pixel having sixth to tenth sub-pixels having a switching element; a data driver and a gate driver; A plurality of data lines connected to the data driver; and a plurality of gate lines connected to the gate driver via respective switching elements, wherein the first and second sub-pixels include first data. The third sub-pixel is connected to the second data line, the fourth and fifth sub-pixels are connected to the third data line, and the sixth and seventh sub-pixels are connected to the fourth data line. Connected to the data line, the 8 sub-pixels are connected to the fifth data line, the ninth and tenth sub-pixels are connected to the sixth data line, Serial LCD device the third sub-pixel of the first pixel, characterized in that it is connected to the eighth sub-pixel of the second pixel.   The first output line of the data driver is connected to the first and second sub-pixels, and the second output line of the data driver is not connected to any of the sub-pixels. 3 output lines are connected to the fourth and fifth sub-pixels, a fourth output line of the data driver is connected to the sixth and seventh sub-pixels, and a fifth output line of the data driver is 12. The liquid crystal display device of claim 11, wherein the sixth output line of the data driver is connected to the eighth subpixel and is connected to the ninth and tenth subpixels.   Each pixel array having five sub-pixels and a plurality of data lines coupled to pixels each connected to a group of three data lines, 3. A liquid crystal display device, wherein three data lines belonging to one group are connected to data lines in a group of three different data lines.

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