JP2008217384A - Circuit chip, manufacturing method thereof, and RFID circuit device having the same - Google Patents

Abstract

【Task】
Suppress the occurrence of breakage or crushing of circuit chips due to “microcracks on the outer edge of the substrate” that are likely to occur in circuit chips (semiconductor chips) cut out from a semiconductor wafer by dicing or the like.
[Solution]
The main surface of the semiconductor substrate of the circuit chip is formed so that its outline changes in the main surface only through the curve, thereby suppressing the generation of ridge lines on the side surface of the semiconductor substrate, Disperses the impact on the main surface and side surfaces over the entire semiconductor substrate. In the process of cutting out such a semiconductor substrate from the semiconductor wafer, dry etching is used to suppress the inclination of the side surface. Further, the shape and arrangement of the structure of the electric circuit formed on the main surface of the semiconductor substrate and the electrodes connected thereto are optimized according to the shape of the main surface.
[Selection] Figure 1

Description

  The present invention relates to a circuit chip (semiconductor device) formed by forming an electric circuit on a semiconductor substrate and a manufacturing method thereof, for example, an RFID circuit device or a circuit chip structure suitable for mounting on an RFID circuit device and a manufacturing method thereof.

  In a conventional semiconductor device, a plurality of circuit patterns formed on a wafer (within its main surface) such as silicon (Si) is divided into circuit patterns by a method called dicing that cuts the main surface vertically and horizontally. A circuit chip (also referred to as a semiconductor chip or Si chip) is singulated, and the circuit chip is completed through a mounting process for connecting each circuit chip to an external circuit. In particular, when a thin circuit chip is necessary, as described in Patent Document 1 below, a method is employed in which a lattice-like groove is formed on the surface of a wafer such as Si with a rotating grindstone, and then the back surface is processed thinly. . For this reason, in many of the prior arts, the main surface of the circuit chip is formed into a quadrangle.

  On the other hand, a circuit chip having a shape other than a quadrangle and a manufacturing method thereof are disclosed in, for example, Patent Documents 2 to 4 below. Patent Document 2 discloses a spherical circuit chip, and Patent Document 3 and Patent Document 4 each include a circuit chip having a polygonal or circular main surface.

  Further, as an application of a circuit chip having a rectangular (rectangular) main surface described in Patent Document 1, an RFID tag formed by mounting this on a base material on which an antenna is formed and connecting this circuit and the antenna (Radio Frequency Identification Tag, also called IC tag) is disclosed in Patent Document 5.

Japanese Patent No. 2814176 Japanese Patent No. 3347333 JP 2004-79667 A JP 2006-49403 A JP 2004-94839 A

  In the conventional cutting method as described in Patent Document 1, a wafer (mother substrate) on which a plurality of circuit chips are formed is cut with a disk-shaped thin blade or grindstone that moves linearly within the main surface. Therefore, a corner can be accidentally taken from the main surface of each circuit chip cut out. That is, even if the main surface of the circuit chip is cut out so as to exhibit a quadrangle (rectangle), strictly speaking, it cannot be avoided that the circuit chip exhibits a polygonal main surface. For this reason, fine side surfaces extending in the thickness direction are formed between the four side surfaces of the circuit chip by “cleaving” or “chips (cracks)” from the “corners” of the main surface. The If the area of such a fine crack surface generated by cutting with a grindstone is within a certain range, the circuit chip is caused by placing the circuit chip in a package protected by a hard resin mold or ceramic case. Experience has shown that degradation and damage can be suppressed.

  However, like the RFID tag described in Patent Document 5, when a circuit chip having a fine crack surface is mounted as an RFID circuit on a flexible substrate on which an antenna is formed without being housed in a package, The chip is easily crushed from the fine crack surface by an external force applied to the chip. The RFID tag is required to be attached to an object (for example, luggage, clothes, magazine) to be managed by this, and not to impair the shape or flexibility of the object. Accordingly, in an RFID tag, a circuit chip is embedded in a base material or a laminated structure of a protective member and a substrate. However, due to the flexibility and vulnerability of the laminated structure (package structure), the RFID tag manufacturing process (for example, the transport process) ) And the external force applied to the circuit chip (particularly, the corner portion) during use attached to the object, the corner is easily broken. Furthermore, the deterioration and damage of the function due to the breakage or chipping of the circuit chip became more prominent as the thickness was reduced.

  In view of such a problem, the spherical circuit chip described in Patent Document 2 is most desirable for suppressing cracks and chips. However, it is difficult to manufacture such a circuit chip by a semiconductor manufacturing process using a normal wafer, and the production cost has to be extremely high. Even if mass production technology for spherical circuit chips is launched, it is no exaggeration to say that it is impossible to improve the storage capacity and function to a level suitable for the RFID circuit mounted on the RFID tag.

  Patent Document 3 discloses a circuit chip having a polygonal or circular main surface by cutting out a plurality of circuit chips having a rectangular main surface from a semiconductor wafer and scraping the corners of each main surface by mechanical processing. A technique for obtaining is disclosed. However, in this mechanical processing (chamfering of the main surface of the circuit chip), there is no denying the possibility that the above-mentioned cracks and chips and the crack surface due to this will occur on the side surface of the circuit chip.

  Patent Document 4 teaches a method of cutting out a plurality of circuit chips having a polygonal or circular main surface from a semiconductor wafer by plasma etching (plasma dicing). Cutting a circuit chip from a silicon (Si) wafer by a dry process using a plasma using a fluorine-based gas is more difficult than cutting a circuit chip from a silicon wafer by mechanical processing. It is easy to suppress the occurrence of cracks and chipping, and the processing speed is hardly controlled by a specific crystal plane of the silicon wafer as in the wet process. However, the chemical reaction between the ions released from the plasma that promotes the dry process and the silicon wafer affects the physical properties of the side surface and the vicinity of the circuit chip (silicon substrate) formed thereby, in particular the circuit chip. In an RFID circuit that is required to form more memory elements in a limited main surface, there is no denying the possibility of changing the characteristics of some memory elements. Therefore, Patent Document 4 teaches a method of giving sufficient mechanical strength to a circuit chip as an RFID mounted on an RFID tag, but suggests the necessity of securing the characteristics and a specific method for that purpose. Not reached.

  The object of the present invention is to improve the circuit chip singulation method so that the outer periphery of the circuit chip (the contour or side surface of the main surface) is shaped so as not to easily crack, and is particularly easily mounted on an RFID tag. The object is to provide a semiconductor circuit (circuit chip) that is tough against external forces.

A typical structure of a circuit chip according to the present invention suitable for solving the above problems is described as follows.
Structure 1: a semiconductor substrate having a pair of main surfaces and a side wall interposed therebetween, an electric circuit formed on one of the pair of main surfaces, and one or both of the pair of main surfaces; A circuit chip comprising a plurality of conductor layers connected to the electrical circuit, respectively, wherein each of the main surfaces of the semiconductor substrate has a contour whose extending direction in the main surface changes only through a curve. Have.

When the main surface of the semiconductor substrate is an xy plane, for example, in the rectangular main surface, the extending direction of the contour changes with respect to the x axis and the y axis due to the intersection of two straight lines. Therefore, a “corner” is formed in the outline of the main surface by the intersection of the straight lines. In the present invention, the main surface of the semiconductor substrate is formed such that the extending direction of the contour with respect to the x-axis and the y-axis changes in a curved manner without passing through a “corner”. The main surface of the semiconductor substrate according to the present invention is formed into, for example, a circle, an ellipse, or a polygon (rectangle or the like) in which the “corner” is replaced with an arc. The details of the circuit chip having the structure 1 are described as follows.
Structure 2: A circuit chip having the structure 1, wherein each outline of the main surface of the semiconductor substrate is composed of at least one straight line and at least one curve respectively extending from both ends thereof. For example, the main surface of the semiconductor substrate may be formed in a shape similar to the main surface of the wafer on which the orientation flat is formed, or in an oval shape (oval shape).
Structure 3: A circuit chip having structure 2, wherein each of the outlines of the main surface of the semiconductor substrate has four straight lines and four lines extending between each pair of adjacent straight lines. Are formed in a rectangular shape.
Structure 4: A circuit chip having the structure 1, wherein the outline of each of the main surfaces of the semiconductor substrate is formed in a circle or an ellipse by a continuously extending curve.
Structure 5: A circuit chip having structure 1, wherein the outline of each of the main surfaces of the semiconductor substrate is not formed with an angle at which a pair of straight lines extending in different directions intersect.
Structure 6: A circuit chip having structure 1, wherein the extending direction of the side wall of the semiconductor substrate is changed only by the curved surface defined by the curve of the contour of the main surface. That is, the side surface of the semiconductor substrate is formed into a smooth surface according to the shape of the main surface described above.
Structure 7: A circuit chip having the structure 6, wherein no ridge line is formed on the side wall of the semiconductor substrate due to the intersection of a pair of planes extending in different directions.
Structure 8: A circuit chip having structure 1, wherein the side wall of the semiconductor substrate is formed by dry etching that is advanced from any of the main surfaces of the semiconductor substrate in the thickness direction of the semiconductor substrate. An example of this feature is detailed in Example 2.

The electrodes used for transmitting and receiving signals between the electric circuit of the circuit chip and the outside thereof are described as follows.
Structure 9: A circuit chip having the structure 8, wherein the plurality of conductor layers include a first electrode formed on the one (first main surface) of the semiconductor substrate main surface and the other (second main surface). The second electrode is formed together with the side wall of the semiconductor substrate by the dry etching advanced from the second main surface in the thickness direction of the semiconductor substrate. It is electrically connected to the electrical circuit through an "opening (through hole)".
Structure 10: A circuit chip having structure 9, wherein the second electrode extends from the second main surface to the side wall and covers the side wall.
Structure 11: A circuit chip having Structure 1, wherein the plurality of conductor layers include a first electrode and a second electrode formed on one of the main surfaces of the semiconductor substrate so as to be separated from each other. At least a portion of one electrode is surrounded by an inner periphery of a second electrode that is provided between this portion and the end of the main surface of the semiconductor substrate and is curved toward this portion. For example, the second electrode is formed in a U shape, a crescent shape, or a donut shape.
Structure 12: A circuit chip having the structure 11, wherein the other part of the first electrode is opposed to the end of the main surface of the semiconductor substrate without facing the second electrode.
Structure 13: A circuit chip having the structure 11, wherein the second electrode is formed in an annular shape in which the inner periphery surrounds the outer periphery of the first electrode.

The arrangement of the electric circuit viewed from the main surface of the semiconductor substrate and the electrodes used for signal transmission / reception with the outside thereof is described as follows.
Structure 14: A circuit chip having structure 1, wherein a diameter of a circumscribed circle surrounding the electric circuit or projection thereof on any one of the principal surfaces of the semiconductor substrate is defined by the plurality of conductor layers or projections thereof on the principal surface. It is smaller than the diameter of the enclosing circumscribed circle.
Structure 15: A circuit chip having the structure 1, wherein the electric circuit is formed in a region separated from the contour of the main surface on the one main surface of the semiconductor substrate, and a plurality of the electric circuits are formed in the region. Active elements (such as transistors and diodes) are formed.
Structure 16: A circuit chip having the structure 15, wherein the outline of the region has a polygonal shape on the one main surface of the semiconductor substrate.

The characteristics of the RFID circuit device on which the circuit chip according to the present invention is mounted are described as follows.
Structure 17: An RFID circuit device comprising a circuit chip having structure 9, a first base material on which a first antenna is formed on a main surface, and a second base material on which a second antenna is formed on a main surface, (A) The first electrode of the circuit chip is connected to one end of the first antenna, the second electrode is connected to one end of the second antenna, and (b) the one end of the first antenna to the other end. The extending direction of the second antenna is different from the extending direction of the second antenna from the one end to the other end.
Structure 18: An RFID circuit device including a circuit chip having the structure 12 and a base material having a main surface formed by separating the first antenna and the second antenna from each other, and (a) the first antenna One end of the first antenna and the one end of the second antenna are opposed to each other on the main surface of the substrate, and (b) one end of the first antenna is on the first electrode, and one end of the second antenna is on the second electrode. And (c) the first antenna extends from the one end to the other end of the first electrode, and (d) the second antenna extends from the one end. It extends to the other end beyond the outer periphery of the second electrode.
Structure 19: The RFID circuit device having the structure 18, wherein an insulating layer covering the first antenna and the second antenna is formed at least in a region where the circuit chip is mounted on the main surface of the substrate. Absent.
Structure 20: a circuit chip having any one of the structures 11 to 13, a base material having a main surface formed by separating the first antenna and the second antenna from each other, and at least the circuit of the main surface of the base material An RFID circuit device comprising an insulating film formed in a region where a chip is mounted, wherein (a) at least two openings are formed in the insulating film to expose the first antenna and the second antenna, respectively. (B) The first electrode and the second electrode of the circuit chip are electrically connected to the first antenna and the second antenna, respectively, through the opening.

A suitable method for manufacturing the circuit chip described above is described as follows.
Process 1: The following four steps are performed sequentially.
(1) A first step of preparing a semiconductor wafer having a first main surface formed with a plurality of electric circuits separated from each other;
(2) A resist film is formed on either the first main surface or the second main surface opposite to the first main surface of the semiconductor wafer, and an opening pattern for separating the plurality of electric circuits from each other is formed on the resist film. Second step,
(3) The one main surface (the first main surface / the second main surface) of the semiconductor wafer is etched through an opening pattern of the resist film, and the one main surface extends in the thickness direction of the semiconductor wafer. A third step of forming a groove extending to the other main surface (the second main surface / the first main surface); and (4) the electric circuit is provided by the groove formed in the third step. And a fourth step of separating the plurality of semiconductor substrates from the semiconductor wafer.

(A) In the second step, the opening pattern of the resist film surrounds each of the electric circuits in the one main surface (the first main surface / the second main surface) or the outer periphery of the projection. Contours are formed, and (b) each of these contours changes in extending direction within one main surface (the first main surface / the second main surface) only through a curve.
Process 2: In the third step of the process 1, the semiconductor wafer is etched by dry etching, whereby the inner wall along the contour of the groove is separated from the “curved surface” or “a plurality of curved surfaces thereby. Formed by a plurality of planes.
Process 3: In the third step of the process 1, the semiconductor wafer is etched by alternately repeating dry etching of the semiconductor wafer and passivation of the surface etched thereby.

  According to each of the structure 1 and the structures 2 to 16 related thereto, the external force applied to the circuit chip does not concentrate on the specific part, and therefore even if the circuit chip is used in an environment where an impact is easily applied, Cracks and breaks are suppressed. Therefore, not only the toughness of the circuit chip is improved, but also the probability of occurrence of defective products in the process of manufacturing the electronic device (for example, RFID circuit device) by mounting it on another substrate is remarkably reduced. . According to each of the structures 9 to 13, since the error range allowed for the alignment of the circuit chip to the base material in the assembly of the electronic device described above is widened, the manufacturing yield of the electronic device is improved. According to each of the structures 14 to 16, for example, damage to the “electric circuit formed on the circuit chip” in the process of cutting out the circuit chip from the semiconductor wafer can be suppressed. According to each of the structures 17 to 20, an error range allowed for the alignment of the circuit chip and the antenna in the assembly of the RFID circuit device is widened, and the mounting position of the circuit chip with respect to the antenna (the substrate on which the circuit chip is formed) is increased. Even with rough control, electrical connection between the circuit chip electrode and the antenna on the substrate, and inductive coupling and capacitive coupling between the circuit chip antenna and the antenna on the substrate are established.

  On the other hand, according to each of the above processes 1 to 3, the semiconductor substrate is cut out from the semiconductor wafer (base material) along the outline of the main surface without the “corner”, so that the side surface is a smooth curved surface. The external force applied to this is distributed over the entire semiconductor substrate. In addition, since the pair of main surfaces (upper surface and lower surface) of the semiconductor substrate are formed in substantially the same shape, not only the toughness to the external force of the circuit chip but also the main surface of the base material in mounting on other base materials Positioning is also easy.

  Embodiments of the present invention will be described in detail below with reference to the drawings of the embodiments.

  A semiconductor device to which an embodiment of the present invention is applied will be described below with reference to FIGS.

  FIG. 1 is an external perspective view of an RF-ID circuit device (RFID tag) to which the present invention is applied. FIG. 1 (a) is an overall view, and FIG. 1 (b) is a detailed view around a circuit chip 1. FIG. Each is shown. FIG. 1C shows a cross section around the circuit chip 1 of the RF-ID circuit device along the c-c ′ line in FIG. The circuit chip 1 is connected to the antenna 21 and the antenna 22 on the front and back sides thereof, and obtains electric power from the radio wave received from the outside (for example, a reader / writer device) received by the dipole antenna including the antenna 21 and the antenna 22 and Communicate with the outside by exchanging signal radio waves to exchange information. The circuit chip 1 includes an electric circuit 11 (formed within a region indicated by a dotted line in FIG. 1B) formed on a disk-shaped silicon substrate 10 and a circular bonding electrode 12 formed on each of the front and back surfaces of the silicon substrate 10. Consists of.

  A circuit chip (also referred to as a semiconductor chip) 1 is exemplified as a plurality of transistors (TR1, TR2) on one (upper surface) of the main surface of a silicon (Si) substrate 10 as shown in FIG. ) And a wiring WL that connects the transistors. In FIG. 1C, the wiring WL is defined as all conductor layers other than the junction electrode 12 formed on one main surface of the silicon substrate 10 including the gate electrode of the illustrated transistor. Further, on one main surface of the silicon substrate 10, at least two layers of insulating films INS that separate the wirings WL from the active regions of the silicon substrate 10 and protect the wirings WL are formed. The RFID circuit formed on the circuit chip 1 includes a transistor array (collection of a plurality of transistors) used for recording and holding information, a terminal placed outside the RF-ID circuit device, and the plurality of transistors. It is generally composed of other transistors and electric elements (capacitors and inductors) included in an interface for exchanging information between the two. The transistor array and the interface are formed in a region defined as the electric circuit 11 on one main surface of the silicon substrate 10. The transistors TR1 and TR2 illustrated in FIG. 1C show an image of the RFID circuit in the electric circuit region 11, and the actual electric circuit 11 includes a larger number of transistors and wirings than those shown in the figure. The formed transistor is not limited to the field effect type, and can be appropriately replaced with, for example, a bipolar type or a diode. The bonding electrode 12 formed on the other main surface (lower surface) of the silicon substrate 10 is a conductor WL formed on one main surface (upper surface) with a conductor formed in a through hole TH passing through the main surfaces. Connected.

  Each of the bonding electrodes 12 is a circuit electrode formed of a metal such as copper or aluminum or an alloy containing the same, but the surface thereof is protected by gold plating. Joined by sonic welding. The antenna 21 is formed on a base film 23 made of a resin material such as polyethylene terephthalate (PET) or polystyrene naphthalate (PEN), and the antenna 22 is also formed on a base film 24 made of a similar resin material. The circuit chip 1 and the antennas 21 and 22 are protected by bonding. The base films 23 and 24 are both formed to extend in one direction, and the antennas 21 and 22 extend in the extending direction on their main surfaces. When the antennas 21 and 22 are formed with sufficient strength at least in a region that does not overlap the circuit chip 1, the main surfaces of the base films 23 and 24 do not have to overlap each other. For example, as shown in FIG. As shown, the antennas 21 and 22 may be exposed at portions extending outward from the junction region with the circuit chip 1.

  As is clear from FIG. 1A, the circuit chip 1 is generally formed in a disc shape, and as shown in FIG. 1B, the main surface of the silicon substrate 10 on which the electric circuit 11 and the bonding electrode 12 are formed. There is no “horn”. That is, in the conventional semiconductor circuit chip formed on the main surface of the rectangular substrate, the circuit chip 1 does not have a corner portion that induces “chip” or “crack” by applying external force. For this reason, when the RF-ID circuit device in which the base film 23 and the base film 24 are made of a flexible thin resin film is attached to an object identified by this, the circuit chip 1 is bent through the base films 23 and 24. Even if an external force such as twisting or twisting is applied, the possibility of the circuit chip breaking or chipping is greatly reduced. Further, the circuit chip 1 is separated into individual pieces by dry etching of a silicon wafer (semiconductor substrate), and the side surface of the silicon substrate (semiconductor substrate) 10 that determines the substantial strength (left and right surfaces in FIG. 1C). It is considered that the suppression of the occurrence of the crack surface in this also contributes to the improvement of the strength of the circuit chip 1.

  Next, a method for manufacturing the above-described RF-ID circuit device will be described step by step. FIG. 2 shows an appearance of the silicon wafer 100 during processing in the semiconductor pre-process related to the manufacture of the circuit chip 1. FIG. 2A shows the entire main surface of the silicon wafer 100, and FIG. 2B shows the arrangement of the plurality of electric circuits 11 being formed on the main surface of the silicon wafer 100. A large number of electric circuits 11 are formed on the main surface of the silicon wafer 100. In an actual embodiment, a silicon wafer has a diameter of 200 mm, and each electric circuit 11 is formed in an area having a diameter of about 0.5 mm. Therefore, there are several hundred thousand electric circuits 11 on one wafer. However, in order to avoid complication of the figure, the plurality of electric circuits 11 are shown separately for each circuit group 110 arranged in a rectangular region. Inside the circuit group 110, as shown in FIG. 2B, a large number of electric circuits 11 are arranged in a rectangular area. In the circuit group 111 adjacent to the outer peripheral portion of the wafer 100, the electric circuit 11 applied to the end of the wafer main surface is missing.

  In FIG. 2B, the plurality of electric circuits 11 constituting the circuit group 110 are drawn several times larger than actual. The shape of the circuit group 110 is set to such a size that all the patterns of the electric circuit 11 constituting the circuit group 110 can be exposed by one exposure process in a photolithography process using a stepper exposure machine.

  The individual electric circuits 11 are not formed in a rectangular layout that is standard in a conventional rectangular semiconductor chip, but are polygonal shapes suitable for being accommodated in a circular region so as to avoid corners lost when cutting individual pieces. Is formed. Ideally, disposing each electric circuit (region) 11 in a shape similar to a circle that is the shape of the final circuit chip 1 increases the integration rate of the circuit chips 1 on the main surface of the wafer 100. Is preferable. However, when each of the plurality of electric circuits 11 is drawn on the main surface of the wafer 100 using a semiconductor integrated circuit design method that has already been put into practical use, each of the electric circuits 11 is divided into a plurality of rectangular pattern regions. Therefore, the outline has a polygonal shape as shown in FIG. The pattern of the electric circuit 11 is staggered within the circuit group 110 (Staggered Layout), and the number of acquired circuit chips 1 is increased in the main surface of the wafer 100 when the silicon substrate 10 is separated in a later process. Closely packed.

  Next, an electrode 12 for connecting the electric circuit 11 and the antenna is formed on the main surface of the wafer 100 which is the surface side of the circuit chip 1. As shown in FIG. 3, a circular electrode 12 is formed at the center of the electric circuit 11. The connection electrode 12 is formed by forming a copper sputtered film as a seed electrode layer and electroplating gold to form a thick gold film to facilitate ultrasonic bonding with the antenna. At this time, by making the circular electrode 12 smaller than the diameter of the circuit chip 1 at the time of completion, the risk of short-circuiting of the connection electrodes 12 formed on the front and back in a later process is reduced.

  Further, as shown in FIGS. 4 and 5, a groove process for separating the plurality of electric circuits 11 formed on the main surface of the wafer 100 for each circuit chip 1 is formed. 4A shows the overall shape of the wafer 100, FIG. 4B shows the layout inside the circuit group 110 on the main surface of the wafer 100, and FIG. 5 shows the cross-sectional structure of the electric circuit 11. As shown in FIG. Inside the circuit group 110, a plurality of circuit elements (electric circuits 11) divided into circuit chips 1 are arranged. A ring-shaped residual portion 112 is formed around the wafer 100.

  As shown in FIG. 4B, the circular photoresist pattern 31 formed so as to cover the electric circuit 11 arranged in the circuit group 110 protects the portion formed on the circuit chip 1. The photoresist pattern 31 has a hole shape 32 in part.

  Using the photoresist pattern 31 as a protective film, the wafer 100 is etched to form grooves 101 and round holes 102. At this time, the electric circuit 11 is circled by the groove 101. Etching is performed by a dry process using a fluorine-based gas plasma, and a preferred example will be described in detail later.

  Next, as shown in FIG. 6, the photoresist pattern 31 is peeled off from the surface of the wafer 100, and a back grinding tape 34 is attached to the surface. Since the back grind tape 34 is pasted on the upper surface of each of the plurality of circuit groups 110 and the ring-shaped residual portion 112 separated from each other by grooves formed on the surface of the wafer 100 by the dry process (dry etching), each of them. The outline of the upper surface of is indicated by a broken line. FIG. 6B shows a cross section of a portion corresponding to one circuit chip 1 formed for each circuit group 110 shown in FIG. 6A, and the silicon substrate divided for each circuit chip 1 by the groove 101. 10 corresponds to the “front surface” of the wafer 100 shown in FIG. 6A, and the lower surface of the silicon substrate 10 corresponds to the “back surface” of the wafer 100 described later. Accordingly, the back grind tape 34 adheres to the upper surface of the silicon substrate 10 (and the bonding electrode 12 and the like formed thereon). A region separating the circuit group 110 and the remaining portion 112 on the surface of the wafer 100 is depressed with respect to these upper surfaces by dry etching.

  When the back surface of the wafer 100 is ground with the back grind tape 34 attached to the front surface, each of the circuit groups 110 is transferred to the plurality of silicon substrates 10 having the electric circuits 11 separated by the grooves 101 on the front surface of the wafer 100. Divided. Each main surface of the silicon substrate 10 has, for example, a circular outline without corners. In grinding processing of the back surface of the wafer 100 by chemical mechanical polishing (CMP) or the like, the remaining portion 112 on the peripheral edge of the wafer 100 reduces the “unevenness of grinding thickness” in the back surface. The phenomenon that the silicon substrate 10 separated from the vicinity becomes thinner than the silicon substrate 10 separated from the central portion thereof is suppressed. FIG. 6B shows a cross section of the silicon substrate 10 when grinding of the back surface of the wafer 100 is completed.

  FIG. 7A is a perspective view of the wafer 100 after grinding (separated into a plurality of circuit groups 110 and a ring-shaped residual portion 112) as viewed from the back surface side. The back grind tape 34 affixed to the surface of the wafer 100 is exposed from the region separating the circuit group 110 and the ring-shaped residual portion 112 of the wafer 100. Although not shown, each of the circuit groups 110 is further separated into silicon substrates 10 corresponding to a plurality of circuit chips 1. A metal film (or alloy film) is formed on the entire back surface of the wafer 100 (in other words, the lower surface side of the circuit chip 1) as shown in FIG. In the present embodiment, in order to improve the adhesion between the metal film (back electrode 13) and silicon, a metal titanium thin film is deposited on the surface of the silicon substrate 10 exposed on the back side of the wafer 100 as a base layer. Further, in order to secure the bonding stability between the circuit chip 1 and an external circuit (for example, an RFID tag antenna), an upper layer film is formed by gold plating on the metal titanium thin film, and the back electrode 13 is formed. Finalize.

  The back electrode 13 is used for electrical joining between the electrical circuit 11 of the circuit chip 1 and the antenna of the RF-ID circuit device, similarly to the joining electrode 12 described above. This is different from the bonding electrode 12 on the surface side. That is, not only the inner wall of the groove 101 formed by dry etching of the silicon wafer 100 (becomes the side wall of the silicon substrate 10 of the circuit chip 1 singulated), but also the inner wall of the round hole 102 formed in the same manner on the back surface. An electrode 13 is formed. Since the electrode 12 previously formed on the surface of the silicon substrate 10 (the surface of the silicon wafer 100) is within a range smaller than the outer diameter of the silicon substrate 10 (within the surface of the silicon substrate 10), the electrode 12 has a back surface. There is no portion in contact with the electrode 13, and therefore a circuit short circuit (electrical short circuit) does not occur between the front and back surfaces of the silicon substrate 10. Further, if a part (conductor layer) of the electric circuit 11 is formed so as to be in contact with the inner wall of the round hole 102, the back electrode 13 is electrically connected to the electric circuit 11 through the inner wall surface of the round hole 102. The metal film that becomes the back electrode 13 also adheres to the portion of the back grind tape 34 that is exposed from the silicon substrate 10, but this excessively formed metal film is composed of a plurality of circuit groups 110 (aggregates of silicon substrates 10). The silicon substrate 10 is peeled off while being attached to the back grind tape 34 in the next step of transferring from the back grind tape 34 to the holding tape.

  8A is an overall perspective view of the holding tape 35 to which a plurality of circuit groups 110 (an assembly of the silicon substrates 10) are transferred from the back grind tape 34, and FIG. 8B is a silicon view of the holding tape 35. Cross-sectional views of portions where one of the substrates 10 has been transferred are shown. A holding tape 35 is affixed to the back surface (the lower surface in FIG. 8B) of the plurality of silicon substrates 10 processed as described above, and then the front surface of the silicon substrate 10 (Otemen, FIG. 8 ( In b), the back grind tape 34 is peeled off from the upper surface). FIG. 8A shows the holding tape 35 after the back grind tape 34 is removed from the plurality of silicon substrates 10 affixed to the holding tape 35. Each surface of the circuit group 110 is the silicon wafer described above. Corresponds to 100 surfaces. The holding tape 35 is stretched on the holding frame 36. Thereby, tension is given to the main surface of holding tape 35, and peeling from each holding tape 35 of silicon substrate 10 by a collet (Collet) etc. is made easy.

  Since the plurality of silicon substrates 10 are transferred from the back grind tape 34 to the holding tape 35 for each circuit group 110 to which each of the silicon substrates 10 belongs, a plurality of the circuit groups 110 are arranged on the main surface of the holding tape 35. On the other hand, the remaining portion 112 that supports the plurality of circuit groups 110 around the back surface of the silicon wafer 100 during back grinding (back grinding) and the excess back electrode 13 (metal film) attached to the back grinding tape 34 are used in the transfer process. Thus, since they adhere to the back grind tape 34 and are removed, they do not appear on the main surface of the holding tape 35. The removal of the plurality of silicon substrates 10 from the main surface of the holding tape 35 is sequentially performed for each circuit chip 1 by a conventional chip peeling technique (for example, vacuum suction of the chip to the collet). The plurality of circuit chips 1 may be collectively removed from the holding tape 35 by deactivating the adhesive force.

  One example of the circuit chip 1 obtained in the present embodiment described above has a cross-sectional structure shown by being surrounded by a broken line in FIG. When this circuit chip 1 is manufactured as a semiconductor chip mounted on an RFID circuit device (RFID tag), the pair of electrodes connected to the antennas (reference numerals 21 and 22 in FIG. 1) of the RFID circuit device are circuit chips. A pair of main surfaces (which face each other in the thickness direction) are separately formed as a bonding electrode 12 and a back electrode 13. The main surface and thickness of the circuit chip 1 are also discussed as the main surface and thickness of the semiconductor substrate 10 made of silicon or the like that determines its shape. An electrical circuit 11 including a plurality of transistors is formed on the main surface (upper surface) of the semiconductor substrate 10 on which one of the pair of electrodes (bonding electrode 12) provided on the circuit chip 1 is formed. The electrode 12 is electrically separated from the electric circuit 11 by an insulating film (not shown), and is electrically connected to a specific portion of the electric circuit 11 by the contact hole formed outside or on the insulating film. The

  On the other hand, the other of the pair of electrodes (back surface electrode 13) is not only the other main surface (lower surface) of the semiconductor substrate 10, but also a side surface (groove separating the circuit chip 1) extending between the two main surfaces. The electrode (metal film) 13 formed on the inner wall of the round hole 102 is electrically connected to another specific portion of the electric circuit 11 on the upper surface of the semiconductor substrate 10. Connected. The electrode (metal film) 13 formed on the side surface of the semiconductor substrate 10 can extend to an end portion in contact with the upper surface of the semiconductor substrate 10 on the side surface, but the bonding electrode 12 and the electric circuit 11 described above are included in the semiconductor substrate 10. Since the upper surface (one of the main surfaces) is separated from the end of the upper surface, unexpected electrical connection with the bonding electrode 12 or the electric circuit 11 is not formed. That is, on the upper surface of the semiconductor substrate 10, a blank space (Dead Space) is provided between each of the bonding electrode 12 and the electric circuit 11 and an end portion (outer periphery of the main surface) of the upper surface.

  Each of the contours (periphery shapes) of the pair of main surfaces of the circuit chip 1, that is, the semiconductor substrate 10, has a shape without a “corner” by dry etching described with reference to FIG. 5. ). From the viewpoint of a shape having no “corner”, not only a circular shape and an elliptical shape but also a shape including at least one “straight side extending from each end of the curved line” is included. For example, even if a curved side is inserted between two straight sides that are to contact each other at each of the four corners of the rectangular main surface, a main surface shape without “corners” can be obtained. A smooth curved surface corresponding to the contour of the main surface is formed on the side surface of the semiconductor substrate 10 having the main surface formed in this way, and no ridge line due to a pair of planes corresponding to the straight side is formed. . According to the knowledge obtained by the present inventors, the influence of an external force (such as an impact) applied to the circuit chip 1 and the RFID circuit device on which the circuit chip 1 is mounted appears remarkably on the side surface of the semiconductor substrate 10. However, by suppressing the formation of a ridge line (so-called “corner”) on the side surface of the semiconductor substrate 10, the concentration of external force applied to the side surface on a specific portion (that is, the ridge line) is alleviated, and the entire semiconductor substrate 10. To be distributed. Therefore, occurrence of “chip” and “cleavage” on the side surface of the semiconductor substrate 10 is suppressed. For the separation of the semiconductor substrate 10 from the base material such as the wafer 100, wet etching can also be applied. However, in dry etching with a large aspect ratio (ratio of etching depth to etching area), the groove 101 for separating the circuit chips 1 from each other. Thus, more circuit chips 1 can be obtained from the base material.

  In this embodiment, the main surface of the silicon wafer 100 (each of the circuit groups 110 formed on the silicon wafer 100) is filled with a plurality of semiconductor substrates (silicon substrates) 10 in order to obtain more circuit chips 1. Further, as shown in FIG. 2B, the main surface of the circular semiconductor substrate (silicon substrate) 10 is alternately arranged in the main surface of the silicon wafer 100. However, depending on the application of the circuit chip 1 (for example, mounting on an RFID circuit device), the shape of the main surface of the semiconductor substrate 10 is appropriately changed as long as the condition that it does not have “corners” is satisfied. The arrangement in 100 main planes is also optimized.

  For example, as shown in FIG. 9, a plurality of semiconductor substrates 10 may be arranged in a lattice pattern on the main surface of the silicon wafer 100. Although this example is not suitable for obtaining the circuit chip 1 having the maximum circular main surface from the silicon wafer 100, a photomask for a pre-process of a conventional product (thick chip) cut out by dicing in the pre-process. Enables the use of. Therefore, it is not necessary to prepare a new expensive photomask, and the manufacturing cost of the circuit chip 1 can be reduced.

  FIG. 10 shows an example in which the main surface of the circuit chip 1 (semiconductor substrate 10) has a contour including at least one “straight side extending from each of the curved sides”. The contour of the main surface of the circuit chip 1a is formed by four straight sides virtually forming a “square” or “rectangle” and arc-shaped sides extending between each pair of adjacent four sides. It is. Since the circuit chip 1a has a main surface shape close to a square, an electric circuit 11 designed in accordance with a normal circuit chip having a square main surface can be formed on the circuit chip 1a. That is, it is not necessary to newly design the electric circuit 11 of the circuit chip 1a, and it is not necessary to produce a photomask according to the new electric circuit 11, so that the manufacturing cost is greatly reduced. Further, by arranging the main surface of the circuit chip 1a in a lattice shape in the main surface of a base material such as a silicon wafer, the manufacturing process can generally follow the manufacturing process of a conventional circuit chip having a rectangular main surface. Depending on the production line, the production of the circuit chip 1a and the conventional circuit chip can be easily mixed.

  On the other hand, since the four straight sides forming the outline of the main surface of the circuit chip 1a shown in FIG. 10 do not intersect with each other due to the interposition of the arc-shaped sides, no “corners” are formed on the main surface. Instead, arc-shaped four corners are formed. Therefore, no ridge line due to the “corner” appears on the side surface of the semiconductor substrate 10 constituting the circuit chip 1a, and four curved surfaces and four planes connected by each of them are formed. Thereby, “chips” due to “corners” of the semiconductor substrate generated at the four corners of the conventional circuit chip having a rectangular main surface are greatly reduced. FIG. 10 shows a method of forming the main surface of the circuit chip into a substantially square shape by connecting four straight sides forming a “square” or “rectangle” with arc-shaped sides. It can also be applied to polygons. For example, a main surface formed into a roughly hexagonal or roughly octagonal shape by connecting six straight sides that virtually form a hexagon or eight straight sides that virtually form an octagon with arcuate sides. Also in the circuit chip having the “chip”, “chip” due to “corner” of the semiconductor substrate is greatly reduced as in the circuit chip 1a.

  In the main surface of the circuit chip 1b shown in FIG. 11, the four straight sides of the circuit chip 1a shown in FIG. 10 are replaced with curves (gradual arcs) having a larger radius of curvature than the arc-shaped sides. Has a contour. That is, the contour of the main surface of the circuit chip 1b is formed by combining at least two types of curves having different radii of curvature, and the curves forming the four corners are arcs having a small radius of curvature, and the other (a pair of adjacent corners of the four corners). The sides are formed by arcs having a larger radius of curvature than the arcs forming the four corners. In the circuit chip 1b of FIG. 11, an arc having the same radius of curvature extends between each pair of adjacent corners of the main surface. The radius of curvature of the arc is a pair extending in the vertical direction of FIG. You may make it differ by the pair extended to. Further, a curve extending between a pair of adjacent corners may be formed by combining a plurality of arcs having different radii of curvature, for example, as a sine curve. In this circuit chip 1b as well, the “chip” of the semiconductor substrate 10 is reduced as in the circuit chip 1a described above. Further, when the radius of curvature of the curve extending between the four corners of the circuit chip 1b is increased, an electric circuit 11 similar to the circuit chip having a rectangular main surface can be formed on the circuit chip 1b, similarly to the circuit chip 1a. .

  Further, the circuit chip 1b has a curved surface at the entire side surface, thereby increasing the strength against external force. For example, in the process of transporting a plurality of circuit chips 1b together, the circuit chips collide with each other or a transport case. The probability of occurrence of “defects” in the circuit chip 1b (side surface of the semiconductor substrate 10 constituting the circuit chip 1b) is greatly reduced.

  In the circuit chips 1, 1 a, and 1 b described above, the two electrodes 12 and 13 connected to the external circuit are separately formed on the two main surfaces of the semiconductor substrate 10. However, the present invention is also applied to a circuit chip in which two electrodes are formed on one of the main surfaces of the semiconductor substrate 10. The circuit chip having such a shape is realized by the manufacturing process described with reference to FIGS. 5 to 8, and the formation of the round hole 102 described with reference to FIG. 6 and the semiconductor described with reference to FIG. It is not necessary to form a metal film on the back surface of the substrate (silicon substrate) 10.

  12 shows a semiconductor circuit chip 1c in which a plurality of electrodes 12-1 including electrodes corresponding to the electrodes 12 and 13 described above are formed on one surface of the semiconductor substrate 10, that is, the main surface on which the electric circuit 11 is formed. A plan view of is shown. The plurality of electrodes 12-1 are electrically separated from the electric circuit 11 by an insulating film (not shown) formed on the main surface of the semiconductor substrate 10, similarly to the bonding electrode 12 of the circuit chip shown in FIG. The contact hole formed in the insulating film is electrically connected to a specific portion of the electric circuit 11. At least one of the four electrodes 12-1 illustrated in FIG. 12 may be used as a so-called dummy electrode only for fixing the circuit chip 1c to an external circuit or a substrate on which it is formed. Such a dummy electrode does not require electrical connection with the electric circuit 11 through a contact hole. In the circuit chip 1c configured as described above, it is not necessary to form a through electrode circuit by attaching a metal film to the inner wall of the round hole 102 that penetrates the semiconductor substrate 10 in the thickness direction. For this reason, the tact time (Takt Time) for manufacturing the circuit chip 1c is shortened by the long process time required for forming the through electrode circuit. The semiconductor substrate 10 of the circuit chip 1c illustrated in FIG. 12 has a circular main surface. As shown in FIG. 9, the plurality of main surfaces are arranged in a lattice pattern on the main surface of the semiconductor wafer as a base material. Moreover, you may shape | mold the main surface in a general | schematic square or a general | schematic rectangle as shown in FIG.10 and FIG.11. As a result, even if a photomask or manufacturing line used for a conventional semiconductor circuit chip is diverted, the circuit chip 1c with few cracks and chips can be mass-produced.

  FIG. 13 shows an example of an RFID circuit device on which the circuit chip 1c shown in FIG. 12 is mounted. Unlike the one shown in FIG. 1, the antenna circuit 21-1 is formed in a loop shape on the main surface of one base film (lower base material) 24. The RFID circuit device shown in FIG. 1 transmits and receives information in the UHF band (300 to 3000 MHz) using a dipole antenna, while the RFID circuit device shown in FIG. 13 uses the loop antenna in the HF band (3 to 30 MHz). Send and receive information. FIG. 13B is a perspective view showing in plan the position where the circuit chip 1c of the RFID circuit device is mounted. The main surface of the base film 24 on which the antenna 21-1 is formed is covered with another base film (upper base material) 23, and the base film 23 has two openings 231 exposing both ends of the antenna 21-1. (Indicated by black circles) are formed.

  As shown in FIG. 13A, in the circuit chip 1c in which all of the electrodes 12-1 are provided on one surface (electrode surface) of the semiconductor substrate 10, the electrode surface (not shown for the back surface) is connected to the antenna 21. -1 facing each other. Also in the RFID circuit device assembled in this way, the circuit chip 1c has an outer periphery connected by a smooth arc, so that it is difficult to break against an external force applied to the RFID circuit device.

  In FIG. 13B, four electrodes 12-1 provided on the circuit chip 1c are shown in the same manner as in FIG. 12, and two of them are electrically connected to both ends of the antenna 21-1 through the openings 231 of the base film 23. Connected. This electrical connection is achieved, for example, by joining the antenna 21-1 and the electrode 12-1 with a conductive paste (silver paste or the like) applied to each of the openings 231. On the other hand, the other two electrodes 12-1 are electrically separated from the antenna 21-1 by the base film 23. Although the opening 231 of the base film 23 is shown small in the drawing, the diameter (diagonal dimension when rectangular) is widened in a range smaller than the distance separating the electrodes 12-1 on the main surface of the circuit chip 1c. The shortest distance separating the openings 231 is preferably longer than the diameter or diagonal dimension of the electrode 12-1. Thereby, an electrical short between both ends of the antenna 21-1 by one of the electrodes 12-1, and an electrical short between the electrodes 12-1 by the antenna 21-1 (conductor layer) exposed from one of the openings 231. Is prevented.

  When the side (side wall) of the circuit chip is formed with a smooth curved surface, it is mounted on the substrate on which the antenna is formed by a collet or the like. ) Is difficult, and the possibility of the circuit chip rotating when adsorbed to the collet cannot be denied. With respect to these possibilities (potential problems), it is preferable that the pair located at the diagonal of the electrode 12-1 of the circuit chip 1c shown in FIG. That is, in FIG. 12, two electrodes 12-1 located at the upper right and lower left of the electrode 12-1 are the bonding electrodes 12 shown in FIG. 8B, and two electrodes 12-1 located at the lower right and upper left of FIG. Wiring is preferably formed in the electric circuit 11 of the circuit chip 1c so as to function as the back electrode 13 shown in FIG. As a result, even if the position of the electrode 12-1 of the circuit chip 1c with respect to the two openings 231 (antenna 21-1) is shifted by about 180 ° within the main surface, a desired RFID circuit device is formed, The incidence is reduced.

  FIG. 14 shows another example of the circuit chip in which the positional deviation of the electrode with respect to the antenna is considered. In contrast to the circuit chip 1c shown in FIG. 12 having the main surface on which the four electrodes 12-1 are arranged in a grid, the main surface of the circuit chip 1d shown in FIG. 12-3 are arranged concentrically. A donut-shaped electrode 12-2 is formed apart from the electrode 12-3 on the outside of the electrode 12-3 formed in a circular shape centering on the center of the main surface of the circuit chip 1d (semiconductor substrate 10). Presents a double circle pattern. FIG. 14B shows a perspective view of a part of the planar structure of the RFID circuit device on which the circuit chip 1d is mounted. The RFID circuit device partially shown in FIG. 14B has another main surface of the base film (lower base material) 24 on which the antenna is formed, similarly to the RFID circuit device shown in FIG. It is formed by covering with one base film (upper base material) 23, but the antenna is a dipole type as shown in FIG. 1 and is different from that shown in FIG. The antenna includes two antennas 21 and 22 that extend in the extending direction (longitudinal direction) of the base film 24 and are terminated at the mounting position of the circuit chip 1d of the RFID circuit device. That is, the antenna 21 is directed from the mounting position of the circuit chip 1d of the RFID circuit device toward one of the extending ends of the base film 24, and the antenna 22 is directed from the mounting position toward the other of the extending ends of the base film 24. , Each extending.

  Two openings 231 (shown by black circles) are formed in the base film 23, one of which exposes the end of the antenna 21 and the other of which exposes the end of the antenna 22. The electrodes 12-2 and 12-3 of the circuit chip 1d are joined to the antennas 21 and 22 with a conductive paste as described with reference to FIG. 13B, for example. The desired diameter of each of the openings 231 (diagonal dimension when rectangular) is as described with reference to FIG. 13B, but the desired shortest distance separating the two openings 231 is The diameter or diagonal dimension of the electrode 12-1 is defined by replacing it with a value having a larger difference between the diameter of the electrode 12-3 or the inner diameter and the outer diameter of the electrode 12-2.

  In FIG. 14, the main surface of the circuit chip 1 d is formed in a circular shape, but its outline may be changed to a substantially rectangular shape or a substantially rectangular shape following FIGS. 10 and 11. In any circuit chip 1d, there is a very low risk that the silicon substrate 10 constituting the circuit chip 1d is cracked by a force applied when the chip is mounted on the RFID circuit device or an external force applied to the RFID circuit device on which the circuit chip 1d is mounted.

  In the circuit chip 1d shown in FIG. 14, one of the electrodes 12-3 formed on the main surface thereof is disposed at a substantially central portion of the electric circuit 11 (for example, a transistor array) formed on the main surface. The electrical circuit 11 needs to be redesigned so that the specific portion can be connected to the electrode 12-3. On the other hand, as long as one electrode 12-3 and the electric circuit 11 are electrically connected, the other electrode 12-2 surrounding the outer periphery of the electrode 12-3 There is no restriction of directionality with respect to the electrode 12-3. In other words, if the electrode 12-3 and the connection portion of the external circuit corresponding to the electrode 12-3 (illustrated by reference numeral 231 in FIG. 14B) are aligned, the circuit chip 1d is mounted on the external circuit. Even if it rotates about the electrode 12-3, the electrode 12-2 and the other connection part of the external circuit corresponding to this are reliably electrically connected. Therefore, significant labor saving is realized in the control of the assembly process of the RFID circuit device using the circuit chip 1d.

  The circuit chip 1e shown in FIG. 15 is a variation of the circuit chip 1d shown in FIG. 14, and a concentric electrode 12-3 is formed into a crescent-shaped (U-shaped) electrode 12-4. Another electrode 12-5 which is replaced and formed into an ellipsoid or an oval shape (Oval) is opposed to the inside. A part of the electrode 12-5 is encased in the electrode 12-4, or is fitted into the recess of the electrode 12-4 on the main surface of the circuit chip 1e. The remaining part of the electrode 12-5 is opposed to the end of the main surface of the circuit chip 1e without the electrode 12-4 interposed therebetween. Similarly to the electrodes 12-2 and 12-3 of the circuit chip 1d, the electrodes 12-4 and 12-5 of the circuit chip 1e also have a linear gap because their opposing contours form a curve. Face each other without intervention. Since the electrode formed in this manner also functions as a metal film that reinforces the main surface of the circuit chip, the probability that the circuit chip is broken by an external force applied to the circuit chip is further reduced.

  Compared with the circuit chip 1d shown in FIG. 14, the circuit chip 1e shown in FIG. 15 needs to limit the rotation of the circuit chip 1e around the electrode 12-5 in the mounting process on the external circuit. In the circuit chip 1d of FIG. 14, even if the electrode 12-3 is rotated within an angle range of 360 ° at the maximum, the electrical connection between both the electrodes 12-2 and 12-3 and the external circuit is established. . On the other hand, in the circuit chip 1e of FIG. 15, in order to electrically connect both the electrodes 12-4 and 12-5 and the external circuit, one of the electrodes 12-4 is the other electrode 12-5. Must be narrower than the angle range in the circuit chip 1d of FIG. The maximum value of the rotation angle allowed for the circuit chip 1e in FIG. 15 is the portion (the shortest distance from the electrode 12-4) that is aligned with the external circuit of the electrode 12-5 (for example, the antenna of the RFID circuit device). Depending on the distance, for example, it changes in the range of 90 to 180 °. However, because of the shape of the electrodes 12-4 and 12-5 described above, the circuit chip 1e of FIG. 15 has the following advantages.

  One of the advantages of the circuit chip 1e in FIG. 15 is that each of the electrodes 12-4 and 12-5 is formed at a desired portion of the electric circuit 11 at the periphery of the main surface of the semiconductor substrate 10 on which the electric circuit 11 is formed. It can be electrically connected. For example, in the RFID circuit device, the information on the “object / person” to which the RFID circuit device is affixed and managed thereby has two or more transistors (for example, electric field type) in the region to be the electric circuit 11 on the main surface of the semiconductor substrate 10. It is stored in a “transistor array” that is arranged in a dimension. Therefore, the information to be managed that is read from or written to the transistor array is provided outside the “transistor array” (that is, closer to the periphery of the main surface of the semiconductor substrate 10 than the transistor array). Another circuit (for example, a driver circuit) and the electrodes 12-4 and 12-5 are passed between the transistor array and the external circuit. In the circuit chip 1 d shown in FIG. 14, the pattern of the electric circuit 11 connected to the pair of electrodes 12 is changed at the periphery of the main surface of the semiconductor substrate 10, and connected to one of the pair of electrodes 12 (12-3). The portion must be moved to the center of the main surface of the semiconductor substrate 10. In other words, the fabrication of the circuit chip 1d shown in FIG. 14 requires a photomask for patterning a new electric circuit 11 on the main surface of the semiconductor substrate 10, but the circuit chip 1e shown in FIG. It can be manufactured without preparing a photomask.

  Another advantage of the circuit chip 1e of FIG. 15 is that it is not necessary to cover the conductor surface of the external circuit to which the electrodes 12-4 and 12-5 are connected, respectively. For example, when the external circuit is a pair of antennas 21 and 22 facing each other in the extending direction as shown in FIG. 14B, the width of the antenna 22 connected to the electrode 12-5 (FIG. 14 ( b) the vertical dimension) is equal to or less than the minor axis of the electrode 12-5 (the vertical dimension in FIG. 15), and the rotation angle of the other electrode 12-4 with respect to the electrode 12-5 is within a predetermined range ( For example, the electrode 12-4 connected to the antenna 21 does not overlap the antenna 22, and the electrode 12-5 does not overlap the antenna 21. Therefore, only by changing the shape of the antennas 21 and 22, it is necessary to cover them with an insulating material such as the base film 23 and to form openings that expose only the connection portions with the respective electrodes 12-4 and 12-5. Also disappear. Compared to a fine integrated circuit forming the electric circuit 11, the antennas 21 and 22 are formed large in a simple shape, and therefore can be patterned without using an expensive photomask.

  In the first embodiment, after a groove for separating the circuit chips 1 is formed on one main surface (circuit surface) of the silicon wafer 100 on which the electric circuits 11 (circuit groups 110) of the plurality of circuit chips 1 are formed. Then, the other main surface (back surface with respect to the circuit surface) of the silicon wafer 100 was ground to cut out a plurality of thin circuit chips 1 from the silicon wafer 100. However, a plurality of circuit chips 1 may be separated from the semiconductor wafer 100 by dry etching the “main surface (back surface)” opposite to the circuit surface of the semiconductor wafer (base material) 100.

  In this embodiment, a “groove corresponding to the contour of the circuit chip 1” is dry-etched on the main surface (back surface) opposite to the circuit surface (formed with a plurality of electric circuits) of the silicon wafer 100 (semiconductor substrate). The process of forming a plurality of circuit chips 1 and the structure of the circuit chip 1 characterized or suitable for this process will be described.

  FIG. 16 shows a cross section of the silicon wafer 100 in the course of an example of the process discussed in this embodiment, the contour of which is defined by a pair of grooves 101 and the electric circuit 10 and the electrode 12 formed on the upper surface thereof. A part of the silicon wafer 100 becomes one base material (the aforementioned silicon substrate 10) of the circuit chip 1 cut out therefrom. A huge amount of time is spent in the process of cutting the wafer (base material) 100 obtained by thinly cutting the crystal ingot (Crystal Ingot) in the thickness direction, not limited to silicon. For this reason, in this embodiment, it is preferable to thinly process the wafer from the back surface in advance before forming the groove by dry etching on the back surface of the wafer. The silicon substrate 10 shown in FIG. 16 has a silicon wafer as its base material, a back grind tape 34 attached to the main surface (circuit surface) on which the electric circuit 11 is formed, and the main surface (circuit surface). ) Shows a cross section ground from the opposite side.

  The groove 101 and the round hole 102 shown in FIG. 16 are formed by applying a photoresist to the polished surface (the lower surface in FIG. 16) of the silicon substrate 10 (silicon wafer), and exposing and developing the resist film pattern ( The silicon wafer is etched through the opening. For this reason, the photoresist on the polished surface of the silicon wafer must be exposed to a pattern in accordance with the arrangement of the electric circuit 11 and the electrode 12 on the circuit surface (the upper surface in FIG. 16). Therefore, proper alignment within the polished surface of the silicon wafer is required. For alignment of the photomask in the polishing surface of the silicon wafer, a method of forming a mask positioning mark or a reference mark in advance on the back surface or polishing surface of the silicon wafer (base material of the silicon substrate 10), the back surface side of the silicon wafer The method of measuring the position of the mask on the polishing surface and referring to the information on the circuit surface, and the method of detecting the circuit pattern on the opposite side (circuit surface) together with the mask on the polishing surface of the silicon wafer using an infrared camera Etc. are available.

  In this embodiment, the groove 101 and the round hole 102 have a tapered shape that narrows from the back surface (polishing surface) side of the silicon substrate 10 toward the circuit surface. That is, the inner wall of the groove 101 or the round hole 102 forms a slope that protrudes into the space of the groove 101 or the round hole 102 as it approaches the circuit surface of the silicon substrate 10. When the grooves 101 and the round holes 102 are formed by dry etching with a large aspect ratio, the inclination of the inner walls becomes steeper than those formed by wet etching. The inner wall of the round hole 102 formed by dry etching forms a taper that narrows in the opposite direction to the round hole 102 of Example 1 illustrated in FIG. 6B. Thus, when the back surface (polished surface) of the silicon substrate 10 is plated or vapor-deposited with a conductive material such as a metal or an alloy, a film of the conductive material that extends without interruption from the polished surface to the circuit surface side is surely formed in the round hole 102. Formed. As a result, when the back electrode as described in the first embodiment is formed on the polished surface of the silicon substrate 10, this and the electric circuit 11 (lower part) can be easily and reliably electrically passed through the conductor film formed in the round hole 102. Connected to.

  In this embodiment, the etching aspect ratio discussed in the first embodiment can be redefined as the ratio of the etching depth to the inclination of the surface (inner wall or side wall) formed by etching. For example, in FIG. 16, the aspect ratio of the etching that forms the circular hole 102 through the silicon substrate 10 from the back surface (polishing surface) to the circuit surface is “the end of the circuit surface” and “the back surface of the circular hole 102. The difference ΔR from the “projection of the end of the substrate onto the circuit surface” is used as the denominator, and the depth of the round hole 102 (that is, the thickness of the silicon substrate 10) is obtained as the numerator t. The value serving as the denominator is also the distance between the “real end” and the “end projected from the back surface” of the round hole 102 in the circuit plane of the silicon substrate 10.

  As the appearance of the circuit chip 1 formed of the silicon substrate 10 having a circular main surface gets closer to a cylinder, the circuit chip 1 becomes harder to break against an external force applied to the side wall. In other words, not only in the present embodiment but also in the first embodiment, when the circuit chip 1 exhibits a truncated cone, the other main surface having a larger area than one main surface has a peripheral edge outside the peripheral edge of the one main surface. As a result, the external force from the side wall of the silicon substrate 10 (circuit chip 1) is intensively received. Therefore, in order to separate the silicon substrate 10 corresponding to each circuit chip 1 from a base material such as a silicon wafer, dry etching with a high aspect ratio is desired. Recently, a deep RIE (Reactive Ion Etching) method capable of forming a groove in a semiconductor substrate such as a silicon wafer with an aspect ratio of 50 or more has been developed, and an etching apparatus suitable for this method is disclosed in, for example, Unixis USA, Inc. (Unaxis USA Inc.) is sold as model name: DSE-III.

  The Deep RIE method is also called a Bosch process, and includes a step of dry etching (isotropic etching) of a semiconductor substrate and a step of covering an etched surface (for example, the inner wall of a groove) with a passivation film (hereinafter referred to as a passivation step). ) Is repeated to dig a deep groove in the silicon substrate with a high aspect ratio. Since the etching surface formed in the dry etching process is protected by a fluororesin layer (for example, a polytetrafluoroethylene-like polymer) in the subsequent passivation process, the etching surface is etched in the subsequent dry etching process. It becomes difficult to be done. As a result, although the groove of the silicon substrate is deeply dug for each dry etching step, the lateral retreat of the inner wall (spreading of the groove in the lateral direction) is negligibly small. Also, by optimizing the supply amount of etching gas in the dry etching process and the output of plasma generated by this etching gas, the etching rate of silicon (Si) by deep RIE method is improved to 20 μm or more per minute. ing.

  An example of the manufacturing process of the circuit chip 1 using the Deep RIE method will be described with reference to FIG. FIG. 17A shows a cross section of the silicon wafer 100 on which a plurality of electric circuits 11 (corresponding to the circuit group 110 in FIG. 2) are formed on the main surface. In FIG. 17A, the formation region of the electric circuit 11 is shown in the thickness direction of the silicon wafer 100. The area of the electric circuit 11 in the main surface of the silicon wafer 100 is shown in FIG. 1C as an interface circuit for transferring signals to / from an external circuit of a memory element (for example, a transistor array) or a circuit chip that can be formed here. Similarly, a pair of field effect transistors TR1 and TR2 are representatively shown. The field effect transistors TR1 and TR2 are modified by adding an active region (channel) CHN or p-type impurity modified by adding an n-type impurity in the vicinity of the main surface of the silicon wafer 100 which is an intrinsic semiconductor. An active field (channel) CHP is formed on an insulating film (gate insulating film) GI and an insulating film GI covering the main surface of the silicon wafer 100 including the active region, and an electric field is applied to the active region via the insulating film GI. A wiring layer (gate electrode) GT to be applied and a wiring layer WL formed on the insulating film GI and electrically connected to the active region through an opening formed in the insulating film GI are provided. Even if the field effect transistor is replaced with a bipolar transistor or a diode, the active region and the wiring layer are formed in the silicon wafer 100 or on the main surface thereof in a shape corresponding to each of these equivalents. The insulating film INS that covers the insulating film GI and the wiring layers GT and WL protects structures such as the wiring layers GT and WL formed on the main surface of the silicon wafer 100 from the atmosphere of the circuit chip, or around the circuit chip. Prevent unexpected electrical shorts with external circuits. In other words, the region defined as the electric circuit 11 in the present specification is distinguished from other regions by forming at least one of an active region obtained by modifying the silicon wafer 100 and a wiring layer. The wiring layers are not limited to those forming active elements such as field effect transistors TR1 and TR2, but also include those that connect them and those that connect them to external circuits. In FIG. 17A, the main surface (upper surface) of the silicon wafer 100 in which the active regions CHN and CHP described above are formed and the wiring layers GT and WL are provided is also referred to as a “circuit surface”.

  On the other hand, the main surface of the silicon wafer 100 (for example, the region defined as the circuit group 110 in FIG. 2A) is adjacent to the element region (I) for providing the electric circuit 11 and this element region (I). A trench 101 for separating the semiconductor substrate 10 corresponding to each circuit chip from the silicon wafer 100 is formed in the separation region (II). .

  FIG. 17B shows a conductor layer CND formed on the main surface (lower surface, hereinafter referred to as the back surface) opposite to the circuit surface of the silicon wafer 100, and a resist RE1 for patterning the conductor layer CND is a conductor. The cross section of the silicon wafer 100 after being formed on the layer CND is shown. The conductor layer CND is formed into a pair of electrodes 12 (for example, the electrodes 124 and 125 shown in FIG. 15) that connect the electric circuit 11 and the external circuit by etching through the opening pattern of the resist RE1. On the back surface of the silicon wafer 100, there is a connection region (III) for connecting the electrode 12 formed thereon and the electric circuit 11 formed on the circuit surface of the silicon wafer 100 together with the separation region (II) described above. It is prescribed. Excavation of the groove 101 and the round hole 102 by the Deep RIE method described later is performed through the opening OP1 of the resist RE1 in each of the separation region (II) and the connection region (III). Compared to the electrical circuit 11 (for example, transistor array) on the circuit surface of the silicon wafer 100, the electrode 12 and the opening OP1 can be patterned more roughly. Therefore, the patterning of the resist RE1 required for this is less expensive than photolithography, such as screen printing. Can be used. In the screen printing of the resist RE1, a pattern of the resist RE1 corresponding to the electrode 12 and the opening OP1 is formed on the conductor layer CND at the stage of applying the resist RE1 on the conductor layer CND. The positions of the electrodes 12 and the openings OP1 with respect to the pattern of the plurality of electric circuits 11 (circuit group 110) formed on the circuit surface of the silicon wafer 100 are the orientation flat OF of the silicon wafer 100 shown in FIG. Can be adjusted based on

The conductor layer CND is usually formed as a thin film of metal or alloy, and when formed of aluminum (Al), it is a plasma generated with boron chloride (BCl ₃ ) and chlorine (Cl ₂ ), and is formed with copper (Cu). When formed, they are each dry-etched with plasma generated from boron chloride (BCl ₃ ), nitrogen (N ₂ ), and argon (Ar). FIG. 17C shows a cross section of the silicon wafer 100 in which the pair of electrodes 12 are provided on the back surface by dry etching of the conductor layer CND. On the back surface of the silicon wafer 100, a new resist pattern RE2 is formed to cover the silicon wafer 100 and the pair of electrodes 12. The resist RE2 is applied on the resist RE1 by screen printing, for example, so that only the opening OP2 corresponding to the excavated portion of the groove 101 and the round hole 102 is formed. The resist RE2 protects a region that is not excavated by the Deep RIE method performed in the next stage, and the coating region may be limited to the opening of the resist RE1 provided only for patterning the electrode 12. The back surface of the silicon wafer 100 having the cross section shown in FIG. 17C is schematically shown in FIG. The silicon wafer 100 shown in FIG. 18A is etched through the opening OP2 of the resist RE2 formed on the back surface thereof, and is separated into ten semiconductor substrates 10 by the groove 101 dug. A region corresponding to one of the semiconductor substrates 10 is surrounded by a broken-line circle in FIG. However, in actual mass production of circuit chips, several thousand to several tens of thousands of semiconductor substrates 10 are cut out from one of them depending on the diameter of the silicon wafer 100.

  The silicon wafer 100 shown in FIG. 17C is the same as the above-described Unaxis USA, Inc. It is carried in the case of an etching apparatus suitable for Deep RIE processing such as DSE-III type. This etching apparatus forms inductively coupled plasma (ICP) of an etching gas in a housing, and a sample such as a wafer in the housing has an etching gas inductively coupled plasma. It is placed so as to face plasma (hereinafter referred to as plasma). Plasma is generated by applying a high frequency electric field of 10 MHz to 50 MHz, and excitation at 13.56 MHz by a crystal oscillator is widely used. Further, the plasma is stabilized by using a self-excited oscillator (for example, oscillation frequency: 40 MHz) that easily follows the replacement of the plasma gas in the dry etching process and the passivation process described above. On the other hand, the holder on which the sample is placed is also called a platen and has a function of applying an alternating voltage to the sample. The silicon wafer 100 is placed on the circuit surface (upper surface in FIG. 17C) in contact with the platen. Thereby, the back surface (the lower surface in FIG. 17C) of the silicon wafer 100 is exposed to radicals and ions emitted from the plasma.

The processing of the silicon wafer 100 by the Deep RIE method is performed using sulfur hexafluoride (SF ₆ ) and oxygen (O ₂ ) in a dry etching process, and octafluorocyclobutane (C ₄ F ₈ ) in a passivation process. ) Are supplied to the plasma generators in the above-depressed cases, and the supply amount of plasma gas (including etching gas) is, for example, SF ₆ : 130 sccm, O ₂ : 20 sccm in the former, and in the latter C ₄ F ₈ is set to 50 sccm, respectively. Note that sccm (Standard Cubic Centimeter per Minute) is a unit of flow rate that indicates the flow rate of gas or the like in a standard state (for example, 0 ° C., 1 atm). In the dry etching process, SF ₅ ⁺ and F (fluorine) radicals released from the plasma generate SiF _x on the surface of the silicon wafer 100 to promote etching of the silicon wafer 100, while O (oxygen) released from the plasma. ) _SiF x _{O y} that is generated to protect the etched surface (especially the inner wall of the groove 101 and the circular hole 102) from further etching by. In the passivation process, CF ₂ released from the plasma generates CF _x to promote protection of the etched surface. Further, the platen is controlled so that an AC voltage is applied to the silicon wafer 100 in the dry etching process and the voltage application is stopped in the passivation process. Thus, in the dry etching process, SF ₅ ⁺ is drawn to the bottom surface of the groove and is instantaneously discharged from the groove. Therefore, the etching of the groove proceeds preferentially in the depth direction, and a cylindrical deep groove having a high aspect ratio of 50 or more is formed.

In the Deep RIE method, the dry etching process and the passivation process are alternately repeated, so that the groove excavation is intermittent. As a result, a plurality of concave surfaces are repeatedly formed on the inner wall of the groove along the depth direction (corresponding to the processing time by Deep RIE method). The groove dug in a circle in the thickness direction of the silicon wafer 100 exhibits a bellows-like outer periphery due to this concave surface. This concave surface is called scallops, and its appearance period along the depth direction of the groove is reduced to 0.5 μm (0.5 × 10 ⁻⁶ m) by improving the etching apparatus. In the processing of a silicon substrate by the Deep RIE method, it is pointed out that if the scallop is formed with a depth of 260 nm (260 × 10 ⁻⁹ m) to 350 nm with respect to the inner wall of the groove, the silicon substrate may be cracked. ing. However, when the silicon substrate 10 described in the first embodiment is cut out from the silicon wafer 100 by the Deep RIE method and the back electrode 13 is formed on the side surface of the silicon substrate 10, cracks due to scallops are suppressed by the back electrode 13. For example, even if a scallop is formed on the side surface of the silicon substrate 10 at a depth of 500 nm, in other words, if the etching depth to the side of the silicon substrate 10 is suppressed to 500 nm or less, the back electrode 13 is reinforced. Cracks are unlikely to occur on the side surface of the silicon substrate 10 thus formed.

  On the other hand, the scallop becomes shallow by shortening the repetition cycle of the dry etching process and the passivation process. For example, if this period is suppressed to 1 second or less, the scallop depth can be suppressed to a range of 30 nm to 40 nm. If the silicon substrate 10 of the present embodiment, which will be described later, is discussed in terms of its application to the circuit chip 1, it is possible to suppress the depth of the scallop to 100 nm or less, so that the silicon substrate can be obtained without the above-described back electrode 13 reinforcement. Cracks on the 10 side surfaces are less likely to occur.

FIG. 17D shows a cross section of the silicon wafer 100 in which the grooves 101 and the round holes 102 are formed by the above-described Deep RIE method. In the dry etching process of the Deep RIE method, there is a possibility that the opening pattern OP2 of the resist RE2 (RE1) that determines the shape of the groove 101 or the round hole 102 is deformed by ions or radicals. Although this possibility can be reduced by baking or curing the resist, in this embodiment, the opening OP2 is also formed in the conductor layer CND protruding into the isolation region (II), and used as a mask for dry etching of the silicon wafer 100 together with the resist. used. The silicon wafer 100 is separated into a plurality of silicon substrates (semiconductor substrates) 10 corresponding to the circuit chip 1 by the grooves 101. These are two layers of insulating films GI and INS formed on the circuit surface of the silicon wafer 100. It is connected. When each of the insulating films GI and INS is formed of silicon oxide (SiO _x ) or silicon nitride (SiN _x ), dry etching using plasma generated from tetrafluoromethane (Tetrafluoromethane, CF ₄ ) These are removed. The dry etching using the CF ₄ plasma does not impair the shape of the groove 101 and the round hole 102 already formed in the silicon wafer 100, and the silicon wafer 100 is placed in the case of the etching apparatus used for the Deep RIE method. You can do it while it is still mounted. In this example, the insulating film GI exposed from the bottom surfaces of the groove 101 and the round hole 102 was etched by dry etching using CF ₄ plasma.

  Thereafter, the silicon wafer 100 was taken out of the housing of the etching apparatus, and the opening OP2 corresponding to the groove 101 was closed by partial reflow of the resist RE2. The opening OP2 of the resist RE2 corresponding to the groove 101 can also be closed by screen printing an additional resist in the opening OP2 of the resist RE2. Furthermore, a conductive film CND2 is formed on the inner wall of the round hole 102 by electroless plating on the back surface of the silicon wafer 100, and the electrode 12 and the electric circuit 11 (specific part thereof) on the circuit surface are electrically connected by this conductive film. Through-holes TH were formed. FIG. 17E shows a cross section of the silicon wafer 100 after the through holes TH are formed. The surplus conductor film CND2 formed on the resist RE2 is removed together with the resists RE1 and RE2 from the back surface thereof by chemical cleaning of the silicon wafer 100.

Finally, the insulating film INS exposed from the bottom surface of the groove 101 formed in the insulating film GI is removed by dry etching using CF ₄ plasma, and a plurality of silicon substrates are removed from the silicon wafer 100 as shown in FIG. 10 is separated. An example of the planar structure of the silicon substrate 10 viewed from the back side of the silicon wafer 100 is shown in FIG. In FIG. 18B, the structure visible on the main surface of the silicon substrate 10 is only the electrode 12, and as illustrated in FIG. 15 in Example 1, one electrode 12-4 formed in an arc shape, The electrode 12-4 is formed into the other electrode 12-5 having a portion facing and surrounded by the inner peripheral side of the arc. The outline of the electric circuit 11 formed on the opposite side of the main surface of the silicon substrate 10 and the through that penetrates the silicon substrate 10 and electrically connects the electric circuit 11 and the lower surfaces of the electrodes 12-4 and 12-5. The outline of the hole TH is indicated by a dotted line. The silicon substrate 10 having such a main surface is formed in a cylindrical shape by the Deep RIE method.

  A circle C11 drawn by a dotted line in the main surface of the silicon substrate 10 in FIG. 18B is a circumscribed circle of the electric circuit 11 viewed from this main surface, and a circle C12 drawn by a broken line is this main surface. Is a circumscribed circle of the electrode groups 12-4 and 12-5 as seen from FIG. It is desirable that both of the electrode groups 12-4 and 12-5 are formed away from the end portion of the main surface of the silicon substrate 10. However, the circumscribed circle C11 and the electric circuit 11 and the electrodes are arranged so that the circumscribed circle C11 is contained within the circumscribed circle C12. It is desirable to design groups 12-4 and 12-5. Thereby, the dry etching process by the Deep RIE method does not affect the characteristics of the active elements (transistors and the like) formed in the electric circuit 11. From the same viewpoint, it is desirable to make the diameter R11 of the circumscribed circle C11 smaller than the diameter R12 of the circumscribed circle C12. In FIG. 18B, the two circumscribed circles C11 and C12 are shown as concentric circles with the center R0 of the main surface of the silicon substrate 10. However, as long as the circumscribed circle C11 is within the circumscribed circle C12, the respective centers may be shifted. Good. When the main surface of the silicon substrate 10 has a contour as shown in FIG. 10, the circumscribed circles C11 and C12 project outside the contour of the main surface, but the relationship between the formation regions of the electrode 12 and the electric circuit 11 is as follows. These are appropriately defined.

  The Deep RIE method described in the present embodiment can also be applied to the method of cutting the silicon substrate 10 by excavating the groove 101 of the silicon wafer 100 described in the first embodiment from the circuit surface. FIG. 19 shows an example of a silicon wafer 100 processed by the process of Example 1 to which the Deep RIE method is applied. A plurality of electric circuits 11 formed on the silicon wafer 100 are also represented by a pair of field effect transistors TR1 and TR2, similarly to the other examples shown in FIG. 1C and FIG. Indicated. Of the structure formed on the silicon wafer 100 and its upper surface (circuit surface), each of the structures shown in FIG. 17A is given the same reference numeral as in FIG. The structure most characteristic of the silicon wafer 100 shown in FIG. 19 is formed on the insulating film INS1 covering each electric circuit 11 with antennas 210 and 220 formed on the circuit surface. The antennas 210 and 220 are connected to the corresponding electric circuit 11 by through holes TH penetrating the insulating film INS1. The antennas 210 and 220 are formed in a spiral shape above the electric circuit 11 as shown in FIG. 13B, and the RFID circuit device may be constituted only by the circuit chip 1 (silicon substrate 10). May be used in a non-contact manner coupled to the antennas 21 and 22 formed on the base films 23 and 24 shown in FIG. In the latter case, the conductor patterns of the antennas 210 and 220 formed on the main surface of the circuit chip 1 (silicon substrate 10) are capacitively coupled or inductively coupled to the antennas 21 and 22 formed on the substrate on which the circuit chip 1 is mounted. To do. Information is written to such an RFID circuit device by an external terminal when signals (for example, electromagnetic waves) corresponding to this information are received by the antennas 21 and 22 of the RFID circuit device, and on the antennas 21 and 22 according to the signal. The electric fields of the circuit chip 1 are detected by the antennas 210 and 220 of the circuit chip 1 and a current corresponding thereto is sent to the electric circuit 11. Further, in reading out information from the RFID circuit device, a “current from the electric circuit 11 to the antennas 210 and 220” is induced in the circuit chip by the signal from the external terminal. The electric field on 220 fluctuates, and the external terminal reads the electromagnetic waves (signals) induced by the antennas 21 and 22 due to the “electric field fluctuation on the antennas 210 and 220”.

  In the RFID circuit device described above with reference to FIGS. 1, 13, and 14, the antennas 21 and 22 that have received electromagnetic waves (signals) flow a current corresponding to the electric field that fluctuates directly to the electric circuit 11. Thus, information is written in this, and the antennas 21 and 22 directly receive the current from the electric circuit 11 and emit an electromagnetic wave (signal) corresponding thereto, thereby causing the external terminal to read this information. It was. However, in the circuit chip 1 obtained from the silicon wafer 100 shown in FIG. 19, it is not necessary to provide a current path between the electric circuit 11 formed on the silicon chip 100 and the antennas 21 and 22 which can be said external circuits. For this reason, the antennas 210 and 220 are provided with at least a part for electrical connection with the antennas 21 and 22 like each electrode (bonding electrode 12 and back electrode 13) of the other circuit chip 1 described above. It is not necessary to expose it. Therefore, it may be covered with another insulating film INS2 together with the insulating film INS1 covering the electric circuit 11 (wiring layers GT, WL). In view of the step of cutting the silicon substrate 10 from the silicon wafer 100 by the Deep RIE method described below, the insulating films INS1 and INS2 are preferably formed of silicon oxide or silicon nitride.

In the silicon wafer 100 shown in FIG. 19, a groove 101 for separating the silicon substrate 10 from the circuit surface (upper surface in FIG. 19) is formed by dry etching. A trench 101a is formed in the insulating films GT, INS1, and INS2 that protect the GT and WL, the antennas 210 and 220, and the active regions CHN and CHP). The step of forming the groove 101a of the insulating films GT, INS1, and INS2 by dry etching is performed in the case of the etching apparatus used for forming the groove 101 of the silicon wafer 100 by deep RIE. In this housing, the silicon wafer 100 is disposed such that the back surface (the lower surface in FIG. 19) is held by the platen and the circuit surface faces the plasma generator. Further, in contrast to the above-described process of the present embodiment, CF ₄ is supplied to the plasma generator in the casing, and thereafter, a mixed gas of SF ₆ and O ₂ and C ₄ F ₈ are alternately supplied. Is done. The dry etching of the insulating films GT, INS1, and INS2 is performed through an opening OPN formed at a position corresponding to the groove 101 of the resist RES applied on the uppermost surface of the insulating film INS2. For example, with respect to the silicon wafer 100 having a thickness of 200 μm to 300 μm, the total thickness of the insulating films GT, INS1, and INS2 stacked on the circuit surface is very small, for example, 1 of the thickness of the silicon wafer 100. / 10 or less. Therefore, the laminated structure of the insulating film GT, INS1, INS2, grooves 101a in a conventional dry etching with plasma generated by the CF ₄ is formed. Thereafter, the groove 101 of the silicon wafer 100 is excavated from the bottom surface of the groove 101a toward the back surface of the silicon wafer 100 by Deep RIE. The process conditions of the dry etching process and the passivation process in Deep RIE can be set in the same manner as in the present embodiment described with reference to FIG. The insulating film INS3 formed on the back surface of the silicon wafer 100 is used to connect the individual silicon substrates 10 separated by the grooves 101 reaching the back surface of the silicon wafer 100, and after the silicon wafer 100 is removed from the platen. It is removed by polishing or etching. The insulating film INS3 may be formed of an insulating material (metal oxide film, nitride film, resin film) other than silicon oxide or silicon nitride. Further, when the singulated silicon substrate 10 is directly recovered from the platen, the insulating film INS3 may not be formed.

  FIG. 20A shows a cross-sectional structure of the silicon substrate 10 (circuit chip) obtained from the silicon wafer 100 shown in FIG. FIG. 20B shows a cross-sectional structure of the silicon substrate 10 on which the electrode 12 is formed instead of the antennas 210 and 220 described above on the insulating film INS1. The sidewalls of any of the silicon substrates 10 are formed with a high aspect ratio by Deep RIE, as in the sidewalls of the silicon substrate 10 shown in FIG. 17 (f), and each appearance has a cylindrical shape, for example. Strictly speaking, the scallops (recesses) described above can be arranged in the thickness direction on each side wall of the silicon substrate 10, but the depth is suppressed to 100 nm or less, and thus, for example, a cylindrical appearance has a bellows shape. The silicon substrate 10 is not cracked due to scallops. The antennas 210 and 220 shown in FIG. 20A and the electrode 12 shown in FIG. 20B are different in planar shape in the main surface of each silicon substrate 10, and at least one of the electrodes 12 is different. The portion is exposed from the insulating film INS2. In FIG. 20B, the entire upper surface of the electrode 12 is exposed by not forming the insulating film INS2 over the insulating film INS1. The connection with the electric circuit 11 is similarly configured with respect to the antennas 210 and 220 in FIG. 20A and the electrode 12 in FIG. The desired arrangement of the antennas 210 and 220 and the electric circuit 11 in the main surface of the silicon substrate 10 is defined with reference to FIG. 18B as in the case of the desired arrangement of the electrode 12 and the electric circuit 11. The

Since the circuit chip and the RFID circuit device according to the present invention can maintain their functions even in an environment susceptible to impact, cargo loaded on an aircraft, vehicle, ship, etc., and laundry in a cleaning industry, linen supply industry, and hospital It is possible to attach to the label, and the information on the cargo and the laundry is surely managed.

BRIEF DESCRIPTION OF THE DRAWINGS The perspective view of the RFID circuit device (RFID tag) by Example 1 of this invention and the enlarged view which shows the mounting structure of the circuit chip in this are shown. In Example 1 of this invention, the perspective view of the semiconductor wafer in which the circuit group cut out to a some circuit chip was formed in the main surface, and the top view of the pattern of the electric circuit formed in each of this circuit pattern are shown. In Example 1 of this invention, the plane arrangement | positioning figure of the electric circuit and electrode according to the some circuit chip formed in the main surface of a semiconductor wafer is shown. The perspective view of the semiconductor wafer prepared for the manufacturing process of the circuit chip in Example 1 of this invention and the top view of the pattern of the electric circuit formed in the main surface are shown. FIG. 4 is a sectional view of a semiconductor wafer having a groove formed by dry etching, “a portion where an electric circuit corresponding to one circuit chip is formed (hereinafter referred to as a chip portion)” and its vicinity according to the first embodiment of the present invention. . 1 is a perspective view of a semiconductor wafer having a back grind tape affixed to a circuit surface from the back side, and a cross-sectional view of the chip portion of the semiconductor wafer after the back surface is ground and the vicinity thereof according to the first embodiment of the present invention. Indicates. 1 is a perspective view of a semiconductor wafer with a back grind tape affixed to a circuit surface from the circuit surface side, and the semiconductor after a metal film is formed on the back surface (ground surface) according to the first embodiment of the present invention; Sectional drawing of the wafer chip part and its vicinity is shown. 1 is a perspective view of a holding tape in which a plurality of semiconductor substrates (circuit chips) cut out from a semiconductor wafer are transferred from a back grind tape, and a semiconductor substrate transferred to the holding tape (the above chip portion) according to Embodiment 1 of the present invention; ) Is a cross-sectional view. FIG. 3 is a plan view of an electric circuit and electrodes in a plurality of chip portions (each cut out on a semiconductor substrate) formed on the main surface of the semiconductor wafer according to the first embodiment of the present invention. FIG. 10 is a plan layout view of electric circuits and electrodes different from FIG. 9 in a plurality of chip portions formed on the main surface of the semiconductor wafer according to the first embodiment of the present invention. FIG. 11 is a plan layout view of electric circuits and electrodes different from those in FIGS. 9 and 10 in a plurality of chip portions formed on the main surface of the semiconductor wafer according to the first embodiment of the present invention. The top view of the semiconductor substrate main surface by Example 1 of this invention is shown. FIG. 13 is a perspective view of an RFID circuit device on which the semiconductor substrate (circuit chip) shown in FIG. 12 is mounted, and an enlarged view of a circuit chip mounting structure in the RFID circuit device. The top view of another circuit chip (semiconductor substrate) principal surface by Example 1 of this invention and the enlarged view of the mounting structure in the RFID circuit device are shown. The top view of another semiconductor substrate main surface by Example 1 of this invention is shown. FIG. 4 is a cross-sectional view of a chip portion of a semiconductor wafer in which a groove is formed by dry etching and its vicinity according to a second embodiment of the present invention. Sectional drawing explaining the process of cutting out the semiconductor substrate (formation of a circuit chip) including the etching by Deep RIE method in Example 2 of this invention is shown. The schematic top view of the opening pattern of the resist film formed in the semiconductor wafer main surface in Example 2 of this invention, and the top view explaining arrangement | positioning of the electric circuit and electrode in a semiconductor substrate main surface are shown. Sectional drawing of the semiconductor wafer processed by the process of Example 1 to which Deep RIE method was applied is shown. FIG. 3 shows a cross-sectional view of another circuit chip according to the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Circuit chip, 10 ... Silicon substrate, 11 ... Electric circuit, 12, 12-1-5 ... Electrode (bonding electrode), 13 ... Back electrode, 21, 22 ... Antenna, 23, 24 ... Film, 31 ... Photoresist Pattern, 32 ... hole shape of photoresist pattern, 34 ... back grind tape, 35 ... holding tape, 36 ... holding frame, 100 ... wafer, 101 ... groove, 102 ... round hole, 110 ... circuit group, 111 ... residual Part, CHN ... active region (channel, N type), CHP ... active region (channel, P type), CND, CND1, CND2 ... conductor layer, GI ... insulating film (gate insulating film), GT ... wiring layer (gate electrode) ), INS ... insulating film, OF ... orientation flat, OPN, OP1, OP2 ... opening, RES, RE1, RE2 ... resist, TH ... through hole, R1, TR2 ... transistor, WL ... wiring.

Claims (23)

A semiconductor substrate comprising a pair of main surfaces and a side wall interposed between the pair of main surfaces;
An electric circuit formed on one of the pair of main surfaces; and a plurality of conductor layers formed on one or both of the pair of main surfaces and connected to the electric circuit, respectively. Each of the surfaces has a contour whose extending direction in the main surface changes only through a curve. 2. The circuit chip according to claim 1, wherein the outline of each main surface of the semiconductor substrate includes at least one straight line and at least one curved line extending from both ends of the straight line. Each of the outlines of the main surface of the semiconductor substrate is formed in a rectangular shape by the four straight lines and the four curved lines respectively extending between adjacent pairs of the straight lines. The circuit chip according to claim 2. 2. The circuit chip according to claim 1, wherein the outline of each of the main surfaces of the semiconductor substrate is formed in a circle or an ellipse by a continuously extending curve. 2. The circuit chip according to claim 1, wherein an angle at which a pair of straight lines extending in different directions intersect is not formed in each of the outlines of the main surface of the semiconductor substrate. 2. The circuit chip according to claim 1, wherein an extending direction of the side wall of the semiconductor substrate is changed only by a curved surface defined by the curve of the contour of the main surface. The circuit chip according to claim 6, wherein a ridge line formed by the intersection of a pair of planes extending in different directions is not formed on the side wall of the semiconductor substrate. 2. The circuit chip according to claim 1, wherein the side wall of the semiconductor substrate is formed by dry etching that is advanced from any one of the main surfaces of the semiconductor substrate in a thickness direction of the semiconductor substrate. The plurality of conductor layers include a first electrode formed on the one of the main surfaces of the semiconductor substrate and a second electrode formed on the other of the main surfaces of the semiconductor substrate,
The second electrode is electrically connected to the electric circuit through an opening of the semiconductor substrate formed together with the side wall of the semiconductor substrate by the dry etching advanced in the thickness direction of the semiconductor substrate from the other main surface. 9. The circuit chip according to claim 8, wherein: The circuit chip according to claim 9, wherein the second electrode extends from the other main surface of the semiconductor substrate to the side wall and covers the side wall. The plurality of conductor layers include a first electrode and a second electrode formed separately from each other on one of the main surfaces of the semiconductor substrate,
The at least part of the first electrode is surrounded by an inner periphery of the second electrode provided between the part and an end of the main surface and curved toward the part. The circuit chip according to 1. 12. The circuit chip according to claim 11, wherein the other part of the first electrode is opposed to the end of the main surface of the semiconductor substrate without being opposed to the second electrode. The circuit chip according to claim 11, wherein the second electrode is formed in an annular shape in which the inner periphery surrounds the outer periphery of the first electrode. The diameter of a circumscribed circle surrounding the electric circuit or projection thereof on any one of the main surfaces of the semiconductor substrate is smaller than a diameter of the circumscribed circle surrounding the plurality of conductor layers or projections on the main surface. Item 1. The circuit chip according to Item 1. The electrical circuit is formed in a region separated from the contour of the main surface on the one main surface of the semiconductor substrate, and a plurality of active elements are formed in the region. Item 1. The circuit chip according to Item 1. The circuit chip according to claim 15, wherein an outline of the region has a polygonal shape on the one main surface of the semiconductor substrate. The circuit chip according to claim 9,
A first base material having a first antenna formed on a main surface; and a second base material having a second antenna formed on a main surface;
The first electrode of the circuit chip is connected to one end of the first antenna, and the second electrode is connected to one end of the second antenna.
An RFID circuit device, wherein an extending direction of the first antenna from the one end to the other end is different from a direction of the second antenna extending from the one end to the other end. A circuit chip according to claim 12, and a substrate having a main surface formed by separating the first antenna and the second antenna from each other,
One end of the first antenna and one end of the second antenna face each other on the base material main surface,
One end of the first antenna is connected to the first electrode, and one end of the second antenna is connected to the second electrode.
The first antenna extends from the one end to the other end beyond the other portion of the first electrode;
The RFID circuit device, wherein the second antenna extends from the one end to the other end beyond the outer periphery of the second electrode. 19. The RFID circuit device according to claim 18, wherein an insulating layer covering the first antenna and the second antenna is not formed in at least a region of the main surface of the base material where the circuit chip is mounted. . The circuit chip according to any one of claims 11 to 13,
A base material having a main surface formed by separating the first antenna and the second antenna from each other, and an insulating film formed in at least a region on which the circuit chip is mounted on the main surface of the base material;
The insulating film is formed with at least two openings exposing the first antenna and the second antenna,
The RFID circuit device, wherein the first electrode and the second electrode of the circuit chip are electrically connected to the first antenna and the second antenna through the opening, respectively. A first step of preparing a semiconductor wafer having a first main surface formed by separating a plurality of electric circuits from each other;
A second step of forming a resist film on one of the first main surface and the second main surface opposite to the first main surface of the semiconductor wafer, and forming an opening pattern for separating the plurality of electric circuits from each other on the resist film. ,
A third step of etching the one main surface of the semiconductor wafer through an opening pattern of the resist film to form a groove extending from the one main surface to the other main surface in the thickness direction of the semiconductor wafer; And a fourth step of separating a plurality of semiconductor substrates each having the electric circuit from the semiconductor wafer by the grooves formed in the third step in this order,
In the second step, an opening pattern of the resist film forms a contour that surrounds each of the electric circuits in the one main surface or an outer periphery of the projection, and each of the contours is in the one main surface. A method of manufacturing a circuit chip, characterized in that the extending direction in the circuit changes only through a curve. In the third step, the semiconductor wafer is etched by dry etching,
22. The method of manufacturing a circuit chip according to claim 21, wherein the inner wall along the contour of the groove is formed by a curved surface or a plurality of curved surfaces and a plurality of planes respectively separated by the curved surface. 22. The method of manufacturing a circuit chip according to claim 21, wherein the etching of the semiconductor wafer in the third step is performed by alternately repeating dry etching of the semiconductor wafer and passivation of the surface etched thereby. .

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