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JP2008211385A - Manufacturing method of piezoelectric thin film, resonator, and filter for uwb using the same - Google Patents

Manufacturing method of piezoelectric thin film, resonator, and filter for uwb using the same Download PDF

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JP2008211385A
JP2008211385A JP2007044556A JP2007044556A JP2008211385A JP 2008211385 A JP2008211385 A JP 2008211385A JP 2007044556 A JP2007044556 A JP 2007044556A JP 2007044556 A JP2007044556 A JP 2007044556A JP 2008211385 A JP2008211385 A JP 2008211385A
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thin film
piezoelectric thin
support substrate
piezoelectric
manufacturing
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Takeo Shirai
健雄 白井
Yoshiki Hayazaki
嘉城 早崎
Chomei Matsushima
朝明 松嶋
Xiong Si-Bei
四輩 熊
Takaaki Yoshihara
孝明 吉原
Norihiro Yamauchi
規裕 山内
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Panasonic Electric Works Co Ltd
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Matsushita Electric Works Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a piezoelectric thin film improving crystallinity in the piezoelectric thin film, to provide a resonator improving crystallinity in the piezoelectric film, and to provide a filter for UWB using the resonator. <P>SOLUTION: In the manufacturing method of the piezoelectric thin film includes, a buffer layer formation process, a piezoelectric thin film formation process, and a stress application layer formation process. In the buffer layer formation process, a buffer layer 2, which is made of a material having a thermal coefficient of expansion intermediate between a piezoelectric material and a substrate material, is formed by a sputtering method, or the like on one surface side of a support substrate 1 made of the material (substrate material) whose thermal coefficient of expansion is smaller than that of the material (piezoelectric material) of the piezoelectric thin film 3. In the piezoelectric thin film formation process, the piezoelectric thin film 3 is formed on the buffer layer 2 by the sputtering method, or the like. In the stress application layer formation process, a stress application layer 4, which is made of a material whose thermal coefficient of expansion is smaller than that of the piezoelectric material and applies stress to the piezoelectric thin film 3, is formed on the piezoelectric thin film 3 by the sputtering method, or the like. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、圧電体薄膜の製造方法、共振装置およびそれを用いたUWB用フィルタに関するものである。   The present invention relates to a method for manufacturing a piezoelectric thin film, a resonance device, and a UWB filter using the same.

従来から、携帯電話機などの移動体通信機器の分野において、3GHz以上の高周波帯で利用する高周波フィルタに適用可能な共振装置として、シリコン基板からなる支持基板の一表面側に下部電極と圧電体薄膜と上部電極とからなる共振子を備え、圧電体薄膜の材料としてAlNを採用したBAW共振器が提案されている(例えば、特許文献1参照)。なお、上記特許文献1には、BAW共振器としてFBAR(Film Bulk Acoustic Resonator)が記載されているが、BAW共振器としては、近年、FBARの他にSMR(Solidly Mounted Resonator)が注目されている。なお、BAW共振器では、共振周波数が圧電体薄膜の膜厚に反比例し、圧電体薄膜の膜厚を薄くするほど共振周波数を高くすることができる。   Conventionally, as a resonance device applicable to a high frequency filter used in a high frequency band of 3 GHz or more in the field of mobile communication equipment such as a mobile phone, a lower electrode and a piezoelectric thin film on one surface side of a support substrate made of a silicon substrate There has been proposed a BAW resonator that includes a resonator composed of an upper electrode and an AlN as a material for a piezoelectric thin film (see, for example, Patent Document 1). In Patent Document 1, FBAR (Film Bulk Acoustic Resonator) is described as a BAW resonator, but recently, SMR (Solidly Mounted Resonator) has attracted attention as a BAW resonator in addition to FBAR. . In the BAW resonator, the resonance frequency is inversely proportional to the film thickness of the piezoelectric thin film, and the resonance frequency can be increased as the film thickness of the piezoelectric thin film is reduced.

ところで、上述の共振装置をUWB(Ultra Wide Band)用フィルタに応用する場合、圧電体薄膜の材料として、帯域幅が中心周波数に対して4〜5%しか広帯域化できないAlNに比べて中心周波数に対して10%程度の帯域幅を得ることが可能なPZT(チタン酸ジルコン酸鉛)を採用することが考えられる。   By the way, when the above-described resonance device is applied to a filter for UWB (Ultra Wide Band), as a material of the piezoelectric thin film, the center frequency is higher than that of AlN whose bandwidth is only 4 to 5% of the center frequency. On the other hand, it is conceivable to employ PZT (lead zirconate titanate) capable of obtaining a bandwidth of about 10%.

ここにおいて、圧電材料としてPZTを採用した共振装置としては、例えば、図5に示すように、シリコン基板からなる支持基板1’の一表面上にシリコン酸化膜からなる絶縁層7’が形成され、絶縁層7’上に下部電極5’が形成され、下部電極5’上にPZTからなる圧電体薄膜3’が形成され、圧電体薄膜3’上に上部電極6’が形成されてなる共振装置が提案されている(例えば、特許文献2参照)。ここで、図5の共振装置では、下部電極5’と圧電体薄膜3’と上部電極6’とで共振子10’を構成している。   Here, as a resonance device employing PZT as a piezoelectric material, for example, as shown in FIG. 5, an insulating layer 7 ′ made of a silicon oxide film is formed on one surface of a support substrate 1 ′ made of a silicon substrate, A resonance device in which a lower electrode 5 'is formed on an insulating layer 7', a piezoelectric thin film 3 'made of PZT is formed on the lower electrode 5', and an upper electrode 6 'is formed on the piezoelectric thin film 3'. Has been proposed (see, for example, Patent Document 2). Here, in the resonance device of FIG. 5, the lower electrode 5 ', the piezoelectric thin film 3', and the upper electrode 6 'constitute a resonator 10'.

なお、圧電材料からなる圧電体薄膜を支持基板の一表面側に製造する圧電体薄膜の製造方法としては、例えば、スパッタ法、CVD法、ゾルゲル法、エアロゾルデポジション法などが知られている(例えば、特許文献1〜3参照)。
特開2002−140075号公報 特開平10−126204号公報 特開2006−165102号公報
As a method for manufacturing a piezoelectric thin film for manufacturing a piezoelectric thin film made of a piezoelectric material on one surface side of a support substrate, for example, a sputtering method, a CVD method, a sol-gel method, an aerosol deposition method, and the like are known ( For example, see Patent Documents 1 to 3).
JP 2002-140075 A JP-A-10-126204 JP 2006-165102 A

上記特許文献1〜3に記載された圧電体薄膜の製造方法では、圧電体薄膜と当該圧電体薄膜の下地とが異種材料を用いるので、両者が格子整合性の良い材料同士であっても、高温での成膜時に両者の熱膨張率差に応じた熱応力が圧電体薄膜に発生し、当該熱応力に起因して圧電体薄膜の結晶性が低下し、電気機械結合係数が小さくなってしまう。   In the method for manufacturing a piezoelectric thin film described in Patent Documents 1 to 3, since the piezoelectric thin film and the base of the piezoelectric thin film use different materials, even if both are materials having good lattice matching, When the film is formed at high temperature, a thermal stress corresponding to the difference in thermal expansion coefficient between the two is generated in the piezoelectric thin film, the crystallinity of the piezoelectric thin film is lowered due to the thermal stress, and the electromechanical coupling coefficient is reduced. End up.

本発明は上記事由に鑑みて為されたものであり、その目的は、圧電体薄膜の結晶性の向上を図れる圧電体薄膜の製造方法、圧電体薄膜の結晶性の向上を図れる共振装置およびそれを用いたUWB用フィルタを提供することにある。   The present invention has been made in view of the above-mentioned reasons, and its object is to provide a method for manufacturing a piezoelectric thin film capable of improving the crystallinity of the piezoelectric thin film, a resonance device capable of improving the crystallinity of the piezoelectric thin film, and the same It is to provide a filter for UWB using the above.

請求項1の発明は、支持基板の一表面側に支持基板とは熱膨張率の異なる材料からなる圧電体薄膜を製造する圧電体薄膜の製造方法であって、支持基板の上記一表面側に支持基板の材料と圧電体薄膜の材料との中間の熱膨張率を有する材料からなるバッファ層を形成するバッファ層形成工程と、バッファ層上に圧電体薄膜を形成する圧電体薄膜形成工程と、圧電体薄膜上に圧電体薄膜の材料よりも熱膨張率の小さな材料からなり圧電体薄膜に応力を印加する応力印加層を形成する応力印加層形成工程とを備えることを特徴とする。   The invention according to claim 1 is a method for manufacturing a piezoelectric thin film, which is formed on a surface of a support substrate and made of a material having a coefficient of thermal expansion different from that of the support substrate. A buffer layer forming step of forming a buffer layer made of a material having a thermal expansion coefficient intermediate between the material of the support substrate and the piezoelectric thin film; and a piezoelectric thin film forming step of forming a piezoelectric thin film on the buffer layer; A stress applying layer forming step of forming a stress applying layer made of a material having a smaller thermal expansion coefficient than the material of the piezoelectric thin film on the piezoelectric thin film and applying a stress to the piezoelectric thin film.

この発明によれば、支持基板の一表面側に支持基板の材料と圧電体薄膜の材料との中間の熱膨張率を有する材料からなるバッファ層を形成するバッファ層形成工程と、バッファ層上に圧電体薄膜を形成する圧電体薄膜形成工程と、圧電体薄膜上に圧電体薄膜の材料よりも熱膨張率の小さな材料からなり圧電体薄膜に応力を印加する応力印加層を形成する応力印加層形成工程とを連続して行うことにより、圧電体薄膜中の残留応力を低減でき、圧電体薄膜の結晶性の向上を図れる。   According to the present invention, the buffer layer forming step of forming a buffer layer made of a material having a thermal expansion coefficient intermediate between the material of the support substrate and the material of the piezoelectric thin film on one surface side of the support substrate, and on the buffer layer Piezoelectric thin film forming step for forming a piezoelectric thin film, and a stress applying layer for forming a stress applying layer on the piezoelectric thin film made of a material having a smaller thermal expansion coefficient than that of the piezoelectric thin film, and applying stress to the piezoelectric thin film By continuously performing the forming process, the residual stress in the piezoelectric thin film can be reduced, and the crystallinity of the piezoelectric thin film can be improved.

請求項2の発明は、支持基板の一表面側に圧電体薄膜を製造する圧電体薄膜の製造方法であって、圧電体薄膜の材料よりも熱膨張率の小さな材料からなる支持基板の上記一表面上に圧電体薄膜を形成する圧電体薄膜形成工程と、圧電体薄膜上に圧電体薄膜の材料よりも熱膨張率の小さな材料からなり圧電体薄膜に応力を印加する応力印加層を形成する応力印加層形成工程とを備えることを特徴とする。   According to a second aspect of the present invention, there is provided a piezoelectric thin film manufacturing method for manufacturing a piezoelectric thin film on one surface side of a support substrate, wherein the one of the support substrates made of a material having a smaller thermal expansion coefficient than the material of the piezoelectric thin film. A piezoelectric thin film forming step for forming a piezoelectric thin film on the surface, and a stress applying layer for applying stress to the piezoelectric thin film made of a material having a smaller thermal expansion coefficient than the piezoelectric thin film material is formed on the piezoelectric thin film. A stress application layer forming step.

この発明によれば、圧電体薄膜の材料よりも熱膨張率の小さな材料からなる支持基板の一表面上に圧電体薄膜を形成する圧電体薄膜形成工程と、圧電体薄膜上に圧電体薄膜の材料よりも熱膨張率の小さな材料からなり圧電体薄膜に応力を印加する応力印加層を形成する応力印加層形成工程とを連続して行うことにより、圧電体薄膜中の残留応力を低減でき、圧電体薄膜の結晶性の向上を図れる。   According to the present invention, the piezoelectric thin film forming step of forming the piezoelectric thin film on one surface of the support substrate made of a material having a smaller thermal expansion coefficient than the material of the piezoelectric thin film, and the piezoelectric thin film on the piezoelectric thin film Residual stress in the piezoelectric thin film can be reduced by continuously performing a stress applying layer forming step of forming a stress applying layer that is made of a material having a smaller thermal expansion coefficient than the material and applies stress to the piezoelectric thin film, The crystallinity of the piezoelectric thin film can be improved.

請求項3の発明は、支持基板と、支持基板の一表面側に形成された下部電極と、下部電極における支持基板側とは反対側に形成された圧電体薄膜と、圧電体薄膜における下部電極側とは反対側に形成された上部電極とを備えた共振装置であって、圧電体薄膜は、請求項1記載の圧電体薄膜の製造方法により製造されてなることを特徴とする。   According to a third aspect of the present invention, there is provided a support substrate, a lower electrode formed on one surface side of the support substrate, a piezoelectric thin film formed on the opposite side of the lower electrode to the support substrate side, and a lower electrode in the piezoelectric thin film The piezoelectric thin film is manufactured by the method for manufacturing a piezoelectric thin film according to claim 1, wherein the piezoelectric thin film is provided with an upper electrode formed on the side opposite to the upper electrode.

この発明によれば、圧電体薄膜が、請求項1記載の圧電体薄膜の製造方法により製造されているので、共振装置における圧電体薄膜の結晶性の向上を図れる。   According to this invention, since the piezoelectric thin film is manufactured by the method for manufacturing a piezoelectric thin film according to the first aspect, the crystallinity of the piezoelectric thin film in the resonance device can be improved.

請求項4の発明は、請求項3記載の共振装置を用いたことを特徴とする。   According to a fourth aspect of the invention, the resonance device according to the third aspect is used.

この発明によれば、圧電体薄膜の結晶性の向上を図った共振装置を用いたUWB用フィルタを提供できる。   According to the present invention, it is possible to provide a UWB filter using a resonance device that improves the crystallinity of a piezoelectric thin film.

請求項1,2の発明では、圧電体薄膜の結晶性の向上を図れるという効果がある。   According to the first and second aspects of the invention, there is an effect that the crystallinity of the piezoelectric thin film can be improved.

請求項3の発明では、共振装置における圧電体薄膜の結晶性の向上を図れるという効果がある。   In the invention of claim 3, there is an effect that the crystallinity of the piezoelectric thin film in the resonance device can be improved.

請求項4の発明では、圧電体薄膜の結晶性の向上を図った共振装置を用いたUWB用フィルタを提供できるという効果がある。   According to the invention of claim 4, there is an effect that it is possible to provide a UWB filter using a resonance device in which the crystallinity of the piezoelectric thin film is improved.

(実施形態1)
本実施形態では、図1に示すように、支持基板1の一表面側に圧電体薄膜3を製造する圧電体薄膜3の製造方法について説明する。
(Embodiment 1)
In the present embodiment, as shown in FIG. 1, a method for manufacturing a piezoelectric thin film 3 for manufacturing a piezoelectric thin film 3 on one surface side of a support substrate 1 will be described.

本実施形態の圧電体薄膜3の製造方法では、圧電体薄膜3の材料(圧電材料)よりも熱膨張率の小さな材料(基板材料)からなる支持基板1の上記一表面側に上記圧電材料と上記基板材料との中間の熱膨張率を有する材料からなるバッファ層2をスパッタ法などにより形成するバッファ層形成工程を行い、その後、バッファ層2上に圧電体薄膜3をゾルゲル法などにより形成する圧電体薄膜形成工程を行い、続いて、圧電体薄膜3上に上記圧電材料よりも熱膨張率の小さな材料からなり圧電体薄膜3に応力を印加する応力印加層4をスパッタ法などにより形成する応力印加層形成工程を行う。   In the method for manufacturing the piezoelectric thin film 3 of the present embodiment, the piezoelectric material and the piezoelectric material are formed on the one surface side of the support substrate 1 made of a material (substrate material) having a smaller coefficient of thermal expansion than the material of the piezoelectric thin film 3 (piezoelectric material). A buffer layer forming step of forming the buffer layer 2 made of a material having a thermal expansion coefficient intermediate to that of the substrate material by a sputtering method or the like is performed, and then the piezoelectric thin film 3 is formed on the buffer layer 2 by a sol-gel method or the like. A piezoelectric thin film forming step is performed, and subsequently, a stress applying layer 4 made of a material having a smaller thermal expansion coefficient than the piezoelectric material is applied on the piezoelectric thin film 3 by a sputtering method or the like. A stress application layer forming step is performed.

ここにおいて、圧電体薄膜3の材料が例えばPZTである場合には、支持基板1の材料として例えばSi、SiOなど、バッファ層2の材料として例えばPT(PbTiO)、PLT((Pb,La)TiO)など、応力印加層4の材料として例えばSiOなどを採用すればよい。なお、圧電体薄膜3の材料はPZTに限らず、例えば、AlNや、BiTi12などのBi−Ti−O系材料や、BaBi−Ti−O系材料や、ZnO、LiNbOなどを採用してもよく、支持基板1の材料、バッファ層2の材料、応力印加層4の材料は圧電体薄膜3の材料の熱膨張率に応じて適宜選択すればよい。 Here, when the material of the piezoelectric thin film 3 is, for example, PZT, the material of the support substrate 1 is, for example, Si or SiO 2, and the material of the buffer layer 2 is, for example, PT (PbTiO 3 ), PLT ((Pb, La For example, SiO 2 may be used as the material of the stress applying layer 4 such as TiO 3 ). The material of the piezoelectric thin film 3 is not limited to PZT, and for example, AlN, Bi—Ti—O based materials such as Bi 3 Ti 4 O 12 , BaBi—Ti—O based materials, ZnO, LiNbO 3, etc. The material of the support substrate 1, the material of the buffer layer 2, and the material of the stress application layer 4 may be appropriately selected according to the coefficient of thermal expansion of the material of the piezoelectric thin film 3.

ところで、本実施形態の圧電体薄膜3の製造方法では、支持基板1の上記一表面側に、バッファ層2、圧電体薄膜3、応力印加層4をゾルゲル法やスパッタ法により連続して形成するようにしている。なお、バッファ層2、圧電体薄膜3、応力印加層4を連続して形成する方法はスパッタ法やゾルゲル法に限らず、例えば、CVD法でもよい。   By the way, in the manufacturing method of the piezoelectric thin film 3 of this embodiment, the buffer layer 2, the piezoelectric thin film 3, and the stress application layer 4 are continuously formed on the one surface side of the support substrate 1 by the sol-gel method or the sputtering method. I am doing so. The method of continuously forming the buffer layer 2, the piezoelectric thin film 3, and the stress applying layer 4 is not limited to the sputtering method or the sol-gel method, and may be a CVD method, for example.

以上説明した本実施形態の圧電体薄膜3の製造方法によれば、上述のバッファ層形成工程と、圧電体薄膜形成工程と、応力印加層形成工程とを連続して行うことにより、圧電体薄膜3中の残留応力を低減でき、圧電体薄膜3の結晶性の向上を図れ、電気機械結合係数の大きな圧電体薄膜3を得ることが可能となる。   According to the method of manufacturing the piezoelectric thin film 3 of the present embodiment described above, the piezoelectric thin film is obtained by continuously performing the above-described buffer layer forming step, the piezoelectric thin film forming step, and the stress applying layer forming step. 3 can be reduced, the crystallinity of the piezoelectric thin film 3 can be improved, and the piezoelectric thin film 3 having a large electromechanical coupling coefficient can be obtained.

上述の圧電体薄膜3の製造方法では、支持基板1の上記一表面上のバッファ層2上に圧電体薄膜3を形成しているが、圧電体薄膜3の圧電材料よりも熱膨張率の小さな材料からなる支持基板1の一表面上に圧電体薄膜3を形成する圧電体薄膜形成工程と、圧電体薄膜3上に上記圧電材料よりも熱膨張率の小さな材料からなり圧電体薄膜3に応力を印加する応力印加層4を形成する応力印加層形成工程とを連続して行うよう製造方法を採用してもよく、当該製造方法でも、圧電体薄膜3中の残留応力を低減でき、圧電体薄膜3の結晶性の向上を図れ、電気機械結合係数の大きな圧電体薄膜3を得ることが可能となる。ここにおいて、応力印加層4の材料として支持基板1の材料と略同じ熱膨張率の材料を採用することにより、圧電体薄膜3中の残留応力をより低減することができ、圧電体薄膜3の結晶性向上による電気機械結合係数の向上を図れる。   In the method for manufacturing the piezoelectric thin film 3 described above, the piezoelectric thin film 3 is formed on the buffer layer 2 on the one surface of the support substrate 1, but the coefficient of thermal expansion is smaller than that of the piezoelectric material of the piezoelectric thin film 3. A piezoelectric thin film forming step for forming the piezoelectric thin film 3 on one surface of the support substrate 1 made of a material, and a stress on the piezoelectric thin film 3 made of a material having a smaller thermal expansion coefficient than the piezoelectric material on the piezoelectric thin film 3. A manufacturing method may be adopted so that the stress applying layer forming step for forming the stress applying layer 4 for applying the stress is continuously performed. Also in this manufacturing method, the residual stress in the piezoelectric thin film 3 can be reduced, and the piezoelectric body. The crystallinity of the thin film 3 can be improved, and the piezoelectric thin film 3 having a large electromechanical coupling coefficient can be obtained. Here, by adopting a material having substantially the same coefficient of thermal expansion as the material of the support substrate 1 as the material of the stress application layer 4, the residual stress in the piezoelectric thin film 3 can be further reduced. The electromechanical coupling coefficient can be improved by improving the crystallinity.

(実施形態2)
本実施形態では、図2(e)に示すように、支持基板1と、支持基板1の一表面側に形成された共振子10とを備え、共振子10が、支持基板1の上記一表面側に形成された下部電極5と、下部電極5における支持基板1側とは反対側に形成された圧電体薄膜3と、圧電体薄膜3における下部電極5側とは反対側に形成された上部電極6とで構成されてなるBAW共振器からなる共振装置について説明する。
(Embodiment 2)
In this embodiment, as shown in FIG. 2 (e), the support substrate 1 and the resonator 10 formed on one surface side of the support substrate 1 are provided, and the resonator 10 is the one surface of the support substrate 1. The lower electrode 5 formed on the side, the piezoelectric thin film 3 formed on the opposite side of the lower electrode 5 from the support substrate 1 side, and the upper part formed on the opposite side of the piezoelectric thin film 3 from the lower electrode 5 side A resonance device composed of a BAW resonator composed of the electrode 6 will be described.

本実施形態の共振装置は、支持基板1に、下部電極5における圧電体薄膜3側とは反対側の表面を露出させる開孔部1aが形成されている。要するに、本実施形態の共振装置は、下部電極5と当該下部電極5直下の媒質との音響インピーダンス比を大きくすることにより支持基板1側への弾性波エネルギの伝搬を抑制するようにしたFBARを構成している。   In the resonance device of this embodiment, an opening 1 a is formed in the support substrate 1 to expose the surface of the lower electrode 5 opposite to the piezoelectric thin film 3 side. In short, the resonance apparatus of the present embodiment has an FBAR that suppresses propagation of elastic wave energy to the support substrate 1 side by increasing the acoustic impedance ratio between the lower electrode 5 and the medium immediately below the lower electrode 5. It is composed.

なお、本実施形態の共振装置では、共振子10の共振周波数を4GHzに設定してあり、圧電体薄膜3の厚みを300nmに設定してあるが、これらの数値は一例であって特に限定するものではない。例えば、共振周波数を3GHz〜5GHzの範囲で設計する場合には、圧電体薄膜32の厚みは200nm〜600nmの範囲で適宜設定すればよい。   In the resonance device of the present embodiment, the resonance frequency of the resonator 10 is set to 4 GHz, and the thickness of the piezoelectric thin film 3 is set to 300 nm. However, these numerical values are only examples and are particularly limited. It is not a thing. For example, when designing the resonance frequency in the range of 3 GHz to 5 GHz, the thickness of the piezoelectric thin film 32 may be appropriately set in the range of 200 nm to 600 nm.

上述の共振子10は、圧電体薄膜3の材料としてPZTを採用しており、下部電極5の材料としてPt、上部電極6の材料としてPtを採用しているが、下部電極5の材料はPtに限らず、例えばIrでもよく、上部電極6の材料はPtに限らず、例えばMo、Ir、Ruなどを採用してもよい。   The above-described resonator 10 employs PZT as the material of the piezoelectric thin film 3, and employs Pt as the material of the lower electrode 5 and Pt as the material of the upper electrode 6, but the material of the lower electrode 5 is Pt. For example, Ir may be used, and the material of the upper electrode 6 is not limited to Pt. For example, Mo, Ir, Ru, or the like may be employed.

ところで、本実施形態における共振子10は、下部電極5と圧電体薄膜3との間に、支持基板1の材料と圧電体薄膜3の材料(圧電材料)との中間の熱膨張率を有する材料からなるバッファ層2が形成され、圧電体薄膜3と上部電極6との間に、圧電体薄膜3の圧電材料よりも熱膨張率の小さな材料からなり圧電体薄膜3に応力を印加する応力印加層4が形成されている。   By the way, the resonator 10 in this embodiment is a material having a thermal expansion coefficient between the material of the support substrate 1 and the material of the piezoelectric thin film 3 (piezoelectric material) between the lower electrode 5 and the piezoelectric thin film 3. The buffer layer 2 is formed, and a stress is applied between the piezoelectric thin film 3 and the upper electrode 6, which is made of a material having a smaller thermal expansion coefficient than the piezoelectric material of the piezoelectric thin film 3 and applies stress to the piezoelectric thin film 3. Layer 4 is formed.

また、本実施形態の共振装置では、応力印加層4における圧電体薄膜3側とは反対側にSiO膜もしくはSi膜からなる絶縁層8が積層されており、絶縁層8に形成した開孔部9を通して上部電極6が応力印加層4と接している。ここにおいて、絶縁層8の開孔部9は、応力印加層4から離れるほど開口面積が徐々に大きくなるテーパ状であり、上部電極6は、ベース基板1の上記一表面側において、絶縁層8の表面と絶縁層8における開孔部9の内側面と応力印加層4の表面とに跨って形成されている。 In the resonance device of this embodiment, the insulating layer 8 made of a SiO 2 film or a Si 3 N 4 film is laminated on the opposite side of the stress applying layer 4 from the piezoelectric thin film 3 side, and is formed on the insulating layer 8. The upper electrode 6 is in contact with the stress applying layer 4 through the opened hole 9. Here, the opening 9 of the insulating layer 8 has a tapered shape in which the opening area gradually increases as the distance from the stress applying layer 4 increases, and the upper electrode 6 has the insulating layer 8 on the one surface side of the base substrate 1. And the inner surface of the opening 9 in the insulating layer 8 and the surface of the stress applying layer 4.

本実施形態では、圧電体薄膜3の材料としてPZTを採用しており、支持基板1の材料として例えばSi、SiOなど、バッファ層2の材料として例えばPT、PLTなど、応力印加層4の材料として例えばSiOなどを採用すればよい。なお、圧電体薄膜3の材料はPZTに限らず、例えば、AlNや、BiTi12などのBi−Ti−O系材料や、BaBi−Ti−O系材料や、ZnO、LiNbOなどを採用してもよく、支持基板1の材料、バッファ層2の材料、応力印加層4の材料は圧電体薄膜3の材料の熱膨張率に応じて適宜選択すればよい。 In this embodiment, PZT is adopted as the material of the piezoelectric thin film 3, the material of the stress applying layer 4 such as Si and SiO 2 as the material of the support substrate 1, and the material of the buffer layer 2 such as PT and PLT as the material of the buffer layer 2. For example, SiO 2 may be used. The material of the piezoelectric thin film 3 is not limited to PZT, and for example, AlN, Bi—Ti—O based materials such as Bi 3 Ti 4 O 12 , BaBi—Ti—O based materials, ZnO, LiNbO 3, etc. The material of the support substrate 1, the material of the buffer layer 2, and the material of the stress application layer 4 may be appropriately selected according to the coefficient of thermal expansion of the material of the piezoelectric thin film 3.

以下、本実施形態の共振装置の製造方法について図2(a)〜(e)を参照しながら説明する。   Hereinafter, a method for manufacturing the resonance device of the present embodiment will be described with reference to FIGS.

まず、支持基板1の一表面側(図2(a)における上面側)の全面に、下部電極5を例えばスパッタ法や蒸着法などにより形成する下部電極形成工程を行うことによって、図2(a)に示す構造を得る。   First, the lower electrode 5 is formed on the entire surface of one surface side of the support substrate 1 (the upper surface side in FIG. 2A) by forming a lower electrode 5 by, for example, sputtering or vapor deposition. ) Is obtained.

次に、支持基板1の上記一表面側(ここでは、下部電極5上)に上述のバッファ層2をスパッタ法により形成するバッファ層形成工程を行い、その後、バッファ層2上に圧電体薄膜3をゾルゲル法により形成する圧電体薄膜形成工程を行い、続いて、圧電体薄膜3上に上述の応力印加層4をスパッタ法により形成する応力印加層形成工程を行うことによって、図2(b)に示す構造を得る。要するに、本実施形態では、圧電体薄膜3の製造方法として、実施形態1にて説明した圧電体薄膜3の製造方法を利用しており、支持基板1の上記一表面側に、バッファ層2、圧電体薄膜3、応力印加層4をスパッタ法により連続して形成するようにしている。なお、バッファ層2、圧電体薄膜3、応力印加層4を連続して形成する方法はスパッタ法やゾルゲル法に限らず、例えば、CVD法でもよい。   Next, a buffer layer forming step is performed in which the buffer layer 2 is formed by sputtering on the one surface side of the support substrate 1 (here, on the lower electrode 5), and then the piezoelectric thin film 3 is formed on the buffer layer 2. 2 (b) by performing a piezoelectric thin film forming step for forming the above-mentioned stress applying layer 4 on the piezoelectric thin film 3 by a sputtering method. The structure shown in is obtained. In short, in this embodiment, the manufacturing method of the piezoelectric thin film 3 described in Embodiment 1 is used as a manufacturing method of the piezoelectric thin film 3, and the buffer layer 2, The piezoelectric thin film 3 and the stress applying layer 4 are continuously formed by sputtering. The method of continuously forming the buffer layer 2, the piezoelectric thin film 3, and the stress applying layer 4 is not limited to the sputtering method or the sol-gel method, and may be a CVD method, for example.

上述の応力印加層4を形成した後、フォトリソグラフィ技術およびエッチング技術を利用してバッファ層2と圧電体薄膜3と応力印加層4とからなる圧電変換部を所望の平面形状にパターニングする圧電変換部パターニング工程を行い、続いて、フォトリソグラフィ技術およびエッチング技術を利用して下部電極31を所望の平面形状にパターニングする下部電極パターニング工程を行うことによって、図2(c)に示す構造を得る。   After the above-described stress applying layer 4 is formed, piezoelectric conversion is performed by patterning the piezoelectric conversion portion including the buffer layer 2, the piezoelectric thin film 3, and the stress applying layer 4 into a desired planar shape by using a photolithography technique and an etching technique. A partial patterning process is performed, and subsequently, a lower electrode patterning process is performed in which the lower electrode 31 is patterned into a desired planar shape using a photolithography technique and an etching technique, thereby obtaining the structure shown in FIG.

その後、例えば、支持基板1の上記一表面側の全面にフォトレジストを回転塗布した後、当該フォトレジストをパターニングすることで絶縁層8の開孔部9の形成予定領域に対応する部分にレジスト層を残存させ、次に、支持基板1の上記一表面側の全面に絶縁層8をCVD法などにより成膜し、その後、リフトオフ法によりレジスト層を除去することで絶縁層8に開孔部9を形成してから、応力印加層4上に上部電極6を形成する上部電極形成工程を行うことによって、図2(d)に示す構造を得る。なお、上部電極形成工程では、例えば、支持基板1の上記一表面側の全面に、上部電極6をスパッタ法や蒸着法などによって形成してから、フォトリソグラフィ技術およびエッチング技術を利用して平面形状にパターニングすればよい。   Thereafter, for example, after a photoresist is spin-coated on the entire surface of the support substrate 1 on the one surface side, the photoresist is patterned to form a resist layer in a portion corresponding to a region where the opening 9 of the insulating layer 8 is to be formed. Next, the insulating layer 8 is formed on the entire surface of the one surface side of the support substrate 1 by the CVD method or the like, and then the resist layer is removed by the lift-off method to thereby form the opening 9 in the insulating layer 8. After forming, an upper electrode forming step of forming the upper electrode 6 on the stress applying layer 4 is performed to obtain the structure shown in FIG. In the upper electrode forming step, for example, the upper electrode 6 is formed on the entire surface of the one surface side of the support substrate 1 by a sputtering method, a vapor deposition method, or the like, and then the planar shape is formed using a photolithography technique and an etching technique. Patterning may be performed.

上述の上部電極形成工程の後、支持基板1の他表面側に上述の開孔部1a形成用にパターニングされたマスク層を形成するマスク層形成工程を行ってから、当該マスク層をマスクとして、支持基板1をドライエッチングあるいはウェットエッチングすることにより開孔部1aを形成する開孔部形成工程を行い、続いて、上記マスク層を除去するマスク層除去工程を行うことによって、図2(e)に示す構造の共振装置を得る。   After performing the above-mentioned upper electrode formation process, after performing the mask layer formation process which forms the mask layer patterned for the above-mentioned opening part 1a formation on the other surface side of support substrate 1, using the said mask layer as a mask, 2 (e) by performing an opening portion forming step for forming the opening portion 1a by dry etching or wet etching of the support substrate 1, and subsequently performing a mask layer removing step for removing the mask layer. A resonance device having the structure shown in FIG.

上述の共振装置の製造にあたっては、上述の支持基板1としてウェハを用いてウェハレベルで多数の共振装置を形成した後、ダイシング工程で個々の共振装置に分割すればよい。   In manufacturing the above-described resonance device, a plurality of resonance devices may be formed at the wafer level using a wafer as the above-described support substrate 1 and then divided into individual resonance devices in a dicing process.

以上説明した本実施形態の共振装置では、圧電体薄膜3が、上述のバッファ層形成工程と、圧電体薄膜形成工程と、応力印加層形成工程とを連続して行うことにより形成されているので、圧電体薄膜3中の残留応力を低減でき、圧電体薄膜3の結晶性の向上を図れる。   In the resonance device of the present embodiment described above, the piezoelectric thin film 3 is formed by continuously performing the above-described buffer layer forming step, the piezoelectric thin film forming step, and the stress applying layer forming step. The residual stress in the piezoelectric thin film 3 can be reduced, and the crystallinity of the piezoelectric thin film 3 can be improved.

ところで、上述の共振装置を、3GHz以上の高周波帯においてカットオフ特性が急峻で且つ帯域幅の広い高周波フィルタ、例えば、UWB用フィルタとして応用する場合には、図3に示すように、共振子10を同一の支持基板1の上記一表面側に複数個形成するようにし(図3には2個しか記載されていないが、例えば、8個形成するようにし)、これらの共振子10を図示しない配線によって図4に示すようなラダー型フィルタを構成するように接続すれば、UWB用フィルタの低コスト化および小型化を図れる。   By the way, when the above-described resonance device is applied as a high frequency filter having a sharp cutoff characteristic and a wide bandwidth in a high frequency band of 3 GHz or more, for example, a UWB filter, as shown in FIG. Are formed on the one surface side of the same support substrate 1 (only two are shown in FIG. 3 but, for example, eight are formed), and these resonators 10 are not shown. If the ladder-type filter as shown in FIG. 4 is connected by wiring, the cost and size of the UWB filter can be reduced.

また、上述の共振装置では、支持基板1上に開孔部1aを設けてあるが、支持基板1に開孔部1aを設ける代わりに、支持基板1の上記一表面上に、圧電体薄膜3で発生したバルク弾性波を反射させる音響ミラー(音響多層膜)を形成し、音響ミラー上に共振子10を形成するようにしてもよい。要するに、上述の共振装置は、FBARを構成していたのに対して、SMRを構成するようにしてもよい。なお、音響ミラーは、相対的に音響インピーダンスの低い材料(例えば、SiOなど)からなる低音響インピーダンス層と相対的に音響インピーダンスの高い材料(例えば、Wなど)からなる高音響インピーダンス層とを交互に積層して形成すればよく、低音響インピーダンス層および高音響インピーダンス層の膜厚は、圧電体薄膜3の共振周波数の弾性波(バルク弾性波)の波長の4分の1の値に設定すればよい。 Further, in the above-described resonance device, the opening portion 1 a is provided on the support substrate 1, but instead of providing the opening portion 1 a on the support substrate 1, the piezoelectric thin film 3 is formed on the one surface of the support substrate 1. It is also possible to form an acoustic mirror (acoustic multilayer film) that reflects the bulk acoustic wave generated in step 1, and form the resonator 10 on the acoustic mirror. In short, the above-described resonance device may constitute an SMR, whereas it constitutes an FBAR. The acoustic mirror includes a low acoustic impedance layer made of a material having a relatively low acoustic impedance (for example, SiO 2 ) and a high acoustic impedance layer made of a material having a relatively high acoustic impedance (for example, W). The film thickness of the low acoustic impedance layer and the high acoustic impedance layer may be formed alternately. The film thickness of the resonance frequency of the piezoelectric thin film 3 is set to a value that is a quarter of the wavelength of the elastic wave (bulk elastic wave). do it.

ところで、このような音響ミラーを備えた共振装置を製造する際、支持基板1の上記一表面上に、SiO層からなる低音響インピーダンス層とW層からなる高音響インピーダンス層とを交互に積層して音響ミラーを形成した後、支持基板1の上記一表面側に、バッファ層を設けることなく、ゾルゲル法によりPZT薄膜からなる圧電体薄膜3を成膜するような場合、PZT薄膜の前駆体膜を高濃度のOガス雰囲気中で焼結するアニール時に高音響インピーダンス層のW層が酸化して高音響インピーダンス層の体積が膨張したり音響インピーダンスが変化したりするのを防止するために、焼結温度の条件が制約されてしまい、焼結条件の最適化が難しい。 By the way, when manufacturing a resonance device including such an acoustic mirror, a low acoustic impedance layer composed of a SiO 2 layer and a high acoustic impedance layer composed of a W layer are alternately laminated on the one surface of the support substrate 1. After forming the acoustic mirror, when the piezoelectric thin film 3 made of the PZT thin film is formed by the sol-gel method without providing the buffer layer on the one surface side of the support substrate 1, the precursor of the PZT thin film is formed. In order to prevent the W layer of the high acoustic impedance layer from being oxidized and expanding the volume of the high acoustic impedance layer or changing the acoustic impedance during annealing in which the film is sintered in a high concentration O 2 gas atmosphere. The sintering temperature conditions are limited, and it is difficult to optimize the sintering conditions.

これに対して、音響ミラー上にPTやPLTからなるバッファ層2をゾルゲル法に比べて低O濃度の雰囲気中での成膜が可能なスパッタ法などにより成膜してから、圧電体薄膜3をゾルゲル法により成膜するようにすれば、圧電体薄膜3をゾルゲル法により成膜する前には、音響ミラーの表面側に下部電極5とバッファ層2との積層膜が形成されているから、ゾルゲル法を利用してPZT薄膜からなる圧電体薄膜3を成膜する際の焼結条件の最適化が容易になり、ゾルゲル法を利用して成膜する圧電体薄膜3の結晶性の向上を図れる。 On the other hand, after the buffer layer 2 made of PT or PLT is formed on the acoustic mirror by a sputtering method or the like that can be formed in an atmosphere having a lower O 2 concentration than the sol-gel method, the piezoelectric thin film is formed. If 3 is formed by the sol-gel method, a laminated film of the lower electrode 5 and the buffer layer 2 is formed on the surface side of the acoustic mirror before the piezoelectric thin film 3 is formed by the sol-gel method. Therefore, it becomes easy to optimize the sintering conditions when the piezoelectric thin film 3 made of the PZT thin film is formed using the sol-gel method, and the crystallinity of the piezoelectric thin film 3 formed using the sol-gel method is improved. Improvements can be made.

実施形態1における圧電体薄膜の製造方法の説明図である。6 is an explanatory diagram of a method for manufacturing a piezoelectric thin film in Embodiment 1. FIG. 実施形態2における共振装置の製造方法を説明するための主要工程断面図である。FIG. 10 is a main process sectional view for illustrating the method for manufacturing the resonance device in the second embodiment. 同上の共振装置を応用したUWB用フィルタの概略断面図である。It is a schematic sectional drawing of the filter for UWB which applied the resonance apparatus same as the above. 同上の共振装置を応用したUWB用フィルタの回路図である。It is a circuit diagram of the filter for UWB which applied the resonance apparatus same as the above. 従来例を示す共振装置の概略断面図である。It is a schematic sectional drawing of the resonance apparatus which shows a prior art example.

符号の説明Explanation of symbols

1 支持基板
2 バッファ層
3 圧電体薄膜
4 応力印加層
5 下部電極
6 上部電極
DESCRIPTION OF SYMBOLS 1 Support substrate 2 Buffer layer 3 Piezoelectric thin film 4 Stress application layer 5 Lower electrode 6 Upper electrode

Claims (4)

支持基板の一表面側に支持基板とは熱膨張率の異なる材料からなる圧電体薄膜を製造する圧電体薄膜の製造方法であって、支持基板の上記一表面側に支持基板の材料と圧電体薄膜の材料との中間の熱膨張率を有する材料からなるバッファ層を形成するバッファ層形成工程と、バッファ層上に圧電体薄膜を形成する圧電体薄膜形成工程と、圧電体薄膜上に圧電体薄膜の材料よりも熱膨張率の小さな材料からなり圧電体薄膜に応力を印加する応力印加層を形成する応力印加層形成工程とを備えることを特徴とする圧電体薄膜の製造方法。   A piezoelectric thin film manufacturing method for manufacturing a piezoelectric thin film made of a material having a coefficient of thermal expansion different from that of a support substrate on one surface side of the support substrate, wherein the material of the support substrate and the piezoelectric body are formed on the one surface side of the support substrate. A buffer layer forming step for forming a buffer layer made of a material having a thermal expansion coefficient intermediate to that of the thin film material, a piezoelectric thin film forming step for forming a piezoelectric thin film on the buffer layer, and a piezoelectric body on the piezoelectric thin film A method of manufacturing a piezoelectric thin film, comprising: a stress applying layer forming step of forming a stress applying layer made of a material having a smaller thermal expansion coefficient than that of the thin film material and applying stress to the piezoelectric thin film. 支持基板の一表面側に圧電体薄膜を製造する圧電体薄膜の製造方法であって、圧電体薄膜の材料よりも熱膨張率の小さな材料からなる支持基板の上記一表面上に圧電体薄膜を形成する圧電体薄膜形成工程と、圧電体薄膜上に圧電体薄膜の材料よりも熱膨張率の小さな材料からなり圧電体薄膜に応力を印加する応力印加層を形成する応力印加層形成工程とを備えることを特徴とする圧電体薄膜の製造方法。   A piezoelectric thin film manufacturing method for manufacturing a piezoelectric thin film on one surface side of a support substrate, wherein the piezoelectric thin film is formed on the surface of the support substrate made of a material having a smaller thermal expansion coefficient than the material of the piezoelectric thin film. A piezoelectric thin film forming step to be formed; and a stress applying layer forming step of forming a stress applying layer made of a material having a smaller thermal expansion coefficient than that of the piezoelectric thin film on the piezoelectric thin film and applying a stress to the piezoelectric thin film. A method of manufacturing a piezoelectric thin film, comprising: 支持基板と、支持基板の一表面側に形成された下部電極と、下部電極における支持基板側とは反対側に形成された圧電体薄膜と、圧電体薄膜における下部電極側とは反対側に形成された上部電極とを備えた共振装置であって、圧電体薄膜は、請求項1記載の圧電体薄膜の製造方法により製造されてなることを特徴とする共振装置。   A support substrate, a lower electrode formed on one surface side of the support substrate, a piezoelectric thin film formed on the opposite side of the lower electrode to the support substrate side, and a piezoelectric thin film formed on the opposite side of the lower electrode side A resonance apparatus comprising: the upper electrode, wherein the piezoelectric thin film is manufactured by the method for manufacturing a piezoelectric thin film according to claim 1. 請求項3記載の共振装置を用いたことを特徴とするUWB用フィルタ。   A UWB filter using the resonance device according to claim 3.
JP2007044556A 2007-02-23 2007-02-23 Manufacturing method of piezoelectric thin film, resonator, and filter for uwb using the same Withdrawn JP2008211385A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013183428A1 (en) 2012-06-04 2013-12-12 Tdk Corporation Dielectric device
US8981627B2 (en) 2012-06-04 2015-03-17 Tdk Corporation Piezoelectric device with electrode films and electroconductive oxide film
US8994251B2 (en) 2012-08-03 2015-03-31 Tdk Corporation Piezoelectric device having first and second non-metal electroconductive intermediate films
US9136820B2 (en) 2012-07-31 2015-09-15 Tdk Corporation Piezoelectric device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013183428A1 (en) 2012-06-04 2013-12-12 Tdk Corporation Dielectric device
US8981627B2 (en) 2012-06-04 2015-03-17 Tdk Corporation Piezoelectric device with electrode films and electroconductive oxide film
US10964879B2 (en) 2012-06-04 2021-03-30 Tdk Corporation Method of manufacturing a dielectric device
US9136820B2 (en) 2012-07-31 2015-09-15 Tdk Corporation Piezoelectric device
US8994251B2 (en) 2012-08-03 2015-03-31 Tdk Corporation Piezoelectric device having first and second non-metal electroconductive intermediate films

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