JP2008209840A - Plasma display apparatus and driving method of plasma display panel - Google Patents

Abstract

An afterimage phenomenon in a plasma display panel is reduced and the display luminance of each discharge cell is made uniform.
A sustain pulse rises or falls by resonating a plasma display panel having a plurality of discharge cells each having a display electrode pair composed of a scan electrode and a sustain electrode, and an interelectrode capacitance of the display electrode pair and an inductor. Sustain pulse generation having a power recovery circuit for performing a sustain pulse generation circuit that generates a sustain pulse and applies it to each of the display electrode pairs, and a lighting rate detection circuit that detects the lighting rate of the discharge cell for each subfield The circuit provides an overlapping period in which the time for performing the sustain pulse rise applied to one of the display electrode pairs and the time for performing the sustain pulse fall applied to the other display electrode pair are overlapped, and the lighting rate detection circuit The overlap period is changed in accordance with the lighting rate detected in step (b).
[Selection] Figure 4

Description

  The present invention relates to a plasma display device and a plasma display panel driving method used for a wall-mounted television or a large monitor.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of display electrode pairs each consisting of a pair of scan electrodes and sustain electrodes are formed in parallel with each other on the front glass substrate, and a dielectric layer and a protective layer are formed so as to cover the display electrode pairs. Yes. The back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of barrier ribs in parallel with the data electrodes formed on the back glass substrate. A phosphor layer is formed on the side walls of the barrier ribs. Then, the front plate and the back plate are arranged opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas containing, for example, 5% xenon in a partial pressure ratio is sealed in the internal discharge space. Has been. Here, a discharge cell is formed at a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of red (R), green (G) and blue (B) colors are excited and emitted by the ultraviolet rays, thereby performing color display. It is carried out.

  As a method of driving the panel, a subfield method, that is, a method of performing gradation display by combining subfields to emit light after dividing one field period into a plurality of subfields is generally used.

  Each subfield has an initialization period, an address period, and a sustain period. In the initializing period, initializing discharge is generated, wall charges necessary for the subsequent address operation are formed on each electrode, and priming particles for stably generating the address discharge (priming agent for discharge = excited particles) ). In the address period, an address pulse voltage is selectively applied to the discharge cells to be displayed to generate an address discharge to form wall charges (hereinafter, this operation is also referred to as “address”). In the sustain period, a sustain pulse voltage is alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode, and a sustain discharge is generated in the discharge cell that has caused the address discharge, and the phosphor layer of the corresponding discharge cell emits light. To display an image.

  On the other hand, in recent years, it has been desired to further improve the image display quality in the plasma display device as the panel becomes higher in definition and larger in screen size. Since increasing the brightness of the panel is one of effective means for improving the image display quality, various efforts have been made to improve the light emission efficiency of the panel and improve the brightness. For example, studies are being made to significantly increase the luminous efficiency by increasing the xenon partial pressure. However, when the xenon partial pressure is increased, the variation in the timing at which discharge occurs increases, and the emission intensity varies from discharge cell to discharge cell, resulting in non-uniform display brightness. In order to improve this non-uniform brightness, a driving method is disclosed in which, for example, a sustain pulse with a steep rise is inserted at a rate of once every several times so that the timing of the sustain discharge is aligned and the display brightness is made uniform. (For example, refer to Patent Document 1).

In addition, when the xenon partial pressure is increased, when a high-luminance image is displayed after a still image or the like is displayed for a long time, the still image may be recognized as an afterimage, which may impair image display quality. . In order to reduce such an afterimage phenomenon, a method of suppressing a decrease in image display quality by moving a display position of an image in which an afterimage is likely to occur is disclosed (for example, see Patent Document 2).
JP-A-2005-338120 JP-A-8-248934

  However, according to the method described in Patent Document 2, the degree of afterimage recognition is reduced to some extent, but the afterimage phenomenon itself is not reduced. In addition, since image processing such as moving the display position of the image is used in combination, the image may not be displayed faithfully.

  The present invention has been made in view of these problems, and it is an object of the present invention to provide a plasma display device and a panel driving method capable of reducing the afterimage phenomenon in the panel and uniformizing the display luminance of each discharge cell. To do.

  The plasma display device according to the present invention causes a sustain pulse to rise or fall by resonating a panel having a plurality of discharge cells each having a display electrode pair composed of a scan electrode and a sustain electrode, an interelectrode capacitance of the display electrode pair, and an inductor. A sustaining pulse generation circuit that applies a sustaining pulse to each of the display electrode pairs by a power recovery circuit that performs a lowering; and a lighting rate detection circuit that detects the lighting rate of the discharge cells. In addition to providing an overlapping period in which the time for the sustain pulse applied to one electrode to rise and the time for the sustain pulse applied to the other electrode of the display electrode pair to overlap, the lighting rate detection circuit detects The overlap period is changed according to the lighting rate.

  Thereby, the afterimage phenomenon in the panel can be reduced, and the display luminance of each discharge cell can be made uniform.

  In this plasma display device, the lighting rate detection circuit compares the detected lighting rate with a predetermined threshold value, and the sustain pulse generation circuit has a predetermined lighting rate threshold in the lighting rate detection circuit. When it is determined to be greater than or equal to the value, the overlap period is changed to be longer than when the lighting rate is determined to be smaller than a predetermined threshold value. As a result, it is possible to accurately reduce the afterimage phenomenon that appears differently depending on the lighting rate, and to make the display luminance of each discharge cell uniform.

  Further, in this plasma display device, the sustain pulse generation circuit may be changed so as to lengthen the overlap period by lengthening the drive time of the power recovery circuit at the rise of the sustain pulse.

  Further, the panel driving method of the present invention provides a panel having a plurality of discharge cells each having a display electrode pair made up of a scan electrode and a sustain electrode, by causing the interelectrode capacitance of the display electrode pair and the inductor to resonate and causing the sustain pulse to rise. Or a power recovery circuit that performs falling and a clamp circuit that clamps the sustain pulse voltage to a predetermined voltage, and a plurality of initialization periods, write periods, and sustain periods provided in one field period. A method of driving a panel using a sustain pulse generating circuit that generates a sustain pulse of the number corresponding to the luminance weight in a sustain period and applies the sustain pulse to each of the display electrode pairs, and the sustain pulse is applied to one of the display electrode pairs. When there is an overlap period in which the time for the rise of the pulse overlaps the time for the fall of the sustain pulse applied to the other of the display electrode pair Moni, and changes the overlap period depending on the lighting rate of discharge cells.

  Thereby, the afterimage phenomenon in the panel can be reduced, and the display luminance of each discharge cell can be made uniform.

  Further, the panel driving method of the present invention is characterized in that when the lighting rate is equal to or higher than a predetermined threshold value, the overlapping period is made longer than when the lighting rate is not. As a result, it is possible to accurately reduce the afterimage phenomenon that appears differently depending on the lighting rate, and to make the display luminance of each discharge cell uniform.

  In the panel driving method of the present invention, the overlap period may be lengthened by lengthening the driving time of the power recovery circuit at the rising edge of the sustain pulse.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to reduce the afterimage phenomenon in a panel and to provide the plasma display apparatus and the panel drive method which can make the display luminance of each discharge cell uniform.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is an exploded perspective view showing the structure of panel 10 according to an embodiment of the present invention. On the front plate 21 made of glass, a plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustain electrode 23 are formed. A dielectric layer 25 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 26 is formed on the dielectric layer 25.

  The protective layer 26 has been used as a panel material in order to lower the discharge start voltage in the discharge cell, and has a large secondary electron emission coefficient and durability when neon (Ne) and xenon (Xe) gas is sealed. It is formed from a material mainly composed of MgO having excellent properties.

  A plurality of data electrodes 32 are formed on the back plate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits light of each color of red (R), green (G), and blue (B) is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front plate 21 and the back plate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect with each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. In the discharge space, for example, a mixed gas of neon and xenon is enclosed as a discharge gas. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall. Further, in the present embodiment, a discharge gas having a xenon partial pressure of about 10% is used for improving the luminance, but the mixing ratio of the discharge gas is not limited to this value, and other mixing ratios are used. There may be.

  FIG. 2 is an electrode array diagram of panel 10 according to the embodiment of the present invention. In panel 10, n scanning electrodes SC1 to SCn (scanning electrode 22 in FIG. 1) and n sustaining electrodes SU1 to SUn (sustaining electrode 23 in FIG. 1) long in the row direction are arranged and long in the column direction. M data electrodes D1 to Dm (data electrode 32 in FIG. 1) are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed. As shown in FIGS. 1 and 2, scan electrode SCi and sustain electrode SUi are formed in parallel with each other, and therefore, between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn. There is a large interelectrode capacitance Cp.

  Next, a driving voltage waveform for driving the panel 10 and an outline of the operation will be described. The plasma display device according to the present embodiment performs gradation display by subfield method, that is, by dividing one field period into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield. Each subfield has an initialization period, an address period, and a sustain period.

  In each subfield, initializing discharge is generated in the initializing period, and wall charges necessary for subsequent address discharge are formed on each electrode. In addition, it has a function of generating priming particles (priming for discharge = excited particles) for reducing discharge delay and generating address discharge stably. The initializing operation at this time includes an initializing operation for generating an initializing discharge in all discharge cells (hereinafter abbreviated as “all-cell initializing operation”), and a discharge in which a sustain discharge is performed in the immediately preceding subfield. There is an initializing operation (hereinafter abbreviated as “selective initializing operation”) in which initializing discharge is selectively generated only in the cell.

  In the address period, an address discharge is selectively generated in the discharge cells to emit light in the subsequent sustain period to form wall charges. In the sustain period, a number of sustain pulses proportional to the luminance weight are alternately applied to the display electrode pair 24 to generate a sustain discharge in the discharge cells that have generated the address discharge, thereby causing light emission. The proportionality constant at this time is called “luminance magnification”.

  FIG. 3 is a diagram showing a subfield configuration in one embodiment of the present invention. FIG. 3 shows an outline of a drive waveform in one field period in the subfield method, and details of the drive voltage waveform will be described later.

  In this embodiment, one field is composed of 10 subfields (first SF, second SF,..., 10th SF), and each subfield is, for example, (1, 2, 3, 6, 11, 18). , 30, 44, 60, 80). Then, the all-cell initialization operation is performed in the initialization period of the first SF, and the selective initialization operation is performed in the initialization period of the second SF to the tenth SF. As a result, the light emission not related to the image display is only the light emission associated with the discharge of the all-cell initialization operation in the first SF, and the luminance of the black display area (hereinafter abbreviated as “black luminance”) is the all-cell initialization operation. Only the weak light emission at, makes it possible to display an image with high contrast. In the sustain period of each subfield, the number of sustain pulses obtained by multiplying the luminance weight of each subfield by a predetermined luminance magnification is applied to each display electrode pair 24.

  However, in the present embodiment, the number of subfields and the luminance weight of each subfield are not limited to the above values, and the subfield configuration may be switched based on an image signal or the like.

  In the present embodiment, the rise of the sustain pulse waveform is controlled according to the lighting rate for each subfield measured by the lighting rate detection circuit described later. Thereby, the afterimage phenomenon in the panel is reduced, and the display luminance of each discharge cell is made uniform. Hereinafter, the outline of the drive voltage waveform and the configuration of the drive circuit will be described first, and then the difference in the sustain pulse waveform controlled according to the lighting rate will be described.

  FIG. 4 is a drive voltage waveform diagram applied to each electrode of panel 10 in one embodiment of the present invention. FIG. 4 shows driving voltage waveforms of two subfields, that is, a subfield that performs an all-cell initializing operation (hereinafter referred to as “all-cell initializing subfield”) and a subfield that performs a selective initializing operation ( Hereinafter, it is referred to as “selective initialization subfield”), but the driving voltage waveforms in the other subfields are substantially the same.

  First, the first SF, which is an all-cell initialization subfield, will be described.

  In the first half of the initializing period of the first SF, 0 (V) is applied to the data electrodes D1 to Dm and the sustain electrodes SU1 to SUn, respectively, and the discharge start voltage with respect to the sustain electrodes SU1 to SUn is applied to the scan electrodes SC1 to SCn. A ramp waveform voltage (hereinafter referred to as “up-ramp waveform voltage”) that gradually rises from the voltage Vi1 below toward the voltage Vi2 that exceeds the discharge start voltage is applied.

  While the rising ramp waveform voltage rises, weak initializing discharges are continuously generated between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm. Negative wall voltage is accumulated on scan electrodes SC1 to SCn, and positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn. Here, the wall voltage above the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the latter half of the initialization period, positive voltage Ve1 is applied to sustain electrodes SU1 to SUn, 0 (V) is applied to data electrodes D1 to Dm, and scan electrodes SC1 to SCn have sustain electrodes SU1 to SUn. Then, a ramp waveform voltage (hereinafter referred to as “down-ramp waveform voltage”) that gently falls from a voltage Vi3 that is equal to or lower than the discharge start voltage to a voltage Vi4 that exceeds the discharge start voltage is applied. During this time, weak initializing discharges are continuously generated between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm. Then, the negative wall voltage above scan electrodes SC1 to SCn and the positive wall voltage above sustain electrodes SU1 to SUn are weakened, and the positive wall voltage above data electrodes D1 to Dm is adjusted to a value suitable for the write operation. The Thus, the all-cell initializing operation for performing the initializing discharge on all the discharge cells is completed.

  Note that, as shown in the initialization period of the second SF in FIG. 4, a drive voltage waveform in which the first half of the initialization period is omitted may be applied to each electrode. That is, a voltage Ve1 is applied to sustain electrodes SU1 to SUn, 0 (V) is applied to data electrodes D1 to Dm, and a ramp voltage waveform that gradually decreases from voltage Vi3 ′ to voltage Vi4 to scan electrodes SC1 to SCn. Apply. As a result, a weak initializing discharge is generated in the discharge cell in which the sustain discharge has occurred in the sustain period of the previous subfield, and the wall voltage above scan electrode SCi and sustain electrode SUi is weakened. Further, in a discharge cell in which a sufficient positive wall voltage is accumulated on the data electrode Dk (k = 1 to m) by the last sustain discharge, an excessive portion of the wall voltage is discharged, and the wall voltage suitable for the address operation is obtained. Adjusted to On the other hand, the discharge cells that did not cause the sustain discharge in the previous subfield are not discharged, and the wall charges at the end of the initialization period of the previous subfield are maintained as they are. Thus, the initializing operation in which the first half is omitted is a selective initializing operation in which initializing discharge is performed on the discharge cells in which the sustaining operation has been performed in the sustain period of the immediately preceding subfield.

  In the subsequent address period, voltage Ve2 is applied to sustain electrodes SU1 to SUn, and voltage Vc is applied to scan electrodes SC1 to SCn.

  Then, a negative scan pulse voltage Va is applied to the scan electrode SC1 in the first row, and the data electrode Dk (k = 1 to m) of the discharge cell to be emitted in the first row among the data electrodes D1 to Dm is positive. The write pulse voltage Vd is applied. At this time, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is the difference between the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1 due to the difference in externally applied voltage (Vd−Va). It becomes the sum and exceeds the discharge start voltage. As a result, a discharge is generated between data electrode Dk and scan electrode SC1. In addition, since voltage Ve2 is applied to sustain electrodes SU1 to SUn, the voltage difference between sustain electrode SU1 and scan electrode SC1 is the difference between the externally applied voltages (Ve2-Va) and on sustain electrode SU1. The difference between the wall voltage and the wall voltage on the scan electrode SC1 is added. At this time, by setting the voltage Ve2 to a voltage value that is slightly lower than the discharge start voltage, the sustain electrode SU1 and the scan electrode SC1 are not easily discharged but are likely to be discharged. Can do. Thereby, the discharge generated between data electrode Dk and scan electrode SC1 can be triggered to generate a discharge between sustain electrode SU1 and scan electrode SC1 in the region intersecting with data electrode Dk. Thus, an address discharge occurs in the discharge cell to emit light, a positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also accumulated on data electrode Dk. Accumulated.

  In this manner, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrodes D1 to Dm to which the address pulse voltage Vd is not applied and the scan electrode SC1 does not exceed the discharge start voltage, so that address discharge does not occur. The above address operation is performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, first, positive sustain pulse voltage Vs is applied to scan electrodes SC1 to SCn, and a ground potential that is a base potential, that is, 0 (V) is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. Exceeding the discharge start voltage.

  Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.

  Subsequently, 0 (V) as a base potential is applied to scan electrodes SC1 to SCn, and sustain pulse voltage Vs is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage difference between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage, so that the sustain discharge occurs again between the sustain electrode SUi and the scan electrode SCi. A negative wall voltage is accumulated on SUi, and a positive wall voltage is accumulated on scan electrode SCi. Thereafter, similarly, the sustain electrodes of the number obtained by multiplying the luminance weight by the luminance magnification are alternately applied to the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn, and a potential difference is given between the electrodes of the display electrode pair 24, thereby writing. The sustain discharge is continuously performed in the discharge cell that has caused the address discharge in the period.

  Then, at the end of the sustain period, voltage Ve1 for weakening the discharge is applied to sustain electrodes SU1 to SUn after a predetermined time since voltage Vs for generating the last sustain discharge is applied to scan electrodes SC1 to SCn. Therefore, a so-called narrow pulse voltage difference is applied between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and the positive wall voltage on data electrode Dk is left and scan electrode SCi and sustain electrode SUi are left. Some or all of the wall voltage above has been erased.

  Subsequent subfield operations are substantially the same as those described above except for the number of sustain pulses in the sustain period, and thus description thereof is omitted. The above is the outline of the drive voltage waveform applied to each electrode of panel 10 in the present embodiment.

  Next, the configuration of the plasma display device in the present embodiment will be described. FIG. 5 is a circuit block diagram of the plasma display device in one embodiment of the present invention. The plasma display apparatus 1 is necessary for the panel 10, the image signal processing circuit 41, the data electrode drive circuit 42, the scan electrode drive circuit 43, the sustain electrode drive circuit 44, the timing generation circuit 45, the lighting rate detection circuit 48, and each circuit block. A power supply circuit (not shown) for supplying power is provided.

  The image signal processing circuit 41 converts the input image signal sig into image data indicating light emission / non-light emission for each subfield. The data electrode drive circuit 42 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm.

  The lighting rate detection circuit 48 detects the ratio of the number of lighting discharge cells to the total number of discharge cells, that is, the lighting rate of the discharge cells for each subfield, based on the image data for each subfield. Then, the detected lighting rate is compared with a predetermined lighting rate threshold value, and a signal representing the determination result is output to the timing generation circuit 45.

  In this embodiment, the lighting rate threshold value is set to 50%, but is not limited to this value at all, and is optimal based on the characteristics of the panel, the specifications of the plasma display device, and the like. It is desirable to set it to a value.

  The timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block on the basis of the horizontal synchronization signal H, the vertical synchronization signal V, and the output from the lighting rate detection circuit 48, and supplies them to each circuit block. To do. As described above, in this embodiment, the rise of the sustain pulse waveform is controlled based on the lighting rate, and a timing signal corresponding to the rise is output to scan electrode drive circuit 43 and sustain electrode drive circuit 44. To do. Thereby, control for reducing the afterimage phenomenon in the panel is performed.

  Scan electrode drive circuit 43 generates an initialization waveform voltage (not shown) for generating an initialization waveform voltage to be applied to scan electrodes SC1 to SCn in the initialization period, and applies to scan electrodes SC1 to SCn in the sustain period. Sustain pulse generation circuit 50 for generating sustain pulse voltage, and a scan pulse generation circuit (not shown) for generating scan pulse voltages to be applied to scan electrodes SC1 to SCn in the address period, are based on the timing signal. The scan electrodes SC1 to SCn are respectively driven. Sustain electrode drive circuit 44 includes sustain pulse generation circuit 60 and a circuit for generating voltages Ve1 and Ve2, and drives sustain electrodes SU1 to SUn based on a timing signal.

  Next, details and operation of sustain pulse generating circuit 50 and sustain pulse generating circuit 60 will be described. FIG. 6 is a circuit diagram of sustain pulse generation circuit 50 and sustain pulse generation circuit 60 in one embodiment of the present invention. In FIG. 6, the interelectrode capacitance of the panel 10 is shown as Cp, and the circuit for generating the scan pulse and the initialization voltage waveform is omitted.

  The sustain pulse generation circuit 50 includes a power recovery circuit 51 and a clamp circuit 52. The power recovery circuit 51 and the clamp circuit 52 include a scan pulse generation circuit (not shown because it is in a short-circuit state during the sustain period). And is connected to scan electrodes SC1 to SCn which are one end of the interelectrode capacitance Cp of the panel 10.

  The power recovery circuit 51 includes a power recovery capacitor C10, a switching element Q11, a switching element Q12, a backflow prevention diode D11, a backflow prevention diode D12, and a resonance inductor L10. Then, the interelectrode capacitance Cp and the inductor L10 are LC-resonated to cause the sustain pulse to rise and fall. Thus, since the power recovery circuit 51 drives the scan electrodes SC1 to SCn by LC resonance without being supplied with power from the power source, the power consumption is ideally zero. The power recovery capacitor C10 has a sufficiently large capacity compared to the interelectrode capacity Cp, and is charged to about Vs / 2, which is half of the voltage value Vs, so as to serve as a power source for the power recovery circuit 51.

  The clamp circuit 52 includes a switching element Q13 for clamping scan electrodes SC1 to SCn to voltage Vs, and a switching element Q14 for clamping scan electrodes SC1 to SCn to 0 (V). Then, scan electrodes SC1 to SCn are connected to power supply VS via switching element Q13 and clamped to voltage Vs, and scan electrodes SC1 to SCn are grounded and clamped to 0 (V) via switching element Q14. Therefore, the impedance at the time of voltage application by the voltage clamp circuit 52 is small, and a large discharge current due to strong sustain discharge can be flowed stably.

  Sustain pulse generation circuit 50 switches power recovery circuit 51 and voltage by switching on and off of switching element Q11, switching element Q12, switching element Q13, and switching element Q14 according to the timing signal output from timing generation circuit 45. The clamp circuit 52 is operated to generate a sustain pulse waveform. Details of this will be described later. Note that these switching elements can be configured using generally known elements such as MOSFETs and IGBTs.

  The sustain pulse generation circuit 60 includes a power recovery circuit 61 having a power recovery capacitor C20, a switching element Q21, a switching element Q22, a backflow prevention diode D21, a backflow prevention diode D22, and a resonance inductor L20. A clamp circuit 62 having a switching element Q23 for clamping the electrodes SU1 to SUn to the voltage Vs and a switching element Q24 for clamping the sustain electrodes SU1 to SUn to the ground potential, and one end of the interelectrode capacitance Cp of the panel 10 Are connected to sustain electrodes SU1 to SUn. The operation of sustain pulse generating circuit 60 is the same as that of sustain pulse generating circuit 50, and therefore description thereof is omitted.

  Further, FIG. 6 shows a power source VE1 that generates the voltage Ve1, a switching element Q26 for applying the voltage Ve1 to the sustain electrodes SU1 to SUn, a switching element Q27, a power source ΔVE that generates the voltage ΔVe, and a backflow prevention diode D30. The switching element Q28 and the switching element Q29 for accumulating the voltage ΔVe on the capacitor C30 and the voltage Ve1 to obtain the voltage Ve2 are shown. For example, at the timing of applying the voltage Ve1 shown in FIG. 4, the switching element Q26 and the switching element Q27 are turned on, and the positive voltage Ve1 is applied to the sustain electrodes SU1 to SUn via the diode D30, the switching element Q26, and the switching element Q27. Apply. At this time, the switching element Q28 is turned on and charged so that the voltage of the capacitor C30 becomes the voltage Ve1. Further, at the timing of applying the voltage Ve2 shown in FIG. 4, the switching element Q26 is cut off and the switching element Q29 is turned on while the switching element Q26 and the switching element Q27 are kept conductive, and the voltage ΔVe is applied to the voltage of the capacitor C30. The voltage Ve1 + ΔVe, that is, the voltage Ve2 is applied to the sustain electrodes SU1 to SUn. At this time, the current from the capacitor C30 to the power source VE1 is cut off by the function of the backflow preventing diode D30.

  Note that the circuit for applying the voltage Ve1 and the voltage Ve2 is not limited to the circuit shown in FIG. 6. For example, the power source that generates the voltage Ve1 and the power source that generates the voltage Ve2 and the respective voltages are maintained electrodes. A plurality of switching elements for applying to SU1 to SUn may be used to apply each voltage to sustain electrodes SU1 to SUn at a necessary timing.

  The period of LC resonance between the inductor L10 of the power recovery circuit 51 and the interelectrode capacitance Cp of the panel 10 and the period of LC resonance between the inductor L20 of the power recovery circuit 61 and the interelectrode capacitance Cp (hereinafter referred to as “resonance period”). Can be obtained by the calculation formula “2π√ (LCp)”, where L is the inductance of the inductor L10 and the inductor L20. In the present embodiment, the inductor L10 and the inductor L20 are set so that the resonance period in the power recovery circuit 51 and the power recovery circuit 61 is about 1800 nsec, but these numerical values are merely examples in the embodiment. What is necessary is just to set to the optimal value according to the characteristic of a panel, the specification of a plasma display apparatus, etc.

  Next, details of the drive voltage waveform in the sustain period will be described. FIG. 7 is a timing chart for explaining the operation of sustain pulse generating circuit 50 and sustain pulse generating circuit 60 in one embodiment of the present invention. Here, one period of the sustain pulse repetition period (hereinafter abbreviated as “sustain period”) is divided into six periods indicated by T1 to T6, and each period will be described.

  In the following description, the operation for conducting the switching element is expressed as ON and the operation for blocking is expressed as OFF. In the drawing, the signal for turning on the switching element is expressed as “ON”, and the signal for turning off is expressed as “OFF”. Further, in FIG. 7, description is made using the positive electrode waveform, but the present invention is not limited to this. For example, although the embodiment in the negative waveform is omitted, the expression “rising” in the positive waveform in the following description is replaced with “falling” in the negative waveform. The same effect can be obtained even with this waveform.

(Period T1)
At time t1, switching element Q12 is turned on. Then, the charges on the scan electrodes SC1 to SCn side start to flow to the capacitor C10 through the inductor L10, the diode D12, and the switching element Q12, and the voltage on the scan electrodes SC1 to SCn starts to decrease. Since inductor L10 and interelectrode capacitance Cp form a resonance circuit, the voltage of scan electrodes SC1 to SCn drops to near 0 (V) at time t2b after the lapse of half the resonance period. However, the voltage of scan electrodes SC1 to SCn does not drop to 0 (V) due to power loss due to the resistance component of the resonance circuit.

  During this period, switching element Q24 is kept on, and sustain electrodes SU1 to SUn are clamped to 0 (V).

(Period T2)
Then, switching element Q14 is turned on at time t2b. Then, scan electrodes SC1 to SCn are directly grounded through switching element Q14, so that the voltages of scan electrodes SC1 to SCn are clamped to 0 (V) which is the ground potential.

  In the present embodiment, switching element Q21 is turned on at time t2a that is earlier than time t2b by a predetermined time. Since the inductor L20 and the interelectrode capacitance Cp form a resonance circuit, current starts to flow from the capacitor C20 for power recovery to the sustain electrodes SU1 to SUn through the switching element Q21, the diode D21, and the inductor L20. The voltage of the electrodes SU1 to SUn starts to increase. Since the resonance period of inductor L20 and interelectrode capacitance Cp is set to about 1800 nsec, the voltage of sustain electrodes SU1 to SUn rises to almost voltage Vs after about 900 nsec from time t2a. However, since the period T2 from time t2a to time t3, that is, the rise time of the sustain pulse using the power recovery circuit 61 is set to 650 nsec or 800 nsec, the voltage of the sustain electrodes SU1 to SUn reaches Vs at time t3. Does not go up.

  In the present embodiment, a period in which the period T1 and the period T2 overlap is provided by turning on the switching element Q21 at a time t2a that is earlier than the time t2b by a predetermined time. Hereinafter, this period, that is, the period from time t2a to time t2b is referred to as an “overlapping period”. Based on the lighting rate detected by the lighting rate detection circuit 48, the rising of the sustain pulse waveform is controlled so that the length of the overlap period is switched between 100 nsec and 250 nsec. In this embodiment, by providing this overlap period, a sufficient sustain cycle is generated to stably generate sustain discharge, and the rise of the sustain pulse waveform is switched by switching the overlap period based on the lighting rate. The afterimage is reduced.

(Period T3)
At time t3, switching element Q23 is turned on. Then, since sustain electrodes SU1 to SUn are directly connected to power supply VS through switching element Q23, the voltage of sustain electrodes SU1 to SUn is clamped to voltage Vs and forcibly rises to voltage Vs. As a result, in the discharge cell in which the address discharge has occurred, the voltage between scan electrode SCi and sustain electrode SUi exceeds the discharge start voltage, and a sustain discharge occurs.

  In the period T3, the voltages of the sustain electrodes SU1 to SUn are maintained at the voltage Vs, and the sustain discharge can be stabilized by securing the period T3 for a sufficient time (about 1050 nsec to 1400 nsec in the present embodiment). Can be generated.

(Period T4)
Switching element Q22 is turned on at time t4. Then, the charges on the sustain electrodes SU1 to SUn side start to flow to the capacitor C20 through the inductor L20, the diode D22, and the switching element Q22, and the voltage of the sustain electrodes SU1 to SUn starts to decrease. Since inductor L20 and interelectrode capacitance Cp form a resonance circuit, the voltage of sustain electrodes SU1 to SUn drops to near 0 (V) at time t5b after the lapse of half the resonance period. However, the voltage of sustain electrodes SU1 to SUn does not drop to 0 (V) due to power loss due to the resistance component of the resonance circuit.

(Period T5)
Then, switching element Q24 is turned on at time t5b. Then, since sustain electrodes SU1 to SUn are directly grounded through switching element Q24, the voltage of sustain electrodes SU1 to SU is clamped to 0 (V) which is the ground potential.

  In the present embodiment, switching element Q11 is turned on at time t5a that is earlier than time t5b by a predetermined time. Since the inductor L10 and the interelectrode capacitance Cp form a resonance circuit, a current starts to flow from the power recovery capacitor C10 to the scan electrodes SC1 to SCn through the switching element Q11, the diode D11, and the inductor L10. The voltage of the electrodes SC1 to SCn starts to increase. Since the resonance period of inductor L10 and interelectrode capacitance Cp is set to about 1800 nsec, the voltage of scan electrodes SC1 to SCn rises to almost voltage Vs after about 900 nsec from time t5a. However, since the period T5 from time t5a to time t6, that is, the rise time of the sustain pulse using the power recovery circuit 51 is set to 650 nsec or 800 nsec, the voltage of the scan electrodes SC1 to SCn reaches Vs at time t6. Does not go up.

  In the present embodiment, an overlapping period in which the period T4 and the period T5 overlap is provided by turning on the switching element Q11 at a time t5a that is a predetermined time earlier than the time t5b. Similarly to time t2a to time t2b, the rising of the sustain pulse waveform is controlled so that the length of the overlap period is switched between 100 nsec and 250 nsec based on the lighting rate detected by the lighting rate detection circuit 48. In the present embodiment, by providing this overlap period, a sufficient sustain cycle for stably generating the sustain discharge is secured, and the rise of the sustain pulse waveform is switched based on the lighting rate to switch the overlap period. The afterimage is reduced.

(Period T6)
At time t6, switching element Q13 is turned on. Then, scan electrodes SC1 to SCn are directly connected to power supply VS through switching element Q13, so that the voltage of scan electrodes SC1 to SCn is clamped to voltage Vs and forcibly rises to voltage Vs. As a result, in the discharge cell that has caused the address discharge, the voltage between scan electrode SCi and sustain electrode SUi exceeds the discharge start voltage, and a sustain discharge occurs.

  In the period T6, the voltages of the scan electrodes SC1 to SCn are maintained at the voltage Vs, and the sustain discharge can be stabilized by securing the period T6 for a sufficient time (about 1050 nsec to 1400 nsec in this embodiment). Can be generated.

  The switching element Q12 may be turned off after time t2b and before time t5a, and the switching element Q21 may be turned off after time t3 and before time t4. Further, the switching element Q22 may be turned off by the next time t2a after the time t5b, and the switching element Q11 may be turned off by the next time t1 after the time t6. In order to lower the output impedance of sustain pulse generating circuit 50 and sustain pulse generating circuit 60, switching element Q24 is preferably turned off immediately before time t2a, switching element Q13 is preferably turned off immediately before time t1, and switching element Q14 is turned off at time. It is desirable that the switching element Q23 is turned off immediately before time t4 just before t5a.

  In the sustain period, the operations in the above periods T1 to T6 are repeated according to the required number of pulses. In this manner, a sustain pulse voltage that shifts from 0 (V), which is the base potential, to a voltage Vs, which is a potential for generating a sustain discharge, is alternately applied to each of the display electrode pairs 24 to sustain discharge the discharge cells. .

  Here, in the present embodiment, the rise of the sustain pulse waveform is controlled in accordance with the lighting rate for each subfield detected by the lighting rate detection circuit 48. The difference in sustain pulse waveform depending on the lighting rate will be described with reference to FIG.

  FIG. 8 is a diagram showing another example of a timing chart of sustain pulse generation circuit 50 and sustain pulse generation circuit 60 in the embodiment of the present invention.

  In the present embodiment, as described above, when the lighting rate is less than the lighting rate threshold (50%) and when the lighting rate is equal to or higher than the lighting rate threshold, time t2a at which switching element Q21 is turned on and switching The overlap period is switched by changing the time t5a at which the element Q11 is turned on.

  Specifically, when the lighting rate detection circuit 48 determines that the detected lighting rate is equal to or higher than the lighting rate threshold value (50% in the present embodiment), that is, the lighting rate is high, as shown in FIG. The switching element Q21 is turned on at a time t2a ′ that is a predetermined time (150 nsec in the present embodiment) earlier than the time t2a. Further, the switching element Q11 is turned on at a time t5a 'that is earlier than the time t5a by a predetermined time (150 nsec in this embodiment).

  Thus, in this embodiment, when the lighting rate is equal to or higher than the lighting rate threshold (50%), the overlapping period time t2a ′ to time t2b and the overlapping period time t5a ′ to time t5b are set to the overlapping period time t2a. The time t2b and the overlapping period time t5a to time t5b are set to 250 nsec, which is longer than 100 nsec, and the rising edge of the sustain pulse is increased from 650 nsec (550 nsec + 100 nsec) to 800 nsec (550 nsec + 250 nsec). As a result, it is possible to reduce the afterimage phenomenon in the panel 10 and to make the display luminance of each discharge cell uniform while stably generating the sustain discharge. This is for the following reason.

  The afterimage phenomenon is considered to be one of the causes of the variation in emission intensity in the discharge cell. Therefore, in order to reduce the afterimage phenomenon, it is considered effective to make the emission intensity as uniform as possible. It has been found that the emission intensity is greatly influenced by the rising slope of the sustain pulse waveform, the time during which the sustain pulse is maintained at the voltage Vs, the lighting rate, and the like.

  Therefore, the inventor conducted an experiment to confirm how the afterimage phenomenon changes depending on the lighting rate and the rising slope of the sustain pulse waveform. FIG. 9 is a diagram showing the relationship between the lighting rate and the afterimage level in one embodiment of the present invention. In FIG. 9, the vertical axis represents the afterimage level, and the horizontal axis represents the lighting rate. Here, in consideration of the number of subfields in one field period, the total number of sustain pulses, the stability of sustain discharge, the power recovery rate, and the like, the time during which sustain pulses are maintained at voltage Vs (period T3, period T6) In this experiment, only the rising edge of the sustain pulse (period T2, period T5) was switched between 650 nsec (550 nsec + 100 nsec) and 800 nsec (550 nsec + 250 nsec) while maintaining constant at about 1000 nsec. The broken line in the drawing represents an overlap period of 100 nsec (rise time 650 nsec), and the alternate long and short dash line represents an overlap period of 250 nsec (rise time 800 nsec). In addition, the afterimage level on the vertical axis shows the appearance of the afterimage divided into six stages of 0 to 5 by subjective evaluation by the evaluator, and the afterimage level indicated by each numerical value is as follows.

  5: The afterimage can be clearly seen, and the afterimage has a color.

  4: An afterimage is visible, and the afterimage has a color.

  3: The afterimage appears thin and the afterimage of the character can be recognized as a character.

  2: The afterimage is very thin and it is difficult to recognize the afterimage of the character as a character.

  1: The afterimage is hardly visible.

  0: No afterimage is visible.

  Here, if the afterimage level is 2 or less, the level is practically satisfactory.

  As shown in FIG. 9, from this experiment, when the overlap period is set to 100 nsec, the afterimage level has no practical problem if the lighting rate is low, but the afterimage level gradually increases as the lighting rate increases. It was found that the afterimage level suddenly deteriorated when the lighting rate exceeded 60%, and the afterimage level reached 4 when the lighting rate was 100%. On the other hand, it was found that when the overlap period was set to 250 nsec, the afterimage level was the worst when the lighting rate was 30% to 40%, and after the lighting rate exceeded 50%, the afterimage level had no practical problem.

  In other words, the afterimage level changes depending on the lighting rate, but the degree of change changes depending on the overlap period. Therefore, changing the overlap period according to the turn-on rate reduces the afterimage phenomenon on the panel regardless of the lighting rate. It was experimentally confirmed that it was possible to do this.

  Therefore, in the present embodiment, only the overlap period is changed according to the lighting rate while the time for maintaining the sustain pulse at the voltage Vs is constant. Specifically, when the lighting rate is less than the lighting rate threshold value (50%), the overlapping period is set to 100 nsec, and when the lighting rate is equal to or higher than the lighting rate threshold value (50%), the overlapping period is set to 250 nsec, which is increased by 150 nsec. The configuration. As a result, the afterimage phenomenon in the panel can be reduced, and stable sustain discharge can be realized without lengthening the sustain period.

  As described above, according to the present embodiment, the time for performing the rise of the sustain pulse applied to one of the display electrode pairs overlaps the time for performing the fall of the sustain pulse applied to the other of the display electrode pairs. The overlap period is provided, and the overlap period is changed according to the lighting rate detected by the lighting rate detection circuit 48, thereby reducing the afterimage phenomenon and making the display luminance of each discharge cell uniform. Display quality can be improved.

  This experiment is performed using a 50-inch panel having 768 display electrode pairs, and the above-described numerical values are merely set based on the panel. The present embodiment is not limited to these numerical values, and specific numerical values such as the rising period and the overlapping period of the sustain pulse are optimally set according to the specifications of the plasma display device, the panel characteristics, and the like. It is desirable.

  In the present embodiment, a configuration has been described in which 50% is set as the predetermined lighting rate threshold value, and the length of the overlapping period is changed depending on whether the lighting rate is less than 50% or more than 50%. The threshold value is not limited to this value, and may be set to an optimum value in accordance with the characteristics of the panel, the specifications of the plasma display device, and the like. Further, the lighting rate threshold value is not limited to one, but two or more lighting rate threshold values may be set, and the overlap period may be switched between three or more. For example, a plurality of threshold values such as 25%, 50%, and 75% may be set, and the length of the overlapping period may be gradually changed every time the lighting rate becomes equal to or higher than each threshold value.

  In this embodiment, the xenon partial pressure of the discharge gas is set to 10%. However, even if the xenon partial pressure is other than that, the driving voltage corresponding to the panel may be set.

  In addition, the other specific numerical values used in the present embodiment are merely examples, and can be appropriately set to optimal values according to panel characteristics, plasma display device specifications, and the like. desirable. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained.

  INDUSTRIAL APPLICABILITY The present invention is useful as a plasma display device and a panel driving method because it can reduce the afterimage phenomenon in the panel and make the display luminance of each discharge cell uniform.

The disassembled perspective view which shows the structure of the panel in one embodiment of this invention. Electrode arrangement of the panel The figure which shows the subfield structure in one embodiment of this invention Drive voltage waveform diagram applied to each electrode of panel in one embodiment of the present invention The circuit block diagram of the plasma display apparatus in one embodiment of the present invention 1 is a circuit diagram of a sustain pulse generation circuit according to an embodiment of the present invention. Timing chart for explaining the operation of the sustain pulse generation circuit The figure which shows the other example of the timing chart of the same sustain pulse generation circuit The figure which shows the relationship between the lighting rate and afterimage level in one embodiment of this invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Plasma display apparatus 10 Panel 21 Front plate (made of glass) 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 25, 33 Dielectric layer 26 Protective layer 31 Back plate 32 Data electrode 34 Partition 35 Phosphor layer 41 Image signal processing circuit 42 data electrode drive circuit 43 scan electrode drive circuit 44 sustain electrode drive circuit 45 timing generation circuit 48 lighting rate detection circuit 50, 60 sustain pulse generation circuit 51, 61 power recovery circuit 52, 62 clamp circuit Q11, Q12, Q13, Q14, Q21, Q22, Q23, Q24, Q26, Q27, Q28, Q29 Switching element C10, C20, C30 Capacitor L10, L20 Inductor D11, D12, D21, D22, D30 Diode VE1, ΔVE Power supply

Claims (6)

A plasma display panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode;
A sustain pulse generating circuit that applies a sustain pulse to each of the display electrode pairs by a power recovery circuit that causes the interelectrode capacitance of the display electrode pair and an inductor to resonate and raises or falls the sustain pulse;
A lighting rate detection circuit for detecting the lighting rate of the discharge cells;
The sustain pulse generation circuit has a time for rising of the sustain pulse applied to one electrode of the display electrode pair and a time for falling of the sustain pulse applied to the other electrode of the display electrode pair. A plasma display device characterized by providing overlapping overlapping periods and changing the overlapping periods according to the lighting rate detected by the lighting rate detection circuit. The lighting rate detection circuit compares the detected lighting rate with a predetermined threshold value,
The sustain pulse generation circuit, when the lighting rate detection circuit determines that the lighting rate is equal to or higher than a predetermined threshold, than the time when the lighting rate is determined to be smaller than the predetermined threshold. The plasma display apparatus according to claim 1, wherein the overlap period is changed to be longer. 2. The plasma display apparatus according to claim 1, wherein the sustain pulse generation circuit is changed so as to lengthen the overlap period by lengthening a drive time of the power recovery circuit at a rising edge of the sustain pulse. A plasma display panel comprising a plurality of discharge cells having a display electrode pair consisting of a scan electrode and a sustain electrode,
A power recovery circuit for causing the sustaining pulse to rise or fall by resonating the interelectrode capacitance of the display electrode pair and the inductor, and a clamp circuit for clamping the sustaining pulse voltage to a predetermined voltage; A sustain pulse generating circuit for generating a sustain pulse of the number corresponding to the luminance weight and applying it to each of the display electrode pairs in the sustain period of the subfield having a plurality of initialization periods, address periods, and sustain periods provided therein A method of driving a plasma display panel driven using
An overlapping period is provided in which a time for performing the rising of the sustain pulse applied to one of the display electrode pairs and a time for performing the falling of the sustain pulse applied to the other of the display electrode pairs are provided, and the discharge cell is turned on. A method for driving a plasma display panel, wherein the overlap period is changed according to a rate. 5. The method of driving a plasma display panel according to claim 4, wherein when the lighting rate is equal to or higher than a predetermined threshold, the overlapping period is made longer than when the lighting rate is not. 5. The method of driving a plasma display panel according to claim 4, wherein the overlap period is lengthened by lengthening the drive time of the power recovery circuit at the rising edge of the sustain pulse.

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