JP2008205759A - Distortion compensation device - Google Patents

Abstract

An object of the present invention is to provide a distortion compensation apparatus that can adjust the timing of an adjustment signal and a feedback signal without performing sequence control.
In order to achieve the above object, a delay adjustment unit 4 for adjusting a delay of a feedback signal is provided independently of a distortion compensation adjustment unit 5. Since the delay adjustment unit 5 independently adjusts the delay of the feedback signal, the timing of the adjustment signal and the feedback signal can be matched without performing sequence control. In particular, the delay adjustment unit 4 determines the delay difference between the delay difference between the feedback signal and the adjustment signal and the signal obtained by delaying one of the feedback signal and the adjustment signal by a predetermined delay amount. By calculating a difference value between the differences, the delay or advance of the feedback signal with respect to the adjustment signal is detected.
[Selection] Figure 1

Description

  The present invention relates to a distortion compensation apparatus used in a radio transmission apparatus, and more particularly to a distortion compensation apparatus that adjusts a delay caused by a power amplifier and a feedback loop.

  A first example of a conventional delay adjustment circuit is shown in FIG. 5 (see, for example, Patent Document 1). The delay adjustment circuit shown in FIG. 5 inputs the delay adjustment filter 70 to the adjustment signal, and performs delay adjustment by changing the tap of the delay adjustment filter 70. It has a tap coefficient for delay time adjustment as a memory, and delay adjustment is performed by selecting the tap with the closest delay difference.

A second example of a conventional delay adjustment circuit is shown in FIG. 6 (see, for example, Patent Document 2). The delay adjustment circuit shown in FIG. 6 detects a delay based on the correlation of a plurality of sample signals in order to perform a sparse adjustment of the delay. Further, the AD detection clock phase of the feedback signal is controlled in order to finely adjust the delay. At this time, an error is detected by a distortion detection circuit 71 that detects distortion.
JP 2004-15769 A Japanese Patent Application No. 2002-584489

  In a distortion compensation device that feeds back a part of the output of the transmission PA and uses the error between the feedback signal and the adjustment signal as a nonlinear distortion amount of the transmission PA to obtain the inverse distortion characteristics. The delay of the feedback signal degrades the distortion detection sensitivity. It becomes a factor to make. In addition, the path delay time of the feedback signal varies depending on the circuit format, and varies depending on the temperature, aging, etc., so that it is necessary to perform sequence control such as performing distortion compensation control after optimizing control of delay error compensation control. .

  Therefore, an object of the present invention is to provide a distortion compensation apparatus that can adjust the timing of an adjustment signal and a feedback signal without performing sequence control.

  In order to achieve the above object, the present invention is characterized in that a delay adjustment unit for adjusting the delay of the feedback signal is provided independently of the distortion compensation adjustment unit. Since the delay adjustment unit independently adjusts the delay of the feedback signal, the timing of the adjustment signal and the feedback signal can be matched without performing sequence control.

  In the distortion compensation apparatus according to the present invention, the delay adjustment unit outputs a first delay detection circuit that detects a delay difference between a feedback signal output from the signal storage circuit and the adjustment signal, and an output from the signal storage circuit. A second delay detection circuit for detecting a delay difference between a feedback signal and a signal obtained by delaying one of the adjustment signals by a predetermined delay amount; a delay difference detected by the first delay detection circuit; A subtractor for outputting a difference value from a delay difference detected by a second delay detection circuit; the distortion compensation circuit; the distortion compensation adjustment unit; the first delay detection circuit; the second delay detection circuit; A clock for advancing or delaying the phase of the driving clock for operating the A / D conversion of the demodulating circuit with respect to the operating digital system operating clock according to the difference value output from the subtractor A settling unit is preferably provided with a. The delay adjustment unit calculates a difference value between the signal output from the first delay detection circuit and the signal output from the second delay detection circuit, thereby detecting a delay or advance of the feedback signal with respect to the adjustment signal, thereby providing a feedback signal. The delay can be adjusted. As a result, the delay amount can be adjusted to be reduced without performing sequence control. Further, since the advance or delay of the clock of the digital signal processing system is controlled in accordance with the delay or advance of the feedback signal with respect to the adjustment signal, the delay amount of the feedback signal can be adjusted.

  In the distortion compensation apparatus according to the present invention, the clock adjustment unit raises or lowers the oscillation frequency according to the sign of the difference value output from the subtracter, and oscillates according to the amount of the difference value output from the subtractor. It is preferable to provide a voltage controlled oscillator that controls the magnitude of increasing or decreasing the frequency and outputs the driving clock. The delay can be easily adjusted using a voltage controlled oscillator.

  According to the present invention, since the delay adjustment unit is provided independently in the distortion compensation device used in the wireless transmission device, the timing of the adjustment signal and the feedback signal can be matched without performing sequence control. Furthermore, since a delay adjustment unit that does not require sequence control is provided independently, the delay amount of the feedback signal can be adjusted each time the delay is detected. Therefore, the accuracy of distortion compensation can be improved.

  Embodiments of the present invention will be described with reference to the accompanying drawings. The embodiment described below is an example of the configuration of the present invention, and the present invention is not limited to the following embodiment. FIG. 1 is a schematic configuration diagram of a distortion compensation apparatus according to the present embodiment. A distortion compensation device 90 shown in FIG. 1 is used in a wireless transmission device that wirelessly transmits an input transmission signal. The distortion compensation device 90 includes an input terminal 1, a distortion compensation circuit 52, a modulation circuit 2, a transmission power amplifier 61, a demodulation circuit 3, a signal storage circuit 17, a delay adjustment unit 4, and a distortion compensation adjustment unit 5. And comprising.

  An input terminal 1 shown in FIG. 1 receives a digital adjustment signal. The adjustment signal is a distortion compensation and delay adjustment signal that is input separately from the transmission signal. Here, the adjustment signal is preferably a digital signal of an ideal signal waveform so that distortion generated in the distortion compensator 90 can be accurately detected. In addition, since the adjustment signal is periodically input to the input terminal 1, it is possible to perform distortion compensation and delay adjustment with respect to a change with time due to a season or a time zone.

  The distortion compensation circuit 52 shown in FIG. 1 compensates the adjustment signal input to the input terminal 1 according to a distortion compensation table. The measured distortion amount is written in the distortion compensation table, and the distortion is compensated by compensating for the inverse characteristic of the distortion. For example, a distortion characteristic opposite to the distortion applied by the modulation circuit 2 and the transmission power amplifier 61, which will be described later, is applied to the adjustment signal to compensate for the distortion of the orthogonal modulation signal output from the transmission power amplifier 61. The distortion compensation table is a table stored in advance and can be changed by the distortion compensation adjustment unit 5.

  The modulation circuit 2 shown in FIG. 1 performs D / A conversion on the adjustment signal whose distortion has been compensated by the distortion compensation circuit 52, and then orthogonally modulates and outputs an orthogonal modulation signal. As shown in FIG. 2 described later, the modulation circuit 2 includes, for example, a 90 ° phase difference wave device 59, mixers 58I and 58Q, an adder 60, and D / A conversion circuits 53I and 53Q.

  The transmission power amplifier 61 shown in FIG. 1 amplifies the quadrature modulation signal output from the modulation circuit 2. By transmitting the quadrature modulation signal to the outside, the transmission signal input to the input terminal 1 can be wirelessly transmitted to the outside.

  The demodulation circuit 3 shown in FIG. 1 demodulates the quadrature modulation signal amplified by the transmission power amplifier 61 and outputs a feedback signal obtained by A / D conversion. For example, as shown in FIG. 2 to be described later, the demodulation circuit 3 includes a distributor 63, a 90 ° phase difference wave detector 64, demodulators 65I and 65Q, and A / D conversion circuits 68I and 68Q.

  The signal storage circuit 17 shown in FIG. 1 stores the feedback signal output from the demodulation circuit 3. The signal storage circuit 17 is preferably capable of adjusting the output timing for each address, and is, for example, a DP RAM (Dual Port Random Access Memory).

  The distortion compensation adjustment unit 5 shown in FIG. 1 detects the distortion of the feedback signal output from the signal storage circuit 17 with respect to the adjustment signal, and changes the distortion compensation table referred to by the distortion compensation circuit 52 according to the distortion. For example, the distortion of the feedback signal is detected by calculating an amplitude difference between the adjustment signal and the feedback signal with respect to the amplitude of the adjustment signal. The distortion compensation adjustment unit 5 includes, for example, a distortion detection circuit 10, a distortion amount compensation value change circuit 21, and a distortion amount compensation value storage circuit 22, as shown in FIG.

  The delay adjustment unit 4 detects a delay difference between the adjustment signal and the feedback signal output from the signal storage circuit 17 and adjusts the timing at which the feedback signal is output from the signal storage circuit 17 according to the delay difference. The adjustment signal is a signal from the input terminal 1. The feedback signal is a signal demodulated by the demodulation circuit 3 and A / D converted. By adjusting the timing of outputting the feedback signal from the signal storage circuit 17, the timing of the adjustment signal detected by the distortion compensation adjustment unit 5 and the feedback signal can be matched. For example, the delay of the feedback signal can be adjusted in units of clocks by adjusting the output timing for each address of the feedback signal. Further, the A / D conversion of the A / D conversion circuits 68I and 68Q and the writing of the signal storage circuit 17 operate with the drive clock adjusted by the delay adjustment unit 4, so that the clock phase of the drive clock is advanced or delayed. Thus, the timing of the feedback signal output from the signal storage circuit 17 can be finely adjusted. For example, as shown in FIG. 2 to be described later, the delay adjustment unit 4 includes a delay coarse adjustment circuit 20, a correlation detection circuit 18, an address control circuit 19, a first delay detection circuit 11, and a delay fine adjustment circuit 12. The second delay detection circuit 13, the subtractor 14, the LPF 15, and the clock adjustment unit 16 are provided.

  FIG. 2 is a configuration diagram illustrating a specific example of the distortion compensation apparatus according to the present embodiment. The distortion compensation apparatus 91 shown in FIG. 2 has a configuration for wirelessly transmitting a transmission signal. For example, the distortion compensator 91 includes an input terminal 1, an adjustment signal output circuit 51, D / A conversion circuits 53I and 53Q, low-pass filters (LPF) 54I and 54Q, a local oscillator 55, a distributor 56, a 90 ° phase difference wave filter 59, mixers 58I and 58Q, an adder 60, a transmission power amplifier 61, and a quadrature modulation signal output terminal 62. A conventional technique can be used for a configuration for wirelessly transmitting a transmission signal.

  The distortion compensation device 91 further includes a configuration for performing feedback control. For example, the distortion compensator 91 includes a distributor 63, a 90 ° phase difference wave detector 64, demodulators 65I and 65Q, low-pass filters (LPF) 66I and 66Q, amplifiers 67I and 67Q, and an A / D. Conversion circuits 68I and 68Q and a signal storage circuit 17 are provided.

  The distortion compensation device 91 further includes a distortion compensation adjustment unit 5 for performing distortion compensation. For example, the distortion compensation device 91 includes a distortion detection circuit 10, a distortion amount compensation value change circuit 21, a distortion amount compensation value storage circuit 22, and a distortion compensation circuit 52.

  The distortion compensation apparatus 91 further includes a delay adjustment unit 4 for performing delay adjustment. For example, the distortion compensator 91 includes a delay coarse adjustment circuit 20, a correlation detection circuit 18, an address control circuit 19, a first delay detection circuit 11, a delay fine adjustment circuit 12, and a second delay detection circuit 13. A subtractor 14, an LPF 15, and a clock adjustment unit 16 are provided.

  The input terminal 1 receives a digital transmission signal and an adjustment signal. The adjustment signal output circuit 51 converts the adjustment signal input to the input terminal 1 into two systems of signals, similar to the transmission signal. The adjustment signal output circuit 51 outputs two baseband adjustment signals. The two baseband adjustment signals are an in-phase component (I) adjustment signal and a quadrature component (Q) adjustment signal. These two systems of signals are used as adjustment signals by the delay adjustment unit 4 and the distortion compensation adjustment unit 5. The distortion compensation circuit 52 compensates for the distortion of the adjustment signal output from the adjustment signal output circuit 51 according to the distortion compensation table stored in the distortion amount compensation value storage circuit 22. The D / A conversion circuits 53I and 53Q convert the adjustment signal compensated for distortion by the distortion compensation circuit 52 from a digital signal to an analog signal. The LPFs 54I and 54Q remove high-frequency noise from the adjustment signals for the two systems from the D / A converters 53I and 53Q, respectively.

  The 90 ° phase difference wave device 59 branches the carrier wave from the distributor 56 into two systems, and adjusts the phase difference so that the two carrier waves are orthogonal to each other. Here, the distributor 56 branches the carrier wave from the local oscillator 55 into two systems. The mixers 58I and 58Q perform quadrature modulation of the carrier waves having a predetermined frequency from the 90 ° phase difference wave detector 59 with the two adjustment signals from the LPFs 54I and 54Q. The adder 60 combines the quadrature modulation signals from the mixer 58I and the mixer 58Q. The transmission power amplifier 61 amplifies the quadrature modulation signal combined by the adder 60. The quadrature modulation signal output terminal 62 outputs the quadrature modulation signal amplified by the transmission power amplifier 61 and wirelessly transmits it to the outside. For example, an antenna that outputs the quadrature modulated signal amplified by the transmission power amplifier 61.

  The distributor 63 distributes a part of the quadrature modulation signal output from the transmission power amplifier 61. The 90 ° phase difference wave detector 64 branches the carrier wave from the local oscillator 55 into two systems, and adjusts the phase difference so that the two carrier waves are orthogonal. Demodulators 65I and 65Q demodulate the quadrature modulation signal from distributor 63 with the carrier wave from 90 ° phase difference wave detector 64, and output a feedback signal. A feedback signal reproducing the baseband I and Q signals can be obtained.

  The LPFs 66I and 66Q remove high frequency noise from the feedback signals from the demodulators 65I and 65Q. The amplifiers 67I and 67Q amplify the feedback signals output from the LPFs 66I and 66Q. The A / D conversion circuits 68I and 68Q convert the feedback signals amplified by the amplifiers 67I and 67Q from an analog format to a digital format and output the converted signals.

  The signal storage circuit 17 stores the digitized feedback signals of the A / D conversion circuits 68I and 68Q. The signal storage circuit 17 stores the feedback signal stored at the timing designated by the address control circuit 19, the distortion detection circuit 10, the first delay detection circuit 11, the delay fine adjustment circuit 12, and the correlation detection circuit 18. And output to By adjusting the timing for outputting the feedback signal, the delay of the feedback signal can be roughly adjusted. Further, since the A / D conversion of the A / D conversion circuits 68I and 68Q and the writing of the signal storage circuit 17 are driven by the drive clock output from the clock adjustment unit 16, the delay of the feedback signal can be finely adjusted. it can.

  The distortion detection circuit 10 detects a difference or error between the adjustment signal output from the delay coarse adjustment circuit 20 and the feedback signal output from the signal storage circuit 17. The distortion detection circuit 10 is, for example, an FFT (Fast Fourier Transform) arithmetic circuit. The error is, for example, LMS (Least Mean Square). The distortion amount compensation value storage circuit 22 stores a distortion amount compensation table of the adjustment signal. The distortion amount compensation value changing circuit 21 changes the distortion amount compensation table stored in the distortion amount compensation value storage circuit 22 so that the difference between the adjustment signal and the feedback signal becomes zero. The distortion compensation circuit 52 compensates the adjustment signal output from the adjustment signal output circuit 51 according to the distortion amount compensation table stored in the distortion amount compensation value storage circuit 22.

  The coarse delay adjustment circuit 20 delays in advance the delay time of the signal path generated in the feedback loop. The coarse delay adjustment circuit 20 is a shift register, for example. An output from the coarse delay adjustment circuit 20 is input to the distortion detection circuit 10, the first delay detection circuit 11, the correlation detection circuit 18, and the fine delay adjustment circuit 12. Since the approximate time required from when the adjustment signal output circuit 51 outputs the adjustment signal to when it is output as the feedback signal is predetermined, the required time is adjusted by the delay coarse adjustment circuit 20.

  The correlation detection circuit 18 detects the correlation between the feedback signal output from the signal storage circuit 17 and the adjustment signal output from the delay coarse adjustment circuit 20. The correlation detection circuit 18 detects, for example, a timing at which the error is minimized by the correlation of a plurality of samples between the feedback signal and the adjustment signal. The address control circuit 19 adjusts the timing at which the signal storage circuit 17 outputs the feedback signal according to the correlation detection result of the correlation detection circuit 18. The delay of one clock or more of the digital processing system can be adjusted by matching the timing at which the signal storage circuit 17 outputs the feedback signal so that the correlation between the adjustment signal and the feedback signal is minimized.

  The first delay detection circuit 11 detects the delay amount between the adjustment signal and the feedback signal. The delay amount is, for example, a difference or error between the adjustment signal and the feedback signal. The delay fine adjustment circuit 12 delays the adjustment signal by a predetermined delay amount. The delay fine adjustment circuit 12 can use, for example, a fixed tap FIR (Finite Impulse Response) filter. Here, the predetermined delay amount is, for example, a delay amount of one clock or less in the digital processing system. The second delay detection circuit 13 detects the delay amount between the signal obtained by delaying the adjustment signal by a predetermined delay amount by the delay fine adjustment circuit 12 and the feedback signal delayed by an integral multiple of the clock by the shift register 23. . Here, the error is, for example, LMS (Least Mean Square). The subtractor 14 outputs a difference value between the delay amount detected by the first delay detection circuit 11 and the delay amount detected by the second delay detection circuit 13. The LPF 15 averages the delay difference signal calculated by the subtractor 14. By delaying or advancing the adjustment signal input to either the first delay detection circuit 11 or the second delay detection circuit 13, the feedback signal is converted into the adjustment signal from the magnitude of the difference from the subtractor 14. It can be determined whether the vehicle is moving forward or behind.

  In the present embodiment, the case where the delay fine adjustment circuit 12 delays the adjustment signal has been described. However, instead of including the delay fine adjustment circuit 12, a delay that delays the feedback signal input to the first delay detection circuit 11 is described. A fine adjustment circuit may be provided. Thereby, similarly to this embodiment, it can be determined from the difference from the subtractor 14 whether the feedback signal is advanced or delayed with respect to the adjustment signal.

  The delay detection in the present embodiment will be described in detail with reference to FIGS. FIG. 3 is an explanatory diagram showing characteristics of delay difference versus error detection level. “Output 1” is an example of an error detection level detected by the first delay detection circuit 11 shown in FIG. 2, and “Output 2” is an error detection level detected by the second delay detection circuit 13 shown in FIG. It is an example.

  The error detection level increases as the absolute value of the delay difference increases. Therefore, by delaying the timing of the second delay detection circuit 13 with respect to the first delay detection circuit 11, either the delay or the advance can be determined based on the comparison result of the error detection level. For example, as shown in FIG. 3, when the error detection level of output 2 is larger than the error detection level of output 1, the feedback signal is advanced than the adjustment signal, so that the phase of the drive clock is controlled to be delayed. Thus, the delay difference can be reduced. On the contrary, although not shown, when the error detection level of output 2 is smaller than that of output 1, the feedback signal is delayed with respect to the adjustment signal, so control is performed to advance the phase of the drive clock. Thus, by calculating the magnitude relationship between the outputs of the first delay detection circuit 11 and the second delay detection circuit 13 by the subtractor 14 shown in FIG. 2, the delay or advance of the delay difference can be detected. The phase of the drive clock can be controlled.

  FIG. 4 is an explanatory diagram comparing delay difference versus error detection level characteristics when nonlinear distortion is large and delay difference versus error detection level characteristics when nonlinear distortion is small. A solid line 101 indicates when the nonlinear distortion is small, and a broken line 102 indicates when the nonlinear distortion is large. As the distortion compensation control proceeds, the slope of the detection characteristic of the delay difference vs. error detection level characteristic increases, and the variation in delay error control decreases. For this reason, by cooperating the delay adjustment unit and the distortion compensation adjustment unit, not only sequence control is unnecessary, but also distortion compensation of the transmission signal can be performed accurately and efficiently.

  From the above, as shown in FIG. 2, the delay adjustment unit 4 includes the distortion compensation circuit 52, the distortion compensation adjustment unit 5, the first delay detection circuit 11, the second delay detection circuit 13, and the subtractor 14. Whether the phase of the drive clock for operating the A / D conversion of the A / D conversion circuits 68I and 68Q and the writing of the signal storage circuit 17 with respect to the digital operation clock to be operated is advanced according to the difference value output from the subtractor 14 Alternatively, it is preferable to include a clock adjusting unit 16 that delays the clock. The timing of the feedback signal output from the signal storage circuit 17 is finely adjusted by controlling the phase of the drive clock. For example, when the feedback signal is delayed from the adjustment signal, the phase of the drive clock is advanced, and when the feedback signal is advanced from the adjustment signal, the phase of the drive clock is delayed to reduce the delay difference. Can approach zero. By adjusting the phase of the drive clock, a delay difference such as a delay or advance of one clock or less in digital processing can be efficiently adjusted to approach zero.

  The clock adjustment unit 16 increases or decreases the oscillation frequency according to the sign of the difference value output from the subtractor 14 and determines the magnitude for increasing or decreasing the oscillation frequency according to the amount of the difference value output from the subtractor 14. And a voltage controlled oscillator (VCO) 36 for outputting a drive clock. The clock adjustment unit 16 includes, for example, a D / A conversion circuit 31, an operational amplifier 35, and a voltage controlled oscillator 36. As shown in the present embodiment, the clock adjustment unit 16 can finely adjust the phase by controlling the phase of the drive clock with respect to the digital operation clock.

  A specific operation will be described. The D / A conversion circuit 31 converts the delay difference signal averaged by the LPF 15 from a digital signal to an analog signal. The oscillator 32 outputs a digital operation clock signal having a predetermined frequency and supplies it to at least the correlation detection circuit 18, the first delay detection circuit 11, and the second delay detection circuit 13. The operational amplifier 35 outputs a calculation signal obtained by differentially amplifying the difference value output from the subtractor 14 by comparison with the reference level. For example, when the difference value output from the subtractor 14 indicates a positive value when the phase of the feedback signal is ahead of the phase of the adjustment signal, the output voltage of the operational amplifier 35 is reduced according to the difference value, The oscillation frequency of the VCO 36 is lowered. Microscopically, the phase of the oscillation signal of the VCO 36 is delayed. As a result, the phase of the feedback signal can be delayed. On the contrary, if the difference value output from the subtractor 14 shows a negative value, the output voltage of the operational amplifier 35 is increased according to the difference value, and the oscillation frequency of the VCO 36 is increased. Microscopically, the phase of the oscillation signal of the VCO 36 is advanced. As a result, the phase of the feedback signal can be advanced. Further, the phase offset of the drive clock can be varied by adjusting the reference level.

  Further, when the difference value output from the subtractor 14 when the phase of the feedback signal is behind the phase of the adjustment signal indicates a positive value, the output voltage of the operational amplifier 35 is increased according to the difference value, The oscillation frequency of the VCO 36 is increased. Microscopically, the phase of the oscillation signal of the VCO 36 is advanced. As a result, the phase of the feedback signal can be advanced. On the contrary, if the difference value output from the subtractor 14 shows a positive value, the output voltage of the operational amplifier 35 is reduced according to the difference value, and the oscillation frequency of the VCO 36 is lowered. Microscopically, the phase of the oscillation signal of the VCO 36 is delayed. As a result, the phase of the feedback signal can be delayed. Further, the phase offset of the drive clock can be varied by adjusting the reference level.

  In this way, the VCO 36 finely adjusts the clock phase of the drive clock that operates the A / D conversion of the A / D conversion circuits 68I and 68Q and the writing of the signal storage circuit 17, so that the adjustment signal and the feedback signal are A delay difference of less than one clock can be brought close to zero.

  It can be used as a distortion compensation device used for high-efficiency transmission of wireless communication.

It is a schematic block diagram of the distortion compensation apparatus which concerns on this embodiment. It is a block diagram which shows the specific example of the distortion compensation apparatus which concerns on this embodiment. It is explanatory drawing which shows the characteristic of a delay difference vs error detection level. FIG. 7 is an explanatory diagram comparing delay difference versus error detection level characteristics when nonlinear distortion is large and delay difference versus error detection level characteristics when nonlinear distortion is small. It is a block diagram which shows the 1st example of the conventional delay adjustment circuit. It is a block diagram which shows the 2nd example of the conventional delay adjustment circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Input terminal 2 Modulation circuit 3 Demodulation circuit 4 Delay adjustment part 5 Distortion compensation adjustment part 10 Distortion detection circuit 11 1st delay detection circuit 12 Delay fine adjustment circuit 13 2nd delay detection circuit 14 Subtractor 15 LPF
Reference Signs List 16 clock adjustment unit 17 signal storage circuit 18 correlation detection circuit 19 address control circuit 20 delay coarse adjustment circuit 21 distortion amount compensation value change circuit 22 distortion amount compensation value storage circuit 23 shift register 31 D / A conversion circuit 32 oscillator 35 operational amplifier 36 Voltage controlled oscillator (VCO)
52 Distortion Compensation Circuit 51 Adjustment Signal Output Circuit 53I, 53Q D / A Conversion Circuit 54I, 54Q Low-Pass Filter (LPF)
55 Local Oscillator 56 Distributor 58I, 58Q Mixer 59 90 ° Phase Difference Waver 60 Adder 61 Transmit Power Amplifier 62 Quadrature Modulation Signal Output Terminal 63 Distributor 64 90 ° Phase Difference Waver 65I, 65Q Demodulator 66I, 66Q Low Frequency Pass filter (LPF)
67I, 67Q amplifier 68I, 68Q A / D conversion circuit 70 delay adjustment filter 71 distortion detection circuit 72 controller 73 distortion amount compensation value change circuit 74 distortion amount compensation value storage circuit 75 controller 76 timing adjustment unit 77 correlation detection circuit 78 controller 79 DP RAM
90, 91 Distortion compensator 101 Delay difference versus error detection level characteristic when nonlinear distortion is small 102 Delay difference versus error detection level characteristic when nonlinear distortion is large

Claims (3)

An input terminal to which an adjustment signal is input;
A distortion compensation circuit that compensates for distortion of the adjustment signal input to the input terminal according to a distortion compensation table that stores a distortion compensation amount for the signal input to the input terminal;
A modulation circuit that outputs a quadrature modulation signal by performing quadrature modulation after D / A converting the adjustment signal whose distortion has been compensated by the distortion compensation circuit;
A transmission power amplifier that amplifies the quadrature modulation signal output from the modulation circuit;
A demodulator that demodulates the amplified quadrature modulated signal of the transmission power amplifier and then performs A / D conversion to output a feedback signal;
A signal storage circuit for storing the feedback signal demodulated by the demodulation circuit;
A delay adjustment unit that detects a delay difference between the adjustment signal and a feedback signal output from the signal storage circuit, and adjusts a timing at which the feedback signal is output from the signal storage circuit according to the delay difference;
A distortion compensation adjustment unit that detects distortion of the feedback signal output from the signal storage circuit with respect to the adjustment signal and writes the distortion compensation amount in the distortion compensation table;
A distortion compensation apparatus comprising: The delay adjustment unit
A first delay detection circuit for detecting a delay difference between the feedback signal output from the signal storage circuit and the adjustment signal;
A second delay detection circuit for detecting a delay difference between a feedback signal output from the signal storage circuit and a signal obtained by delaying one of the adjustment signals by a predetermined delay amount;
A subtractor for outputting a difference value between a delay difference detected by the first delay detection circuit and a delay difference detected by the second delay detection circuit;
A drive clock for operating A / D conversion of the demodulating circuit with respect to a digital operation clock for operating the distortion compensating circuit, the distortion compensating adjusting unit, the first delay detecting circuit, the second delay detecting circuit, and the subtractor. The distortion compensation apparatus according to claim 1, further comprising: a clock adjustment unit that advances or delays a phase according to a difference value output from the subtractor. The clock adjustment unit
The driving frequency is controlled by increasing or decreasing the oscillation frequency according to the sign of the difference value output from the subtractor, and increasing or decreasing the oscillation frequency according to the amount of the difference value output by the subtractor. The distortion compensation apparatus according to claim 2, further comprising a voltage-controlled oscillator that outputs a clock.

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