JP2008299914A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of solving the problem caused when simultaneous access is executed from two ports to the same address. <P>SOLUTION: A selector circuit selecting read data DOA amplified by a sense amplifier SAA and read data DOB amplified by a sense amplifier SAB and a sense amplifier enable control circuit ANDS controlling activation of the sense amplifier SAB on the basis of the external sense amplifier enable signal SEB of a port B and the output signal RACO of a row address comparator RAC are provided to the semiconductor memory device. Thereby, the read data DOA amplified by the sense amplifier SAA can be output as read data DOB' from the port B and when row addresses of a port A and the port B are equal to each other, operation of the sense amplifier SAB of the port B can be turned off. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to an SRAM (Static Random Access Memory) having a multiport.

  As a semiconductor storage device mounted on an LSI (Large Scale Integration), an on-chip SRAM mounted on a semiconductor chip is mainly a single-port SRAM that reads and writes memory data from one port. In the SoC (System On a Chip) such as image processing and communication processing, there is an increasing demand for mounting a multi-port SRAM that can be accessed simultaneously from a plurality of ports and can speed up the processing. . An example of such a multi-port on-chip SRAM is a dual-port SRAM that can be accessed simultaneously from two ports.

  In order to increase the performance and functionality of LSIs, these on-chip SRAMs are rapidly increasing in capacity, and accordingly, the area ratio of on-chip SRAM in the entire LSI circuit tends to increase. is there. On the other hand, for example, the dual port SRAM has two major problems: simultaneous access from two ports to the same address, and area penalty. In order to secure the noise margin of the memory cell against the problem of simultaneous access to the same address, it is necessary to increase the gate width of the driver transistor constituting the memory cell. As a result, the cell area is more than doubled.

  On the other hand, semiconductor memory devices that reduce the memory cell area while ensuring a noise margin are known (see, for example, Patent Document 1 and Non-Patent Document 1).

  As shown in FIG. 6, the conventional semiconductor memory device 100 (dual port SRAM) includes memory cells MC0 to MCm−1, a row decoder ROWDECA that is a peripheral circuit for the first port A, a sense amplifier SAA, and a write circuit. And a row decoder ROWDECB, a sense amplifier SAB, a write driver WDB, a bit line shift circuit BLS, and a row address comparator RAC, which are peripheral circuits for the port B as the second port.

  An example of the configuration of the memory cells MC0 to MCm-1 is shown in FIG. 2, and an example of the configuration of the row address comparator RAC is shown in FIG. 3 (details will be described later).

An operation of the semiconductor memory device 100 will be described. When the row address of the address signal input to the port A is different from the row address of the address signal input to the port B, the output signal of the row address comparator RAC becomes “H” level. In port A, the selected word line WLA and bit lines BLA and BLA # are used for write and read operations. In the port B, the word line WLB and the bit lines BLB and BLB # are selected and used. When only one of the ports operates, the row address comparator RAC outputs an “H” level output signal. In this case, each port operates in the same manner as a single port SRAM. On the other hand, when the row addresses of port A and port B are the same, the row address comparator RAC outputs an output signal of “L” level. In this case, the row decoder ROWDECB of the port B activates only the word line WLA. Further, the bit shift circuit BLS selects the bit lines BLA and BLA # of the port A as the bit line pair of the port B. Port B bit lines BLB and BLB # are not used, and port A and port B share port A bit lines BLA and BLA #. As a result, only the word line WLA of the port A is activated, and the reading of the port A and the port B can be performed simultaneously using the bit lines BLA and BLA #. Therefore, in the memory cell MC, a noise margin can be ensured even if the gate width of the driver transistor is set to be equal to that of a single port SRAM, so that the area of the memory cell MC can be reduced. For example, in the case of the semiconductor memory device 100, it can be realized with an area about 1.6 times larger than the conventional one.
JP 2006-127669 A 2006 Symposium on VLSI Circuits Digest of Technical Paper (1-4244-0006-6 / 06 / S20.00 (c) 2006 IEEE) "A 65nm Ultra-High-Density Dual-Sur-Cours "

  However, in the conventional semiconductor memory device 100, when the same row address is simultaneously read out at the port A and the port B, the sense amplifiers SAA and SAB at both the port A and the port B operate. There was a problem that was large.

  On the other hand, there has been a problem that if simultaneous writing to the same address from two ports is performed with respect to the same address, data cannot be written properly.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor memory device that can solve a problem that occurs when two ports simultaneously access the same address. .

  To achieve the above object, in the semiconductor memory device according to claim 1, the first and second storage nodes are respectively set to one and the other of the ground potential and the power supply potential in accordance with stored data. A flip-flop circuit and a gate electrically coupled to a corresponding first word line, and a first for electrically coupling between the corresponding first bit line and the flip-flop circuit A second gate having a gate transistor and a gate electrically coupled to a corresponding second word line, and electrically coupling between the corresponding second bit line and the flip-flop circuit A plurality of memory cells including transistors, a plurality of memory cells arranged in a matrix, and a plurality of first and second word lines provided corresponding to the memory cell rows, A memory cell array including a plurality of first and second bit lines provided corresponding to each of the memory cell columns, first and second ports capable of transmitting and receiving input / output signals independently of each other, and First and second row decoders provided corresponding to the second ports, respectively, for outputting memory cell row selection instructions according to the input addresses, respectively, and the first port and the second port, respectively. A row address comparator for comparing the row address of the input data, provided corresponding to each of the first and second ports, and electrically coupled to each of the plurality of first and second bit lines; The first and second amplifiers include first and second amplifier circuits that amplify the voltages transmitted to the first and second bit lines, respectively, based on the amplification permission signal, and amplify and execute data reading. An amplification control circuit for controlling activation of the amplification circuit of the second port based on a read circuit, an amplification permission signal for the amplification circuit of the second port, and a comparison result of the row address comparator; And a read data selection circuit for selecting one of the data signals, the voltages of which have been amplified by the first and second amplifier circuits, as read data from the second port.

  The semiconductor memory device according to claim 2 is the semiconductor memory device according to claim 1, wherein the comparison result by the row address comparator is a row address of data respectively input to the first port and the second port. Are in agreement, the amplification control circuit inactivates the amplification circuit of the second port, and the read data selection circuit transmits the data amplified by the first amplification circuit to the second port. Is selected as output data from.

  According to a third aspect of the present invention, there is provided a semiconductor memory device including a flip-flop circuit for setting the first and second storage nodes to one and the other of the ground potential and the power supply potential in accordance with stored data, and a corresponding first A first gate transistor having a gate electrically coupled to one word line and electrically coupling between the corresponding first bit line and the flip-flop circuit; and a corresponding second A memory cell having a gate electrically coupled to the word line and a second gate transistor for electrically coupling between the corresponding second bit line and the flip-flop circuit; A plurality of memory cells arranged on a matrix, and a plurality of first and second word lines provided corresponding to the memory cell rows, respectively, and corresponding to the memory cell columns; Respectively corresponding to the memory cell array including a plurality of first and second bit lines, first and second ports capable of transmitting and receiving input / output signals independently of each other, and the first and second ports. First and second row decoders, each of which outputs a memory cell row selection instruction in accordance with each inputted address, and row addresses of data inputted to the first port and the second port, respectively. A row address comparator to be compared and provided corresponding to each of the first and second ports, electrically coupled to the plurality of first and second bit lines, respectively, and to an inputted write data signal First and second write circuits for executing data writing for transmitting a corresponding voltage to the first and second bit lines based on a write enable signal, and the first port and the second port A write selection control circuit that generates a selection signal based on a write permission signal and a comparison result of the row address comparator, and the first signal based on the selection signal generated by the write selection control circuit A write data selection circuit that selects one of the write data input to the port and the second port, and a write control circuit that controls activation of the write circuit of the first port It is characterized by that.

  According to a fourth aspect of the present invention, there is provided a semiconductor memory device including a flip-flop circuit for setting the first and second storage nodes to one and the other of the ground potential and the power supply potential in accordance with stored data, and a corresponding first A first gate transistor having a gate electrically coupled to one word line and electrically coupling between the corresponding first bit line and the flip-flop circuit; and a corresponding second A memory cell having a gate electrically coupled to the word line and a second gate transistor for electrically coupling between the corresponding second bit line and the flip-flop circuit; A plurality of memory cells arranged on a matrix, and a plurality of first and second word lines provided corresponding to the memory cell rows, respectively, and corresponding to the memory cell columns; Respectively corresponding to the memory cell array including a plurality of first and second bit lines, first and second ports capable of transmitting and receiving input / output signals independently of each other, and the first and second ports. First and second row decoders, each of which outputs a memory cell row selection instruction in accordance with each inputted address, and row addresses of data inputted to the first port and the second port, respectively. A row address comparator for comparison, provided corresponding to each of the first and second ports, and electrically coupled to the plurality of first and second bit lines, respectively, and the first and second bit lines Includes first and second amplifier circuits that amplify the voltage transmitted to each based on the amplification permission signal, execute data reading, and write permission for the voltage corresponding to the input write data signal First and second read / write circuits for performing data writing to be transmitted to the first and second bit lines based on the signal, an amplification enable signal for the amplifier circuit of the second port, and the row address One of an amplification control circuit that controls activation of the amplification circuit of the second port based on the comparison result of the comparator, and a data signal in which the voltage is amplified by the first and second amplification circuits, respectively. Is selected as read data from the second port, a write enable signal for the first port and the second port, and a comparison result of a row address comparator. One of write data input to the first port and the second port is generated based on a write selection control circuit to be generated and a selection signal generated by the write selection control circuit. A write data selection circuit to be selected and a read / write control circuit for controlling activation of the read / write circuit of the first port are provided.

  According to the first aspect of the present invention, any one of the amplification control circuit that controls the activation of the amplification circuit of the second port, and the data signal in which the voltage is amplified by the first and second amplification circuits, respectively. And a read data selection circuit for selecting one of them as read data from the second port, so that the read data is output from the second port even if the operation of the amplifier circuit of the second port is inactivated. Therefore, power consumption can be reduced. As a result, it is possible to solve the problem that occurs when simultaneous access is performed from two ports to the same address.

  According to the second aspect of the present invention, when the row addresses of the data respectively input to the first port and the second port match, the data is amplified from the second port by the first amplifier circuit. Data can be output. As a result, there is an effect that desired read data is output without operating the amplifier circuit of the second port.

  According to the third aspect of the present invention, the write selection control circuit that generates the selection signal based on the write permission signals of the first port and the second port and the comparison result of the row address comparator, A write data selection circuit for selecting one of the write data input to the first port and the second port based on the selection signal, and activation of the write circuit of the first port And a write control circuit for controlling the second port, even if the second port is prioritized at the time of redundant writing to the same address in the first port and the second port, Data can be written from the first port. As a result, it is possible to solve the problem that occurs when simultaneous access is performed from two ports to the same address.

  According to the fourth aspect of the present invention, any one of the amplification control circuit that controls the activation of the amplification circuit of the second port, and the data signal in which the voltage is amplified by the first and second amplification circuits, respectively. And a read data selection circuit for selecting one of them as read data from the second port, so that the read data is output from the second port even if the operation of the amplifier circuit of the second port is inactivated. Therefore, power consumption can be reduced. A write selection control circuit for generating a selection signal based on a write enable signal for the first port and the second port and a comparison result of the row address comparator; and A write data selection circuit for selecting one of the write data input to one port and the second port; and a read / write control circuit for controlling activation of the read / write circuit of the first port; Therefore, even when the second port is prioritized at the time of redundant writing to the same address in the first port and the second port, the write data of the second port is transferred from the first port, Can be written. As a result, it is possible to solve the problem that occurs when simultaneous access is performed from two ports to the same address.

[First Embodiment]
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing a schematic configuration of a semiconductor memory device 10 according to the present embodiment.

  The semiconductor memory device 10 according to the present embodiment includes memory cells MC0 to MCm-1, a row decoder ROWDECA, a sense amplifier (amplifier circuit) SAA, and a write driver (peripheral circuits for the port A that is the first port). Read circuit) WDA, row decoder ROWDECB which is a peripheral circuit for port B which is the second port, sense amplifier (amplifier circuit) SAB, write driver (read circuit) WDB, and output selector circuit (read data selection circuit) It comprises a MUX, a sense amplifier enable control circuit (amplification control circuit) ANDS, and a row address comparator RAC.

  In the present embodiment, as an example, memory cells MC0 to MCm-1 shown in FIG. 2 are used. The memory cell MC includes a flip-flop circuit FF including load transistors P1 and P2 and driver transistors N1 and N2, access transistors N3 and N4 for the port A, and access transistors N5 and N6 for the port B. As an example, the transistors P1 and P2 are P-channel MOS transistors, and the transistors N1 to N6 are N-channel MOS transistors.

  Transistor P1 is arranged between power supply voltage VDD and storage node Nd1, and has its gate electrically coupled to storage node Nd2. Transistor N1 is arranged between storage node Nd1 and ground voltage GND, and has its gate electrically coupled to storage node Nd2. Transistor P2 is arranged between power supply voltage VDD and storage node Nd2, and has its gate electrically coupled to storage node Nd1. Transistor N2 is arranged between storage node Nd2 and ground voltage GND, and has its gate electrically coupled to storage node Nd1. Transistor N3 is arranged between storage node Nd1 and bit line BLA, and has its gate electrically coupled to word line WLA. Transistor N4 is arranged between storage node Nd2 and bit line BLA #, and has its gate electrically coupled to word line WLA. Transistor N5 is arranged between storage node Nd1 and bit line BLB, and has its gate electrically coupled to word line WLB. Transistor N6 is arranged between storage node Nd2 and bit line BLB #, and has its gate electrically coupled to word line WLB.

  Data writing and reading are performed by turning on the transistors N3 and N4 in response to the activation of the word line WLA or the word line WLB ("H" level) or turning on the transistors N5 and N6, and the storage nodes Nd1 and Nd1. This is executed by electrically coupling the bit lines BLA and BLA # or the bit lines BLB and BLB #.

  The storage node Nd1 and the storage node Nd2 have the power supply voltage VDD corresponding to the “H” level of the data signal and the ground voltage GND corresponding to the “L” level of the data signal in accordance with the data level held in the memory cell MC. One and the other are combined.

  In this embodiment, m rows of memory cells are arranged in one column. However, the present invention is not limited to this. For example, m rows of memory cells may be arranged in a plurality of columns.

  In this embodiment, as an example, a row decoder ROWDECB shown in FIG. 3 is used. In this embodiment, the case where the number of bits of the row address signal is i bits is shown.

  The row address comparator RAC is an XOR circuit that performs a coincidence comparison for each bit value of the row address AA of the port A and the row address AB of the port B, and a negative logic input AND circuit (NOR circuit) that generates a logical product of the outputs. , Composed of NAND circuits. When the row address AA and the row address AB are all the same bit value, the row address comparator output signal RACO is at the “L” level.

  Write drivers WDA and WDB respond to external write enable signals WEA and WEB, respectively, and at the time of data writing, voltage levels corresponding to write data DIA and DIB are applied to bit lines BLA, BLA # or BLB, BLB #. introduce. At the time of data reading, the data signal transmitted to the bit lines BLA, BLA # or BLB, BLB # is amplified by the sense amplifiers SAA, SAB and output as read data DOA, DOB. The sense amplifier SAA operates in response to an external sense amplifier enable signal (amplification enable signal) SEA, and the sense amplifier SAB operates in response to an output signal of the sense amplifier enable control circuit ANDS.

  The sense amplifier enable control circuit ANDS turns on and off the sense amplifier SAB based on the external sense amplifier enable signal (amplification permission signal) SEB and the row address decoder ROWDECB. In this embodiment, an AND circuit is used as an example, but the present invention is not limited to this.

  The output selector circuit MUX switches the read data DOB 'output from the port B to either the read data DOA or the read data DOB.

  Next, the operation of the semiconductor memory device 10 of the present embodiment will be described in detail with reference to FIG.

  When the row address of port A and port B are different, the output signal RACO of the row address comparator RAC is at “H” level. In port A, the selected word line WLA and bit lines BLA and BLA # are used for write and read operations. In the port B, the word line WLB and the bit lines BLB and BLB # are selected and used. Even when only one of the ports operates, the output signal RACO of the row address comparator RAC becomes “H” level. In this case, each port operates in the same manner as a single port SRAM.

  On the other hand, when the row addresses of the port A and the port B are the same, the output signal RACO of the row address comparator RAC becomes “L” level. In this case, the row decoder ROWDECB of the port B does not activate the word line WLB, and activates only the word line WLA selected by the row decoder ROWDECA of the port A. The output selector circuit MUX selects the read data DOA amplified by the sense amplifier SAA of the port A as read data DOB 'from the port B. Further, the sense amplifier enable control circuit ANDS turns off the sense amplifier SAB of the port B. As a result, the readout system circuit of port B is turned off.

  That is, only the word line WLA of the port A is activated, the read operation of the port A is executed using the bit lines BLA and BLA #, and then the read data DOB ′ output from the port B is output by the output selector circuit MUX. As a result, the read data DOA amplified by the sense amplifier SAA of the port A is selected. Therefore, the same data as the read data DOA output from port A is output from port B.

  As described above, in the memory cell MC, even if the gate width of the driver transistor is set to be equal to that of the single port SRAM, a noise margin can be ensured as in the conventional example, so that the area of the memory cell can be reduced. It becomes.

  Further, since the operation of the sense amplifier SAB of the port B is turned off, no power is consumed. When the operation of the sense amplifier SAB is simply turned off, for example, in the conventional semiconductor memory device 100, the sense amplifier SAB is disposed between the bit line shifter circuit BLS and the output terminal of the port B. Therefore, there is a problem that the read data DOB cannot be output from the port B. In this embodiment, the read data DOA amplified by the sense amplifier SAA of the port A is read from the port B and read data DOB ′. Therefore, when the row addresses of the port A and the port B are the same, desired read data can be obtained even if the operation of the sense amplifier SAB of the port B is turned off.

  Thus, in the semiconductor memory device 10 of the present embodiment, it is possible to secure a noise margin, reduce the memory cell area, and reduce the power consumption in the sense amplifier SAB of the port B that is the second port. .

  For convenience of explanation, in FIG. 1, the sense amplifier SAA and the write driver WDA are separated from the sense amplifier SAB and the write driver WDB, but in actuality, they are arranged adjacent to each other. FIG. 4 shows an image of an actual layout arrangement of the semiconductor memory device 10. FIG. 4 shows a configuration in which n memory cell arrays CELL_ARRAY including memory cells MC0 to MCm−1 are arranged. In FIG. 4, the row address comparator RAC, the sense amplifier enable control circuit ANDS, and the output selector circuit MUX are not shown, and the external sense amplifier enable signals SEA and SEB and the external write are omitted for simplification. Control circuits CNTLA and CNTLB are described as those for controlling the enable signals WEA and WEB. Accordingly, in FIG. 1, since the wiring for outputting the read data DOA amplified by the sense amplifier SAA from the port B as the read data DOB ′ is routed from the port A to the port B, the read by the area penalty and the wiring resistance is performed. Although there seems to be a problem of a decrease in speed, the sense amplifier SAA and the write driver WDA and the sense amplifier SAB and the write driver WDB are actually adjacent to each other, so that no problem occurs.

  Although this embodiment is an example when applied to a dual-port SRAM including port A and port B, the present embodiment is not limited to this and can also be applied to a multi-port SRAM having a plurality of ports.

  Further, when the sense amplifier enable control circuit ANDS and the output selector circuit MUX are arranged on the port A side instead of the boat B side, and the row addresses of the port A and the port B are the same, the operation of the sense amplifier SAA of the port A May be configured to reduce the power consumption of the sense amplifier SAA.

  As described above, according to the semiconductor memory device 10 of the present embodiment, the output selector circuit that selects the read data DOA amplified by the sense amplifier SAA and the read data DOB amplified by the sense amplifier SAB. Since the sense amplifier enable control circuit ANDS for controlling the activation of the sense amplifier SAB based on the MUX and the external sense amplifier enable signal SEB of the port B and the output signal RACO of the row address comparator RAC is provided, it is amplified by the sense amplifier SAA The read data DOA thus outputted can be output as read data DOB ′ from the port B. When the row addresses of the port A and the port B are the same, the operation of the sense amplifier SAB of the port B can be turned off. Therefore, power consumption can be reduced. As a result, it is possible to solve a problem that occurs when simultaneous access is performed from the two ports to the same address.

[Second Embodiment]
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 5 is a circuit diagram showing a schematic configuration of the semiconductor memory device 20 according to the present embodiment. Since the present embodiment has substantially the same configuration and operation as the first embodiment, the same parts are denoted by the same reference numerals and detailed description thereof is omitted.

  The semiconductor memory device 20 of the present embodiment is similar to the semiconductor memory device 10 of the first embodiment in that the write data DIA ′ and the write data DIA ′ input to the write driver WDA of the port A that is the first port are written. Control for generating a selection signal based on selector circuit (write data selection circuit) MUXD selected from embedded data DIB, external write enable signal (write enable signal) WEA, WEB and output signal RACO of row address comparator RAC A circuit (write selection control circuit) ANDD and a write enable control circuit (write control circuit, read / write control circuit) MUXE, ANDE for controlling activation of the write driver WDA are provided. In this embodiment, the write drivers WDA and WDB correspond to the write circuit according to claim 3 and the read / write circuit according to claim 4.

  Next, the operation of the semiconductor memory device 20 of the present embodiment will be described in detail with reference to FIG.

  Since the operation for reading data from the memory cell MC is the same as that of the semiconductor memory device 10 of the first embodiment, the description thereof is omitted here. Therefore, also in the semiconductor memory device 20 of the present embodiment, the same data as the read data DOA output from the port A is output from the port B. In the memory cell MC, the gate width of the driver transistor is set to be equal to that of the single port SRAM. Since the noise margin can be ensured even when set to, the area of the memory cell MC can be reduced. Further, since the operation of the sense amplifier SAB of the port B is turned off, no power is consumed.

  Next, the write operation will be described in detail. When writing to memory cells having different addresses from the port A and the port B, the operation is performed in the same manner as usual, and thus the description thereof is omitted here. On the other hand, when writing is repeated from the port A and the port B to the memory cell MC of the same address, a priority signal is supplied to the port to be prioritized from an external arbitration circuit (not shown) that adjusts the overlapping writing. The When port A is prioritized, external write enable signal WEA becomes active, selected word line WLA is activated by row decoder ROWDECA, and write data DIA ′ (DIA) is written to bit line by write driver WDA. Drive to BLA and BLA # to write data to memory cell MC.

  On the other hand, when port B has priority, the external write enable signal WEB becomes active. First, the word line WLA of the port A is activated. Since the output signal RACO of the row address comparator RAC is at “L” level, the row decoder ROWDECB of the port B does not activate the word line WLB, but activates only the word line WLA selected by the row decoder ROWDECA of the port A. . Next, the write driver control circuit MUXE, ANDE activates the write driver WDA, and the selector circuit MUXD, the data selection control circuit ANDD writes not the port A write data DIA but the port B write data. Data DIB is selected as write data DIA ′ of write driver WDA. Finally, the data is driven to the bit lines BLA and BLA # by the write data DIA 'of the write driver WDA, and the data is written into the memory cell MC.

  Thus, in the present embodiment, even when port B has priority and the word line WLB is not activated, the write data DIB can be written from the port A to the memory cell MC.

  As described above in detail, according to semiconductor memory device 20 of the present embodiment, write data DIA ′ to be input to write driver WDA of port A is selected from write data DIA and write data DIB. Selector circuit MUXD, control circuit ANDD for generating a selection signal based on external write enable signals WEA, WEB and output signal RACO of row address comparator RAC, and write enable control circuit for controlling activation of write driver WDA Since MUXE and ANDE are provided, even if port B is prioritized by the arbitration circuit when the same address is written to port A and port B, write data DIB of port B is written from port A to memory cell MC. Can be included. As a result, it is possible to solve a problem that occurs when simultaneous access is performed from the two ports to the same address.

  Although the semiconductor memory device 20 of the present embodiment is provided with the output selector circuit MUX and the sense amplifier enable control circuit ANDS, the selector circuit MUXD, the control circuit ANDD, and the write circuit are not provided even if they are not provided. By providing the enable control circuits MUXE and ANDE, similarly, even if the port B is prioritized by the arbitration circuit when the same address is written to the same address in the port A and the port B, the write data from the port A to the port B DIB can be written into the memory cell MC. As a result, it is possible to solve a problem that occurs when simultaneous access is performed from the two ports to the same address.

1 is a circuit diagram showing a schematic configuration of a semiconductor memory device according to a first embodiment of the present invention. It is a circuit diagram which shows schematic structure of an example of a memory cell. It is a circuit diagram which shows schematic structure of an example of a row address comparator. 2 is a circuit diagram for explaining an image of an actual layout arrangement of the semiconductor memory device according to the first embodiment of the present invention; FIG. FIG. 5 is a circuit diagram showing a schematic configuration of a semiconductor memory device according to a second embodiment of the present invention. It is a circuit diagram which shows schematic structure of the conventional semiconductor memory device.

Explanation of symbols

10, 20 Semiconductor memory device ANDD Control circuit ANDE, MUXE Write enable control circuit ANDS Sense amplifier enable control circuit MC Memory cell MUX Output selector circuit MUXD Selector circuit RAC Row address comparator RODECA, ROWDECB Row decoder SAA, SAB Sense amplifiers WDA, WDB Write driver

Claims (4)

A flip-flop circuit for setting the first and second storage nodes to one and the other of the ground potential and the power supply potential in accordance with the data to be stored, and the corresponding first word line are electrically coupled A first gate transistor having a gate and electrically coupled between the corresponding first bit line and the flip-flop circuit; and a gate electrically coupled to the corresponding second word line A memory cell including a second gate transistor for electrically coupling between the corresponding second bit line and the flip-flop circuit;
A plurality of memory cells arranged on a matrix, a plurality of first and second word lines provided corresponding to the memory cell rows, and a plurality provided corresponding to the memory cell columns, respectively; A memory cell array including the first and second bit lines;
First and second ports capable of transmitting and receiving input / output signals independently of each other;
First and second row decoders provided corresponding to the first and second ports, respectively, each for outputting a memory cell row selection instruction according to an input address;
A row address comparator for comparing row addresses of data respectively input to the first port and the second port;
Voltages respectively provided corresponding to the first and second ports and electrically coupled to the plurality of first and second bit lines, respectively, and transmitted to the first and second bit lines, respectively. First and second read circuits that perform data read, including first and second amplifier circuits that amplify based on the amplification permission signal;
An amplification control circuit that controls activation of the amplification circuit of the second port based on an amplification permission signal for the amplification circuit of the second port and a comparison result of the row address comparator;
A read data selection circuit that selects any one of the data signals whose voltages are amplified by the first and second amplifier circuits as read data from the second port;
A semiconductor memory device comprising:   When the comparison result by the row address comparator indicates that the row addresses of the data respectively input to the first port and the second port match, the amplification control circuit performs the amplification of the second port. 2. The semiconductor memory device according to claim 1, wherein the read data selection circuit selects the data amplified by the first amplification circuit as output data from the second port. A flip-flop circuit for setting the first and second storage nodes to one and the other of the ground potential and the power supply potential in accordance with the data to be stored, and the corresponding first word line are electrically coupled A first gate transistor having a gate and electrically coupled between the corresponding first bit line and the flip-flop circuit; and a gate electrically coupled to the corresponding second word line A memory cell including a second gate transistor for electrically coupling between the corresponding second bit line and the flip-flop circuit;
A plurality of memory cells arranged on a matrix, a plurality of first and second word lines provided corresponding to the memory cell rows, and a plurality provided corresponding to the memory cell columns, respectively; A memory cell array including the first and second bit lines;
First and second ports capable of transmitting and receiving input / output signals independently of each other;
First and second row decoders provided corresponding to the first and second ports, respectively, each for outputting a memory cell row selection instruction according to an input address;
A row address comparator for comparing row addresses of data respectively input to the first port and the second port;
Provided corresponding to each of the first and second ports, electrically coupled to the plurality of first and second bit lines, respectively, and allowed to write a voltage corresponding to the input write data signal First and second write circuits for performing data writing to be transmitted to the first and second bit lines based on a signal;
A write selection control circuit for generating a selection signal based on a write enable signal of the first port and the second port and a comparison result of the row address comparator;
A write data selection circuit that selects one of the write data input to the first port and the second port based on a selection signal generated by the write selection control circuit;
A write control circuit that controls activation of the write circuit of the first port;
A semiconductor memory device comprising: A flip-flop circuit for setting the first and second storage nodes to one and the other of the ground potential and the power supply potential in accordance with the data to be stored, and the corresponding first word line are electrically coupled A first gate transistor having a gate and electrically coupled between the corresponding first bit line and the flip-flop circuit; and a gate electrically coupled to the corresponding second word line A memory cell including a second gate transistor for electrically coupling between the corresponding second bit line and the flip-flop circuit;
A plurality of memory cells arranged on a matrix, a plurality of first and second word lines provided corresponding to the memory cell rows, and a plurality provided corresponding to the memory cell columns, respectively; A memory cell array including the first and second bit lines;
First and second ports capable of transmitting and receiving input / output signals independently of each other;
First and second row decoders provided corresponding to the first and second ports, respectively, each for outputting a memory cell row selection instruction according to an input address;
A row address comparator for comparing row addresses of data respectively input to the first port and the second port;
Voltages respectively provided corresponding to the first and second ports and electrically coupled to the plurality of first and second bit lines, respectively, and transmitted to the first and second bit lines, respectively. Includes first and second amplifier circuits that amplify based on the amplification permission signal, execute data reading, and apply a voltage corresponding to the input write data signal based on the write permission signal. First and second read / write circuits for performing data writing to be transmitted to two bit lines;
An amplification control circuit that controls activation of the amplification circuit of the second port based on an amplification permission signal for the amplification circuit of the second port and a comparison result of the row address comparator;
A read data selection circuit that selects any one of the data signals whose voltages are amplified by the first and second amplifier circuits as read data from the second port;
A write selection control circuit for generating a selection signal based on a write permission signal of the first port and the second port and a comparison result of a row address comparator;
A write data selection circuit that selects one of the write data input to the first port and the second port based on a selection signal generated by the write selection control circuit;
A read / write control circuit that controls activation of the read / write circuit of the first port;
A semiconductor memory device comprising:

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