JP2008289716A - Illegal operation prevention device for game machine, its method, and game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an illegal operation prevention device for a game machine, capable of preventing the game machine from performing illegal operation on the basis of an illegal program when the program of the game machine is illegally altered. <P>SOLUTION: A program PRGM of a ROM 13 is written to a monitoring ROM 37 in advance as a collation program. In an idle mode after the execution of the program PRGM in a main CPU 17, coincidence between the program PRGM stored in the ROM 13 and the collation program PRGMC stored in the monitoring ROM 37 is verified by a monitoring CPU 39. When the monitoring CPU 39 detects noncoincidence, it closes a bus gate 9 on a data bus 6. Thus, a game processing circuit 5 does not execute a command issued by the main CPU 17. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a gaming machine unauthorized operation preventing apparatus, a method thereof, and a gaming machine for preventing unauthorized operation of a gaming machine due to execution of an unauthorized program.

Conventionally, game machines such as pachinko machines and slot machines have built-in microcomputers for control, and various controls such as the rotation control of the electric accessory and the spinning cylinder are performed under the control of the microcomputer.
A microcomputer program used in such a gaming machine is written by a development manufacturer in a ROM (Read Only Memory) in the microcomputer.
By the way, gaming machines such as pachinko machines and slot machines cannot be sold unless they are certified and certified according to the rules based on the customs business law. Therefore, it is necessary for a gaming machine incorporating a microcomputer to pass a formal test of a predetermined association.

JP 2002-306806 A

However, even if the above-mentioned gaming machine is modified after the formal test is passed, it is difficult to find it and there is a possibility that it will be handled as a regular gaming machine.
If an unauthorized gaming machine with a modified program is used in this way, it will cause an unexpected disadvantage to the player, and the trust of the development manufacturer or distributor handling the gaming machine that has passed the formal test will be lost. End up.

  The present invention has been made in view of such circumstances, and an object thereof is to prevent a gaming machine from performing an illegal operation based on the unauthorized program when the program of the gaming machine is illegally modified. An object of the present invention is to provide a gaming machine illegal operation preventing apparatus and method, and a gaming machine.

  In order to achieve the above-described object, the gaming machine unauthorized operation preventing apparatus according to the first aspect of the invention is an illegal gaming machine that performs a gaming operation by controlling a processing circuit based on a program stored in a first memory. A gaming machine illegal operation preventing apparatus for preventing operation, wherein the program read from the first memory is written as a comparison program in an initial operation before controlling the game operation. And a command issued by the processing circuit when a mismatch is detected between the program read from the first memory and the comparison program read from the second memory after the initial operation. A control circuit for prohibiting the game operation based on the above or the operation of the processing circuit executing the program stored in the first memory.

In the gaming machine illegal operation preventing apparatus according to the first aspect of the invention, in the initial operation before controlling the game operation, the program read from the first memory is stored in the second memory as a comparison program. Written.
Then, after the initial operation, the control circuit detects a match / mismatch between the program read from the first memory and the comparison program read from the second memory.
When the control circuit detects the inconsistency, the game operation based on the command issued by the processing circuit or the operation of the processing circuit executing the program stored in the first memory is prohibited. To do.
Thereby, it is possible to prevent an illegal play operation from being performed by the control of the processing circuit based on the unauthorized program.

  The gaming machine unauthorized operation preventing apparatus according to the second aspect of the invention is a game in which a game operation is performed by controlling a processing circuit based on a program read from a volatile memory that retains a memory state on condition that power is supplied. A gaming machine unauthorized operation preventing apparatus for preventing unauthorized operation of a machine, wherein a modification detection means for detecting modification of a program stored in the volatile memory, and when the modification detection means detects the modification, And a control circuit for stopping the power supply to the volatile memory.

In the gaming machine unauthorized operation preventing apparatus according to the second aspect of the invention, the alteration detecting means detects whether or not the program stored in the volatile memory is altered.
Then, the control circuit stops the power supply to the volatile memory when the modification detection unit detects the modification.
Thereby, the illegal program stored in the non-volatile memory is erased, and the control circuit can be prevented from controlling the play operation based on the illegal program.

  A gaming machine according to a third aspect of the invention provides a game processing means for executing various game operations based on an input command, a main processing circuit for outputting the command to the game processing means, and an illegality of the game processing means. A monitoring circuit for preventing operation, and the main processing circuit operates based on the first memory for storing a program and the program read from the first memory, and controls the game operation before In the initial operation, the program read from the first memory is output to the monitoring circuit, and the program read from the first memory is output to the monitoring circuit at a predetermined timing after the initial operation. And the monitoring circuit writes the program input from the main processing circuit as a comparison program in the initial operation. When the mismatch between the second memory to be read and the program read from the first memory after the initial operation and the comparison program read from the second memory is detected, the processing circuit A second control circuit for prohibiting the game operation based on the issued command or the operation of the processing circuit executing the program stored in the first memory.

  A gaming machine according to a fourth aspect of the invention includes a volatile memory that retains a memory state on condition that power is supplied, and a main processing circuit that controls a game operation based on a program read from the volatile memory. A game having a modification detection unit for detecting a modification of a program stored in the volatile memory, and a monitoring circuit for stopping the power supply to the volatile memory when the modification detection unit detects the modification. Machine.

  A gaming machine unauthorized operation prevention method according to a fifth aspect of the invention is a gaming machine unauthorized operation prevention method for preventing an unauthorized operation of a gaming machine performing a gaming operation by controlling a processing circuit based on a program stored in a first memory. An initial step of reading the program from the first memory and writing it as a comparison program into a second memory before controlling the play operation, and after the initial step, from the first memory A comparison step for determining whether or not the read program and the comparison program read from the second memory match, and when it is determined that there is a mismatch in the comparison step, The game operation based on a command issued by the processing circuit or the operation of the processing circuit executing the program stored in the first memory is prohibited. And a stop process.

  According to a sixth aspect of the present invention, there is provided a gaming machine illegal operation preventing method in which a game operation is performed by controlling a processing circuit based on a program read from a volatile memory that retains a memory state on condition that power is supplied. A gaming machine unauthorized operation prevention method for preventing unauthorized operation of a machine, wherein a modification detection step for detecting modification of a program stored in the volatile memory, and when the modification is detected in the modification detection step, A power supply stopping step of stopping the power supply to the volatile memory.

According to the present invention, when a game machine program is illegally altered, a gaming machine illegal operation preventing apparatus and method and game machine for preventing the gaming machine from performing illegal operations based on the unauthorized program. Can be provided.

Hereinafter, a gaming machine according to an embodiment of the present invention will be described.
In this specification, the correspondence relationship between the configuration requirements of the present invention and the embodiments described in the specification or the drawings is illustrated. This description is intended to clarify that the embodiments supporting the present invention are described in the specification or the drawings. Therefore, the configuration requirements of the present invention are not limited to the configuration of the present embodiment associated therewith.
The gaming machine of this embodiment described below is, for example, a pachinko machine or a slot machine.

<First Embodiment>
FIG. 1 is a hardware configuration diagram of a signal processing device 10 of a gaming machine according to the first embodiment of the present invention.
1, the ROM 13 is an example of the first memory of the present invention, the monitoring ROM 37 is an example of the second memory of the present invention, the main CPU 17 is an example of the processing circuit of the present invention, and the monitoring CPU 39 Is an example of the control circuit of the present invention.
As shown in FIG. 1, the signal processing device 10 has a configuration in which, for example, an input unit 3, a game processing circuit 5, a main processing circuit 11, and a monitoring circuit 31 are connected via a data bus 6.
Bus gates 7 and 9 are arranged between the main processing circuit 11 and the monitoring circuit 31 on the data bus 6.

Further, the signal processing apparatus 10 includes a monitoring ROM 37 that stores the program PRGM input from the main processing circuit 11 by the monitoring circuit 31 in the initial operation.
The bus gate 9, the monitoring circuit 31, and the monitoring ROM 37 are accommodated in the shield case 62. The shield case 62 is a tamper-resistant container that is physically difficult to disassemble and that is difficult to obtain operation information and data of circuits housed therein.
Further, the signal processing device 10 includes an address decoder 21 that generates an address for designating an output destination of data or the like sent from the main processing circuit 11 to the data bus 6.
In the signal processing device 10, the command issued by the main processing circuit 11 is output to the game processing circuit 5 via the data bus 6, and the game processing circuit 5 executes the command to control the rotation of the electric accessory or the spinning cylinder. Is controlled.
The input unit 3 inputs a signal from an operation means operated by the player according to the progress of the game or an operation means operated by the administrator. The bus gate 7 is opened and closed by the main processing circuit 11 when a predetermined condition is satisfied, for example.

[Main processing circuit 11]
As shown in FIG. 1, the main processing circuit 11 includes a ROM 13 and a RAM (Random
An access memory (15) and a main CPU (central processing unit) 17 are connected to the data bus 6.
The ROM 13 stores an (application) program PRGM executed by the main processing circuit 11. In the present embodiment, the term “program” includes data necessary for executing the program code in addition to the program code.
The RAM 15 stores various data used for processing of the main CPU 17.
The main CPU 17 reads out and executes the program PRGM from the ROM 13 and generates various commands for controlling the game processing circuit 5. The main CPU 17 comprehensively controls the operation of the gaming machine according to the command.
The main CPU 17 sends the generated command to the data bus 6. In the signal processing device 10, as described later, when an unauthorized modification of the program PRGM stored in the ROM 13 is detected in the monitoring ROM 37, the bus gate 9 is closed and sent from the main CPU 17 to the data bus 6. The command is not acquired by the game processing circuit 5. Thereby, it is possible to prevent the game processing circuit 5 from performing an illegal operation based on an unauthorized program.

[Monitoring circuit 31]
As shown in FIG. 1, the monitoring circuit 31 includes a ROM 33, a RAM 35, and a monitoring CPU 39.
The ROM 33 stores a program PRGS executed by the monitoring circuit 31.
The RAM 35 stores various data used for processing of the monitoring CPU 39.
The monitoring CPU 39 reads the program PRGS from the ROM 33 and executes it, and performs the monitoring operation of the main processing circuit 11.

The monitoring CPU 39 verifies the validity of the ROM 13 of the main processing circuit 11 and turns off the bus gate 9 when an illegality is detected. As a result, the path on the data bus 6 between the main processing circuit 11 and the game processing circuit 5 is disconnected, and the game processing circuit 5 inputs a command issued by the main processing circuit 11 based on an illegal program. Can be prevented.
Specifically, the monitoring CPU 39 writes the program PRGM input in advance from the main processing circuit 11 into the monitoring ROM 37 as the comparison program PRGC.
Then, the monitoring CPU 39 compares the program PRGM stored in the ROM 13 input from the main processing circuit 11 at a predetermined timing with the comparison program PRGC read from the monitoring ROM 37, and confirms its validity (match). Validate.

Hereinafter, an operation example of the signal processing apparatus 10 illustrated in FIG. 1 will be described.
FIG. 2 is a flowchart for explaining an operation example of the signal processing apparatus 10 shown in FIG.
First, the operation of the main processing circuit 11 will be mainly described.
The main CPU 17 of the main processing circuit 11 performs initialization processing (step ST11).
Next, the main CPU 17 performs random number generation processing and writes the generated random number a in the RAM 15 (step ST12).
Next, the main CPU 17 reads the random number a from the RAM 15 and outputs it to the monitoring circuit 31 via the data bus 6 (step ST13). At this time, the main CPU 17 outputs an address designating the monitoring circuit 31 to the address decoder 21.

Further, the main CPU 17 calculates an exclusive OR (XOR) of the program PRGM read from the ROM 13 and the random number a read from the RAM 15, and writes the resulting program PRGMX in the RAM 15.
Then, the main CPU 17 outputs the program PRGMX from the RAM 15 to the monitoring circuit 31 via the data bus 6 (step ST14). At this time, the main CPU 17 outputs an address designating the monitoring circuit 31 to the address decoder 21.

Next, the main CPU 17 executes the program PRGM read from the ROM 13 (step ST15).
The main CPU 17 generates a command in the course of executing the program PRGM and outputs it to the data bus 6. At this time, the main CPU 17 outputs an address designating the game processing circuit 5 to the address decoder 21.

Next, in the idle mode after the execution of the program PRGM, the main CPU 17 calculates an exclusive OR (XOR) of the program PRGM read from the ROM 13 and the random number a read from the RAM 15, and the program PRGMX as a result is calculated. Is output to the monitoring circuit 31 via the data bus 6 (step ST16). At this time, the main CPU 17 outputs an address designating the monitoring circuit 31 to the address decoder 21.
Thereafter, the main CPU 17 repeats the processes of steps ST15 and ST16 described above.
As described above, the main processing circuit 11 performs the processing of steps ST11 to ST14 as an initial operation at the time of activation, and then repeats the processing of steps ST15 and ST16.

Hereinafter, the operation of the monitoring circuit 31 will be described in association with the operation of the main processing circuit 11 described above.
The monitoring CPU 39 of the monitoring circuit 31 performs an initialization process (step ST21).
Next, the monitoring CPU 39 receives the random number a output from the main processing circuit 11 to the data bus 6 in step ST13 described above, and writes it into the RAM 35 (step ST22).

  Next, the monitoring CPU 39 receives the program PRGMX output from the main processing circuit 11 to the data bus 6 in step ST14 described above, and calculates the exclusive OR (XOR) of this and the random number a read from the RAM 35. The resulting program PRGM is written into the RAM 35 (step ST23). That is, the program PRGM is acquired (restored) by calculating again in the main processing circuit 11 the exclusive OR of the program PRGM and the random number a and the program PRGM and the random number a.

The monitoring CPU 39 determines whether or not the monitoring ROM 37 is in an initialization state. If the monitoring ROM 37 is in the initialization state, the process proceeds to step ST25, and if not, the process proceeds to step ST26 (step ST24).
When the monitoring ROM 37 is in the initialized state, the monitoring CPU 39 reads the program PRGM from the RAM 35 and writes it in the monitoring ROM 37 as a verification program PRGC (step ST25).

On the other hand, when the monitoring ROM 37 is not in the initialized state, the monitoring CPU 39 compares the verification program PRGC read from the monitoring ROM 37 with the program PRGM read from the RAM 35 (step ST26).
Next, the monitoring CPU 39 proceeds to step ST28 when it is determined as a result of the comparison in step ST26 that the two match, and proceeds to step ST32 otherwise (step ST27).
Next, the monitoring CPU 39 starts counting by a monitoring timer (not shown) (step ST28).

Next, the monitoring CPU 39 determines whether or not the program PRGMX has been received from the main processing circuit 11 and whether or not the monitoring timer has reached a predetermined threshold value.
When the monitoring CPU 39 determines that the program PRGMX has been received from the main processing circuit 11 in response to the above-described step ST16, the monitoring CPU 39 proceeds to step ST30, and the value of the monitoring timer reaches a predetermined threshold value ( If it is determined that a timeout has occurred, the process proceeds to step ST32 (step ST29).

When the monitoring CPU 39 determines that the program PRGMX has been received from the main processing circuit 11, the monitoring CPU 39 calculates the exclusive OR (XOR) of the received program PRGMX and the random number a read from the RAM 35. A certain program PRGM is written in the RAM 35 (step ST30).
The monitoring CPU 39 compares the program PRGM read from the RAM 35 with the verification program PRGC read from the monitoring ROM 37 (step ST31).
Then, the monitoring CPU 39 returns to step ST28 when determining that the values match in the comparison at step ST31, and proceeds to step ST32 otherwise.

  The monitoring CPU 39 closes the bus gate 9 shown in FIG. 1 when it is determined in steps ST27 and ST31 that they do not match or when it is determined in step ST29 that the value of the monitoring timer has reached a predetermined threshold value. Control is performed (step ST32). As a result, the path on the data bus 6 between the main processing circuit 11 and the game processing circuit 5 is disconnected, and the game processing circuit 5 inputs a command issued by the main processing circuit 11 based on an illegal program. Can be prevented.

As described above, according to the signal processing device 10, as shown in FIG. 2, in the idle mode after the execution of the program PRGM in the main CPU 17, the program PRGM stored in the ROM 13 and the monitoring ROM 37 are stored. The consistency with the verification program PRGMC is verified, and if not, the bus gate 9 on the data bus 6 is closed.
Thereby, it is possible to prevent the game processing circuit 5 from inputting and executing a command issued by the main processing circuit 11 based on an unauthorized program. That is, it is possible to prevent the gaming machine of this embodiment from operating based on an unauthorized program.
Further, in the signal processing device 10, in steps ST14 and ST16 shown in FIG. 2, the program PRGM is not output from the main processing circuit 11 to the monitoring circuit 31 via the data bus 6, but the program PRGM and the random number a are excluded. A program PRGMX which is a logical OR (XOR) is output. Therefore, it is possible to prevent the program PRGM from being illegally acquired by monitoring the data bus 6.

Second Embodiment
In the first embodiment described above, the case where the main CPU 17 closes the bus gate 9 on the data bus 6 that outputs a command to the game processing circuit 5 when the program PRGM executed by the main CPU 17 is illegally modified is illustrated. In the present embodiment, the main CPU 117 executes the program PRGM2 read from the ROM 113 to the SRAM 115, and when the fraud is detected, the main CPU 117 stops the power supply of the SRAM 115 by the power supply circuit 141 and erases the storage of the SRAM 115.

FIG. 3 is a hardware configuration diagram of the signal processing device 110 of the gaming machine according to the second embodiment of the present invention.
In FIG. 3, an SRAM 115 is an example of a nonvolatile memory according to the present invention, and a monitoring CPU 139 is an example of a modification detection unit and a control circuit.

As shown in FIG. 3, the signal processing device 110 has a configuration in which, for example, the input unit 3, the game processing circuit 5, the main processing circuit 111, and the monitoring circuit 131 are connected via the data bus 6.
The signal processing device 110 includes a monitoring ROM 137 that stores the program PRGM2 input from the main processing circuit 111 by the monitoring circuit 131 in the initial operation.
The monitoring circuit 131 and the monitoring ROM 137 are accommodated in the shield case 162.
In the signal processing device 110, the functions of the input unit 3, the game processing circuit 5, and the address decoder 21 are the same as those described in the first embodiment.

In addition, the signal processing device 110 includes a power supply circuit 141 that supplies power from the battery 43 to the components of the signal processing device 110.
In the signal processing device 110, when the monitoring circuit 131 detects falsification or the like of the program PRGM2 executed by the main CPU 117 of the main processing circuit 111, the power feeding circuit 141 controls the main processing circuit 111 under the control of the monitoring circuit 131. Power supply to the SRAM 115 is stopped. As a result, the unauthorized program stored in the SRAM 115 is automatically deleted, and the main CPU 117 can be prevented from executing the unauthorized program.

[Main processing circuit 11]
As shown in FIG. 3, the main processing circuit 111 includes a ROM 113, an SRAM (Static
Random Access Memory) 115 and main CPU 117, which are connected to the data bus 6.
The ROM 113 stores an (application) program PRGM2 executed by the main processing circuit 111. The ROM 113 is, for example, a nonvolatile memory.
The SRAM 115 stores various data used for processing of the main CPU 117.
The SRAM 115 is a volatile memory in which data is stored using a sequential circuit such as a flip-flop, and the stored contents are lost when the power supply (power) is not supplied from the power supply circuit 141.
Even when the signal processing device 110 is turned off, in a normal state, the power from the battery 43 is supplied to the SRAM 115 via the power supply circuit 141, and the data stored in the SRAM 115 is saved unless the battery runs out. .

The main CPU 117 reads out and executes the program PRGM2 from the SRAM 115, and generates various commands for controlling the game processing circuit 5. The main CPU 117 comprehensively controls the operation of the gaming machine by the command. The main CPU 117 sends the generated command to the data bus 6.
As described above, the main processing circuit 111 does not directly read and execute the program PRGM2 from the ROM 113, but reads and executes the program PRGM2 read from the ROM 113 to the SRAM 115.

[Monitoring circuit 131]
As shown in FIG. 3, the monitoring circuit 131 includes a ROM 133, a RAM 135, and a monitoring CPU 139.
The ROM 133 stores a program PRGS2 executed by the monitoring circuit 131.
The RAM 135 stores various data used for the processing of the monitoring CPU 137.
The monitoring CPU 139 reads and executes the program PRGS2 from the ROM 133, and performs the monitoring operation of the main processing circuit 111.
The monitoring CPU 139 verifies the validity of the program PRGM2 executed by the main processing circuit 111, and stops the power supply by the power supply circuit 141 to the SRAM 115 of the main processing circuit 111 when an illegality is detected. Thereby, it is possible to prevent the game processing circuit 5 from executing a command generated by the main processing circuit 111 based on an unauthorized program.

Hereinafter, an operation example of the signal processing apparatus 110 illustrated in FIG. 3 will be described.
FIG. 4 is a flowchart for explaining an operation example of the signal processing apparatus 110 shown in FIG. In FIG. 4, the processes denoted by the same reference numerals as those in FIG.

First, the operation of the main processing circuit 111 will be mainly described.
The main CPU 117 of the main processing circuit 111 performs initialization processing (step ST111).
Next, the main CPU 117 reads out the program PRGM2 from the ROM 113 and writes it in the SRAM 115 (step ST112).
At this time, for example, the main CPU 117 authenticates the administrator of the signal processing apparatus 110, reads the program PRGM2 from the ROM 113, and writes it in the SRAM 115 on the condition that the legitimacy of the administrator is authenticated.
For example, the authentication is performed using an IC card in which a manager stores a predetermined common key, performing encrypted communication with the main CPU 117 via the input unit 3, or using a password or the like. .

Next, the main CPU 117 performs random number generation processing and writes the generated random number a in the SRAM 115 (step ST113).
Next, the main CPU 117 reads the random number a from the SRAM 115 and outputs it to the monitoring circuit 131 via the data bus 6 (step ST114). At this time, the main CPU 117 outputs an address designating the monitoring circuit 131 to the address decoder 21.

Further, the main CPU 117 calculates an exclusive OR (XOR) of the program PRGM2 read from the SRAM 115 and the random number a read from the SRAM 115, and writes the resulting program PRGM2X in the SRAM 115.
Then, the main CPU 117 outputs the program PRGM2X from the SRAM 115 to the monitoring circuit 131 via the data bus 6 (step ST115). At this time, the main CPU 117 outputs an address designating the monitoring circuit 131 to the address decoder 21.

Next, the main CPU 117 executes the program PRGM2 read from the SRAM 115 (step ST116).
The main CPU 117 generates a command in the course of executing the program PRGM2 and outputs it to the data bus 6. At this time, the main CPU 117 outputs an address designating the game processing circuit 5 to the address decoder 21.

Next, in the idle mode after execution of the program PRGM2, the main CPU 117 calculates an exclusive OR (XOR) of the program PRGM2 read from the SRAM 115 and the random number a read from the SRAM 115, and the program PRGM2X as a result is calculated. The data is output to the monitoring circuit 131 via the data bus 6 (step ST117). At this time, the main CPU 117 outputs the address designated by the monitoring circuit 131 to the address decoder 21. Thereafter, the main CPU 117 repeats the processes of steps ST116 and ST117 described above.

Hereinafter, the processing of the monitoring circuit 131 will be described in association with the processing of the main processing circuit 111 described above.
4, steps ST21 to ST31 denoted by the same reference numerals as those in FIG. 2 are substantially the same as those described in the first embodiment except that the program PRGM2X is received and stored. Is omitted.
When the monitoring CPU 139 determines that there is a possibility of falsification of the program PRGM2 executed by the main CPU 117 of the main processing circuit 111, the monitoring CPU 139 controls the power feeding circuit 141, and the power feeding circuit 141 starts the main processing circuit 111. The power supply to the SRAM 115 is stopped (step ST132). As a result, the unauthorized program stored in the SRAM 115 is automatically deleted, and the main CPU 117 is prevented from executing the unauthorized program.

<Modification of the above-described embodiment>
The present invention is not limited to the embodiment described above.
That is, those skilled in the art may make various modifications, combinations, subcombinations, and alternatives regarding the components of the above-described embodiments within the technical scope of the present invention or an equivalent scope thereof.

In the first embodiment described above, the case where random numbers are transmitted from the main processing circuits 11 and 111 to the monitoring circuits 31 and 131 in the initial operation is exemplified. However, a common value is held in advance, and no random number is transmitted. May be.
In the above-described embodiment, the main processing circuits 11 and 111 calculate the exclusive OR of the programs PRGM and PRGM2 and the random number a and generate the programs PRGMX and PRGM2X to be transmitted to the monitoring circuits 31 and 131. Although illustrated, predetermined operations other than exclusive OR may be performed.

  In the above-described embodiment, the monitoring circuits 31 and 131 restore the programs PRGM and PRGM2 by calculating the exclusive logical sum of the received programs PRGMX and PRGM2X and the random number a. You may memorize and compare as it is.

  Further, in the above-described embodiment, when it is determined that the programs PRGM and PRGM2 read from the ROMs 13 and 113 and the verification program do not match, the bus gate 9 on the data bus 6 shown in FIG. 1 is closed. An example and a case where power supply to the SRAM 115 by the power supply circuit 141 illustrated in FIG. 3 is stopped are illustrated. In the present invention, when it is determined that there is a mismatch, operations other than these examples may be performed to prohibit the operation of the game processing circuit 5 by an unauthorized program. For example, an operation for forcibly stopping the operation of the main CPU 117 or the game processing circuit 5 may be performed. In parallel with these prohibition operations, an operation of reporting to a predetermined center or outputting an alarm may be performed.

  In addition, the signal processing devices 10 and 110 include, for example, a removal detection unit that detects whether or not the main CPU 117 and the main processing circuit 111 are removed, and the monitoring CPU 39 is triggered by the detection of the removal by the removal detection unit. , 139 may perform the prohibition operation described above.

  In the above-described embodiment, the configuration in which the main processing circuits 11 and 111 and the monitoring circuits 31 and 131 are connected via the data bus 6 is illustrated. However, these may be connected without using the data bus. The functions of the monitoring circuits 31 and 131 may be incorporated in the main processing circuits 11 and 111.

  In the second embodiment described above, the case where the power supply circuit 141 stops the power supply to the SRAM 115 when the monitoring circuit 131 detects the modification of the program PRGM2 is exemplified. However, the power supply to the entire main processing circuit 111 is stopped. You may make it do.

  The present invention can be applied to a gaming machine that needs to prevent unauthorized operation due to execution of an unauthorized program.

FIG. 1 is a hardware configuration diagram of a signal processing device of a gaming machine according to the first embodiment of the present invention. FIG. 2 is a flowchart for explaining an operation example of the signal processing apparatus shown in FIG. FIG. 3 is a hardware configuration diagram of the signal processing device of the gaming machine according to the second embodiment of the present invention. FIG. 4 is a flowchart for explaining an operation example of the signal processing apparatus shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 3 ... Input part, 5 ... Game processing circuit, 6 ... Data bus, 7, 9 ... Bus gate, 10, 110 ... Signal processing device, 13, 113 ... ROM, 15 ... RAM, 115 ... SRAM, 17, 117 ... Main CPU, 21 ... Address decoder, 33, 133 ... ROM, 35, 135 ... RAM, 37, 137 ... Monitoring ROM, 39, 139 ... Monitoring CPU, 43 ... Battery, 41, 141 ... Power feeding circuit

Claims (12)

A gaming machine unauthorized operation preventing device for preventing an unauthorized operation of a gaming machine performing a gaming operation by controlling a processing circuit based on a program stored in a first memory,
A second memory in which the program read from the first memory is written as a comparison program in an initial operation before controlling the play operation;
If a mismatch is detected between the program read from the first memory and the comparison program read from the second memory after the initial operation, a command issued by the processing circuit is used. And a control circuit for prohibiting the game operation or the operation of the processing circuit executing the program stored in the first memory. The control circuit includes:
In the initial operation, a program obtained by performing a predetermined operation on the program read from the first memory is input, an operation corresponding to the predetermined operation is performed on the input program, and the program before the operation is calculated. A program is restored, and the restored program is written in the second memory as the comparison program,
After the initial operation, a program obtained by performing a predetermined operation on the program read from the first memory is input, and an operation corresponding to the predetermined operation is performed on the input program before the operation. The gaming machine unauthorized operation preventing device according to claim 1, wherein the program is restored, and it is determined whether or not the restored program matches the comparison program read from the second memory. The predetermined operation is an operation for calculating an exclusive OR of a program read from the first memory and a random number,
The control circuit inputs the random number in the initial operation, and after the initial operation,
The gaming machine unauthorized operation preventing apparatus according to claim 2, wherein an exclusive OR of the input program and the input random number is calculated to restore the program before the calculation. When the control circuit detects the mismatch, the control circuit sets the transmission path for transmitting the command issued by the processing circuit to the game processing circuit that controls the operation of the gaming machine based on the command. Item 4. The gaming machine unauthorized operation prevention device according to any one of Items 1 to 3. A removal detecting means for detecting removal of the processing circuit;
When the removal detection unit detects removal of the processing circuit, the control circuit stores the game operation based on a command issued by the processing circuit or the processing circuit is stored in the first memory. The apparatus according to claim 1, wherein an operation for executing a program is prohibited. A gaming machine unauthorized operation prevention device that prevents unauthorized operation of a gaming machine that performs a game operation by controlling a processing circuit based on a program read from a volatile memory that retains a storage state under the condition that power is supplied. And
Modification detection means for detecting modification of a program stored in the volatile memory;
And a control circuit that stops the power supply to the volatile memory when the alteration detection means detects the alteration. The gaming machine unauthorized operation preventing apparatus according to claim 6, wherein the control circuit permits an operation of reading the program from a nonvolatile memory to the volatile memory on condition that a predetermined authentication process has been performed. A removal detecting means for detecting removal of the processing circuit;
The apparatus according to claim 6, wherein the control circuit stops the power supply to the nonvolatile memory when the removal detection unit detects removal of the processing circuit. Game processing means for executing various game operations based on the input command;
A main processing circuit for outputting the command to the game processing means;
A monitoring circuit for preventing illegal operation of the game processing means,
The main processing circuit includes:
A first memory for storing a program;
It operates based on the program read from the first memory and outputs the program read from the first memory to the monitoring circuit in an initial operation before controlling the game operation, and after the initial operation. A first control circuit that outputs the program read from the first memory to the monitoring circuit at a predetermined timing of:
The monitoring circuit is
In the initial operation, a second memory in which the program input from the main processing circuit is written as a comparison program;
When a mismatch between the program read from the first memory and the comparison program read from the second memory is detected after the initial operation, the processing circuit is based on the command issued by the processing circuit. A game machine comprising: a second control circuit that prohibits a game operation or an operation in which the processing circuit executes a program stored in the first memory. A volatile memory that maintains a memory state on condition that power is supplied;
Based on the program read from the volatile memory, a main processing circuit for controlling the game operation,
Modification detection means for detecting modification of a program stored in the volatile memory;
A gaming machine comprising: a monitoring circuit that stops the power supply to the volatile memory when the modification detection unit detects the modification. A gaming machine unauthorized operation prevention method for preventing an unauthorized operation of a gaming machine performing a gaming operation by controlling a processing circuit based on a program stored in a first memory,
An initial step of reading the program from the first memory and writing it as a comparison program in the second memory before controlling the play operation;
A comparison step for determining whether or not the program read from the first memory and the comparison program read from the second memory match after the initial step;
If it is determined in the comparison step that they do not match, the game operation based on a command issued by the processing circuit or an operation in which the processing circuit executes a program stored in the first memory is prohibited. A method for preventing illegal operation of a gaming machine having a prohibited process. It is a gaming machine illegal operation prevention method for preventing an illegal operation of a gaming machine that performs a game operation by controlling a processing circuit based on a program read from a volatile memory that holds a storage state on condition that power is supplied. And
A modification detection step for detecting modification of the program stored in the volatile memory;
A gaming machine improper operation prevention method comprising: a power supply stopping step of stopping the power supply to the volatile memory when the modification is detected in the modification detection step.