JP2008288350A - Manufacturing method of semiconductor device - Google Patents

Abstract

A semiconductor device manufacturing method capable of improving the crystallinity of an epitaxial layer and reducing leakage current and on-voltage.
A after forming the n ⁺ epitaxial growth layer 9 on the oxide film 4 having an opening 5, and laser annealing the n ⁺ epitaxial growth layer 9 was quenched crystal defects, n on the n ⁺ epitaxial growth layer 9 By forming a ⁺ buffer layer (a part of n ⁺ epitaxial growth layer 9), p ⁺ base layer 13 and n ⁺⁺ emitter layer 14 (source layer) to manufacture a semiconductor device (IGBT, MOSFET, etc.), leakage current and The on-voltage (on-resistance) can be reduced.
[Selection] Figure 17

Description

    The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a method for manufacturing a power semiconductor device constituting an IGBT (Insulated Gate Bipolar Transistor) or the like.

    With regard to IGBTs, performance has been improved by many improvements so far. Here, the performance of the IGBT is as a switch that keeps the voltage and shuts off the current completely when it is off, while flowing the current with the smallest possible voltage drop, that is, the smallest on-resistance when it is on. It's about performance. Below, the characteristic etc. of IGBT are demonstrated.

    First, the trade-off between the breakdown voltage and the on-voltage of the IGBT will be described. There is a trade-off relationship (so-called trade-off relationship) between the maximum voltage that can be held by the IGBT, that is, the magnitude of the withstand voltage and the voltage drop at the time of ON, and the higher the withstand voltage IGBT, the higher the on-voltage. Ultimately, the limits of this trade-off relationship will be determined by the physical properties of silicon due to improvements through technology development. In order to improve this trade-off to the limit, it is necessary to devise on the design side, such as preventing local electric field concentration when holding the voltage.

    Next, the trade-off between the on-voltage of the IGBT and the switching loss (particularly the turn-off loss) will be described. Since the IGBT is a switching device, it operates from on to off or off to on. At the moment of this switching operation, a large loss per hour occurs. In general, an IGBT having a lower on-voltage has a slower turn-off loss, and therefore has a larger turn-off loss. By improving the trade-off relationship as described above, the performance of the IGBT can be improved. Note that the dependency of the turn-on loss on the on-voltage is small. The turn-on loss greatly depends on the characteristics of the freewheeling diode used in combination with the IGBT.

In order to optimize the trade-off relationship between the on-voltage and the turn-off loss (hereinafter referred to as the on-voltage-turn-off loss relationship), it is effective to optimize the internal excess carrier distribution when the IGBT is on. is there. In order to lower the on-voltage, the resistance value of the drift layer may be decreased by increasing the excess carrier amount.
However, at the time of turn-off, it is necessary to sweep all the excess carriers out of the device or to disappear by electron-hole recombination. Therefore, when the excess carrier amount is increased, the turn-off loss increases. Therefore, in order to optimize this trade-off relationship, the turn-off loss may be minimized with the same on-voltage.

    In order to achieve the optimum trade-off, the carrier concentration on the collector side and the emitter side are increased by decreasing the collector concentration on the collector side and increasing the carrier concentration on the emitter side so that the ratio of the carrier concentration on the collector side and the emitter side is about 1: 5. Good. Furthermore, the average carrier concentration in the drift layer may be increased by keeping the carrier lifetime of the drift layer as large as possible.

    When the IGBT is turned off, the depletion layer extends from the pn junction on the emitter side into the drift layer and progresses toward the collector layer on the back surface. At that time, holes out of excess carriers in the drift layer are extracted from the end of the depletion layer by the electric field. In this way, the electron excess state occurs, and surplus electrons pass through the neutral region and are injected into the p-type collector layer. Since the collector-side pn junction is slightly forward-biased, holes are reversely injected according to the injected electrons. The reversely injected holes merge with the holes extracted by the electric field described above and enter the depletion layer.

Since carriers (here, holes) which are charge carriers pass through the electric field region and escape to the emitter side, the electric field works on the carriers. The work that the carriers receive from the electric field eventually becomes lattice vibration due to collision with a crystal lattice such as silicon, and is dissipated as heat. This dissipating energy becomes a turn-off loss.
By the way, the energy dissipated by the carriers extracted before the depletion layer is fully extended is smaller than the energy dissipated by the carriers extracted when the depletion layer is fully extended. This is because if the depletion layer is not fully extended, the potential difference when carriers pass through the depletion layer is small, so that the work received from the electric field of the depletion layer is small.

    From a micro perspective, it looks like the above. From a macro perspective of device terminal voltage, the product of the voltage and current (the current that flows before the collector-emitter voltage finishes rising, that is, the current that flows while the voltage rises) This means that the contribution to the loss expressed by (voltage × current) is small. From the above, the carrier distribution biased to the emitter side due to the IE effect described later is more turned off than the carrier distribution biased to the collector side under the condition that the proportion of carriers extracted at a low voltage is large and the on-voltage is the same. It can be seen that the loss is small.

    In order to reduce the carrier concentration on the collector side, the total impurity amount in the collector layer may be reduced. This is not particularly difficult. However, in an IGBT with a low rated breakdown voltage such as 600 V, it is necessary to handle a wafer of about 100 μm thickness or thinner during the manufacturing process in order to reduce the total impurity amount of the collector layer. There are difficulties in production technology. On the other hand, the mechanism for increasing the carrier concentration on the emitter side is called the IE effect.

    As a cathode structure having a large IE effect, a HiGT structure in which a high-concentration n layer is inserted so as to surround a p base of a planar structure has been proposed (see, for example, Patent Document 1 and Patent Document 2). Further, in the trench gate structure, a CSTBT structure in which an n layer having a higher concentration than the drift layer is inserted in a mesa between adjacent trenches, an IEGT (Injection Enhancement Gate Transistor) structure, and the like have been proposed (for example, patents). Reference 3). In general, the IE effect in the trench type is larger than the IE effect in the planar type.

    The nature of the IE effect has been discussed and reported. An IGBT equivalent circuit that is often drawn is a combination of a MOSFET (insulated gate field effect transistor having a metal-oxide-semiconductor structure) and a bipolar transistor. However, considering the actual device operation, it is considered to be a combination of the MOSFET 51, the pnp bipolar transistor 52, and the pin diode 53 as in the equivalent circuit shown in FIG.

FIG. 21 is a cross-sectional view showing a configuration of a main part of the planar IGBT. In FIG. 21, reference numeral 54 denotes a pnp bipolar transistor region (hereinafter referred to as a pnp-BJT region), and reference numeral 55 denotes a pin diode region. Further, in FIG. 21, the solid line arrow represents the flow of electron current, and the dotted line arrow represents the flow of hole current. In this specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. In addition, the n ⁺ or p ⁺ region (including the layer) means that the impurity concentration is higher than that of the n or p region (including the layer) not marked with “+”. Furthermore, (including layers) n ⁺⁺ region means that even a higher impurity concentration than n ⁺ region (including the layer).

As shown in FIG. 21, electrons from the ^{n ++} region 56 of the surface of the MOS ^portion, an ^{n +} inversion layer 58 in the surface of the p layer 57 surrounding the ^{n ++} region 56, n ^- of the surface of the drift layer 59 ^{n +} It flows through the electron storage layer 60 toward the p collector layer 61 on the back surface. A part of this electron current becomes a base current of the pnp-BJT region 54. In the pnp-BJT region 54, holes that have flowed from the p anode layer 61 due to diffusion or drift only flow into the p layer 57, and the pn junction is slightly reverse-biased. Therefore, the concentration of minority carriers, that is, holes in the n ⁻ drift layer 59 near the pn junction is extremely low.

On the other hand, the n cathode of the pin diode region 55 is the n ⁺ electron storage layer 60 on the surface of the n ⁻ drift layer 59. Since this n ⁺ / n ⁻ junction is slightly forward-biased, electrons are injected into the n ⁻ drift layer 59. When the current is large, the electron concentration is much higher than the doping concentration of the n ⁻ drift layer 59 (high injection state). In order to satisfy the charge neutrality condition, holes having the same concentration as the electrons also exist. Accordingly, the concentration of minority carriers in the n ⁻ drift layer 59 in the vicinity of the n ⁺ / n ⁻ junction, that is, the hole concentration, is extremely high.

In the IGBT, it is important to reduce the pnp-BJT region and increase the pin diode region in order to realize the optimum carrier distribution of the emitter side bias. It is also very important to increase the n ⁺ / n ⁻ forward bias amount to promote electron injection. In the structure having the IE effect proposed so far, the ratio of the pin diode region is increased, and at the same time, the increase of n ⁺ / n ⁻ forward bias is realized.

By the way, in the planar structure, when the ratio of the p base in the cell pitch is reduced, the on-voltage is reduced. This has the effect of increasing the forward bias of the n ⁺ / n ⁻ junction by increasing the lateral current density near the surface and increasing the voltage drop in addition to increasing the ratio of the pin diode region. It is considered large. The reason why the forward bias of the n ⁺ / n ⁻ junction becomes large is that the n ⁺ layer has a low resistance, so its potential is equal to the emitter potential (cathode potential), but the n ⁻ layer has a high resistance, so its potential Is lifted by a large current.

Similarly, the IE effect can be enhanced by reducing the ratio of the pnp-BJT region in the trench structure. In order to reduce the ratio of the pnp-BJT region, for example, the p base region may be set in a floating state in some mesa portions. The IE effect can also be increased by deepening the trench and separating the bottom of the trench from the pn junction. Further, the IE effect is increased by reducing the width of the mesa portion. In any case, it is considered that the density of the hole current flowing through the mesa portion increases, and the n ⁺ / n ⁻ forward bias due to the voltage drop increases.

Here, when the doping concentration of the drift layer is Nd and the forward bias applied to the n ⁺ / n ⁻ junction is Vn, the electron concentration n on the n ⁻ layer side of the n ⁺ / n ⁻ junction is expressed by the following equation: . However, k is a Boltzmann constant and T is an absolute temperature.
n = Nd ^* exp (Vn / kT)
As is apparent from the above equation, the electron concentration n on the cathode side increases exponentially according to the forward bias applied to the n ⁺ / n ⁻ junction. As means for increasing the forward bias amount, there is one that uses a voltage drop due to a large current as described above. Further, as described in Patent Documents 1 to 3, the forward bias amount can be increased also by increasing the n ⁺ concentration. However, since the HiGT structure described in Patent Document 1 is a planar structure, if the concentration of the n ⁺ buffer layer on the surface side is too high, the forward breakdown voltage is greatly reduced.

On the other hand, in the CSTBT structure described in Patent Document 3, the n ⁺ buffer layer on the surface side is sandwiched between trench gate oxide films, and continues to the polysilicon potential via the gate oxide film. Therefore, when the forward voltage is maintained, that is, in the blocking mode, the n ⁺ buffer layer on the surface side is depleted not only from the pn junction but also from the boundary with the trench gate oxide film on both sides, so that it is completely depleted with a low forward bias. Turn into. Therefore, the electric field inside the n ⁺ buffer layer on the surface side is relaxed despite the high concentration. Even if the forward bias is further increased, a local peak electric field is unlikely to appear due to the relaxation of the electric field at the mesa between the trenches.

This drifts a parallel pn structure in which vertical layered n-type regions and vertical layered p-type regions with increased impurity concentration are alternately joined instead of a uniform and single drift type drift layer. This is also in accordance with the principle of the superjunction MOSFET provided in the part. As described above, the CSTBT structure has a characteristic that the forward breakdown voltage is hardly lowered while enhancing the IE effect. The n ⁺ buffer layer on the surface side creates a diffusion potential with the n ⁻ drift layer and becomes a potential barrier for holes, so that the hole concentration in the drift layer increases.

As another explanation, it can be said that electrons are injected from the n ⁺ layer because the n ⁺ buffer layer and the n ⁻ layer on the surface side are forward-biased. That is, in the n ⁺ / n ⁻ junction, if the n ⁺ layer has a high concentration, the electron injection efficiency is improved. Therefore, the ratio of the electron current injected into the n ⁻ layer to the hole current entering the n ⁺ layer. Becomes larger. In order for holes to diffuse and flow as minority carriers in the n ⁺ layer, the n ⁺ / n ⁻ junction needs to be forward biased. The higher the n ⁺ layer concentration, the smaller the hole concentration as minority carriers in the thermal equilibrium state. Therefore, a higher forward bias amount is required to flow the same hole current. If the forward bias amount is large, the electron current flowing into the n ⁻ layer increases, so that the electron concentration increases. This second description is physically a paraphrase of the first description.

    As described above, even in the conventional IGBT, a carrier distribution concentrated on the emitter side due to the IE effect is realized. However, in order to optimize the trade-off between on-voltage and turn-off loss, it is necessary to further increase the carrier concentration on the cathode side in the on-state. That is, the IE effect is still insufficient in the conventional IGBT. Even though a trench gate structure such as a CSTBT structure or an IEGT structure has improved trade-off characteristics, there is still room for improvement by further miniaturization.

    However, the manufacturing process of the trench structure is long and complicated compared to the manufacturing process of the planar structure. Therefore, the yield rate of trench type devices is lower than that of planar type devices. Therefore, the product cost of the trench type device is high. Nevertheless, if further miniaturization is performed in order to improve the characteristics, the manufacturing cost will be further increased. In the trench gate structure, the electric field tends to concentrate on the bottom of the trench and the avalanche breakdown is likely to occur, so that the trade-off between on-voltage and withstand voltage tends to deteriorate. In addition, due to the structure, when the gate is set to a negative potential with respect to the emitter, there is a problem that the electric field strength at the bottom of the trench increases and the breakdown voltage deteriorates.

In order to solve the above-described problems, a semiconductor device having a larger IE effect than that of the prior art, that is, an on-voltage-turn-off loss trade-off is optimized. Patent Document 4 discloses a semiconductor device and a manufacturing method thereof that do not cause deterioration in breakdown voltage trade-off.
FIG. 22 is a configuration diagram of an example of the semiconductor device described in Patent Document 4, in which FIG. 22A is a cross-sectional view of the main part, and FIG. 22B is a perspective view of the main part. FIG. 4B shows each semiconductor layer.

An oxide film 4 having an opening 5 at the center is formed on the n ⁻ semiconductor substrate 1, and an n ⁺ semiconductor layer 66 surrounded by the oxide film 4 is formed using a polysilicon layer 65. The n ⁺ semiconductor layer 66 becomes an n ⁺ buffer layer. A gate oxide film 10 is formed on the n ⁺ semiconductor layer 66, and a polysilicon layer 11 to be the gate electrode 12 is formed at the center. Using this polysilicon layer 11 as a mask, a p base layer 13 and an n ⁺⁺ emitter layer 14 are formed by ion implantation of boron and phosphorus. The surface is covered with an interlayer insulating film 16, contact holes 17 are formed in the interlayer insulating film 16 and the oxide film 10, and an emitter electrode 18 in contact with the p ⁺ base layer 13 and the n ^{+ +} emitter layer 14 is formed. the n ^- back surface 19 of the semiconductor substrate 1 to form a p-type collector layer 20 IGBT forms the collector electrode 21 thereon is completed.
JP 2003-347549 A Japanese translation of PCT publication No. 2002-532885 JP-A-8-316479 JP 2006-237553 A

However, in the structure shown in FIG. 22 of Patent Document 4 described above, the n ⁺ semiconductor layer 66 (the n ⁺⁺ source layer 14, the p ⁺ base layer 13, and the n ⁺ buffer layer 67 is formed in the polysilicon layer 65. )), The lifetime is reduced due to crystal defects. Therefore, the recombination of carriers in the n ⁺ semiconductor layer 66 is increased, and the leakage current is increased. In addition, the resistance in the n ⁺ semiconductor layer 66 increases and the on-voltage increases. Patent Document 4 also describes forming the n ⁺ semiconductor layer 66 as a single crystal layer, but does not show a specific formation method.

For example, when the single crystal layer is formed of an epitaxial growth layer, crystal defects occur in the epitaxial growth layer on the oxide film, leading to a reduction in lifetime and an increase in leakage current and on-voltage.
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the above-described problems, improves the crystallinity of a semiconductor layer (epitaxial layer), and can reduce leakage current and ON voltage. That is.

In order to achieve the above object, a step of forming an insulating film having an opening on a semiconductor substrate of a first conductivity type, and an impurity concentration higher than that of the semiconductor substrate on the opening and the insulating film of the semiconductor substrate. The manufacturing method includes a step of forming an epitaxial growth layer having the first conductivity type and a step of laser annealing by irradiating the epitaxial growth layer with laser light.
A step of forming an insulating film having an opening on the semiconductor substrate of the first conductivity type; and the insulating film has a side wall and a portion thinner than the side wall, the opening of the semiconductor substrate and the insulating film Forming a first conductivity type epitaxial growth layer having an impurity concentration higher than that of the semiconductor substrate on the thin portion higher than the side wall; grinding and planarizing the epitaxial growth layer using the side wall as a stopper; and the epitaxial growth layer. And a step of laser annealing by irradiating with laser light.

Further, the energy of the laser beam may is ^{3J / cm 2 ~6J / cm 2} .
Further, the irradiation of the laser beam is a spot, the spot of the laser beam is irradiated for a predetermined time, and the laser beam is irradiated by moving to the next location so that the irradiated location is overlapped. The ratio may be 60% or more of the spot area.

According to the present invention, a crystal defect is eliminated by laser annealing an epitaxial growth layer formed on an oxide film and having a buffer layer and a base layer, and a leakage current and an on-voltage (on-state) of a semiconductor device (IGBT, MOSFET, etc.) are eliminated. Resistance) can be reduced.
In laser annealing, it can reduce leakage current by the laser energy amount and ^3J / cm ^{2 ~6J} / cm 2 significantly (about 40%).

    Further, by setting the overlapping amount of laser light spots to 60% or more, the leakage current can be reduced by about 50% with respect to the initial value (value before laser annealing).

    Embodiments will be described in the following examples. In the following description, the same parts as those in the conventional structure are denoted by the same reference numerals.

1 to 12 are cross-sectional views showing a main part manufacturing process showing the semiconductor device manufacturing method according to the first embodiment of the present invention in the order of steps. This sectional view shows a section of one cell.
In FIG. 1, an insulating film (for example, oxide film 2) is formed on an n ⁻ semiconductor substrate 1.
In FIG. 2, the oxide film 2 which becomes the peripheral portion of the cell is left as a side wall 3 and the oxide film 2 in other portions is removed.

In FIG. 3, an insulating film (for example, oxide film 4) is formed on an n ⁻ semiconductor substrate 1, and an opening 5 is formed in the center.
In FIG. 4, epitaxial growth is performed from above the opening 5 and lateral growth is performed on the oxide film 4, so that the n ⁺ epitaxial growth layer 6 having a higher concentration than the n ⁻ semiconductor substrate 1 (the undiffused layer becomes the n ⁺ buffer layer). Is formed higher than the height (for example, about 1 μm) of the side wall 3 of the oxide film as a semiconductor layer. At this time, crystal defects 7 occur in the n ⁺ epitaxial growth layer 6.

In FIG. 5, the n ⁺ epitaxial growth layer 6 is ground and planarized by using the side wall 3 of the oxide film as a stopper, for example, to a thickness of about 1 μm.
In FIG. 6, the n ⁺ epitaxial growth layer 6 is irradiated with laser light 8 and laser annealed to eliminate the crystal defects 7, thereby forming the n ⁺ epitaxial growth layer 9 without the crystal defects 7.
In FIG. 7, an insulating film (gate oxide film 10) is formed on the n ⁺ epitaxial growth layer 9, and a polysilicon layer 11 to be the gate electrode 12 is formed on the gate oxide film 10.

In FIG. 8, the gate electrode 12 is formed by removing both sides while leaving the polysilicon layer 11 to be the gate electrode 12 in the center. At this time, the width of the gate electrode 12 is made wider than the opening 5.
In FIG. 9, a p ⁺ base layer 13 is formed by boron ion implantation so as to be in contact with the oxide film 4 using the polysilicon layer 11 as the gate electrode 12 as a mask, and the gate electrode 12 is formed on the surface layer of the p ⁺ base layer 13. The n ⁺⁺ emitter layer 14 is formed by phosphorus ion implantation using the polysilicon layer 11 as a mask, and a resist (not shown) is formed on the p ⁺⁺ contact layer 15 so as to be in contact with the p ⁺ base layer 13 and the n ⁺⁺ emitter layer 14. The mask is formed by boron ion implantation. At this time, the p ⁺ base layer 13 is in contact with the oxide film 13 and is not in contact with the n ⁻ semiconductor substrate 1. When contacted, a pn diode is formed and the device does not operate.

In this case p ⁺ base layer 13 and the p ⁺⁺ contact layer 15 in FIG. 9 is in contact with the oxide film 4, formed so as not to be in contact with p ⁺ base layer 13 to the oxide film 4 as shown in FIG. 13, the The n ⁺⁺ emitter layer 14 may be formed on the surface layer of the p ⁺ base layer 13, and the p ⁺⁺ contact layer 15 may be formed in contact with the n ⁺⁺ emitter layer 14.
In FIG. 10, an interlayer insulating film 16 is formed on the surface, and contact holes 17 are formed in the interlayer insulating film 16 and the gate oxide film 10.

In FIG. 11, an emitter electrode 18 in contact with the n ⁺⁺ emitter layer 14 and the p ⁺⁺ contact layer 15 through the contact hole 17 is formed on the interlayer insulating film 16.
In FIG. 12, after the back surface side of the n ⁻ semiconductor substrate 1 is ground to reduce the thickness, a p ⁺ collector layer 20 is formed on the ground back surface 19, and a collector electrode 21 is formed on the p ⁺ collector layer 20. Thus, an FS (field stop) type IGBT is completed.

In the process of FIG. 2 described above, it is not always necessary to form the sidewall 3 of the oxide film that functions as a stopper when the n ⁺ epitaxial layer 6 is ground and planarized. In that case, in the step of FIG. 5, the thickness of the n ⁺ epitaxial growth layer 6 after grinding and planarization may be determined by managing the grinding and planarization time.
FIG. 14 is a diagram showing the relationship between the laser energy amount and the leakage current (normalized).

If the amount of energy is insufficient, the crystal defects are not repaired and do not disappear, so the leakage current is large. If the amount of energy is excessive, the rate at which crystal defects are generated again becomes superior to the rate at which crystal defects in the n ⁺ epitaxial growth layer are repaired (disappeared) by this energy, and the leakage current increases.
The results of the experiment, the laser energy amount is the leakage current is greatly reduced in the range of ^{3J / cm 2 ~6J / cm 2} . Although not shown, the on-voltage is also reduced.

Further, as shown in FIG. 15, when the amount of overlap of laser light irradiation (overlap amount: overlap amount) is increased, the rate at which crystal defects are repaired (disappeared) increases.
FIG. 16 is a diagram illustrating the relationship between the amount of laser beam spot overlap and the leakage current (normalized). In laser annealing, laser beam irradiation is a spot 22 (for example, a rectangle having a width of about 0.5 mm and a length of about 2 mm). After irradiation for a predetermined time (for example, on the order of μs), this spot is irradiated. 22 is shifted to the next position (spot 23) to be irradiated so as to overlap in the width direction. At the end of one scan, scanning is performed by shifting the spot 22 in the longitudinal direction and moving the spot 22 in the lateral direction. The overlap in the longitudinal direction is about 0.3 mm.

    In this way, laser annealing is performed by irradiating the laser beam while moving the spot 22 so as to partially overlap (spot 23). By setting the ratio of the area of the spots 22 and 23 overlapping in the width direction (the area obtained by dividing the area S2 of the overlapping parts by the spot area S1 as a percentage and the amount of overlap 24) is 60% or more. Leakage current can be reduced by about 50%. Of course, it is also effective in reducing the on-voltage.

By increasing the overlap amount 24, the temperature of the n ⁺ epitaxial growth layer 6 increases, and the rate at which the crystal defects 7 are restored (returned) to normal crystals increases. However, when the overlap amount 24 is 60% or more, the leakage current becomes constant at the initial level of 50% because the crystal defect 7 in the n ⁺ epitaxial layer 6 disappears when the overlap amount is 60% and normal crystals Presumed to have returned to.

As described above, by eliminating the crystal defects 7 generated in the n ⁺ epitaxial growth layer 6 by laser annealing by irradiation with the laser beam 8, a semiconductor device having a small leakage current can be obtained. Although not shown, the on-voltage can be reduced.
As a laser light source, a YAG laser, an excimer laser, or the like is preferable because a predetermined energy amount can be easily obtained.

FIGS. 17A and 17B are configuration diagrams of a semiconductor device according to a second embodiment of the present invention, in which FIG. 17A is a sectional view of the principal part and FIG. 17B is a perspective view of the principal part. This structure is basically the same as the conventional structure shown in FIG. 20 of Patent Document 4, except that the crystal defect 7 of the semiconductor layer (n ⁺ epitaxial growth layer 6) is eliminated by irradiation with laser light 8 (laser annealing). It is a point.
An oxide film 4 is formed on the n ⁻ semiconductor substrate 1, an opening 5 is formed at the center of the oxide film 4, and a sidewall 3 of the oxide film is formed around the cell. At a location opening 5 above and surrounded by the oxide film 4,3 to form a laser annealed n ⁺ epitaxial growth layer 9. The ^{p +} base layer formed in contact with the oxide film 4 in the ^{n +} epitaxial growth layer 9 on the oxide film 4, the ^{n ++} emitter layer 14 is formed on the surface layer of the ^{p +} base layer 13, further ^{n ++} emitter layer 14, p ⁺⁺ contact layer 15 is formed in contact with p ⁺ base layer 13 and oxide film 4, respectively. The n ⁺ epitaxial growth layer 9 in which the p ⁺ base layer 14 is not formed becomes an n ⁺ buffer layer 9a. on top ^{p +} base layer 13 sandwiched between the n ⁺⁺ emitter layer 14 and the ^{n +} epitaxial layer 9 to form the gate electrode 12 through the gate oxide film 10. In the figure, the gate oxide film 10 is formed on a part of the n ⁺⁺ emitter layer 14, the p ⁺ base layer 13, and the n ⁺ epitaxial growth layer 9. An interlayer insulating film 16 is formed on the surface of the gate electrode 12. A contact hole 17 is formed in the interlayer insulating film 16 and the gate oxide film 10, and an emitter electrode 18 is formed so as to be in contact with the n ⁺⁺ emitter layer 14 and the p ⁺⁺ contact layer 15.

When a p ⁺ layer (p ⁺ collector layer 20) is formed on the back surface 19 of the n ⁻ semiconductor substrate 1, an IGBT as shown in FIG. 15 is formed, and when an n ⁺ layer (n ⁺ drain layer) is formed, a MOSFET (not shown) is formed. In either case, leakage current and on-voltage (on-resistance) can be reduced by laser annealing the n ⁺ epitaxial growth layer 6 having the crystal defects 7 to form the n ⁺ epitaxial growth layer 9 in which the crystal defects 7 are eliminated. . In particular, in the case of IGBT, conductivity modulation occurs due to the injection of minority carriers, so eliminating the crystal defects 7 in the n ⁺ epitaxial growth layer 6 increases the amount of carriers that cause conductivity modulation, so the effect of reducing the on-voltage is large. The same can be said for the following third and fourth embodiments.

FIG. 18 is a fragmentary cross-sectional view of the semiconductor device according to the third embodiment of the present invention. The difference from FIG. 17 is that the p ⁺ base layer 13 is formed on the surface layer of the n ⁺ epitaxial growth layer 9, and the n ^{+ +} emitter layer 14 is formed on the surface layer of the p ⁺ base layer 13. Also in this structure, since the n ⁺ epitaxial growth layer 9 without crystal defects 7 is formed by laser annealing, the leakage current and the on-voltage can be reduced.

FIG. 19 is a fragmentary cross-sectional view of the semiconductor device according to the fourth embodiment of the present invention. The difference from FIG. 17 is that the sidewall 3 of the oxide film is not formed. Also in this structure, since the n ⁺ epitaxial growth layer 9 without crystal defects 7 is formed by laser annealing, the leakage current and the on-voltage can be reduced.

Sectional view of manufacturing process of main part of semiconductor device according to first embodiment of this invention. 1 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the first embodiment of the present invention, continued from FIG. FIG. 2 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the first embodiment of the present invention continued from FIG. FIG. 3 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the first embodiment of the present invention continued from FIG. FIG. 4 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the first embodiment of the present invention continued from FIG. FIG. 5 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the first embodiment of the present invention continued from FIG. FIG. 6 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the first embodiment of the present invention continued from FIG. FIG. 7 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the first embodiment of the present invention continued from FIG. FIG. 8 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the first embodiment of the present invention continued from FIG. FIG. 9 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the first embodiment of the present invention continued from FIG. FIG. 10 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the first embodiment of the present invention continued from FIG. FIG. 11 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the first embodiment of the present invention continued from FIG. Diagram when p ⁺ base layer is not connected to underlying oxide film Diagram showing the relationship between laser energy and leakage current (standardization) Diagram of overlapping laser beam spots Diagram showing the relationship between laser beam spot overlap and leakage current (standardization) FIG. 3 is a configuration diagram of a semiconductor device according to a second embodiment of the present invention, in which (a) is a cross-sectional view of the main part and (b) is a perspective view of the main part. Sectional drawing of the principal part of the semiconductor device of 3rd Example of this invention. Sectional drawing of the principal part of the semiconductor device of 4th Example of this invention. The figure which shows the equivalent circuit of IGBT Sectional drawing which shows the structure of the principal part of planar type IGBT It is a block diagram of an example of the conventional semiconductor device, (a) is principal part sectional drawing, (b) is principal part perspective view.

Explanation of symbols

1 n ^- semiconductor substrate 2 oxide film 3 side wall 4 oxide film 5 opening 6 n ⁺ epitaxial layer 7 crystal defects 8 laser beam 9 n ⁺ epitaxial growth layer (defect annihilation)
9a n ⁺ buffer layer 10 gate oxide film 11 a polysilicon layer 12 gate electrode 13 p ⁺ base layer 14 n ⁺⁺ emitter layer 15 p ⁺⁺ contact layer 16 interlayer insulating film 17 contact hole 18 emitter electrode 19 rear surface 20 p ⁺ collector layer 21 Collector electrode

Claims (4)

Forming an insulating film having an opening on a semiconductor substrate of a first conductivity type; and forming an epitaxial growth layer of a first conductivity type having an impurity concentration higher than that of the semiconductor substrate on the opening and the insulating film of the semiconductor substrate. A method of manufacturing a semiconductor device, comprising: a step of forming; and a step of laser annealing by irradiating the epitaxial growth layer with laser light. Forming an insulating film having an opening on a semiconductor substrate of the first conductivity type; and the insulating film has a side wall and a portion thinner than the side wall, and the opening of the semiconductor substrate and a thin portion of the insulating film Forming a first conductivity type epitaxial growth layer having an impurity concentration higher than that of the semiconductor substrate on the upper side, a step of grinding and planarizing the epitaxial growth layer using the side wall as a stopper, and a laser on the epitaxial growth layer A method of manufacturing a semiconductor device, comprising the step of laser annealing by irradiating light. The method of manufacturing a semiconductor device according to claim 1 or 2, characterized in that the energy of the laser light is ^{3J / cm 2 ~6J / cm 2} . The laser beam irradiation is a spot, the laser beam spot is irradiated for a predetermined time, and the laser beam is irradiated by moving to the next spot so that the irradiated spot is overlapped. The method for manufacturing a semiconductor device according to claim 1, wherein the spot area is 60% or more of the spot area.

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