JP2008287794A - Semiconductor integrated circuit and operation method thereof - Google Patents

Abstract

To provide a semiconductor integrated circuit including a nonvolatile memory in which a write disturb or an erase disturb is reduced even in a miniaturization process.
A memory gate of a plurality of memory arrays MA <0>, MA <1>, MA <2>... MA <n> in a write unit WU of a nonvolatile memory module NVMU is used for writing or erasing. Are connected to the memory gate line MG <0>. Multiple memory arrays MA <0>, MA <1>, MA <2>... MA <n> source lines SL <0>... SL <n> or multiple column-direction source lines SLB <in the write unit WU 0>... SLB <n> is connected to a plurality of output terminals of a counter COUNT as a write / erase drive circuit. The plurality of output terminals of the counter COUNT drive the plurality of source lines SL <0>... SL <n> or the plurality of column direction source lines SLB <0>.
[Selection] Figure 5

Description

  The present invention relates to a semiconductor integrated circuit incorporating a non-volatile memory and an operation method thereof, and more particularly to a technique useful for reducing write disturb or erase disturb even in a miniaturization process.

  Non-Patent Document 1 describes that MNOS type non-volatile memory based on local trap charge of nitride film (SiN) is a promising candidate for future memory due to scalability, low cost and inherent data reliability. Is described. This cell has a split gate structure having a control gate (CG) MOS and a memory gate (MG) MOS. In writing, hot electrons are injected into the nitride film trap at the edge of the memory gate (MG) by source side injection (SSI). For erasing, hot hole injection is used. Note that MNOS is an abbreviation for Metal Nitride Oxide Semiconductor.

  On the other hand, the following Patent Document 1 discloses a technique for reducing variation in write characteristics due to variation in threshold voltage of a control gate MOS (selection gate MOS) of the MNOS type nonvolatile memory described in Non-Patent Document 1. Are listed. For this reason, in Patent Document 1 below, a high level voltage is applied to the bit line of the non-write target memory cell connected to the same select gate line, the same memory gate line, and the same source line as the write target memory cell. Applied. As a result, the selection MOS transistor of the non-write target memory cell is turned off, thereby prohibiting writing. When writing, a time-division type writing in which a write pulse is sequentially applied to a plurality of bit lines in a state where a voltage necessary for writing is applied to each of a selection gate line, a memory gate line, and a source line to be written. Is executed.

  Japanese Patent Application Laid-Open No. 2004-259259 describes a technique for solving the problem that the amount of hot hole injection during erase is larger than the amount of hot electron injection during writing. For this purpose, in Patent Document 2 below, erase pulses are sequentially applied to a plurality of sectors of the nonvolatile memory. The sector is composed of one row of nonvolatile memory cells, and the selection gate, source, and memory gate of the plurality of nonvolatile memory cells in one sector are the same selection gate line, the same source line, and the same memory. Connected to the gate line.

F. Ito et al, “A Novel MNOS Technology Using Gate Hole Injection in Erase Operation for Embedded Nonvolatile Memory Applications”, 2004 Symposium. 80-81. JP 2004-319065 A International Publication WO 2006/085373 A1 Specification

  Prior to the present invention, the present inventors engaged in the development of a built-in flash memory module mounted on a single chip microcontroller. In this development, the miniaturization process was adopted with a line width of 150 nm to 90 nm of the previous generation. Even in the built-in flash memory module studied at the beginning of this development, the adoption of the write method described in Patent Document 1 was studied. However, when this writing method is adopted in a 90 nm miniaturization process, a problem that writing disturb occurs is clarified.

  When the present inventors examined the cause, the following facts were found. That is, in the write method described in Patent Document 1, a high level voltage is applied to the bit line of the memory cell that is not to be written. Further, a higher voltage is applied to the source line and the memory gate line of the non-write target memory cell. Accordingly, a mechanism has been elucidated in which a leak current is generated between the source and drain of a non-write target memory cell to be turned off and weak writing occurs.

  The present invention has been made as a result of the study of the present inventors prior to the present invention as described above. Accordingly, an object of the present invention is to provide a semiconductor integrated circuit having a built-in nonvolatile memory in which write disturb or erase disturb is reduced even in a miniaturization process.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A typical one of the inventions disclosed in the present application will be briefly described as follows.

  That is, a typical semiconductor integrated circuit of the present invention includes a nonvolatile memory array (MA <0>, MA <1>, MA <2>... MA <n>) and a write / erase circuit (WrCkt <0>. WrCkt <n (y + 1) + y>) and a write / erase drive circuit (COUNT) having a plurality of outputs for driving the source line (see FIG. 5). Upon injection of electrons into the charge storage layers of a plurality of memory cells, the plurality of outputs of the write / erase drive circuit sequentially drive a plurality of source lines (SL <0>... SL <n>) by time division ( (See FIG. 6).

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, it is possible to provide a semiconductor integrated circuit including a nonvolatile memory in which writing disturb or erasing disturb is reduced even in a miniaturization process.

<Typical embodiment>
First, an outline of a typical embodiment of the invention disclosed in the present application will be described. The reference numerals in the drawings referred to with parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A semiconductor integrated circuit according to a typical embodiment of the present invention includes a nonvolatile memory array (MA <0>, MA <1>, MA <2>... MA <n>), a write / erase circuit ( WrCkt <0>... WrCkt <n (y + 1) + y>).

  In the nonvolatile memory array, the gate (MG) is connected to the gate line (MG <0>... MG <x>) in the row direction, and the drain (D) is the bit line (BL <0>... BL <in the column direction). n (y + 1) + y>) and a plurality of memory cells (MM <0, 0>... MM <0) whose sources are connected to source lines (SL <0>... SL <n>) in the column direction. x, n (y + 1) + y>).

  A positive gate voltage (+10 V) is applied to the gates of the plurality of memory cells via the gate line. A positive source voltage (+5 V) is applied to the sources of the plurality of memory cells via the source line. A drain voltage for nonvolatile storage (writing) is supplied to the drains of the plurality of memory cells by the write / erase circuit via the bit lines. Thereby, electrons are injected into the charge storage layers of the plurality of memory cells.

  A negative gate voltage (−5V) is applied to the gates of the plurality of memory cells via the gate line, while a positive source voltage (+ 5V) is applied to the sources of the plurality of memory cells via the source line. ) Is applied. Accordingly, holes are injected from the source into the charge storage layer in the plurality of memory cells, and the electrons injected into the charge storage layer are neutralized by the holes.

  The semiconductor integrated circuit further includes a write / erase drive circuit (COUNT) having a plurality of outputs for driving the source lines in the column direction (see FIG. 5). Upon injection of the electrons into the charge storage layer of the plurality of memory cells, the plurality of outputs of the write / erase drive circuit are connected to a plurality of source lines (SL <0>... SL <n>) in the column direction. Drive sequentially by time division (see FIG. 6).

  According to the means of the above embodiment, when the number of time divisions for source line driving is N, the time during which the positive source voltage is applied during the electron injection is reduced to 1 / N. As a result, the disturbance at the time of electron injection can be reduced.

  In the semiconductor integrated circuit according to a preferred embodiment, when the electrons are injected, the voltage for the nonvolatile storage is selectively applied to the drains of the plurality of memory cells by the write / erase circuit via the bit lines. To supply. Thereby, the injection of the electrons into the charge storage layer of the selected memory cell of the plurality of memory cells is performed.

  In a semiconductor integrated circuit according to another preferred embodiment, a plurality of source / drain current paths of memory cells are connected in parallel between the source line and the bit line.

  A semiconductor integrated circuit according to a more preferred embodiment includes a plurality of source line drivers (SLD <0,0>... SLD <m, n>) and a plurality of row direction source lines (SLA <0>... SLA in the row direction. <M>) and a plurality of column direction source lines (SLB <0>... SLB <n>) in the column direction. Outputs of the plurality of source line drivers are connected to the plurality of source lines (SL <0, 0>... SL <m, n>), and the plurality of row direction source lines in the row direction are the plurality of source line drivers. Is connected to the power terminal. The plurality of column direction source lines in the column direction are connected between input terminals of the plurality of source line drivers and the plurality of outputs of the write / erase drive circuit (see FIG. 7).

  A semiconductor integrated circuit according to another more preferred embodiment includes a plurality of source line transfer MOS transistors (SLTM <0, 0>... SLTM <m, n>) and a plurality of row direction source lines (SLA < 0>... SLA <m>) and a plurality of column direction source lines (SLB <0>... SLB <n>) in the column direction. The plurality of source / drain current paths of the plurality of source line transfer MOS transistors are connected to the plurality of outputs of the write / erase drive circuit and the plurality of source lines (SL) via the plurality of column direction source lines in the column direction. <0, 0>... SL <m, n>). The plurality of gates of the plurality of source line transfer MOS transistors are driven by a plurality of signals of the plurality of row direction source lines in the row direction (see FIG. 9).

  In the semiconductor integrated circuit according to an even more preferred embodiment, the bit line connected to the drain of the plurality of memory cells is a sub bit line (SBL <0>... SBL <n (y + 1) + y>). It is. Between a plurality of main bit lines in the column direction (MBL <0>... MBL <n (y + 1) + y>) and a plurality of sub bit lines, a plurality of bit line MOS transistors (ZM <0>... ZM <n (y + 1) + y>) is connected (see FIG. 11).

  In a semiconductor integrated circuit according to another even more preferred embodiment, the sub-bit line is connected to one main bit line (MBL <0>) with two bit line MOS transistors (ZM <0,0>, ZM < 1, 0>) parallel subbit lines (SBL <0> l SBL <0> r) (see FIG. 13).

  In the semiconductor integrated circuit according to a specific embodiment, the charge storage layer is formed at a deep level near the interface between two types of silicon insulating films.

  In a semiconductor integrated circuit according to a more specific embodiment, the two types of silicon insulating films are a silicon oxide film and a silicon nitride film.

  In a semiconductor integrated circuit according to a more specific embodiment, hot holes are injected from the source into the charge storage layer in order to neutralize the electrons injected into the charge storage layer.

  In the semiconductor integrated circuit according to the most specific embodiment, the injection of the electrons into the charge storage layer of the plurality of memory cells is performed by hot electron source side injection.

  [2] A semiconductor integrated circuit according to a representative embodiment of another aspect of the present invention includes a nonvolatile memory array (MA <0>, MA <1>, MA <2>... MA <n>) and a write An erasing circuit (WrCkt <0>... WrCkt <n (y + 1) + y>) is provided.

  The nonvolatile memory array includes a plurality of memory cells (MM <0, 0>... MM <x) in which a plurality of gates (MG) are connected in parallel to a plurality of gate lines (MG <0>... MG <x>). , 0>, MM <0, y>... MM <x, y>, MM <m (x + 1), n (y + 1) + y> ... MM <m (x + 1) + x, n ( y + 1) + y>). The plurality of source / drain current paths of the plurality of memory cells include a source line (SL <0,0>... SL <m, n>) and a bit line (BL <0>... BL <n (y + 1) + y>) in series.

  A positive gate voltage (+10 V) is applied to the gates of the plurality of memory cells via the gate line. A positive source voltage (+5 V) is applied to the source line. A drain voltage for nonvolatile storage (writing) is supplied to the bit line by the writing / erasing circuit. Thereby, electrons are injected into the charge storage layers of the plurality of memory cells.

  A negative gate voltage (−5V) is applied to the gates of the plurality of memory cells via the gate line, while a positive source voltage (+ 5V) is applied to the source line. Accordingly, holes are injected from the source into the charge storage layer in the plurality of memory cells, and the electrons injected into the charge storage layer by the hole injection are neutralized by the holes.

  The semiconductor integrated circuit further includes a write / erase drive circuit (COUNT) having a plurality of outputs for driving the source line (see FIG. 22). Upon injection of the electrons into the charge storage layer of the plurality of memory cells, the plurality of outputs of the write / erase drive circuit sequentially generate a plurality of source lines (SL <0>... SL <n>) by time division. Drive (see FIG. 23).

  In the semiconductor integrated circuit according to a preferred embodiment, when the electrons are injected, the voltage for the nonvolatile memory is selectively supplied to the plurality of bit lines by the write / erase circuit. Thereby, the injection of the electrons into the charge storage layer of the selected memory cell of the plurality of memory cells is performed.

  In a semiconductor integrated circuit according to a more preferred embodiment, injection of the electrons into the charge storage layer of the plurality of memory cells is performed by hot electron source side injection.

  [3] In a method of operating a semiconductor integrated circuit according to a representative embodiment of another aspect of the present invention, the semiconductor integrated circuit includes a plurality of nonvolatile memory cells on word lines (MG <0>... MG <x>). Non-volatile memory array (MA <0>, MA <1>, MA <2> ... MA <n> to which (MM <0,0> ... MM <x, n (y + 1) + y>) is connected ).

  A corresponding bit line (BL <0>... BL <n (y + 1) + y>) is connected to each drain terminal of the plurality of nonvolatile memory cells.

  A corresponding source line (SL <0>... SL <n>) is connected to each source terminal of the plurality of nonvolatile memory cells.

  In order to write data to the plurality of nonvolatile memory cells, a write voltage is applied to the word line. In the write period, a predetermined write voltage is applied to the bit line in accordance with a value to be written in a nonvolatile memory cell connected to the bit line. The writing period has a first period and a second period. In the first period, a predetermined voltage is applied to one source line, and the predetermined voltage is not applied to the other source line. In the second period after the first period, the predetermined voltage is not applied to the one source line but the predetermined voltage is applied to the other source line (see FIG. 5).

<< Description of Embodiment >>
Next, the embodiment will be described in more detail.

<Single-chip microcontroller>
FIG. 1 is a diagram illustrating a single chip microcontroller according to one embodiment of the present invention. A built-in flash memory as a built-in nonvolatile memory module NVMU is formed on the LSI chip of the single-chip microcontroller together with the CPU and SRAM. The memory module NVMU includes a memory array Array and a control circuit Cnt_CKT. The CPU, SRAM, and built-in nonvolatile memory module NVMU are connected to the bus BUS.

<< Operation of writing, erasing and reading of MNOS non-volatile memory >>
FIG. 2 is a diagram for explaining the write operation of the MNOS nonvolatile memory of the nonvolatile memory module NVMU built in the LSI chip shown in FIG. As shown in FIG. 2, this memory cell has a split gate structure having a control gate (CG) MOS and a memory gate (MG) MOS, and one cell is constituted by two transistors. In FIG. 2, 100 is a selection gate (CG), 101 is a memory gate (MG), 102 is a charge storage layer, 103 is an N-type drain (D), 104 is an N-type source (S), and 105 is a substrate. P-type well. The drain 103 is connected to the bit line BL, and the source 104 is connected to the source line SL. Note that the charge storage layer 102 can be formed of a floating gate formed of polycrystalline silicon. However, due to its scalability, low cost, and inherent data reliability, the charge storage layer 102 has a deep trap level near the interface between two types of silicon insulating films, such as silicon oxide (SiO2) and silicon nitride (Si3N4). It is desirable to form with. When data is written in this memory cell, for example, 1V is applied to the selection gate 100, 10V is applied to the memory gate 101, 0V is applied to the drain 103, 5V is applied to the source 104, and 0V is applied to the substrate 105 as shown in FIG. Then, electrons flow from the drain 103 to the source 104, hot electron source side injection occurs, and the electrons are accumulated in the charge accumulation layer 102 formed at a deep trap level near the interface between the two types of silicon insulating films. The Therefore, the threshold value of the memory cell is increased, and the memory cell current at the time of reading is decreased.

  FIG. 3 is a diagram for explaining the erasing operation of the MNOS nonvolatile memory shown in FIG. When erasing data in a memory cell, as shown in FIG. 3, for example, 0V is applied to the select gate 100, −5V is applied to the memory gate 101, for example, the drain 103 is opened, 5V is applied to the source 104, and 0V is applied to the substrate 105, for example. Apply. Then, a large number of hole electron pairs are generated by the avalanche breakdown of the depletion layer of the reverse bias PN junction of 5 V of the N-type source 104 and 0 V of the P-type well of the substrate 105. That is, a breakdown current flows from the source 104 to the substrate 105, hot holes are generated, and the hot holes are injected into the charge storage layer. The injected hot holes are combined with electrons stored in the charge storage layer 102, and the electrons are eliminated by neutralization. Therefore, the threshold value of the memory cell is lowered and the current of the memory cell at the time of reading is increased. Electrons injected into the charge storage layer formed by the polycrystalline silicon floating gate can be easily released from the charge storage layer by an erasing operation using a low energy FN tunnel phenomenon. Note that FN is an abbreviation for Fowler Nordheim. However, in order to eliminate the electrons injected into the charge storage layer formed in the deep trap level near the interface between the two types of silicon insulating films by neutralization, an erase operation using high energy hot hole injection is effective. It is.

  FIG. 4 is a diagram for explaining a read operation of the MNOS nonvolatile memory shown in FIG. When reading data from a memory cell, as shown in FIG. 4, for example, 1.5V is applied to the selection gate 100, 0V is applied to the memory gate 101, 1V is applied to the drain 103, 0V is applied to the source 104, and 0V is applied to the substrate 105. The magnitude of the memory cell current is determined by a sense amplifier.

<Memory array of built-in flash memory>
FIG. 5 is a diagram showing a configuration of a built-in flash memory as the nonvolatile memory module NVMU built in the LSI chip shown in FIG. The built-in flash memory includes a plurality of memory arrays MA <0>, MA <1>, MA <2> ... MA <n>, and a plurality of write circuits WrCkt <0> ... WrCkt <n (y + 1) + y> And a counter COUNT. The plurality of memory arrays MA <0>, MA <1>, MA <2>... MA <n> are composed of a plurality of P-type wells. A plurality of memory cells MM <0,0> ... MM <x, n (y) arranged in a matrix shape inside a plurality of memory arrays MA <0>, MA <1>, MA <2> ... MA <n> +1) + y> performs the write operation shown in FIG. 2, the erase operation shown in FIG. 3, and the read operation shown in FIG.

  Note that the plurality of memory arrays MA <0>, MA <1>, MA <2>... MA <n> do not need to be formed on different well regions for each memory array. That is, all the memory arrays can be formed on one well region or on every two or more memory arrays. This is the same in other embodiments.

  A plurality of memory arrays MA <0>, MA <1>, MA <2>... MA <n>, a selection gate line CG <0>... CG <x> and a memory gate line MG <0>. > Is arranged in the row direction, and bit lines BL <0>... BL <n (y + 1) + y> are arranged in the column direction. The plurality of memory gate lines MG <0>... MG <x> in the row direction are also word lines.

  A plurality of bit lines BL <0>... BL <n (y + 1) + y> in the column direction are connected to a plurality of write circuits WrCkt <0>... WrCkt <n (y + 1) arranged at the bottom of FIG. connected to + y>. Although not shown in FIG. 5, a plurality of bit lines BL <0>... BL <n (y + 1) + y> in the column direction include sense circuits, data registers, column selection circuits, and data input / output buffers. Is connected. The sense circuit determines the magnitude of the memory cell current by reading a plurality of memory cells MM <0,0>,..., MM <x, n (y + 1) + y>, and the data register is a nonvolatile memory module NVMU. Is used to hold memory cell storage information to be saved before erasing data. The column selection circuit is driven by a decode output signal of a Y address decoder to which a Y address signal is supplied, and a data input / output buffer is used for a data interface of a bus BUS between the nonvolatile memory module NVMU and the CPU.

  Although not shown in FIG. 5, a plurality of selection gate lines CG <0>... CG <x> in the row direction are a plurality of word selection gates supplied with a decode signal of an X address decoder supplied with an X address signal. Connected to driver output. Although not shown in FIG. 5, the plurality of memory gate lines MG <0>... MG <x> in the row direction are supplied with decode signals of a write / erase address decoder to which write / erase address signals are supplied. Connected to the outputs of a plurality of write / erase drivers. Therefore, for example, a plurality of memory cells MM <0, 0>,..., MM <0, y>... MM <0, n (y + 1))>,..., MM <0, n (y + 1) + y> constitute one write unit WU. That is, the memory gates of the memory cells of the plurality of memory arrays MA <0>, MA <1>, MA <2>... MA <n> of the plurality of write units WU are connected to the memory gate line MG < 0> ... connected to MG <x>. Further, the selection gates of the memory cells of the plurality of memory arrays MA <0>, MA <1>, MA <2>... MA <n> of the plurality of write units WU are selected by the selection gate line CG <0. > ... connected to CG <x>.

  In the prior art of the present invention, the sources of a plurality of memory cells of one write unit WU are connected to the same source line as described in Patent Document 1 and Patent Document 2. On the other hand, in the nonvolatile memory module NVMU of FIG. 5 which is one embodiment of the present invention, there is one source of the plurality of memory cells in one memory array MA <0> of the write unit WU. Source line SL <0>. The plurality of sources of the plurality of memory cells inside one other memory array MA <n> of the write unit WU are connected to the other one source line SL <n>, and the other memory of the write unit WU The same applies to arrays MA <1>, MA <2>, and so on. A plurality of source lines SL <0>... SL <n> of the write unit WU are connected to a plurality of output terminals of a counter COUNT as a write / erase drive circuit. A plurality of output terminals of the counter COUNT as a write / erase drive circuit drive a plurality of source lines SL <0>.

  In the nonvolatile memory module NVMU shown in FIG. 5, all the memory cells in one memory array MA <0> can be erased simultaneously, and the other memory arrays MA <1>, MA <2>,. The same applies to <n>. Therefore, the memory arrays MA <0>, MA <1>, MA <2>,..., MA <n> are erase blocks as erase units.

  In the nonvolatile memory module NVMU of FIG. 5, a plurality of memory cells MM <0,0> are provided between the bit line BL <0> and the source line SL <0> within one memory array MA <0>. ... source / drain current paths of MM <x, 0> are connected in parallel. When a plurality of memory cells MM <0,0>... MM <x, 0> are composed of N-channel MOS transistors, a high threshold voltage is defined as a write state, and a low threshold voltage is defined as an erase state. A type memory array is formed. Conversely, when the low threshold voltage is set to the write state and the high threshold voltage is defined to be the erased state, an AND type memory array is formed.

<Internal flash memory write operation>
FIG. 6 is a waveform diagram of each part of the built-in flash memory for explaining the write operation of the nonvolatile memory module NVMU of FIG. The memory cells to be written in this case are internal to a plurality of memory arrays MA <0>,..., MA <n> commonly connected to one select gate line CG <0> in the nonvolatile memory module NVMU of FIG. MM <0, 0>,..., MM <0, y>... MM <0, n (y + 1)>,..., MM <0, n (y + 1) + y> .

  Accordingly, as shown in FIG. 6, for example, 1V is applied to the selection gate line CG <0>, 10V is applied to the memory gate line MG <0>, and 0V is applied to the bit line BL <0>... BL <n (y + 1)>. Is applied. Here, since no data is written in the memory cells MM <0, n (y + 1) +1>... MM <0, n (y + 1) + y>, as shown in FIG. For example, 1.5 V is applied to n (y + 1) +1>... BL <n (y + 1) + y>. After that, a write pulse with a voltage (5 V) and time optimal for writing generated by the counter COUNT as a writing / erasing drive circuit is sequentially applied to the source lines SL <0>... SL <n>. Further, the selection gate line CG <1>... CG <x>, the memory gate line MG <connected to the memory cells MM <1, 0>... MM <x, n (y + 1) + y> that are not to be written. For example, 0V is applied to 1>... MG <x> as shown in FIG. As described above, in the embodiment shown in FIGS. 5 and 6, the sources of the memory cells in the plurality of memory arrays MA <0>,..., MA <n> in the write unit WU are set by the counter COUNT. It is driven by division. Therefore, in this embodiment, the application time for simultaneously applying the write high voltage to the source at a specific time in a plurality of memory cells to be written at the time of writing is reduced to 1 / (n + 1) compared to the conventional case. In this way, the write disturb can be reduced.

《Built-in flash memory of memory array with source line hierarchy》
FIG. 7 is a diagram showing a configuration of a nonvolatile memory module NVMU according to another embodiment of the present invention. The non-volatile memory module of FIG. 7 basically differs from the non-volatile memory module shown in FIG. 5 in that it employs a source line hierarchical structure, and the others are basically the same.

  In the nonvolatile memory module NVMU shown in FIG. 7, a plurality of memory arrays MA <0>,..., MA <n> include a plurality of row direction source lines SLA <0>... SLA <m> and a plurality of column direction sources. Lines SLB <0>... SLB <n> are connected. The plurality of row-direction source lines SLA <0>... SLA <m> are connected to a source high voltage supply circuit that supplies a high voltage of 5 V to the source of the memory cell when writing / erasing, although not shown. A plurality of column direction source lines SLB <0>... SLB <n> are connected to a plurality of output terminals of a counter COUNT as a write / erase drive circuit. Within a plurality of memory arrays MA <0>,..., MA <n>, a plurality of row direction source lines SLA <0>... SLA <m> and a plurality of column direction source lines SLB <0>. A plurality of source line drivers SLD <0,0>... SLD <m, n> are arranged at the intersections. Sources of multiple source line drivers SLD <0,0> ... SLD <m, n> are connected to multiple row direction source lines SLA <0> ... SLA <m>, and NMOS source is connected to ground voltage Is done. The gates of the PMOS and NMOS of the plurality of source line drivers SLD <0,0>... SLD <m, n> are connected to the plurality of column-direction source lines SLB <0>. The drains of the PMOS and NMOS of the plurality of source line drivers SLD <0,0>, SLD <0, n>, SLD <m, 0>, SLD <m, n> are the plurality of source lines SL <0,0>. , SL <0, n>, SL <m, 0>, SL <m, n>. Inside the memory array MA <0>, the source lines SL <0,0> are connected to the memory cells MM <0,0>,... MM <0, y> in the row direction, and the source lines SL <0,0 > Is connected to the memory cells MM <0,0>,..., MM <x, 0> in the column direction. Inside the memory array MA <n>, the source lines SL <m, n> are memory cells MM <m (x + 1), n (y + 1)>,..., MM <m (x + 1) in the row direction. ), N (y + 1) + y>. Inside the memory array MA <n>, the source lines SL <m, n> are memory cells MM <m (x + 1), n (y + 1)>,..., MM <m (x + 1) in the column direction. ) + x, n (y + 1)>.

<< Write operation of built-in flash memory with source line hierarchy >>
FIG. 8 is a waveform diagram of each part of the built-in flash memory for explaining the write operation of the nonvolatile memory module NVMU having the source line hierarchical structure of FIG. The source lines SL <0,0>, SL <0,1>, SL <0,2>,..., SL <0, n> are driven to a high level of 5 V in a time division manner. Compared with the waveform diagram of FIG. 6, in the waveform diagram of FIG. 8, a plurality of column direction source lines SLB <0>, SLB <1>, SLB <2>,. It is characterized by being driven to 0V of the level.

《Built-in flash memory of memory array with source line hierarchy using transfer MOS》
FIG. 9 is a diagram showing a configuration of a nonvolatile memory module NVMU according to another embodiment of the present invention. 9 is basically different from the nonvolatile memory module shown in FIG. 7 in that the source line drivers SLD <0,0>... SLD <m, n> in FIG. The line transfer MOS transistors SLTM <0,0>... SLTM <m, n> are replaced, and the others are basically the same. That is, in FIG. 9, a plurality of row direction source lines SLA <0>... SLA <m> and a plurality of column direction source lines SLB <0>. A plurality of source line transfer MOS transistors SLTM <0,0>... SLTM <m, n> are arranged at the intersection with SLB <n>. The source line transfer MOS transistors SLTM <0,0>... SLTM <m, n> are composed of N-channel MOS transistors.

<< Write operation of internal flash memory with source line hierarchy using transfer MOS >>
FIG. 10 is a waveform diagram of each part of the built-in flash memory for explaining the write operation of the nonvolatile memory module NVMU having the source line hierarchical structure of FIG. The source lines SL <0,0>, SL <0,1>, SL <0,2>,..., SL <0, n> are driven to a high level of 5 V in a time division manner. Compared to the waveform diagram of FIG. 8, in the waveform diagram of FIG. 10, a plurality of column direction source lines SLB <0>, SLB <1>, SLB <2>,..., SLB <n> are time-divided by the counter COUNT. It is characterized by being driven to 5V of the level.

<Built-in flash memory in bit line hierarchical memory array>
FIG. 11 is a diagram showing a configuration of a nonvolatile memory module NVMU according to another embodiment of the present invention. The nonvolatile memory module of FIG. 11 basically differs from the nonvolatile memory module shown in FIG. 9 in that it employs a bit line hierarchical structure, and the others are basically the same.

  That is, in FIG. 11, sub-bit lines SBL <0>, SBL <y>... SBL <n (y + 1)>, SBL <n (y + 1) + y> Transistors ZM <0>, ZM <y> ... ZM <n (y + 1)>, ZM <n (y + 1) + y> through main bit lines MBL <0>, MBL <y> ... MBL These are connected to <n (y + 1)> and MBL <n (y + 1) + y>, respectively. The gates of the bit line MOS transistors ZM <0>, ZM <y>... ZM <n (y + 1)>, ZM <n (y + 1) + y> are common to the bit line gate signal line Z. It is connected. In the memory array MA <0>, the subbit line SBL <0> is connected to the memory cells MM <0,0>,... MM <x, 0> in the column direction, and the subbitline SBL <y > Is connected to memory cells MM <0, y>,..., MM <x, y>.

<< Write operation of internal flash memory with bit line hierarchy >>
FIG. 12 is a waveform diagram of each part of the built-in flash memory for explaining the write operation of the nonvolatile memory module NVMU having the bit line hierarchical structure of FIG. Compared with the waveform diagram of FIG. 10, in the waveform diagram of FIG. 12, for writing, the main bit lines MBL <0>, MBL <y>... MBL <n (y + 1)> are set to a low level of 0V by the write circuit. The bit line gate signal line Z is driven and is driven to a high level of 1.5V. As a result, the sub bit lines SBL <0>, SBL <y>... SBL <n (y + 1)> are also driven to the low level of 0V.

<< Built-in flash memory of memory array with parallel subbit line hierarchy >>
FIG. 13 is a diagram showing a configuration of a nonvolatile memory module NVMU according to another embodiment of the present invention. The nonvolatile memory module of FIG. 13 basically differs from the nonvolatile memory module shown in FIG. 11 in that it employs a parallel sub-bit line hierarchical structure, and the others are basically the same. . That is, two parallel sub-bit lines in parallel are connected to one main bit line.

  For example, in FIG. 13, in the memory array MA <0>, two parallel sub-lines are connected to the main bit line MBL <0> via the bit line MOS transistors ZM <0,0> and ZM <1,0>. Bit lines SBL <0> l and SBL <0> r are connected. Further, two parallel sub-bit lines SBL <y> l and SBL <y> r are connected to the main bit line MBL <y> via bit line MOS transistors ZM <0, y> and ZM <1, y>. Is connected. A charge PMOS transistor CM <0,0> and memory cells MM <0,0> l,... MM <x, 0> l are connected to one parallel subbit line SBL <0> l. A charge PMOS transistor CM <1, 0> and memory cells MM <0, 0> r,..., MM <x, 0> r are connected to the other parallel subbit line SBL <0> r. The gates of the bit line MOS transistors ZM <0,0>, ZM <0, y> are commonly connected to the bit line gate signal line Z <0>, and the bit line MOS transistors ZM <1,0>, ZM <1 , Y> are commonly connected to the bit line gate signal line Z <1>. The gates of the charge PMOS transistors CM <0,0> and CM <0, y> are commonly connected to the charge control signal C <0>, and the charge PMOS transistors CM <1,0> and CM <1, y> Are commonly connected to the charge control signal C <1>. Other memory arrays MA <1>, MA <2>... MA <n> are configured in the same manner as the memory array MA <0>.

<< Write operation of built-in flash memory with parallel subbit line hierarchy >>
FIG. 14 is a waveform diagram of each part of the built-in flash memory for explaining the write operation of the nonvolatile memory module NVMU having the parallel subbit line hierarchical structure of FIG. In the write operation according to the waveform diagram of FIG. 14, memory cells MM <0,0> l,..., MM <x, 0> l connected to one parallel sub-bit line SBL <0> l are to be written. . However, the memory cells MM <0,0> r,..., MM <x, 0> r connected to the other parallel subbit line SBL <0> r are not written. Therefore, in comparison with the waveform diagram of FIG. 12, in the waveform diagram of FIG. 14, the charge control signal C <0> is controlled to a high level of 1.5V and connected to one parallel sub-bit line SBL <0> l. The charge PMOS transistor CM <0, 0> is turned off. In the waveform diagram of FIG. 14, the bit line gate signal line Z <0> is controlled to a high level of 1.5V, and the bit line MOS transistor ZM <0 connected to one parallel subbit line SBL <0> l. , 0> is turned on. As a result, one of the sub-bit lines SBL <0> l, SBL <y> l... SBL <n (y + 1)> l connected to the memory cell to be written is also driven to 0V at the low level. However, one sub-bit line SBL <0> r, SBL <y> r... SBL <n (y + 1) + y> r connected to the non-write target memory cell is controlled to a high level of 1.5V. The

<Write circuit>
FIG. 15 is a diagram showing a configuration of a write circuit of the nonvolatile memory module NVMU according to the various embodiments of the present invention. For example, the write circuit includes a plurality of write circuits WrCkt <0>... WrCkt <n (y) connected to a plurality of bit lines BL <0>... BL <n (y + 1) + y> in the column direction in FIG. +1) + y>. In addition, in FIG. 11, the write circuit supplies a plurality of main bit lines MBL <0>, MBL <y>... MBL <n (y + 1)>, MBL <n (y + 1) + y> in the column direction. It can also be used as a plurality of connected write circuits WrCkt <0>... WrCkt <n (y + 1) + y>.

  The write circuit of FIG. 15 includes a non-inverted latch signal Latsw, NMOS Qn1 and PMOS Qp1 whose gates are driven by an inverted latch signal Latsw_n, and a write latch Wr_Latch with two cross-coupled inverters. Prior to the writing of the nonvolatile memory module NVMU, the write data DB is stored in the write latch Wr_Latch via the NMOS Qn1 and the PMOS Qp1 from the bus BUS connected to the CPU. Thereafter, when writing to the nonvolatile memory module NVMU, the bit line BL or the main bit line MBL can be driven by the write data stored in the write latch Wr_Latch.

  FIG. 16 is a diagram showing the configuration of the write circuit of the nonvolatile memory module NVMU according to the above-described various embodiments of the present invention, as in FIG. The write circuit of FIG. 16 uses the circuit shown in FIG. 15 for storing the write data DB, while the write drive for driving the bit line BL or the main bit line MBL in the subsequent write of the nonvolatile memory module NVMU. Includes circuitry. This write drive circuit includes PMOS Qp2, Qp3, NMOS Qn2, Qn3, and Qn4. The gate of NMOS Qn3 and the gate of PMOS Qp2 are supplied with an enable signal Enb and an inverted enable signal Enb_n for driving, respectively. The NMOS Qn2 gate and the PMOS Qp3 gate are supplied with an output signal of a write latch Wr_Latch by two cross-coupled inverters. The NMOS Qn4 connected between the drain of the NMOS Qn2 and the drain of the PMOS Qp3 is supplied with the write constant voltage Wri trimmed with high precision, so that the NMOS Qn4 has a constant current for high precision write. Will flow.

<< Counter as write / erase drive circuit >>
FIG. 17 is a diagram showing a configuration of a counter COUNT as a write / erase drive circuit of the nonvolatile memory module NVMU according to the various embodiments of the present invention. For example, the counter COUNT drives a plurality of source lines SL <0>... SL <n> in the column direction in FIG. Further, the counter COUNT can also drive, for example, a plurality of column-direction source lines SLB <0>... SLB <n> in the column direction in FIG.

  The counter COUNT in FIG. 17 includes an oscillator OSC, a frequency dividing circuit DIV, a selector SEL, a write pulse generation circuit WPG, shift registers SR0... SRn, and level converters LC0.

  The oscillator OSC generates a clock signal with a constant frequency, and the divider circuit DIV generates a divided clock output signal with a period of 2 times, 4 times, 8 times,..., 2n times from the clock signal from the oscillator OSC. Generate. The selector SEL selects and outputs one divided clock output signal from the plurality of divided clock output signals output from the divider circuit DIV based on the write pulse select signal SEL_SIG. The write pulse generation circuit WPG generates a write pulse having a predetermined pulse width from the clock output from the selector SEL. The write pulse from the write pulse generation circuit WPG is sequentially delayed by a plurality of shift registers SR0... SRn connected in series. The clock from the selector SEL is supplied as a shift clock to the plurality of shift registers SR0... SRn. A small amplitude signal of 1.5 V at each output of the plurality of shift registers SR0... SRn is converted into a large amplitude signal of 5 V by the level converter LC0... LCn, and a plurality of source lines SL <0>. Used for time division driving of a plurality of column direction source lines SLB <0>... SLB <n>.

<Single-chip microcontroller>
FIG. 18 is a diagram showing a configuration of a single chip microcontroller including the nonvolatile memory module NVMU as the built-in flash memory FLASH according to the above-described various embodiments of the present invention.

  In the single-chip microcontroller shown in FIG. 18, programs and fixed data to be executed by the CPU are stored in a read-only memory ROM, and calculation results and CPU work areas are secured by a random access memory RAM. The flash memory FLASH stores application programs used by application systems such as automobiles, and also stores operation information of application systems. Further, the flash memory FLASH can also store a control program for writing, erasing and rewriting the flash memory.

  Data transfer between an internal memory such as ROM, RAM, FLASH, etc. and the main memory of the system (not shown) is performed by block transfer in a predetermined transfer unit by the direct memory access controller DMAC. The single-chip microcontroller has a serial communication interface circuit SCI, a timer TIMER, and a clock pulse generation circuit CPG as peripheral circuits. These internal circuits and the outside of the chip are connected via input / output ports IOP1 to IOP9. In this microcontroller, the CPU, FLASH, ROM, RAM, DMAC, and some input / output ports IOP1... IOP5 are connected by an internal address bus IAB and an internal data bus IDB. Further, peripheral circuits such as SCI and TIMER and the input / output ports IOP1... IOP9 are connected by a peripheral address bus PAB and a peripheral data bus PDB. Furthermore, this microcontroller has a bus sequence controller BSC that controls the state of these buses along with control of signal transfer using the internal address bus IAB, internal data bus IDB, peripheral address bus PAB, and peripheral data bus PDB. Contains.

<< Write, Erase, and Read Operations of MNOS Nonvolatile Memory with Other Structure >>
FIG. 19 is a diagram illustrating a write operation of the MNOS nonvolatile memory having another structure that can be used in the nonvolatile memory module NVMU according to the various embodiments of the present invention. The MNOS nonvolatile memory having the structure shown in FIG. 19 does not have a split gate structure, but constitutes one cell with a single transistor.

  The MNOS nonvolatile memory having the structure shown in FIG. 19 includes a memory gate 201, a charge storage layer 202, an N-type drain 203, an N-type source 204, and a P-type well 205 as a substrate. The drain 203 is connected to the bit line BL, and the source 204 is connected to the source line SL. The charge storage layer 202 includes a nitride film. When data is written in the memory cell, for example, 10V is applied to the memory gate 201, 0V is applied to the drain 203, 5V is applied to the source 204, and 0V is applied to the substrate 205, as shown in FIG. Then, electrons flow from the drain 203 to the source 204, hot electron source side injection occurs, and electrons are accumulated in the charge accumulation layer 202. Therefore, the threshold value of the memory cell is increased, and the memory cell current at the time of reading is decreased. Note that the charge storage layer 202 can be formed of a floating gate. However, it is desirable to form the charge storage layer 202 with a deep trap level near the interface between the two types of silicon insulating films.

  FIG. 20 is a diagram for explaining the erasing operation of the MNOS nonvolatile memory shown in FIG. When erasing the data in the memory cell, as shown in FIG. 20, for example, −5V is applied to the memory gate 201, the open state is applied to the drain 203, 5V is applied to the source 204, and 0V is applied to the substrate 205, for example. Then, a large number of hole electron pairs are generated due to the avalanche breakdown of the depletion layer of the reverse bias PN junction of 5 V of the N-type source 204 and 0 V of the P-type well of the substrate 205. That is, a breakdown current flows from the source 204 to the substrate 205, hot holes are generated, and the hot holes are injected into the charge storage layer 202. The injected hot holes are combined with the electrons accumulated in the charge storage layer 202 and disappear. Therefore, the threshold value of the memory cell is lowered and the current of the memory cell at the time of reading is increased. In addition, by erasing operation using high energy hot hole injection, electrons injected into the charge storage layer 202 formed at a deep trap level near the interface between the two types of silicon insulating films are effectively eliminated by neutralization. be able to.

  FIG. 21 is a diagram for explaining the read operation of the MNOS nonvolatile memory shown in FIG. When reading data from a memory cell, as shown in FIG. 21, for example, 0V is applied to the memory gate 201, 1V is applied to the drain 203, 0V is applied to the source 204, and 0V is applied to the substrate 205, and the magnitude of the memory cell current is sensed. Judge with amplifier.

《Built-in flash memory memory array with single transistor cell》
FIG. 22 is a diagram showing a configuration of a built-in flash memory as a nonvolatile memory module NVMU using the MNOS nonvolatile memory having the single transistor cell structure shown in FIGS.

  Compared to the nonvolatile memory module shown in FIG. 9, in FIG. 22, a plurality of memory cells are connected in series. That is, in the nonvolatile memory module shown in FIG. 22, a plurality of memory cells MM <0 in the column direction are arranged between the bit line BL <0> and the source line SL <0> in one memory array MA <0>. , 0>, MM <1, 0>,..., MM <x−1, 0>, MM <x, 0> are connected in series. A plurality of memory cells MM <0,0>, MM <1,0>,..., MM <x−1,0>, MM <x, 0> connected in series in the column direction are configured by N-channel MOS transistors. When a high threshold voltage is set as a writing state and a low threshold voltage is defined as an erasing state, a NAND type memory array is formed.

  A plurality of memory cells MM <0,0>, MM <1,0>,..., MM <x−1,0>, MM <x, 0> and a bit line BL <0> connected in series in the column direction A bit line selection NMOS transistor BLSM <0, 0> is connected between them. A plurality of similar bit line selection NMOS transistors BLSM <0,0>, BLSM <0, y>,... BLSM <0, n (y + 1)>, BLSM <0, n (y + 1) + y> The gates are connected to a common bit select line BLS <0>. In addition, a plurality of memory cells MM <0,0>, MM <1,0>,..., MM <x−1,0>, MM <x, 0> connected in series are memory gate lines. MG <0>, MG <1>,..., MG <x−1>, and MG <x>, respectively. Further, the memory cells MM <0,0>... MM <0, n (y + 1) + y> in the row direction in which the gates are connected to the memory gate line MG <0> in the row direction are one write unit WU. Is configured. However, in one write unit WU, time division writing is performed by a plurality of column direction source lines SLB <0>... SLB <n> connected to a counter COUNT as a write / erase drive circuit.

<Built-in flash memory write operation with single transistor cell>
FIG. 23 is a waveform diagram of each part of the built-in flash memory for explaining the write operation of the nonvolatile memory module NVMU of FIG. 23, the memory cell MM <x, 0 connected to the memory gate line MG <x> and the bit line BL <0>,..., BL <n (y + 1) + y>. >... MM <x, n (y + 1) + y> is set as a write target, and other memory cells are set as non-write targets.

  As shown in the waveform diagram of FIG. 23, for example, a write voltage of 10 V is applied to the memory gate line MG <x> of the memory cell MM <x, 0>... MM <x, n (y + 1) + y> to be written. On the other hand, the memory gate lines MG <0>... MG <x−1> of the non-write target memory cell have a turn-on voltage of, for example, 5 V so that the MOS transistor is turned on without writing in the memory cell. Apply. The row direction source lines SLA <0> are driven to a high level of, for example, 10 V from the plurality of row direction source lines SLA <0>... SLA <m>, and the other row direction source lines SLA <1>. It is maintained at a low level of 0V. Further, the bit selection line BLS <0> is driven to a high level of 1.5V, for example, and the other bit selection lines BLS <1>... BLS <m> are maintained at a low level of 0V. In this state, the plurality of column-direction source lines SLB <0>, SLB <1>, SLB <2>,..., SLB <n> are driven to high level 5V by the counter COUNT in a time division manner. Therefore, the source lines SL <0,0>, SL <0,1>, SL <0,2>,..., SL <0, n> are driven to a high level of 5 V in a time division manner. Further, for example, 0V is applied to the bit lines BL <0>... BL <n (y + 1)>, while other bit lines BL <n (y + 1) +1>... BL <n (y + 1) For example, 1.5V is applied to + y>. Then, hot electrons are time-divided into memory cells MM <x, 0>... MM <x, n (y + 1)> to be written connected to the memory gate line MG <x> to which a write voltage of 10V is applied. Writing by source side injection occurs. Therefore, also in this embodiment, the application time for simultaneously applying the write high voltage to the source at a specific time in a plurality of memory cells to be written is reduced to 1 / (n + 1) as compared with the conventional case. Thus, the write disturb can be reduced.

<< Erase operation of built-in flash memory by single transistor cell >>
FIG. 24 is a waveform diagram of each part of the built-in flash memory for explaining the erase operation of the nonvolatile memory module NVMU of FIG. 24, the memory cells MM <0, 0>... MM <0, n (y + 1) connected to the memory gate lines MG <0>, MG <1>. + y>, MM <1,0> ... MM <1, n (y + 1) + y>, ..., MM <x, 0> ... MM <x, n (y + 1) + y> It is said.

  As shown in the waveform diagram of FIG. 24, in order to erase the memory cells MM <0, 0>... MM <0, n (y + 1) + y> connected to the memory gate line MG <0> An erase voltage of, for example, −5V is applied to the line MG <0>. The row direction source lines SLA <0> are driven to a high level of, for example, 10 V from the plurality of row direction source lines SLA <0>... SLA <m>, and the other row direction source lines SLA <1>. It is maintained at a low level of 0V. All the bit selection lines BLS <0>... BLS <m> are maintained at a low level of 0V. In this state, the plurality of column-direction source lines SLB <0>, SLB <1>, SLB <2>,..., SLB <n> are driven to high level 5V by the counter COUNT in a time division manner. Therefore, the source lines SL <0,0>, SL <0,1>, SL <0,2>,..., SL <0, n> are driven to a high level of 5 V in a time division manner. As a result, the erase operation by hot hole injection in a plurality of memory arrays MA <0>, MA <1>, MA <2>... MA <n> connected to the memory gate line MG <0> is time-shared. Will be executed. Next, in order to erase the memory cells MM <1, 0>... MM <1, n (y + 1) + y> connected to the memory gate line MG <1>, the memory gate line MG <1> Apply -5V erase voltage. Similarly, erase operation by hot hole injection in a plurality of memory arrays MA <0>, MA <1>, MA <2>... MA <n> connected to the memory gate line MG <1> is time-shared. Run with. Finally, in order to erase the memory cells MM <x, 0>... MM <x, n (y + 1) + y> connected to the memory gate line MG <x>, for example, the memory gate line MG <x> Apply -5V erase voltage. Similarly, erase operation by hot hole injection in a plurality of memory arrays MA <0>, MA <1>, MA <2>... MA <n> connected to the memory gate line MG <x> is time-shared. Run with.

  FIG. 25 is a waveform diagram of each part of the built-in flash memory for explaining the erase operation of the nonvolatile memory module NVMU of FIG. The erase operation according to the waveform diagram of FIG. 25 is substantially the same as the erase operation according to the waveform diagram of FIG. 24, but the drive pulses of the plurality of column direction source lines SLB <0>, SLB <1>... SLB <n> overlap. The drive pulses of the plurality of source lines SL <0,0>, SL <0,1>,... SL <0, n> are also overlap pulses. Thereby, the entire erasing time can be shortened.

<< Erasing operation in parallel in row direction and time division in column direction >>
FIG. 26 is a waveform diagram of each part of the built-in flash memory for explaining the erase operation of the nonvolatile memory module NVMU of FIG. 26, the memory cells MM <0, 0>... MM <0, n (y + 1) connected to the memory gate lines MG <0>, MG <1>. + y>, MM <1,0> ... MM <1, n (y + 1) + y>, ..., MM <x, 0> ... MM <x, n (y + 1) + y> It is targeted for erasure. However, in the erase operation according to the waveform diagram of FIG. 26, row-direction parallel and column-direction time-division erase operations are executed.

  As shown in the waveform diagram of FIG. 26, a plurality of memory cells connected to a plurality of memory gate lines MG <0>, MG <1>... MG <x> in the row direction are erased in parallel. For example, an erase voltage of −5V is applied in parallel to the plurality of memory gate lines MG <0>, MG <1>... MG <x>. The row direction source lines SLA <0> are driven to a high level of, for example, 10 V from the plurality of row direction source lines SLA <0>... SLA <m>, and the other row direction source lines SLA <1>. It is maintained at a low level of 0V. All the bit selection lines BLS <0>... BLS <m> are maintained at a low level of 0V. In this state, the plurality of column-direction source lines SLB <0>, SLB <1>, SLB <2>,..., SLB <n> are driven to high level 5V by the counter COUNT in a time division manner. Therefore, the source lines SL <0,0>, SL <0,1>, SL <0,2>,..., SL <0, n> are driven to a high level of 5 V in a time division manner. As a result, a plurality of memory arrays MA <0>, MA <1>, MA <2>... MA <connected to a plurality of memory gate lines MG <0>, MG <1>. The erase operation by hot hole injection when n> is executed in a time-sharing manner.

  FIG. 27 is a waveform diagram of each part of the built-in flash memory for explaining the erase operation of the nonvolatile memory module NVMU of FIG. The erase operation according to the waveform diagram of FIG. 27 is substantially the same as the erase operation according to the waveform diagram of FIG. 26, but the drive pulses of the plurality of column direction source lines SLB <0>, SLB <1>... SLB <n> overlap. The drive pulses of the plurality of source lines SL <0,0>, SL <0,1>,... SL <0, n> are also overlap pulses. Thereby, the entire erasing time can be shortened.

<< Counter as write / erase drive circuit >>
FIG. 28 is a diagram showing a configuration of a counter COUNT as a write / erase drive circuit of the nonvolatile memory module NVMU according to the embodiment of the present invention shown in FIG.

  The counter COUNT in FIG. 28 includes an oscillator OSC, a frequency divider DIV, a pulse width selector PW_SEL, a pulse shift selector PS_SEL, a pulse generation circuit PG, shift registers SR0... SRn, and level converters LC0.

  The oscillator OSC generates a clock signal with a constant frequency, and the divider circuit DIV generates a divided clock output signal with a period of 2 times, 4 times, 8 times,..., 2n times from the clock signal from the oscillator OSC. Generate. Based on the pulse width select signal PW_SEL_SIG, the pulse width selector PW_SEL selects and outputs one divided clock output signal from a plurality of divided clock output signals having different periods output from the divider circuit DIV. The pulse shift selector PS_SEL selects one clock output signal from a plurality of clock output signals having different frequencies output from the frequency divider DIV based on the pulse shift select signal PS_SEL_SIG and outputs it to the signal line A. The pulse generation circuit PG generates a pulse having a predetermined pulse width on the signal line B from the clock output from the pulse width selector PW_SEL. Pulses from the pulse generation circuit PG of the signal line B are sequentially delayed by a plurality of shift registers SR0... SRn connected in series. Note that the clock from the pulse shift selector PS_SEL of the signal line A is supplied as a shift clock to the plurality of shift registers SR0... SRn. A 1.5 V small amplitude signal at each output of the plurality of shift registers SR0... SRn is converted into a 5 V large amplitude signal by the level converter LC0... LCn, and a plurality of column-direction source lines SLB <0>. > Used for time-division driving.

  FIG. 29 is a diagram showing waveforms at various parts of the counter COUNT as the write / erase drive circuit shown in FIG. FIG. 29 shows a case where the pulse width of the divided clock output signal of the signal line B is longer than the delay amount of the signal line A by the pulse shift clock PS. The waveform obtained by sequentially delaying the divided clock output signal of the signal line B by the delay amount by the pulse shift clock PS of the signal line A is changed from the level converter LC0 ... LCn to the column direction source lines SLB <0> ... SLB <n>. Supplied.

  FIG. 30 is a diagram showing waveforms at various parts of the counter COUNT as the write / erase drive circuit shown in FIG. 28, as in FIG. In FIG. 30, the pulse width of the divided clock output signal of the signal line B is substantially the same as the delay amount by the pulse shift clock PS of the signal line A. The waveform obtained by sequentially delaying the divided clock output signal of the signal line B by the delay amount by the pulse shift clock PS of the signal line A is changed from the level converter LC0 ... LCn to the column direction source lines SLB <0> ... SLB <n>. Supplied.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, if a plurality of memory cells are composed of N-channel MOS transistors and the low threshold voltage is set to the write state and the high threshold voltage is defined to be the erase state, the erase disturb can be reduced during the erase operation.

  Furthermore, the present invention can be applied to a system LSI, a SoC (system on chip), and a large-capacity nonvolatile memory for files that incorporate a nonvolatile memory module in addition to a single chip microcontroller that incorporates a nonvolatile memory module.

FIG. 1 is a diagram illustrating a single chip microcontroller according to one embodiment of the present invention. FIG. 2 is a diagram for explaining the write operation of the MNOS nonvolatile memory of the nonvolatile memory module built in the LSI chip shown in FIG. FIG. 3 is a diagram for explaining the erasing operation of the MNOS nonvolatile memory shown in FIG. FIG. 4 is a diagram for explaining a read operation of the MNOS nonvolatile memory shown in FIG. FIG. 5 is a diagram showing a configuration of a built-in flash memory as a nonvolatile memory module built in the LSI chip shown in FIG. FIG. 6 is a waveform diagram of each part of the built-in flash memory for explaining the write operation of the nonvolatile memory module of FIG. FIG. 7 is a diagram showing a configuration of a nonvolatile memory module according to another embodiment of the present invention. FIG. 8 is a waveform diagram of each part of the built-in flash memory for explaining the write operation of the nonvolatile memory module of FIG. FIG. 9 is a diagram showing a configuration of a nonvolatile memory module according to another embodiment of the present invention. FIG. 10 is a waveform diagram of each part of the built-in flash memory for explaining the write operation of the nonvolatile memory module of FIG. FIG. 11 is a diagram showing a configuration of a non-volatile memory module according to still another embodiment of the present invention. FIG. 12 is a waveform diagram of each part of the built-in flash memory for explaining the write operation of the nonvolatile memory module of FIG. FIG. 13 is a diagram showing a configuration of a nonvolatile memory module according to still another embodiment of the present invention. FIG. 14 is a waveform diagram of each part of the built-in flash memory for explaining the write operation of the nonvolatile memory module of FIG. FIG. 15 is a diagram showing a configuration of a write circuit of the nonvolatile memory module according to the various embodiments of the present invention. FIG. 16 is a diagram showing the configuration of the write circuit of the nonvolatile memory module according to the above-described various embodiments of the present invention, similar to FIG. FIG. 17 is a diagram showing a configuration of a counter as a write / erase drive circuit of the nonvolatile memory module according to the various embodiments of the present invention. FIG. 18 is a diagram showing a configuration of a single chip microcontroller including the nonvolatile memory module according to the above-described various embodiments of the present invention as a built-in flash memory. FIG. 19 is a diagram illustrating a write operation of the MNOS nonvolatile memory having another structure that can be used in the nonvolatile memory module according to various embodiments of the present invention. FIG. 20 is a diagram for explaining the erasing operation of the MNOS nonvolatile memory shown in FIG. FIG. 21 is a diagram for explaining the read operation of the MNOS nonvolatile memory shown in FIG. FIG. 22 is a diagram showing a configuration of a built-in flash memory as a nonvolatile memory module using the MNOS nonvolatile memory having the structure shown in FIG. 19, FIG. 20, and FIG. FIG. 23 is a waveform diagram of each part of the built-in flash memory for explaining the write operation of the nonvolatile memory module of FIG. FIG. 24 is a waveform diagram of each part of the built-in flash memory for explaining the erase operation of the nonvolatile memory module of FIG. FIG. 25 is a waveform diagram of each part of the built-in flash memory for explaining the erase operation of the nonvolatile memory module of FIG. FIG. 26 is a waveform diagram of each part of the built-in flash memory for explaining the erasing operation of the nonvolatile memory module of FIG. FIG. 27 is a waveform diagram of each part of the built-in flash memory for explaining the erase operation of the nonvolatile memory module of FIG. FIG. 28 is a diagram showing a configuration of a counter as a write / erase drive circuit of the nonvolatile memory module according to the embodiment of the present invention shown in FIG. FIG. 29 is a diagram showing waveforms at various parts of the counter as the write / erase drive circuit shown in FIG. FIG. 30 is a diagram showing waveforms at various parts of the counter as the write / erase drive circuit shown in FIG. 28, as in FIG.

Explanation of symbols

LSI for LSI single chip microcontroller
NVMU built-in nonvolatile memory module Array memory array Cnt_CKT control circuit BUS bus
100 selection gate (CG)
101 Memory gate (MG)
102 Charge storage layer
103 Drain (D)
104 Source (S)
105 P-type well as substrate
BL bit line
SL source line
COUNT Counter as write / erase drive circuit
SL <0> ... SL <n> Source line
MA <0>,… MA <n> Memory array
WU write unit
MM <0,0>, MM <0, y> ... MM <x, n (y + 1)>, MM <x, n (y + 1) + y> Memory cell
CG <0>… CG <x> Select gate line
MG <0>… MG <x> Memory gate line
BL <0> ... BL <n (y + 1) + y> Bit line
WrCkt <0>… WrCkt <n (y + 1) + y> Write circuit
SLA <0> ... SLA <m> Row direction source line
SLB <0> ... SLB <n> Column direction source line
SLD <0,0> ... SLD <m, n> Source line driver
SLTM <0,0> ... SLTM <m, n> Source line transfer MOS transistor
MBL <0>, MBL <y> ... MBL <n (y + 1)>, MBL <n (y + 1) + y> Main bit line
SBL <0>, SBL <y> ... SBL <n (y + 1)>, SBL <n (y + 1) + y> Sub-bit line
ZM <0>, ZM <y> ... ZM <n (y + 1)>, ZM <n (y + 1) + y> Bit line MOS transistor
Z bit line gate signal line
SBL <y> l, SBL <y> r Parallel subbit line
ZM <0, y>, ZM <1, y> Bit line MOS transistors
Z <0>, Z <1> Bit line gate signal line
CM <0,0>, CM <0, y> Charge PMOS transistor
C <0>, C <1> Charge control signal

Claims (21)

A nonvolatile memory array and a write / erase circuit;
The nonvolatile memory array includes a plurality of memory cells having a gate connected to a gate line in a row direction, a drain connected to a bit line in a column direction, and a source connected to a source line in a column direction,
Applying a positive gate voltage to the gates of the plurality of memory cells via the gate line; applying a positive source voltage to the sources of the plurality of memory cells via the source line; Injecting electrons into the charge storage layers of the plurality of memory cells by supplying a drain voltage for nonvolatile storage by the write / erase circuit via the bit line to the drain of the memory cells,
Applying a negative gate voltage to the gates of the plurality of memory cells via the gate line, while applying a positive source voltage to the sources of the plurality of memory cells via the source line; In a plurality of memory cells, holes are injected from the source into the charge storage layer, and the electrons injected into the charge storage layer are neutralized by the holes,
A write / erase drive circuit having a plurality of outputs for driving the source lines in the column direction;
A semiconductor integrated circuit in which the plurality of outputs of the write / erase drive circuit sequentially drive a plurality of source lines in the column direction in a time division manner upon injection of the electrons into the charge storage layer of the plurality of memory cells.   Upon the injection of electrons, the plurality of memory cells are selected by selectively supplying the voltage for the non-volatile memory to the drains of the plurality of memory cells via the bit lines by the write / erase circuit. The semiconductor integrated circuit according to claim 1, wherein the injection of the electrons into the charge storage layer of the memory cell is performed.   3. The semiconductor integrated circuit according to claim 2, wherein a plurality of source / drain current paths of the memory cell are connected in parallel between the source line and the bit line. Including a plurality of source line drivers, a plurality of row direction source lines in the row direction, and a plurality of column direction source lines in the column direction,
The outputs of the plurality of source line drivers are connected to the plurality of source lines,
The plurality of row direction source lines in the row direction are connected to power supply terminals of the plurality of source line drivers,
4. The semiconductor integrated circuit according to claim 3, wherein the plurality of column direction source lines in the column direction are connected between input terminals of the plurality of source line drivers and the plurality of outputs of the write / erase drive circuit. . Including a plurality of source line transfer MOS transistors, a plurality of row direction source lines in the row direction, and a plurality of column direction source lines in the column direction,
The plurality of source / drain current paths of the plurality of source line transfer MOS transistors are connected between the plurality of outputs of the write / erase drive circuit and the plurality of source lines via the plurality of column direction source lines in the column direction. Connected between and
4. The semiconductor integrated circuit according to claim 3, wherein the plurality of gates of the plurality of source line transfer MOS transistors are driven by a plurality of signals of the plurality of row direction source lines in the row direction. The bit line connected to the drain of the plurality of memory cells is a sub-bit line;
6. The semiconductor integrated circuit according to claim 5, wherein a plurality of bit line MOS transistors are connected between a plurality of main bit lines and a plurality of sub bit lines in the column direction.   7. The semiconductor integrated circuit according to claim 6, wherein said sub bit line is a parallel sub bit line connected to one main bit line via two bit line MOS transistors.   4. The semiconductor integrated circuit according to claim 3, wherein the charge storage layer is formed at a deep level near an interface between two types of silicon insulating films.   9. The semiconductor integrated circuit according to claim 8, wherein the two types of silicon insulating films are a silicon oxide film and a silicon nitride film.   The semiconductor integrated circuit according to claim 9, wherein hot holes are injected from the source into the charge storage layer for neutralization of the electrons injected into the charge storage layer.   The semiconductor integrated circuit according to claim 10, wherein the injection of the electrons into the charge storage layer of the plurality of memory cells is performed by source side injection of hot electrons. A nonvolatile memory array and a write / erase circuit;
The nonvolatile memory array includes a plurality of memory cells in which a plurality of gates are connected in parallel to a plurality of gate lines, and a plurality of source / drain current paths of the plurality of memory cells include a source line and a bit line. Connected in series between,
A positive gate voltage is applied to the gates of the plurality of memory cells via the gate line, a positive source voltage is applied to the source line, and a non-volatile memory is applied to the bit line by the write / erase circuit. Injecting electrons into the charge storage layers of the plurality of memory cells by supplying a drain voltage for
Applying a negative gate voltage to the gates of the plurality of memory cells via the gate line, while applying a positive source voltage to the source lines, the charge accumulation from the source in the plurality of memory cells. Hole injection into the layer is performed, and the electrons injected into the charge storage layer by the hole injection are neutralized by the holes,
A write / erase drive circuit having a plurality of outputs for driving the source line;
A semiconductor integrated circuit in which the plurality of outputs of the write / erase drive circuit sequentially drives a plurality of source lines in a time division manner upon injection of the electrons or holes into the charge storage layer of the plurality of memory cells.   Upon injection of electrons, the write / erase circuit selectively supplies the voltage for the nonvolatile storage to the bit lines to the charge storage layer of the selected memory cell of the plurality of memory cells. The semiconductor integrated circuit according to claim 12, wherein the injection of the electrons is performed.   14. The semiconductor integrated circuit according to claim 13, wherein the charge storage layer is formed at a deep level near an interface between two types of silicon insulating films.   15. The semiconductor integrated circuit according to claim 14, wherein the two types of silicon insulating films are a silicon oxide film and a silicon nitride film.   16. The semiconductor integrated circuit according to claim 15, wherein hot holes are injected from the source into the charge storage layer for neutralization of the electrons injected into the charge storage layer.   17. The semiconductor integrated circuit according to claim 16, wherein the injection of the electrons into the charge storage layer of the plurality of memory cells is performed by hot electron source side injection. A method of operating a semiconductor integrated circuit having a nonvolatile memory array in which a plurality of nonvolatile memory cells are connected to a word line,
A corresponding bit line is connected to each drain terminal of the plurality of nonvolatile memory cells,
A corresponding source line is connected to each source terminal of the plurality of nonvolatile memory cells,
A value to be written to a nonvolatile memory cell connected to the bit line in the bit line in a writing period in which a write voltage is applied to the word line in order to perform data writing to the plurality of nonvolatile memory cells A predetermined write voltage is applied in accordance with the write period, and the write period has a first period and a second period. In the first period, a predetermined voltage is applied to one source line and the other The predetermined voltage is not applied to the one source line, and the predetermined voltage is not applied to the one source line in the second period after the first period. A method for operating a semiconductor integrated circuit in which a voltage is applied.   19. The semiconductor integrated circuit according to claim 18, further comprising a third period in which the predetermined voltage is applied to both the one source line and the other source line between the first period and the second period. How it works.   20. The method of operating a semiconductor integrated circuit according to claim 18, wherein the plurality of nonvolatile memory cells connected to the word line are formed on one well region.   20. The semiconductor integrated circuit according to claim 18, wherein the nonvolatile memory cell connected to the one source line and the nonvolatile memory cell connected to the other source line are formed on one well region. How it works.

Images