JP2008287319A - Semiconductor device, electronic apparatus, and access log acquisition method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an access log in a flexible manner corresponding to an access that requires monitoring, and to eliminate a processing load due to an unnecessary operation and a waste of resources.
A memory in which an address decoder 200 that receives CPU access to each module 104 of a semiconductor device via a CPU I / F 102 performs operations related to logs, such as acquisition of an access log, in addition to an inherent CS generation unit 201 A control unit 202 is included. The memory control unit 202 monitors the CPU access ADDRESS data, the WR signal, and the CS signal, detects whether the access type is one of the defined CPU access types, and the detected access acquires the access log. If it is set as the type of access required, for example, write access to a specific register of the module, the access log is acquired only for this CPU access.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device having a module capable of accessing a CPU (Central Processing Unit). More specifically, even a semiconductor device with a built-in CPU can obtain a log of access to the module and obtain an access log. The present invention relates to a semiconductor device, an electronic apparatus including the semiconductor device, and an access log acquisition method that can eliminate unnecessary operations and wasteful use of resources.

In recent years, semiconductor devices having a CPU I / F (interface) have been used in various electronic devices.
When a failure occurs in such an electronic device, a general method that has been conventionally performed is a method of tracing the access contents of the CPU and analyzing the contents to investigate the cause of the failure. For tracing the access contents of the CPU, for example, a method of connecting a measuring instrument to the CPU I / F and observing the CPU I / F with the measuring instrument when a failure occurs is conventionally known.
However, the above method takes time to prepare for bringing in and connecting measuring instruments before observation, and the obtained observation results are accessed from all CPUs. The task of finding the location causing the occurrence becomes difficult. In the case of a device incorporating a CPU, a measuring instrument cannot be connected to the CPU I / F, so it is impossible to take a method of observing with a measuring instrument.

As a method capable of solving such a problem, there is a method of recording CPU access as an access log. In the case of access from the CPU, a method of writing log information as a CPU access log in the memory in the device by software can be adopted.
However, according to this method, the log acquisition process itself is a memory write using a CPU, which causes a problem of delaying the original system operation. Delaying the system operation not only decreases productivity, but also prevents the failure that occurs when the log is not created or conversely causes another failure by creating the log. It also causes adverse effects due to side effects.

Therefore, a method for creating an access log without causing such side effects has been proposed. The following Patent Document 1 shows an example of this prior art.
In parallel with the processing for CPU access to the data storage location used by the device, the device described in Patent Document 1 performs processing for creating a log in response to input of the CPU access, and stores the data storage location in the access log storage location. The circuit is also configured to be used for this purpose, and with this configuration, the access contents of the CPU can be traced even if a measuring instrument cannot be connected to the CPU I / F with a device incorporating the CPU.

In addition, in the device described in Patent Document 1, the access analysis circuit provided for performing the process of creating a log has a function of selecting a log to be stored in addition to a function of creating a log. The latter function is a function that does not save all the created logs, but selects only the set addresses among the accessed addresses as the target of saving, so that the address setting can be changed. Yes. Furthermore, by making it possible to change register settings by software, the operation of the circuits used for log processing including the access analysis circuit is stopped / moved.
JP 2006-11969 A

However, since the function for selecting a storage target log in the above-described conventional example selects a storage target log from the created logs, it is possible to improve the utilization efficiency of resources used for storing the log. However, the burden of processing to create a log is not reduced. In addition, since the selection condition of the log to be saved is only the address, the effectiveness is limited.
In the above-described conventional example, it is possible to change the operation of the circuits used for log processing including the access analysis circuit by changing the register setting by software, but it is incompatible and needs to be changed. Even in such a case, the software must be operated as it is until the software is rewritten, which may cause problems such as processing load due to unnecessary operations and wasteful use of resources.
The present invention has been made in view of the problems of the above-described conventional example in a semiconductor device having a circuit unit for creating an access log for modules such as a memory and a register. The problem to be solved is an access that requires monitoring. The purpose is to be able to acquire the access log flexibly, and to eliminate the processing burden and unnecessary use of resources due to unnecessary operations.

The invention of claim 1 is a module accessed by a CPU, an address decoder that decodes CPU access to the module, a memory that stores an access log generated by accessing the module, and an input of the CPU access, A semiconductor device having an access log for CPU access and having a memory control unit for controlling access to the memory of the acquired access log, wherein the memory control unit detects the type of CPU access input, Whether the access log is necessary / unnecessary is determined based on the detection result, and the operations of acquiring the access log and accessing the memory are controlled according to the determination.
According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the memory control unit determines whether the access log is necessary / unnecessary for at least one of a predetermined address and a read / write type in the input CPU access. Judgment is based on detection.
According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, an internal signal indicating an operation state of the module is input to the memory control unit. The memory control unit is input from the module. A change in the internal signal is detected, and the internal signal in which the change is detected is acquired as a log of the module.
According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, the memory control unit can acquire the data of the internal register of the module from the memory control unit at a predetermined timing. The acquired internal register data of the module is acquired as a log of the module.
According to a fifth aspect of the present invention, in the semiconductor device according to any one of the first to fourth aspects, the memory control unit detects an access to a specific register in the input CPU access, and the access log is detected based on a detection result. The start or stop of the acquisition of at least one of the internal signal log and the internal register log is determined, and the acquisition of the log is started or stopped according to the determination.
According to a sixth aspect of the present invention, in the semiconductor device according to the third aspect, the memory control unit detects a change in the input specific internal signal, and the access log, the internal signal log, The start or stop of acquisition of at least one log of the internal register log is determined, and log acquisition is started or stopped according to the determination.
According to a seventh aspect of the present invention, in the semiconductor device according to the fourth aspect, the memory control unit detects a data change in the acquired specific internal register, and the access log and the internal signal log are detected according to a detection result. The start or stop of the acquisition of at least one log of the internal register log is determined, and the acquisition of the log is started or stopped according to the determination.
The invention of claim 8 is an electronic apparatus comprising the semiconductor device according to any one of claims 1 to 7 and a CPU that performs CPU access to the module of the semiconductor device.
The invention of claim 9 is an access log acquisition method for acquiring an access log for a module of a semiconductor device, the step of detecting the type of CPU access to the module input to the semiconductor device, and the detected CPU It is characterized by having a step of determining whether or not an access log is necessary depending on the type of access, and a step of controlling an access log acquisition operation according to the determination of whether or not an access log is necessary.
According to a tenth aspect of the present invention, in the access log acquisition method according to the ninth aspect, the step of determining whether or not the access log is necessary is at least one of a predetermined address and a read / write type in the input CPU access. It is characterized in that the necessity / unnecessity of the access log is determined on the basis of the detection of.
The invention of claim 11 is the access log acquisition method according to claim 9 or 10, wherein the step of inputting an internal signal indicating the operating state of the module and the step of detecting a change in the internal signal input from the module And a step of acquiring an internal signal in which a change is detected as a log of the module.
A twelfth aspect of the invention is the access log acquisition method according to any one of the ninth to eleventh aspects, the step of acquiring the data of the internal register of the module at a predetermined timing, and the acquisition of the internal register of the module It has the process of acquiring data as a log of the module concerned.

According to the present invention, in parallel with the CPU access address decoding, the CPU access input is received, the necessity / unnecessity of the access log is determined according to the type of CPU access, and the access log is acquired and stored according to this determination, Even with a device with a built-in CPU, access logs can be acquired without affecting system operation during normal operation, and without burdening processing and resources due to unnecessary access log acquisition. Analyzing the log using the access log acquired in this way makes it possible to improve the analysis efficiency. In addition, problems that occur with the conventional method of analyzing access logs by connecting instruments ([Background [0002] of [Technology] can be solved.
In addition to the CPU access log, more detailed log analysis can be performed by storing the internal signal in which the change is detected and the data of the internal register of the module as a log.
Also, start or stop acquisition of access log, internal signal log, and internal register log by controlling access to a specific register, change of a specific internal signal, and change of data in a specific internal register. Thus, without losing the necessary timing, it is possible to perform an operation that makes it possible to eliminate the processing burden due to unnecessary operations and the wasteful use of resources, thereby improving the performance.

Embodiments of a semiconductor device, an electronic apparatus, and an access log acquisition method according to the present invention will be described below.
The semiconductor device according to the present embodiment has no feature in the original operation of the device corresponding to the CPU access to each module of the semiconductor device. In parallel with the original operation, the access log is acquired by receiving the CPU access. The operation related to the access log is characterized. Therefore, in the following embodiment, the configuration and operation related to the access log will be mainly described.

First, an outline of the semiconductor device of the present embodiment that receives access from the CPU will be described with reference to FIG.
A target substrate 112 shown in FIG. 1 is one substrate used as a component constituting a circuit unit of an electronic device (not shown).
On the target substrate 112, the CPU 101, the semiconductor device 100 that receives CPU access, and other devices (not shown) are mounted.
In the configuration example shown in FIG. 1, the CPU 101 is external to the semiconductor device 100, and a storage device (memory) that stores an access log acquired in the semiconductor device 100 is built in the device. Any element can be external or internal.

The semiconductor device 100 is a device having a CPU I / F, such as an ASIC (Application Specific Integrated Circuit) for printer control, if the electronic device on which the device is mounted is an image forming apparatus, for example.
As illustrated in FIG. 1, the semiconductor device 100 includes a CPU I / F 102, an address decoder 103, modules A to E 104 to 108, a built-in memory 109, and a serial controller 110.

The CPU I / F 102 is connected to the CPU 101 via the CPU bus, and converts the CPU bus into an internal bus of the semiconductor device 100.
The address decoder 103 decodes the CPU access input via the CPU I / F 102 and generates CS (chip select) to the modules A to E104 to 108. Further, the address decoder 103 has an element unit (described in detail later) that performs an operation related to an access log, which is a characteristic configuration of the present embodiment.
Modules A to E104 to 108 are device built-in modules, each having a CPU accessible register, and the CPU access is performed via the internal bus to the register of the module designated by CS generated by the address decoder 103. Here, an example having five modules A to E104 to 108 is shown, but the number of modules is not limited.

The built-in memory 109 is a storage device used for storing an access log. The access log stored in the built-in memory 109 can be directly accessed from the CPU 101 and the terminal PC 111 described later.
The serial controller 110 functions as a serial I / F for accessing the built-in memory 109 from the terminal PC 111 via the address decoder 103.
A terminal PC (Personal Computer) 111 is a PC for serial operation and display, and is a management terminal capable of accessing the built-in memory 109 via the serial controller 110 and acquiring stored access log data. is there.

Here, the address decoder 103 that performs the operation related to the access log will be described in more detail.
The address decoder 103 decodes the CPU access and generates a CS to the modules A to E104 to 108, thereby related to the access log in addition to the basic operation of relaying the access from the CPU 101 to the modules A to E104 to 108. As operations, operations such as obtaining an access log and accessing the internal memory 109 storing the access log are performed. The access to the built-in memory 109 is writing of the acquired access log and reading of the stored access log.

FIG. 2 is a diagram illustrating an embodiment of an address decoder that performs an operation related to an access log.
In this embodiment, an embodiment (hereinafter referred to as “Embodiment 1”) in which a basic operation of receiving an access log is performed in response to an input of CPU access is shown.
In the configuration example illustrated in FIG. 2, the address decoder 200 includes a memory control unit 202 that performs an operation related to an access log, in addition to the CS generation unit 201 originally included in the address decoder. The address decoder 200 corresponds to the address decoder 103 in the configuration of FIG.
The CS generation unit 201 decodes based on the CPU access ADDRESS data, the WR (write / read) signal, and the CS signal input via the CPU I / F 102, and generates a CS signal and the like to the internal module.

  As one operation related to the access log, the memory control unit 202 receives an input of CPU access and performs an operation of acquiring the access log in a predetermined format. As another operation related to the access log, access control to the built-in memory 109 is performed. That is, a write (write) access for storing the acquired access log or the like in the internal memory 109 and a read (read) access performed by the terminal PC 111 via the serial controller 110 for the access log stored in the internal memory 109 are performed. In this embodiment, the access log data in the built-in memory 109 can be read only from the serial via the serial controller 110, but the data can also be read via the CPU I / F 102.

In this embodiment, an access log is acquired only for necessary access among the input CPU accesses.
Here, the CPU access category that determines the necessity / unnecessity of access log acquisition is the CPU access type defined by the rule. The rules for determining the type of CPU access will be described later. Also, the necessity / unnecessity of the access log can be set in accordance with the type of CPU access determined by the rule.
In accordance with the above principle, in order to obtain an access log for only necessary CPU access, the memory control unit 202 monitors the CPU access ADDRESS data, WR (write read) signal, and CS signal input via the CPU I / F 102. Detecting which of the defined CPU access types is the access type. Also, from this detection result, it is determined whether or not the access type requires access log acquisition, and only the CPU access determined to be necessary acquires the access log.

The CPU access determined to require access log acquisition is taken into the memory control unit 202 as data or a signal and used to acquire the access log. That is, the CPU access is converted into a fixed format in the memory control unit 202 and stored as an access log in the built-in memory 109.
FIG. 3 is a diagram illustrating an example of a formatted access log. In this example, the access log for one access unit is represented by log data of 9 bytes (bytes) = 72 bits (bits).

The contents of the access log in the format shown in FIG. 3 are attribute data “log type”, “R / W type”, “H / L type”, “ADDRESS”, and “DATA” having the information amount (bit) shown in <data format> below. ". Note that this format is applied when an internal signal log and an internal register log are added in the second embodiment to be described later. In the first embodiment related to the CPU access log, a comment is attached to * of <data format> below. As described above, “H / L type” is invalid.
<Data format>
Log type (2 bits)
00: CPU access log
01: Internal signal log
10: Internal register log
11: Reserve
R / W type (1 bit)
0: Lead
1: Write * Valid only during CPU access log
H / L type (1 bit)
0: Change to L
1: Change to H * Effective only when logging internal signals
ADDRESS (32bit)
CPU access log: Stores access address Internal signal log: Stores internal signal number * Number assigned to internal signal in advance Internal register log: Stores internal register address
DATA (32bit)
CPU access log: Transfer data is stored Internal signal log: Invalid Internal register log: Internal register data is stored

Further, the memory control unit 202 in FIG. 2 relays access to the built-in memory 109 performed through the serial controller 110.
The memory control unit 202 includes a selector that switches between a path for writing the CPU access log into the built-in memory 109 and a path for reading the access log performed through the serial controller 110.
If the built-in memory 109 is configured as a 1-port RAM (Random Access Memory), if there is an access from the serial controller 110 during acquisition of the access log, access conflict of the built-in memory 109 occurs, and the access log acquisition is not delayed. Since it cannot be performed, the access from the serial controller 110 needs to be performed after the system operation ends.
On the other hand, when the built-in memory 109 has a 2-port RAM (not shown), even if there is a read access from the serial controller 110 during acquisition of the access log, contention of the built-in memory 109 does not occur. In addition, access from the serial controller 110 can be permitted. Any configuration is possible, but it is a necessary condition that the system does not miss the access log.

Here, a rule for determining the type of CPU access for acquiring only a necessary access log by setting necessity / unnecessity of access log acquisition will be described.
In this embodiment, the type of access is determined based on CPU access ADDRESS data, WR (write / read) signal, and CS signal, and the rules shown in Examples 1 to 3 below can be adopted. In this example, an access that requires acquisition of an access log is determined by a rule, and other access does not require acquisition of an access log.
Example 1: It is in the area of “upper limit log acquisition address” and “lower limit log acquisition address”.
Example 2: To determine either R (read access) or W (write access) of the WR signal.
Example 3: Having a setting address in the “address setting register” corresponding to the bit set to 1 in the “address valid register”.
In addition, when the above example 3 is explained, for example,
`` Address valid register '' = 0x11110000
`` Address setting register '' = 0x10101100
If the input CPU access is 0x1010xxxx (where x is Don't Care), it is necessary to acquire an access log. That is, 0x10100011 requires acquisition of an access log, but 0x10111100 does not require access log acquisition.

Access that requires acquisition of an access log on the condition that data conforming to the definitions in Examples 1 to 3 above is prepared in the register of the CS generation unit 201 and corresponds to one or several simultaneously And each acquisition operation is performed.
Therefore, the internal memory 109 stores only log data for access that requires access log acquisition.
In this way, by acquiring the access log, the capacity of the storage device is reduced, and the cost of the device (system) is reduced. Further, since only necessary logs can be acquired, the efficiency of log analysis is improved.

When the CPU write access is an access that requires acquisition of an access log in the rule of Example 2 described above, the operation of the memory control unit 202 that receives this CPU access is as follows.
FIG. 4 shows a timing chart in the access log acquisition operation of CPU write access.
The memory control unit 202 detects a write access at a predetermined timing of the clock CLK on the condition that the CS signal: CS = Low and the WR signal: WR = Low shown in <Input from CPU I / F> in FIG. At that timing, the data “ADDRESS”, “DATA_I”, and “W / R type” are latched.
At the next clock CLK, as indicated by an arrow in FIG. 4, the process proceeds to <output to built-in memory>, and each data of “ADDRESS”, “DATA_I”, and “W / R type” is stored in the built-in memory 109. Write by burst transfer.

If the data written to the internal memory 109 conforms to the data format shown in FIG. 3, the access log for each access unit is 9 bytes of data. For example, when the data bus width of the internal memory 109 is 4 bytes, Writing to the memory can be completed by three burst transfers.
After writing to the built-in memory 109, the address counter of the memory control unit 202 is incremented by 9 bytes to prepare for the next access.
The initial value of the address counter of the memory control unit 202 is generally set to “0”. For processing when the address counter exceeds the memory capacity,
・ Returning to the top address and overwriting ・ Two types of actions are possible: cancel log acquisition, but it is not specified here.

The memory control unit 202 that receives the CPU read access performs the operation shown in FIG. 5 showing a timing chart in the access log acquisition operation of this access.
At the time of CPU read access, the memory control unit 202 detects read access on the condition that the WR signal: WR = Low detected at a predetermined timing of the clock CLK is not continuously detected for a period of 2 clocks, and at that timing Each data of “ADDRESS”, “DATA_I”, and “W / R type” is latched.
The operation of writing the latched data to the internal memory 109 as an access log is the same as the write operation in the access log acquisition operation of the CPU write access (FIG. 4).

Next, another embodiment of an address decoder that performs an operation related to an access log will be described.
In the above-described first embodiment, the embodiment in which only the necessary access log is obtained among the CPU accesses is shown. However, in order to perform more detailed log analysis, not only the CPU access but also the signals indicating the operation states of the modules A to E104 to 108 are logged as internal signals that enable analysis related to hardware operations. It is necessary to save as.
Therefore, in this embodiment, an embodiment (hereinafter referred to as “Embodiment 2”) in which an operation of acquiring a log in response to an input of an internal signal indicating the operation state of the modules A to E104 to 108 is shown.

FIG. 6 is a diagram illustrating an embodiment of an address decoder that performs an operation related to a log of an internal signal indicating an operation state of a module.
Here, the memory control unit 702 detects a change in an internal signal indicating an operation state of the modules A to E104 to 108, and uses the internal signal in which the change is detected as a log of the module, in the access log in the first embodiment. In addition to a part of the log shown in FIG.
In order to perform this operation, as shown in FIG. 6, internal signals from modules A to E104 to 108 are input to the memory control unit 702.

Since the address decoder 700 shown in FIG. 6 is based on the address decoder 200 that performs the operation related to the access log of the CPU access shown in the first embodiment, it has the function of the address decoder 200 of the first embodiment.
In addition, in the address decoder 700 of FIG. 6, a line for transmitting and receiving data and signals is shown between the memory control unit 702 and the CS generation unit 701. This is a configuration related to an embodiment described later.

The memory control unit 702 detects changes in internal signals indicating the operation states of the modules A to E104 to 108 for each internal signal, and when the signal changes, identifies the internal signal detected in the log information by the internal signal number. At the same time, it indicates whether the signal has changed to L: Low or H: high, and is written in the built-in memory 109 as a log.
When this log is acquired, the log acquisition can be set to be valid / invalid for each signal, so that efficiency can be improved. For example, a method of setting whether or not to set a valid bit of a signal in an internal register provided in the CS generation unit 701 can be considered. By setting the effective bit, it is possible to avoid unnecessary log acquisition and improve performance.

The memory control unit 702 writes log information in the built-in memory 109 according to the data format (FIG. 3) shown in the first embodiment when the state of the internal signal set to log acquisition valid changes.
In <data format> of FIG. 3, the log of the internal signal indicating the operation state of the module corresponds to the data indicated by the underline of the attribute data below.
<Data format>
Log type (2 bits)
00: CPU access log
01: Internal signal log
10: Internal register log
11: Reserve
R / W type (1 bit)
0: Lead
1: Write * Valid only during CPU access log
H / L type (1 bit)
0: Change to L
1: Change to H * Valid only when logging internal signals
ADDRESS (32bit)
CPU access log: Stores access address
Internal signal logging: Stores internal signal number * Number assigned to internal signal in advance Internal register logging: Stores internal register address
DATA (32bit)
CPU access log: Transfer data is stored Internal signal log: Invalid Internal register log: Internal register data is stored

By the way, the operation of the second embodiment overlaps with the operation of the first embodiment, and it is considered that a conflict occurs between the writing of the log of the internal signal and the access of the internal memory 109 when acquiring the CPU access log. In order to prevent it from happening, it is necessary to devise on implementation. For example, since it is known that the CPU access is an interval of several microseconds or more, contention can be avoided by writing internal signal information to the internal memory immediately after the CPU access occurs.
As described above, since the log indicating the state change of the internal signal and the CPU access log are accumulated in time series, the relation between software and hardware can be analyzed, so that more detailed log analysis can be performed.

Next, still another embodiment of an address decoder that performs an operation related to an access log will be described.
In order to perform more detailed log analysis, it is possible to analyze not only the CPU access log of the first embodiment and the log indicating the state change of the internal signal of the second embodiment, but also the relationship with the internal state of the device. As data, it is necessary to store register data indicating the internal state of the device such as the register state in the CS generation unit as a log (hereinafter, this log is referred to as “internal register log”).
Therefore, in this embodiment, an embodiment (hereinafter referred to as “Embodiment 3”) that performs an operation of acquiring an internal register log is shown.

One embodiment of the address decoder of the present embodiment that performs the operation of acquiring the internal register log will be described again with reference to FIG.
The memory control unit 702 of the address decoder 700 shown in FIG. 6 is connected via a communication line so that control signals, addresses, and data can be transmitted to and received from the CS generation unit 701. Then, the register provided in the CS generation unit 701 is automatically polled, and the data stored in the register is taken in, whereby data indicating the state of the register is acquired as a log and recorded in the built-in memory 109.

The polling of the register in the CS generation unit 701 can change the log acquisition operation by, for example, setting the register address to be polled and the polling cycle in the memory control unit 702.
The memory control unit 702 polls the register according to the register address to be polled and the polling cycle, and acquires data indicating the register state. The acquired register data and register address are stored in the internal memory 19 in addition to a part of the log (FIG. 3) shown as the data format applied to the access log in the first embodiment.

In <data format> of FIG. 3, the data indicated by the underline of the attribute data below corresponds to the register data log indicating the state of the register in the CS generation unit.
<Data format>
Log type (2 bits)
00: CPU access log
01: Internal signal log
10: Internal register log
11: Reserve
R / W type (1 bit)
0: Lead
1: Write * Valid only during CPU access log
H / L type (1 bit)
0: Change to L
1: Change to H * Effective only when logging internal signals
ADDRESS (32bit)
CPU access log: Access address is stored Internal signal log: Internal signal number is stored * Number assigned to internal signal in advance
Internal register log: Stores internal register address
DATA (32bit)
CPU access log: Stores transfer data Internal signal log: Invalid
Internal register log: Stores internal register data

By the way, the operation of the third embodiment overlaps with the operation of the first embodiment, and it is considered that a conflict occurs between the writing of the internal register log and the access of the internal memory 109 when acquiring the CPU access log. In order to avoid this, it is necessary to devise on mounting. For example, since CPU access is known to be at intervals of several microseconds or more, contention can be avoided by polling the internal register immediately after CPU access occurs.
As described above, by accumulating the internal register log and the CPU access log in time series, the relationship between software and hardware can be analyzed, so that more detailed log analysis can be performed.

Next, an embodiment relating to the start or stop control of the log acquisition operation will be described.
In the CPU access log processing circuit, circuit operation stop / movable control is conventionally done by register setting by software, so even if you feel incompatibility with the operation, you can't change the operation until the software is rewritten. Problems arise in terms of processing burden due to unnecessary operations and wasteful use of resources.

In view of this, a control method for eliminating the processing load due to unnecessary operations and wasteful use of resources without losing necessary timing is introduced to solve the above problems.
The start / stop control adapted to the CPU access log, internal signal log, and internal register log acquisition operations shown in the first to third embodiments will be described below as “start / stop control (1)”. Description will be made as “start / stop control (3)”.

"Start / stop control (1)"
The log acquisition operation start / stop control according to the present embodiment is a form adapted to the CPU access log acquisition operation, and is a method of performing start / stop control triggered by the occurrence of access to a specific register in the device. take.
The memory control units 202 and 702 have means for detecting a specific CPU access as a trigger, and start / stop the access log acquisition operation according to the detection result.

The specific CPU access as a trigger is set by, for example, writing setting data such as a specific CPU access address and an operation type of start / stop control in the registers of the CS generation units 201 and 701.
The register setting is referred to at the time of CPU access input to determine whether the input access corresponds to the set specific CPU access. Also, the start / stop operation of the log acquisition operation can be changed by rewriting the register setting data.

Also, as in the arrangement of FIG. 6, when the CPU access log, the internal signals of the log, and the log of the internal registers can be acquired is previously set whether to apply the start / stop control to advance any logging operation Therefore, the operation can be optimized. This setting may be applied to any of the CPU access log, the internal signal log, and the internal register log, or to a plurality of logs among these logs.
The CPU access that is the trigger is controlled to start / stop the log acquisition operation by this access. In any case, it is desirable that the CPU access is acquired as a log.
With the above control, the log acquisition operation can be started / stopped without losing the necessary timing, and the performance can be improved by eliminating the processing load and waste of resources due to unnecessary operations. be able to.

"Start / stop control (2)"
The log acquisition operation start / stop control of the present embodiment is a form adapted to the internal signal log acquisition operation, and adopts a method of performing start / stop control using a change in a specific internal signal in the device as a trigger. . This method can be adopted in a configuration in which internal signals from modules A to E104 to 108 are input to the memory control unit 702 as in the device shown in FIG.
The memory control unit 702 has means for detecting a change in a specific internal signal as a trigger, and starts / stops an access log acquisition operation according to the detection result. Since the memory control unit 702 has a means for detecting a change in the internal signal as shown in the second embodiment, here, a means for determining whether or not the signal is a specific internal signal. Add and have.

The change of a specific internal signal used as a trigger is set by writing setting data such as a specific internal signal and an operation type of start / stop control in the register of the CS generation unit 701, for example.
The register setting is referred to in order to determine whether or not the input internal signal whose change is detected corresponds to the set specific internal signal when the internal signals from the modules A to E104 to 108 are input. The Also, the start / stop operation of the log acquisition operation can be changed by rewriting the register setting data.

Also, as in the arrangement of FIG. 6, when the CPU access log, the internal signals of the log, and the log of the internal registers can be acquired is previously set whether to apply the start / stop control to advance any logging operation Therefore, the operation can be optimized. This setting may be applied to any of the CPU access log, the internal signal log, and the internal register log, or to a plurality of logs among these logs.
Note that the change in the specific internal signal that has been triggered is controlled to start / stop the log acquisition operation by this change. In any case, it is desirable to acquire the change as a log.
With the above control, the log acquisition operation can be started / stopped without losing the necessary timing, and the performance can be improved by eliminating the processing load and waste of resources due to unnecessary operations. be able to.

"Start / stop control (3)"
The log acquisition operation start / stop control according to the present embodiment is a form adapted to the internal register log acquisition operation, and is a method of performing start / stop control using a data change in a specific internal register in the device as a trigger. take. In this method, as in the device shown in FIG. 6, a register provided in the CS generation unit 701 is automatically polled using communication means, and data stored in the register is transferred to the memory control unit 702. It is a method that can be adopted in a configuration that can be included.
The memory control unit 702 has means for detecting a change in data in a specific internal register serving as a trigger, and starts / stops an access log acquisition operation according to the detection result. Note that, as shown in the third embodiment, the memory control unit 702 has a means for detecting a change in data in the internal register, so here, it is determined whether or not it is a specific internal register. Have additional means.

Data change in a specific internal register as a trigger is set by, for example, writing setting data such as the address of the specific internal register and the operation type of start / stop control in the register of the CS generation unit 701 .
The register setting is referred to in order to determine whether or not the register in which the change is detected corresponds to the set specific internal register when polling the register data of the CS generation unit 701. Further, the start / stop operation of the log acquisition operation can be changed by rewriting the setting data of the register.

Also, as in the arrangement of FIG. 6, when the CPU access log, the internal signals of the log, and the log of the internal registers can be acquired is previously set whether to apply the start / stop control to advance any logging operation Therefore, the operation can be optimized. This setting may be applied to any of the CPU access log, the internal signal log, and the internal register log, or to a plurality of logs among these logs.
Note that the change in data in a specific internal register that is a trigger controls the start / stop of the log acquisition operation by this change. In any case, it is desirable to acquire the data as a log.
With the above control, the log acquisition operation can be started / stopped without losing the necessary timing, and the performance can be improved by eliminating the processing load and waste of resources due to unnecessary operations. be able to.

It is a figure showing a schematic structure of a semiconductor device concerning an embodiment of the present invention. It is a figure which shows one Embodiment of the address decoder in the semiconductor device (refer FIG. 1) which performs the operation | movement which concerns on an access log. It is a figure which shows an example of the formatted log data. It is a figure which shows the timing chart in the access log acquisition operation | movement of CPU write access. It is a figure which shows the timing chart in the access log acquisition operation | movement of CPU read access. It is a figure which shows other embodiment of the address decoder in the semiconductor device (refer FIG. 1) which performs the operation | movement which concerns on an access log.

Explanation of symbols

100 .. Semiconductor device, 101... CPU (Central Processing Unit), 102... CPU I / F (interface), 103, 200, 700 .. Address decoder, 104 to 108 .. Modules A to E, 109. Memory 110, serial controller 111, terminal PC 201, 701, CS generation unit 202, 702, memory control unit

Claims (12)

A module accessed by the CPU, an address decoder that decodes the CPU access to the module, a memory that stores an access log generated by accessing the module, and an input log of the CPU access, and obtains an access log of the CPU access And a semiconductor device having a memory control unit for controlling access to the memory of the acquired access log,
The memory control unit detects the type of CPU access input, determines whether the access log is necessary or unnecessary based on the detection result, and controls each operation of acquiring the access log and accessing the memory according to the determination. A featured semiconductor device. The semiconductor device according to claim 1, wherein
The memory control unit determines whether or not an access log is necessary based on detection of at least one of a predetermined address and read / write type in an input CPU access. The semiconductor device according to claim 1, wherein an internal signal indicating an operation state of the module is input to the memory control unit.
The memory control unit detects a change in an internal signal input from the module, and acquires the internal signal in which the change is detected as a log of the module. 4. The semiconductor device according to claim 1, wherein data of an internal register of the module can be acquired from the memory control unit. 5.
The memory control unit acquires the data of the internal register of the module acquired at a predetermined timing as a log of the module. The semiconductor device according to claim 1,
The memory control unit detects an access to a specific register in the input CPU access, and starts or stops acquisition of at least one log of the access log, the internal signal log, and the internal register log according to a detection result. A semiconductor device characterized by determining and starting or stopping log acquisition according to the determination. The semiconductor device according to claim 3, wherein
The memory control unit detects a change in a specific input internal signal, and determines whether to start or stop acquiring at least one of the access log, the internal signal log, and the internal register log based on a detection result. A semiconductor device characterized in that log acquisition is started or stopped according to the judgment. The semiconductor device according to claim 4,
The memory control unit detects a data change in the acquired specific internal register, and determines whether to start or stop acquiring at least one log of the access log, the internal signal log, and the internal register log based on the detection result And starting or stopping log acquisition according to the determination.   An electronic apparatus comprising: the semiconductor device according to claim 1; and a CPU that performs CPU access to the module included in the semiconductor device. An access log acquisition method for acquiring an access log of access to a module of a semiconductor device,
Detecting a type of CPU access to the module input to the semiconductor device;
Determining whether the access log is necessary / unnecessary according to the type of CPU access detected;
An access log acquisition method comprising a step of controlling an access log acquisition operation in accordance with determination of necessity / unnecessity of an access log. In the access log acquisition method according to claim 9,
The step of determining necessity / unnecessity of the access log is characterized by determining necessity / unnecessity of the access log based on detection of at least one of a predetermined address and read / write type in the input CPU access. Access log acquisition method. In the access log acquisition method according to claim 9 or 10,
Inputting an internal signal indicating the operating state of the module;
Detecting a change in an internal signal input from the module;
An access log acquisition method comprising: acquiring an internal signal in which a change is detected as a log of the module. The access log acquisition method according to any one of claims 9 to 11,
Obtaining data of the internal register of the module at a predetermined timing;
An access log acquisition method comprising: acquiring the acquired internal register data of the module as a log of the module.

Images