JP2008283274A - Input interface circuit, integrated circuit device, and electronic device - Google Patents

Abstract

Provided is an input interface circuit capable of reliably and reliably preventing transmission of noise to an internal circuit when electrostatic noise is applied to a signal input terminal.
A noise detection circuit (200) for detecting noise and a noise canceller (300) having a function of turning off a first switch circuit (SW1) and blocking noise transmission when noise is detected. Provide. When the first switch circuit (SW1) is turned off, the second switch circuit (SW2) is turned on to latch the previous voltage. The noise detection transistor included in the noise detection circuit 200 is configured by a floating N well transistor that can adaptively optimize the potential of the N well.
[Selection] Figure 1

Description

  The present invention relates to an input interface circuit, an integrated circuit device, and an electronic apparatus.

  When an electronic device such as a mobile phone is exposed to electrostatic discharge from a charged operator, a transistor of an integrated circuit device built in the electronic device may be electrostatically damaged. In order to prevent such electrostatic breakdown, the integrated circuit device is generally provided with a protective element (protective diode or the like) for preventing electrostatic breakdown.

  On the other hand, although electrostatic breakdown of the transistor does not occur due to electrostatic discharge from the operator, malfunctions such as an abnormal display state of the display panel of the electronic device may occur. When such a malfunction occurs, the reliability of the electronic device is impaired, and in recent years, resistance to malfunction due to electrostatic discharge (ESD) (ESD immunity) tends to be emphasized. Therefore, in recent years, an ESD immunity test is frequently performed on an integrated circuit device.

  FIG. 16 is a diagram for explaining an example of the ESD immunity test. In FIG. 16, static electricity (electrostatic discharge: ESD) is intentionally applied to the display device 6 incorporating the display panel 8 and the integrated circuit device (display driver) 10 by the static electricity applying device 4. It is checked whether a malfunction (for example, an abnormality occurs in the display of the display panel 8) occurs.

As a conventional circuit for preventing malfunction caused by an ESD pulse, there is a circuit described in Patent Document 1, for example. In Patent Document 1, when an abnormal signal is output from an output pin due to an ESD pulse, an abnormality of the output pin is detected via a feedback path, and a reset signal is generated. By resetting the electronic device or the like, the electronic device is recovered from the abnormal state.
JP 2003-234647 A

  FIG. 17 is a circuit diagram for explaining a malfunction of a circuit block caused by applying electrostatic noise to a signal input terminal.

  As illustrated, the first circuit (block A) 100 and the second circuit (block B) 110 are connected. Both the first circuit 100 (circuit block A) and the second circuit 110 (circuit block B) operate between a high potential power supply (VD) and a low potential power supply (VSS).

  The first circuit (block A) 100 is an input interface circuit, and the second circuit (block B) 110 is, for example, a logic circuit including a memory (MR). The input terminal X of the first circuit (block A) is, for example, a reset terminal to which a reset signal (“H” is an active level) RSP for resetting the memory (MR) is input.

  When electrostatic noise (EDP) is applied to the input terminal X when the reset signal (RSP) is at a low level, the output level of the first circuit (circuit block A) is inverted, which means that the active level (“ The effect is the same as when the reset signal (RSP) of “H”) is input, and the memory (MR) of the second circuit (circuit block B) is erroneously reset.

  Such a problem arises when the input terminal X is, for example, a terminal for inputting a chip enable signal or a chip select signal (in a broad sense, a terminal to which a signal having a significant influence on the operation of the internal circuit is input). Can also occur.

  The technique described in Patent Document 1 provides an ex-post remedy by detecting an abnormal signal from an output pin and resetting the next-stage circuit erroneously reset. It is not possible to prevent an erroneous reset.

  The present invention has been made based on such considerations, and its purpose is to prevent and reliably prevent transmission of electrostatic noise to an internal circuit when electrostatic noise is applied to a signal input terminal. It is an object of the present invention to provide an input interface circuit capable of performing the above.

  (1) According to one aspect of the input interface circuit of the present invention, noise that detects noise at a voltage level exceeding a high potential power source applied to an input terminal or noise at a voltage level lower than that of a low potential power source and outputs a noise detection signal A noise canceller that is provided between a detection circuit, the input terminal, and a circuit that receives a signal from the input terminal, and that blocks signal transmission from the input terminal to the circuit when the noise detection signal is active; The noise canceller is provided between the input terminal and the circuit, and is turned off when the noise detection signal is active and turned on when the noise detection signal is inactive, and the noise A second switch circuit that is turned on when the detection signal is active and turned off when the detection signal is inactive, the first switch circuit Off, when the second switch circuit is turned on, holding the voltage at the output terminal of said first switching circuit, supplies a voltage that held in the circuit.

  A noise canceller is provided in the input interface circuit to prevent transmission of static noise applied to the input terminal to the internal circuit (the type of noise is not limited to static noise but includes all types of noise). Is. The noise canceller has a noise detection circuit that distinguishes and detects noise and a regular input signal. A regular input signal operates between a high-potential power supply (VDD) and a low-potential power supply (VSS), but noise that significantly affects the operation of the next-stage circuit has a peak voltage value exceeding VDD. Alternatively, in many cases, the voltage value is lower than VSS, and the noise detection circuit detects the noise separately from the normal input signal by paying attention to the difference in voltage level. The noise canceller has a first switch circuit interposed in a path for transmitting an input signal to the next-stage circuit. When noise is detected, the first switch circuit is turned off to completely transmit the noise. To prevent. On the other hand, when the first switch circuit is off, the second switch circuit is turned on to hold the previous voltage (voltage without noise) and supply the held voltage to the next stage circuit. To do. In this way, when noise is input, the noise is cut off based on the detection result of the noise and a noise-free voltage is output, so that transmission of the noise to the next stage circuit is reliably prevented. .

  (2) In another aspect of the input interface circuit of the present invention, the noise detection circuit is formed in a floating N-well region in which a potential is adjusted according to the voltage of the input terminal, and a gate of the high-potential power supply voltage A noise detecting PMOS transistor connected to a node, a source connected to the input terminal, and a signal output from a drain; one end connected to the drain of the noise detecting PMOS transistor; and the other end connected to the low potential power source And a resistance element for generating the noise detection signal connected to the node.

  An example of a specific configuration of the noise detection circuit is clarified. The noise detecting PMOS transistor whose gate is connected to the power supply potential (VDD) is turned on only when the potential of the source (first terminal) becomes equal to or higher than (VDD + Vthp: Vthp is the threshold voltage of the PMOS transistor). And a normal input signal can be distinguished and detected.

  Further, when noise is input and the noise detection PMOS transistor is turned on, a source / drain is formed in the floating N well region so that a parasitic diode between the source and the well (substrate in a broad sense) cannot be turned on. . Here, the “floating well region” means “a well region in which the potential is not fixed and the potential can be adjusted adaptively (in a broad sense, a semiconductor substrate in which a transistor element is formed (general If the well potential is fixed, when noise is input, the source of the noise detecting PMOS transistor and the N well (N substrate in a broad sense) The parasitic diode turns on and a transient current flows.At this time, since there is no element that limits the amount of current, an excessive current flows, for example, the wiring is blown, and the element is destroyed or latched up. In addition, when a parasitic diode is turned on, the N-well potential is lowered by the forward voltage of the diode, which causes a noise detection PMOS transistor. Therefore, the potential of the N-well region can be adjusted according to the situation without fixing the potential of the N-well region, thereby preventing the parasitic diode from being turned on. This is intended to prevent destruction and fluctuation of the threshold value.

  In addition, the resistance element that generates the noise detection signal has the following four functions. In other words, the function as “pull-down resistor (resistor that fixes the voltage of the noise detection path to a predetermined potential when there is no noise)” and “discharge resistor (excess noise energy at the time of noise input is AC grounded) And "sensing resistance (resistor that generates a noise detection signal by changing the voltage level of the noise detection path when noise current is flowing)" And a function as a “time constant setting resistor (a resistor having a function of adjusting a return time until the noise detection signal returns to the inactive level after the noise detection signal becomes the active level)”. Thus, according to this aspect, with a simplified configuration, noise can be detected quickly and reliably without causing adverse effects on the circuit, and the return timing of the noise canceller after the noise has passed. It is possible to realize an excellent noise detection circuit that can be adjusted.

  (3) In another aspect of the input interface circuit of the present invention, the noise detection circuit is formed in a floating P well region in which a potential is adjusted according to a voltage of the input terminal, and a gate is a node of the low potential power source. A noise detecting NMOS transistor whose source is connected to the input terminal and a signal is output from the drain; one end connected to the drain of the noise detecting NMOS transistor; the other end is the high-potential power supply voltage And a resistance element for generating the noise detection signal connected to the node.

  In this embodiment, a well having a conductivity type (floating P well) opposite to that in the previous embodiment is used, and an NMOS transistor is used as a noise detection transistor. The gate of the noise detection NMOS transistor is connected to a low potential power supply voltage (VSS: GND, for example). This makes it possible to detect negative noise below VSS. The obtained effect is substantially the same as the aspect of the preceding paragraph.

  (4) In another aspect of the input interface circuit of the present invention, the gate is connected to the node of the high potential power supply voltage, the source is connected to the input terminal, the drain is connected to the floating N-well region, and the noise When the detection PMOS transistor is turned on, the voltage applied to the input terminal is applied to the floating N well region, whereby the potential of the floating N well region is set to the potential of the input terminal. A first PMOS transistor.

  When a positive noise exceeding the high potential power supply voltage (HVDD) is applied to the source (first terminal) of the noise detecting PMOS transistor, the floating N is passed through the potential adjusting first PMOS transistor. The same noise voltage is also applied to the well region, whereby the potentials of the anode and cathode of the parasitic diode between the source and the well region are made the same potential to prevent the parasitic diode from being turned on. As a result, it is possible to prevent a transient current from flowing, and to prevent fluctuations in Vthp (threshold voltage) of the noise detection PMOS transistor.

  (5) In another aspect of the input interface circuit of the present invention, a gate is connected to the low potential power source, a source is connected to the input terminal, a drain is connected to the floating P well region, and the noise detecting NMOS When the transistor is turned on, the voltage applied to the input terminal is applied to the floating P-well region, whereby the potential of the floating P-well region is set to the potential of the input terminal. 1 NMOS transistor.

  When negative noise lower than the low-potential power supply voltage (VSS) is applied to the source (first terminal) of the noise detection NMOS transistor, it floats via the first NMOS transistor for potential adjustment. The same noise voltage is also applied to the P well region, whereby the potentials of the anode and cathode of the parasitic diode between the source and the P well region are set to the same potential to prevent the parasitic diode from being turned on. As a result, it is possible to prevent a transient current from flowing, and it is possible to prevent a variation in Vthn (threshold voltage) of the noise detecting NMOS transistor.

  (6) In another aspect of the input interface circuit of the present invention, the gate is connected to the input terminal, the source is connected to the node of the high potential power supply voltage, the drain is connected to the floating N well region, and the noise When both the detection PMOS transistor and the first PMOS transistor for adjusting the potential of the floating N well region are turned off, the high potential power supply voltage is applied to the floating N well region. A second PMOS transistor is further included.

  In the embodiment using the floating N well, when the first PMOS transistor for potential adjustment is turned off (the noise detecting PMOS transistor is also turned off at this time), the potential of the floating N well region cannot be fixed. In this case, it cannot be said that there is no case where some inconvenience in circuit operation occurs. Therefore, a second PMOS transistor for potential adjustment is added, and when the first PMOS transistor is off, the second PMOS transistor is turned on, and the floating N well region passes through the second PMOS transistor. Is adjusted to the high potential power supply voltage (HVDD), and the parasitic diode between the source and the N well is reverse-biased so that it cannot be turned on, thereby ensuring the stability (reliability) of the circuit.

  (7) In another aspect of the input interface circuit of the present invention, a gate is connected to the input terminal, a source is connected to the low potential power source, a drain is connected to the floating P well region, and the noise detecting NMOS When both the transistor and the first NMOS transistor for adjusting the potential of the floating P well region are turned off, the second potential adjusting second potential for the floating P well region is applied to the floating P well region. An NMOS transistor is further included.

  In the embodiment using the floating P-well, when the first NMOS transistor is off, the second NMOS transistor is turned on, and the potential of the floating P-well region is set to the low potential power supply voltage via the second NMOS transistor. (VSS: GND, for example) is adjusted so that the parasitic diode between the source and the P-well is reverse-biased so as not to be turned on, thereby ensuring the stability (reliability) of the circuit.

  (8) In another aspect of the input interface circuit of the present invention, the noise detection PMOS transistor is connected to the source terminal connected to the input terminal, and the threshold voltage of the noise detection PMOS transistor is set to the high potential power supply voltage. Turns on when a voltage higher than the sum of the voltages is applied.

  The noise detecting PMOS transistor is turned on only when the potential of the source (first terminal) is equal to or higher than (HVDD + Vthp). Thereby, it is possible to distinguish and detect a regular signal and positive noise.

  (9) In another aspect of the input interface circuit of the present invention, the noise detection NMOS transistor is connected to the source terminal connected to the input terminal (X) from the low potential power source to the noise detection NMOS transistor. Is turned on when a voltage equal to or lower than the voltage obtained by subtracting the threshold voltage is applied.

  The noise detection NMOS transistor is turned on only when the potential of the source (first terminal) is equal to or lower than (VSS−Vthn). Thereby, it is possible to distinguish and detect a regular signal and negative noise.

  (10) In another aspect of the input interface circuit of the present invention, the noise canceller includes a transfer gate as the first switch circuit, a transfer gate as the second switch circuit, and the first switch circuit. A first inverter having an input terminal connected to a common connection point of the output terminal and the second switch circuit, an input terminal connected to the output terminal of the first inverter, and an output terminal serving as the second switch circuit A second inverter connected to an input terminal of the first switch circuit, and through the output signal of the first switch circuit toward the circuit, or the output signal of the first switch circuit as the first and A through-latch that can be switched by a positive feedback path via the second inverter and the second switch circuit, and the resistance element. A third inverter for receiving the noise detection signal; and a fourth inverter connected to an input terminal at an output terminal of the third inverter; and an output terminal of the third inverter and the fourth inverter. A switching control signal for complementarily turning on / off the first switch circuit and the second switch circuit is generated from each of the common connection point with the input terminal of the inverter and the output terminal of the fourth inverter. A switching circuit.

  A specific circuit configuration example of the noise canceller is clarified. That is, the noise canceller of this aspect includes a through latch (holding circuit) configured to include first and second switch circuits, and a switching circuit. In a normal state, the switching circuit turns on the first switch circuit and outputs the input signal as it is from the output terminal of the through latch. When noise is detected by the noise detection circuit, the switching circuit turns off the first switch circuit. By turning on the switch circuit 2, the transmission of the input signal on which the noise is superimposed is interrupted, and at the same time, the signal immediately before being held in the holding circuit is output from the output terminal of the through latch. In this way, the noise cancellation circuit can be configured by a simple circuit having versatility. This is advantageous in terms of power saving and space saving.

  (11) In another aspect of the input interface circuit of the present invention, the input interface circuit further includes a timing adjustment delay circuit provided between the input terminal and the first switch.

  The timing at which the first and second switch circuits are complementarily turned on / off depends on the realization of reliable blocking of noise and the return of the first switch circuit to the on state during the duration of the noise. This is important from the viewpoint of reliably preventing malfunctions. In this aspect, a delay circuit for timing adjustment is provided between the input terminal and the first switch circuit. This delays the noise from reaching the first switch circuit. Therefore, it can be ensured that the first switch circuit is turned off before the noise reaches the first switch circuit, and the noise can be reliably cut off.

  (12) In another aspect of the input interface circuit of the present invention, the second timing before the first timing at which the potential of the input terminal of the first switch circuit changes due to the application of noise to the input terminal. The potential at the input terminal of the first switch circuit changes so that the first switch circuit shifts from the on state to the off state at the timing of and the noise is no longer applied to the input terminal. The delay amount of the delay circuit and the resistance value of the resistance element are set so that the first switch circuit returns from the off state to the on state at a fourth timing after the third timing. The

  By optimizing both the delay amount of the delay circuit for timing adjustment and the resistance value of the resistance element (also serving as the resistor for timing adjustment) for detecting noise, noise is detected in the first switch circuit at the time of noise detection. When the first switch circuit is turned off before reaching and no noise is applied, the first switch circuit returns to the on state after the noise is sufficiently suppressed (noise application is surely eliminated). As such, the timing can be adjusted. As a result, it is possible to surely cut off the noise and to surely prevent the malfunction that causes the first switch circuit to return to the ON state during the duration of the noise.

  (13) In another aspect of the input interface circuit of the present invention, the input interface circuit further includes a timing adjustment circuit connected to one end of the resistance element, and the timing adjustment circuit is based on a delay amount of the delay circuit for timing adjustment. A first path having a larger delay amount, a second path having a delay amount smaller than the delay amount of the delay circuit, a signal from the first path, and a signal from the second path. And a gate circuit that outputs one signal, and when the noise detection transistor is turned on and the voltage level at one end of the resistance element changes in accordance with the noise application to the input terminal, the voltage change Is transmitted via the second path, and the noise detection transistor is turned off when the noise is no longer applied to the input terminal, and one end of the resistance element is When the pressure level changes, the voltage change is transmitted via the first path.

  In the aspect of the preceding paragraph, the timing at which the first switch circuit is returned from OFF to ON depends on the time constant of the resistance element. However, in this aspect, instead of the timing adjustment by the time constant of the resistance element, the delay time is changed. The timing is adjusted by a timing adjustment circuit including a large first path, a second path with a small delay, and a gate circuit (for example, a NOR gate: a gate circuit based on an OR gate). Thereby, timing adjustment can be performed with higher accuracy. In this aspect, the timing adjustment circuit is inserted in the noise detection path, and when noise is detected, the first delay amount is smaller than that of the timing adjustment delay circuit inserted in the normal signal path. Through this path, the noise detection signal is quickly transmitted, the first switch circuit is quickly turned off, and the noise is reliably cut off. On the other hand, when the noise detection signal is no longer detected, the voltage change is transmitted via the second path having a larger delay amount than the timing adjustment delay circuit inserted in the regular signal path. Therefore, the first switch circuit is switched from OFF to ON after the potential at the input terminal of the first switch circuit returns to the potential without noise, and the first switch circuit is switched on during the period when the noise continues. Therefore, no malfunction occurs when the switch circuit is turned on, so that the noise removal operation can be ensured.

  (14) In another aspect of the input interface circuit of the present invention, the input interface circuit further includes a timing adjustment circuit provided between the input terminal and the first switch circuit, and the timing adjustment circuit is provided for timing adjustment. A first delay path having a predetermined delay amount, a second path having a smaller delay amount than the first delay path, a signal from the first path, and a signal from the second path When the voltage level at the input terminal of the timing adjustment circuit changes with the application of noise to the input terminal, the voltage change is the first circuit. When the voltage level at the input terminal of the timing adjustment circuit changes as the noise is no longer applied to the input terminal, the voltage change is transmitted to the second terminal. It is transmitted via the.

  In this aspect, the timing adjustment circuit is inserted into a normal signal transmission path. This timing adjustment circuit includes a first path having a predetermined delay amount, a second path having a small delay, and a gate circuit (for example, a NAND gate: a gate circuit based on an AND gate). Since the noise applied to the input terminal is delayed and transmitted via the first path, the first switch circuit can be turned off with a margin before the noise reaches the first switch circuit. it can. When noise is no longer applied, the voltage change is transmitted to the first circuit switch via the second path having a small delay amount. Therefore, after the voltage at the input terminal of the first switch circuit returns to the potential when there is no noise, the first switch circuit can be more easily returned from off to on.

  (15) In another aspect of the input interface circuit of the present invention, an input buffer having hysteresis characteristics inserted into a path connecting the input terminal and the first switch circuit, and one end at the output end of the input buffer Is further connected to the smoothing capacitor.

  In the above aspect, it is assumed that excessive noise exceeding the power supply voltage is applied to the input terminal, but small noise that does not exceed the power supply voltage is also assumed as noise. It is preferable to remove such small-scale noise. Therefore, an input buffer (for example, a Schmitt circuit) having hysteresis in input / output characteristics and a smoothing capacitor are provided in a regular signal transmission path. The input buffer has an input dead band (that is, an input range in which the output level does not change even if the input signal level fluctuates) due to hysteresis characteristics, and the amplitude of a small noise is within this input dead band width. If so, the small-scale noise is not output from the input buffer. In the unlikely event that a small-scale noise is output, the smoothing capacitor smoothes the noise, thereby preventing an erroneous control signal (such as a reset signal or a chip enable signal) from being input to the next stage circuit. be able to. As a result, the noise removal function of the input interface circuit can be enhanced.

  (16) In another aspect of the input interface circuit of the present invention, the power supply voltage of the noise detection circuit and the power supply voltage of the circuit receiving a signal from the input terminal are power supply voltages of different systems.

  In the input interface, for example, the front part operates with the first power supply voltage, the rear part operates with the second power supply voltage of another system, and the internal circuit in the integrated circuit device also operates with the second power supply voltage. Assuming a circuit system that In each circuit block that operates with a power supply voltage of a different system, each circuit operates independently, and noise is also generated independently. Therefore, noise countermeasures in the interface circuit are particularly important. By employing the input interface circuit with a noise canceller according to the present invention, it is possible to reliably prevent malfunction caused by electrostatic noise or the like between circuits operating in a separate power supply system. Therefore, the reliability of the circuit is improved.

  (17) The integrated circuit device of the present invention has the input interface circuit of the present invention.

  By mounting the interface circuit of the present invention, a serious malfunction of the internal circuit due to noise (for example, malfunction that the memory is reset) does not occur. Therefore, the reliability of the integrated circuit device is improved.

  (18) An electronic device of the present invention has the integrated circuit device of the present invention.

  By mounting the integrated circuit device of the present invention, a serious malfunction of the electronic device due to noise (for example, malfunction that the display on the panel disappears) does not occur. Therefore, the reliability of the electronic device is improved.

  Next, embodiments of the present invention will be described with reference to the drawings. Note that the present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are as means for solving the present invention. It is not always essential.

(First embodiment)
(Overall configuration of input interface circuit)
FIG. 1 is a block diagram showing an example of an input / output interface circuit of the present invention. Although an electrostatic protection circuit is usually provided in the input unit, the description is omitted in FIG. 1 for convenience.

  As illustrated, an IC (integrated circuit device) 90 includes an input terminal X to which a control signal (Vin) such as a reset signal (RSP) is input, an input interface circuit (block A), and an internal circuit (for example, And a logic circuit composed of a gate array having a memory: block B). The input interface circuit (block A) 100 is, for example, an I / O cell (input / output cell) arranged near the pad (external connection terminal) of the integrated circuit device 90.

  As described with reference to FIG. 17, when noise (electrostatic noise or the like) is input to the input terminal X instead of the regular control signal (Vin), for example, the memory in the block B is reset due to the noise. In order to prevent such a situation from occurring, the input interface circuit (block A) is provided with a noise detection circuit 200 and a noise canceller 500.

  The noise detection circuit 200 detects the noise input to the input terminal X separately from the normal input signal (Vin). A normal input signal operates between a high potential power supply (VDD) and a low potential power supply (VSS), but noise that significantly affects the operation of the circuit block B (internal logic circuit) 110 in the next stage. Often has a peak voltage value exceeding VDD or a voltage value lower than VSS, and focusing on the difference in voltage level, the noise detection circuit 200 detects noise by distinguishing it from a normal input signal (this) The point will be described later).

  The noise canceller 500 is complementarily turned on / off with respect to the first switch circuit SW1 inserted in a regular signal path connecting the input terminal X and the block B (internal logic circuit) 110 and the first switch circuit SW1. The second switch circuit SW2, the two inverters (INV1 and INV2), and the switching circuit 300 that switches the switches SW1 and SW2 in a complementary manner.

  When the noise detection signal NL from the noise detection circuit 200 is at an inactive level (L), the switching circuit 300 turns on the first switch circuit SW1, turns off the second switch circuit SW2, and also detects the noise detection signal. When NL is at the active level (H), the first switch circuit SW1 is turned off and the second switch circuit SW2 is turned on.

  When the first switch circuit SW1 is on, the normal signal (Vin) input to the input terminal X is passed through and transmitted to the block B (internal logic circuit) 110 in the next stage.

  When noise is applied to the input terminal X, the first switch circuit SW1 is quickly turned off, and transmission of noise to the block B is interrupted. At the same time when the first switch circuit SW1 is turned off, the second switch circuit SW2 is turned on, thereby forming a positive feedback path via the switch SW2 and the two inverters (INV1, INV2), and the output terminal of the switch SW1. The immediately preceding voltage is latched, and the latched voltage is supplied to the block B (internal logic circuit) 110.

  As described above, according to the input interface circuit of FIG. 1, when noise is input, the noise is cut off based on the detection result of the noise and a voltage without noise is output. Noise transmission to block B is reliably prevented.

(Specific configuration example and operation of input interface circuit)
FIG. 2 is a circuit diagram showing an example of a specific circuit configuration of the input interface circuit (block A) of FIG.

  As shown in the figure, the noise detection circuit 200 includes a noise detection P-channel transistor MP (with a source (first terminal) connected to the input terminal X and a gate connected to a high potential power supply voltage (HVDD) node. PtiMOS transistor FNWL formed in a floating N well region in which the potential of the N well can be adaptively adjusted, and when noise is applied to the input terminal X, the potential of the floating N well region is set to the potential of the input terminal X. One end is connected to the drain (second terminal) of the potential adjusting PMOS transistor M61 and the noise detecting transistor MP (FNWL), and the other end is connected to the low potential power supply voltage (VSS) node. And a resistance element R1.

  The source / drain of the noise detection PMOS transistor MP (floating N well transistor FNWL) is formed in the floating N well region. Here, the “floating well region” means “a well region in which the potential is not fixed and the potential can be adjusted adaptively (in a broad sense, a semiconductor substrate in which a transistor element is formed: general Either N type or P type).

  The potential adjustment transistor M61 is a transistor of the same size formed by the same manufacturing process as the noise detection PMOS transistor MP (FNWL), and the source is the input terminal X as in the noise detection PMOS transistor MP (FNWL). And the gate is connected to a high potential power supply voltage (HVDD) node.

  In addition, the noise canceller 500 includes a timing adjustment delay circuit 800 (configured by INV6 to INV9) inserted in a regular signal path, a through latch 400 that can switch through / latch of input signals, and 2 A switching circuit 300 (also serving as a noise detection path timing adjustment circuit 700) configured by inverters (INV4, INV5) in stages.

  The first switch circuit SW1 includes a transfer switch configured by combining a pair of PMOS transistors P1 / NMOS transistors N1, and similarly, the second switch circuit SW2 includes a pair of PMOS transistors P2 / NMOS transistors N2. Consists of transfer switches configured in combination.

  The output terminal of the first-stage inverter INV4 constituting the switching circuit 300 is connected to the gate of the NMOS transistor N1 and the gate of the PMOS transistor P2 constituting the transfer switch, and the output of the next-stage inverter INV5 constituting the switching circuit 300 The ends are connected to the gate of the PMOS transistor P1 and the gate of the NMOS transistor N2 constituting the transfer switch.

  The operation of the input interface circuit of FIG. 2 is as follows. In the following description, Vthp is the threshold voltage of the PMOS transistor (similarly, Vthn is the threshold voltage of the NMOS transistor).

  The noise detection PMOS transistor MP (floating N-well transistor FNWL) whose gate is connected to the high potential power supply potential (HVDD) node is turned on only when the potential of the source (first terminal) becomes (HVDD + Vthp) or higher. When the normal input signal Vin (voltage level is VDD or VSS) is input, the OFF state is maintained. The noise detection PMOS transistor MP (FNWL) is a gate-grounded transistor having excellent high frequency response characteristics, and can be turned on at high speed when noise is applied.

  When positive noise is applied to the input terminal X when Vin is at the L level (inactive level), the voltage level SL of the input terminal X changes from the low level to the high level. This change in voltage level is delayed by a predetermined amount by the delay circuit 800 and reaches the first switch circuit SW1.

  On the other hand, when the voltage level SL of the input terminal X rises to HVDD + Vthp or more by applying noise to the input terminal X, the noise detection transistor MP (FNWL) is turned on, and the noise is transmitted to the drain (second terminal). The At this time, the potential adjustment transistor M61 is also turned on at the same time, and the voltage level of the floating N well becomes the same as the voltage level of the source (first terminal) of the noise detection transistor. The PN junction diode D1 to be turned on does not turn on (this will be described later with reference to FIGS. 5 and 6).

  Assuming that the potential of the N well is fixed (for example, fixed to VSS), when noise is input, the parasitic diode D1 between the source of the noise detecting PMOS transistor MP and the N well (substrate in a broad sense) is Turns on and a transient current flows. At this time, since there is no element that limits the amount of current, an excessive current flows, and for example, the wiring may be blown and the element may be destroyed, or it may cause a latch-up.

  Further, when the parasitic diode D1 is turned on, the N-well potential is lowered by the forward voltage of the diode, thereby causing a fluctuation in the threshold voltage of the noise detecting PMOS transistor. That is, if the voltage level applied to the input terminal X is not higher than VDD + Vthp + Vf (Vf is the forward voltage of the parasitic diode), the noise detection transistor MP will not turn on, and the actual noise detection voltage and design value Deviation occurs between the two.

  Therefore, the potential can be adjusted according to the situation without fixing the potential of the N well region, and as described above, the potential adjusting PMOS transistor M61 is simultaneously turned on to make the potential of the floating N well the same as the source. The potential is set to prevent the parasitic diode D1 from being turned on, thereby preventing element destruction and Vth fluctuation due to excessive current.

  When the noise detection PMOS transistor MP is turned on, the potential at one end of the resistance element R1 (potential at the point b) rises, and thereby the noise detection signal becomes active level (H).

  Here, the resistance element R1 that generates the noise detection signal NL also has the following four functions. In other words, the function as “pull-down resistor: resistor that works to fix the voltage level of the noise detection path to ground when there is no noise” and “discharge resistor (excess noise energy at the time of noise input is AC grounded) Function as a "resistor that works to quickly break down and prevent the destruction of the noise detection transistor MP etc." and "sensing resistance (noise by changing the voltage level of the noise detection path when noise current is flowing) "Resistance having the function of generating the detection signal NL" and "Time constant setting resistance (Adjusting the recovery time until the noise detection signal returns to the inactive level after the noise detection signal becomes active level") Resistance) ”as well as a function.

  The resistance value of the resistance element R1 is set to a considerably high resistance. Therefore, when noise is input, the potential at the point b (one end of the resistance element R1) rises rapidly, whereby the first switch circuit SW1 can be quickly turned off.

  On the other hand, after the noise has passed, since the discharge of the electric charge to the ground is gradual, the potential at the point b gradually falls, thereby the first switch circuit after the noise has sufficiently decreased. SW1 can be turned back on (this point will be described in more detail later with reference to FIG. 4).

  As described above, the resistance element R1 has many functions, and thus, noise can be detected quickly and reliably with a simplified configuration without causing adverse effects on the circuit. Furthermore, by optimizing the resistance value of the resistance element R1, it is possible to adjust the return timing of the noise canceller after the noise has passed.

  As described above, the noise canceller 500 includes a through latch (holding circuit) 400 including the first and second switch circuits (SW1, SW2), and a switching circuit 300 (also having a function as the timing adjustment circuit 700). And having. In the normal state, the switching circuit 300 turns on the first switch circuit SW1 and outputs the input signal as it is from the output terminal of the through latch, and turns off the first switch circuit when noise is detected by the noise detection circuit 200. Then, by turning on the second switch circuit, the transmission of the input signal on which the noise is superimposed is interrupted, and at the same time, the signal immediately before being held in the through latch (holding circuit) 400 is changed to the inverter INV3 in the output stage. Through the output terminal (Y) of the through latch (see FIGS. 3A and 3B).

  In this way, a high-performance noise canceller can be configured by a simple circuit having versatility, which is advantageous in terms of power saving and space saving.

  In addition, as described above, in the input interface circuit of FIG. 2, the delay circuit 800 for timing adjustment (configured by the four-stage inverters INV6 to INV9) is provided between the input terminal X and the first switch circuit SW1. Is provided.

  The timing at which the first and second switch circuits (SW1 and SW2) are complementarily turned on / off depends on the realization of reliable blocking of noise and the first switch circuit SW1 in the duration of noise. This is important from the viewpoint of surely preventing a malfunction that returns to the ON state.

  Therefore, a delay circuit 800 for timing adjustment is provided between the input terminal X and the first switch circuit SW1. As a result, the timing at which noise reaches the first switch circuit SW1 is delayed. It is easy to shift the first switch circuit SW1 from on to off during the delayed period, considering that the noise detection signal NL can be obtained at high speed.

  Therefore, it is possible to ensure that the first switch circuit SW1 is turned off before the noise reaches the first switch circuit SW1, and therefore, reliable blocking of the noise is realized.

  3A and 3B are circuit diagrams showing the operation of the through latch. In FIG. 3A and FIG. 3B, a state in which a signal is transmitted is indicated by a thick arrow or a thick broken line.

  As shown in FIG. 3A, in the normal state (the state without noise), the first switch circuit SW1 is turned on, and the input signal is output as it is from the output terminal Y of the through latch. Further, as shown in FIG. 3B, at the time of noise detection, the immediately preceding signal (signal without noise) is latched, and the latched voltage is output from the output terminal Y.

  FIG. 4 is a timing chart showing the voltage change timing of each part in the input interface circuit of FIG. In FIG. 4, Vth (inv) is an inverter H / L determination threshold value (here, the midpoint voltage of the power supply voltage).

  When positive polarity noise is applied to the input terminal X, the voltage at the input terminal X rises rapidly, reaches the H / L determination threshold of the inverters (INV6 to INV9) at time t1, and reaches the high potential power supply voltage at time t2. (HVDD) is reached.

  The voltage at the point a (the input terminal of the first switch circuit SW1) rises to a high level at time t5 after the delay time T1 by the delay circuit 800 has elapsed from time t1.

  On the other hand, the voltage level at the point b (one end of the resistance element R1) is quickly increased from the timing t2 when the noise voltage level exceeds the high potential power supply voltage (HVDD) because the resistance element R1 has a high resistance. At a time t3, the threshold voltage (Vth (inv)) of the inverter INV4 is exceeded.

  The voltage level at the point c (the gate voltage of the PMOS transistor P1 constituting the transfer switch SW1 and the gate voltage of the NMOS transistor N2 constituting the transfer switch SW2) is slightly delayed by the switching circuit 300 (also serving as the timing adjustment circuit 700). After that, at time t4, the level becomes high. At this timing, the first switch circuit SW1 shifts from on to off, and the second switch circuit SW2 shifts from off to on. As a result, the transmission of noise is cut off and the previous voltage latch mode is switched.

  Since the first switch circuit SW1 shifts to the off state at a timing (time t4) before the timing at which the noise reaches the first switch circuit SW1 (time t5), the noise is reliably cut off, and the circuit is driven by the noise. Block B (internal logic circuit) 110 does not malfunction.

  When noise is no longer applied to the input terminal X, the voltage at the point a (the input terminal of the first switch circuit SW1) rises to a low level from time t7 to time t8 after the delay time T1 from the delay circuit 800 has elapsed. Go down.

  On the other hand, when the voltage level at the point b (one end of the resistance element R1) falls below the high potential power supply voltage (HVDD) at time t6, the noise detecting transistor MP is turned off, and the point b is discharged due to the discharge of the charge from the resistance element R1. The voltage level of gradually decreases. The resistance value of the resistance element R1 is set to be quite high. For this reason, since the discharge of the electric charge through the resistance element R1 to the ground is gradual, the voltage level at the point b gradually falls. The voltage level at point b falls below Vth (inv) at time t9.

  The voltage level at the point c (the gate voltage of the PMOS transistor P1 constituting the transfer switch SW1 and the gate voltage of the NMOS transistor N2 constituting the transfer switch SW2) is slightly delayed by the switching circuit 300 (also serving as the timing adjustment circuit 700). After that, at time t10, the level becomes low, and at this timing, the second switch circuit SW1 shifts from off to on, and the second switch circuit SW2 shifts from on to off. As a result, the through latch 400 returns from the latch mode to the through mode.

  As described above, the first switch circuit SW1 returns to the on state at time t10 that is slightly delayed from t9. Since the voltage level without noise has reached the input terminal of the switch circuit SW1 at time t8, no noise remains when the first switch circuit SW1 returns to the ON state, and there is no problem.

  In this way, the first switch circuit SW1 can be returned to the on state after a predetermined time (sufficient time) has elapsed from the timing at which noise is no longer detected, so that the delayed noise is erroneously detected. The situation that it is output does not occur.

  The timing control as described above can be easily realized by appropriately setting the resistance value of the resistance element R1 and the delay amount of the delay circuit 800.

(Optimization of potential in floating N well region)
FIGS. 5A and 5B are diagrams for explaining potential adjustment during noise detection in the floating N-well region of the noise detection transistor. FIG. 5A shows the configuration of the noise detection circuit 200 of FIG. 2 (the same reference numerals are given to the portions common to FIG. 2).

  FIG. 5B shows the device structure of the noise detection transistor (MP) (and the connection state of the potential adjustment transistor (M61) at the time of noise detection).

  As shown in the figure, a floating N well region 320 is provided on a P-type substrate 310, and source / drain regions (322 a and 322 b) are formed in the floating N well region 320.

  The surface of the P-type substrate 310 is covered with a gate insulating film 324, and a gate electrode 326 made of polysilicon or the like is formed on the gate insulating film 324.

  The floating N well region 320 is provided with an N + diffusion layer 323 for contact. A wiring L10 is connected to the N + diffusion layer 323, and an end of the wiring L10 is connected to, for example, another circuit. As a result, a predetermined voltage level is obtained.

  Parasitic diodes (parasitic PN junction diodes) D1 and D2 exist at the junction surface between the source / drain regions 322a and 322b and the floating N well region 320.

  When a noise is input to the input terminal X and the noise detecting PMOS transistor MP (floating N-well transistor FNWL) is turned on, a parasitic diode between the source 322a and the N-well (substrate in a broad sense) 320 is turned on. Since there is no element that limits the amount of current, for example, as shown in FIG. 5B, an excessive current I1 flows through the wiring L10, and the wiring is blown, for example, and the element is destroyed. Or may cause latch-up.

  Further, when the parasitic diode D1 is turned on, the N-well potential is lowered by the forward voltage of the diode, thereby causing a variation in the threshold voltage of the noise detection transistor. That is, if the voltage level applied to the input terminal X is not higher than VDD + Vthp + Vf (Vf is the forward voltage of the parasitic diode), the noise detection transistor MP will not turn on, and the actual noise detection voltage and design value Deviation occurs between the two.

  Therefore, the potential of the N well region 322a can be adjusted according to the situation without fixing the potential of the N well region 322a. At the same time, as described above, the noise detecting transistor MP is turned on and at the same time the potential adjusting transistor (first transistor) The potential adjusting transistor (M61) is also turned on, whereby the potential of the floating N well region 320 is set to the same potential as that of the source region 322a, and the parasitic diode D1 is prevented from being turned on, thereby preventing element destruction and threshold fluctuation due to excessive current. . As described above, the floating well region 320 is “a well region in which the potential is not fixed and the potential can be adaptively adjusted (a semiconductor region in a broad sense, a semiconductor region in which a transistor element is formed: general Is either N-type or P-type).

  6A and 6B are diagrams for explaining potential adjustment in the floating N well region in the noise detection transistor when noise is detected and when noise is not applied.

  6A and 6B, in addition to the configurations of FIGS. 5A and 5B, a potential for adjusting the potential of the floating N well region 320 in a state where noise is not applied. An adjustment PMOS transistor (second potential adjustment PMOS transistor) M63 is provided.

  The second potential adjusting PMOS transistor M63 has a gate connected to the input terminal X, a source (first terminal) connected to the high-potential power supply voltage HVDD, and a drain (second terminal) connected to the floating N well region 320. It is connected to the.

  5A and 5B, when the first potential adjustment PMOS transistor M61 is off (in this case, the noise detection PMOS transistor is also off), the floating N The potential of the well region is indefinite. Although this is not particularly a problem, it cannot be said that there will be no inconvenience in circuit operation.

  6A and 6B, a second PMOS transistor M63 for potential adjustment is added, and when the first potential adjustment PMOS transistor M61 is off, the second PMOS potential adjustment is performed. The transistor M63 is turned on, and the potential of the floating N well region 320 is adjusted to the high potential power supply voltage (HVDD) via the second potential adjusting PMOS transistor M63.

  As apparent from FIG. 6B, when the second potential adjusting PMOS transistor M63 is turned on, the potential of the floating N well region 320 becomes HVDD, whereby both the parasitic diodes D1 and D2 are reverse-biased, It is reliably prevented that a current path via the diode is formed.

  6A and 6B, the potential of the floating N well region 320 is stabilized both when noise is applied and when noise is not applied. As a result, there is no fear of adversely affecting the peripheral circuit due to the well region, and the stability (reliability) of the circuit can be further improved.

(Example of inserting a timing adjustment circuit into the noise detection path)
FIG. 7 is a circuit diagram showing another example of a method for optimizing the timing of complementary on / off of the first and second switches (SW1, SW2).

  In the input interface circuit of FIG. 2, the timing for returning the first switch circuit SW1 from OFF to ON depends on the time constant of the resistance element R1, but in the input interface circuit of FIG. 7, the resistance of the resistance element R1 The value is set low to reduce the time constant. Instead, the timing adjustment circuit 702 is inserted in the noise detection path.

  The timing adjustment circuit 702 has a first path having a delay amount larger than the delay amount of the delay circuit 800 for timing adjustment (path passing through INV10 to INV13) and a delay amount smaller than the delay amount of the delay circuit 800. And a gate circuit (specifically, NOR circuit) that receives a signal from the first path and a signal from the second path and outputs one signal. Gate: a gate circuit based on an OR gate) NOR1.

  The output voltage of the NOR gate NOR1 changes from H to L when the voltage level of the input terminal G becomes H, while only when the voltage levels of the two input terminals (F, G) become L. , L changes to H.

  Therefore, when the noise detection transistor MP is turned on and the voltage level at one end (point b) of the resistance element R1 changes from L to H, the voltage change passes through the second path (path with a small delay). The voltage level of the input terminal G changes from L to H. Therefore, the voltage level of the output of NOR1 changes from H to L, and thus noise is detected quickly.

  On the other hand, when the noise detection transistor MP is turned off and the voltage level at one end (point b) of the resistance element changes from H to L as noise is no longer applied, the voltage change occurs in the first path. It is transmitted to the input terminal F of NOR1 via (path passing through INV10 to INV13). The voltage of the input terminal G is inverted to L at an earlier timing, and the voltage level of the output of NOR1 returns from L to H after waiting for the voltage level of the input terminal F to change to L. The voltage change indicating that noise is no longer detected is substantially transmitted to the NOR 1 via the first path.

  In the case of FIG. 7, the resistance value of the resistor element R1 is set small to lower the discharge time constant. Instead, the delay amount of the inverters (INV10 to INV13) in the timing adjustment circuit 702 and the inverter (INNV6) in the delay circuit 800 are set. The ON / OFF timings of the first and second switches (SW1, SW2) can be adjusted with high accuracy by the delay amount by .about.INV9).

(Example of inserting the timing adjustment circuit into the regular signal path)
FIG. 8 is a circuit diagram showing still another example of a method for optimizing the timing of complementary on / off of the first and second switches (SW1, SW2).

  In FIG. 8, the timing adjustment circuit 810 is provided on the regular input signal side. The timing adjustment circuit 810 includes a first delay path having a predetermined delay amount for timing adjustment (a path passing through INV14 to INV17) and a second path having a delay amount smaller than the first delay path ( INV14 to INV17 bypass) and a gate circuit that receives a signal from the first path and a signal from the second path and outputs one signal (specifically, NAND gate: logical product gate) Gate circuit).

  The output voltage level of the NAND gate NAND1 changes from L to H when the voltage level of the input terminal Y becomes L, while the voltage levels of both of the two input terminals (X, Y) become H. Only when changes from H to L.

  The timing adjustment circuit is inserted into the normal signal transmission path. The timing adjustment circuit includes a first path having a predetermined delay amount, a second path having a small delay, and a gate circuit (specifically, a NAND gate: a gate circuit based on an AND gate). Constitute.

  Since the positive noise applied to the input terminal X is substantially delayed and transmitted via the first path, the first switch before the noise reaches the first switch circuit SW1. It is easy to turn off the circuit SW1 with a margin.

  When noise is no longer applied, the voltage change is quickly transmitted via the second path with a small delay amount. Therefore, after the voltage at the input terminal (point a) of the first switch circuit SW1 returns to the potential when there is no noise, it is easier to return the first switch circuit from OFF to ON (that is, When the first switch circuit SW1 is returned to the ON state, a situation in which delayed noise remains is prevented). Therefore, the on / off timing of the first and second switch circuits (SW1, SW2) can be more easily optimized.

(Configuration with a Schmitt circuit inserted in the regular signal path)
FIG. 9 is a circuit diagram showing an input interface circuit having a configuration in which a Schmitt circuit is inserted in a regular signal path.

  As shown in the figure, a regular signal path connecting the input terminal X and the first switch circuit SW1 has an input buffer SH having hysteresis characteristics as input / output characteristics and one end connected to an output terminal of the input buffer SH. And a smoothing capacitor C10.

  In the above-described input interface circuit, it is assumed that excessive noise exceeding the power supply voltage is applied to the input terminal, but small noise that does not exceed the power supply voltage is also assumed as noise. It can be said that it is preferable to remove such small-scale noise from the viewpoint of more surely preventing malfunction of the circuit in the next stage.

  Therefore, an input buffer (for example, a Schmitt circuit) SH having hysteresis in input / output characteristics and a smoothing capacitor C10 are provided in a regular signal transmission path. The input buffer SH has an input dead band (that is, an input range in which the output level does not change even if the input signal level fluctuates) due to the hysteresis characteristic, and the amplitude of a small noise is within this input dead band width. If it is within the range, the small-scale noise is not output from the input buffer SH.

  In the unlikely event that a small-scale noise is output, an erroneous control signal (such as a reset signal or a chip enable signal) is input to the next stage circuit (circuit block B) by smoothing the noise by the smoothing capacitor C10. Can be prevented. This can enhance the noise removal function of the input interface circuit.

(Second Embodiment)
In the above-described embodiment, the case of canceling the positive polarity noise exceeding the high potential power supply voltage (HVDD) has been described. However, in this embodiment, the negative polarity noise lower than that of the low potential power supply (VSS: GND) is used. A case of canceling will be described.

  In this embodiment, a floating P-well is used, and an NMOS transistor is used as the noise detection transistor and the first and second potential adjustment transistors. A pull-up resistor is used as the resistance element. The obtained effect is substantially the same as the above-described embodiment.

  FIG. 10 is a circuit diagram showing a configuration of an input interface circuit having a noise canceller that cancels negative noise lower than a low-potential power supply voltage.

  The basic configuration of the input interface circuit of FIG. 10 is the same as the configuration of the input interface circuit of FIG. 2, but in the case of FIG. 10, the configuration of the noise detection circuit 202 is different from that of FIG.

  That is, the noise detection circuit 202 in FIG. 10 includes an NMOS transistor MN whose gate is grounded (connected to the ground) (a floating P well transistor FPWL in which a source and a drain are formed in a floating P well region). And a resistor element R2 having one end connected to the node of the high potential power supply voltage (HVDD).

  The noise detection transistor (NMOS transistor) MN is turned on when the voltage at the input terminal X becomes (GND−Vthn) or less, and as a result, the voltage at one end of the resistance element R2 changes from H to L (when noise is detected). The active level).

  FIG. 11 is a timing chart showing the voltage change timing of each part of the input interface circuit of FIG. As shown in FIG. 11, when noise lower than the low potential power supply (GND) is input to the input terminal X, the noise is delayed by the delay amount T1 of the delay circuit 800 and transmitted. The noise detection transistor MN is turned on, and the voltage at the point b starts to drop from time t12. At time t14, the first switch circuit SW1 shifts from on to off.

  Similarly, when noise is no longer applied, the voltage at point a returns to the original voltage level at time t18, and the first switch circuit SW1 returns from OFF to ON at time t20. Note that t11 to t20 in FIG. 11 correspond to t1 to t10 in FIG.

  12A and 12B are circuit diagrams showing a configuration example of a noise detection circuit using a floating P-well transistor.

  FIG. 12A corresponds to the circuit configuration of FIG. As shown in the figure, a first potential adjusting NMOS transistor M71 is provided to adjust the potential of the floating P well region of the noise detecting NMOS transistor (MN).

  FIG. 12B corresponds to the circuit configuration of FIG. In FIG. 12B, a second potential adjusting NMOS transistor M73 is added to adjust the potential of the floating P well when noise is not detected. When noise is not detected, the second potential adjusting NMOS transistor M73 is turned on, and the voltage level of the floating P well region is adjusted to the ground level. As a result, the parasitic diode is reverse-biased, and the generation of a current path via the parasitic diode is reliably prevented.

  Note that the same circuit configuration as shown in each of FIGS. 7 to 9 can also be employed in an input interface circuit having a configuration for removing negative noise.

(Third embodiment)
In the present embodiment, a layout configuration example of an integrated circuit device (IC) equipped with the input interface circuit of the present invention and variations in the configuration of the input interface circuit (I / O cell) will be described.

  FIG. 13 is a diagram for explaining a layout configuration example of an integrated circuit device (IC) on which the input interface circuit of the present invention is mounted.

  I / O cells 100a to 100d as input interface circuits are provided around the chip of the integrated circuit device (IC) 90 of FIG. In the center of the chip, a core circuit 610 having an internal logic circuit 110 formed by a semi-custom IC design method such as a gate array is provided.

  In FIG. 13, the I / O cells (100a to 100d) and the core circuit 610 are operated by a power supply of a different system. That is, the I / O cells (100a to 100d) operate with a high potential power supply voltage (HVDD: 3V, for example), and the core circuit 610 operates with a low potential power supply voltage (LVDD: 1.8V, for example). The I / O cells (100a to 100d) include a level shift circuit (not shown) at the output stage, and the level shift circuit operates with a high potential power supply voltage (HVDD).

  That is, in the IC of FIG. 13, the front stage portion of the I / O cell (input interface circuit) operates with the first power supply voltage, the rear stage portion operates with the second power supply voltage, and the internal circuit in the integrated circuit device. The circuit is also a circuit system that operates with the second power supply voltage.

  In such a circuit block that operates with a power supply voltage of another system, each circuit operates independently and noise is also generated independently. Therefore, noise countermeasures are particularly important in the interface circuit (I / O cell).

  By employing the I / O cells (input interface circuits) 100a to 100d with the noise canceller of the present invention, it is possible to reliably prevent malfunction caused by electrostatic noise or the like between circuits operating in a separate power supply system. it can. Therefore, the reliability of the circuit is improved.

  In FIG. 13, it is assumed that a path (route indicated by a bold line in the figure) connecting the I / O cells (input interface circuits) 100a and 100b and the internal logic 110 is critical to the internal circuit due to noise. When the other path is not a critical path, an I / O cell equipped with the noise canceller of the present invention may be provided only in the critical path. In this case, an increase in the occupied area of the I / O cell can be minimized.

  FIG. 14 is a diagram for explaining a method of selectively forming a floating well and a normal well with a fixed potential when an I / O cell equipped with the noise canceller of the present invention is provided only in the critical path. It is.

  When an I / O cell equipped with the noise canceller of the present invention is provided only in a critical path, it is necessary to form a floating well in the I / O cell intervening in the critical path, and intervene in paths other than the critical path. It is necessary to form a normal potential-fixed well in the I / O cell.

  In the case of FIG. 13, since the I / O cells 100a to 100d are also formed by a gate array-like method, the wells can be easily used only by changing the wiring form. In FIG. 14A, a floating N-well is constructed. In FIG. 14B, a normal potential fixed N well is constructed by changing the wiring and connecting the floating N well 320 to HVDD.

  By mounting the input interface circuit having the noise canceller of the present invention on the integrated circuit device (IC) 90, a serious malfunction of the internal circuit due to noise (for example, malfunction that the memory is reset) does not occur. Therefore, the reliability of the integrated circuit device (IC) 90 is improved.

(Fourth embodiment)
In this embodiment, an example of an electronic device equipped with an integrated circuit device (IC) incorporating the input interface circuit of the present invention will be described. Although this electronic device is ultra-compact and lightweight, it does not malfunction due to, for example, the input of an ESD pulse (electrostatic discharge pulse), and the reliability of ESD is guaranteed. For example, the malfunction that the display on the panel disappears due to noise does not occur, and thus the reliability of the electronic device is improved.

FIG. 15A to FIG. 15C are diagrams each showing an external appearance of an example of an electronic device equipped with the malfunction prevention circuit of the present invention.
FIG. 15A illustrates an example of an external view of a cellular phone 950 that is one of electronic devices. The cellular phone 950 includes a dial button 952 that functions as an input unit, an LCD 954 that displays a telephone number, a name, an icon, and the like, and a speaker 956 that functions as a sound output unit and outputs sound.

  FIG. 15B illustrates an example of an external view of a portable game device 960 that is one of electronic devices. The portable game device 960 includes an operation button 962 that functions as an input unit, a cross key 964, an image output unit 966 that displays a game image, and a speaker 968 that functions as a sound output unit and outputs game sound.

  FIG. 15C illustrates an example of an external view of a portable information device (PDA) 970 that is one of electronic devices. The portable information device (PDA) 970 includes a keyboard 972 that functions as an input unit, an image output unit 974 that displays characters, numbers, graphics, and the like, and a sound output unit 976.

  Note that the present invention can be applied in addition to those shown in FIGS. 15A, 15B, and 15C. For example, the present invention can be applied to electronic devices such as personal computers, pagers, electronic desk calculators, devices equipped with touch panels, projectors, word processors, viewfinder type or monitor direct view type video tape recorders, car navigation devices, and the like. Is possible.

As described above, according to the embodiment of the present invention, the following main effects can be obtained. However, the following effects are examples, and not all effects can be obtained at the same time. The enumeration of the following effects should not be used as a basis for illegally interpreting the technical scope of the present invention.
(1) Since noise is detected and signal transmission is interrupted by the noise cancellation circuit during the period in which noise continues, erroneous signal transmission between circuit blocks is reliably prevented regardless of the duration of noise. Can do. In addition, for example, a special case in which continuous pulsed noise is input when a regular input signal is active (for example, the reset signal is H) can be assumed. Every time it is detected, the signal transmission path is interrupted and the previous voltage level is maintained, so that even oscillating noise can be reliably removed, and no problem occurs.
(2) Both positive and negative noises can be handled.
(3) Timing control is performed when generating the noise detection signal, and in particular, by combining with the delay of the input signal to the noise cancellation circuit, transmission of an erroneous signal (noise) from the circuit block A to the circuit block B is further improved. It can be surely prevented.
(4) By configuring the noise cancellation circuit with a holding circuit (through latch), noise can be removed with a simple circuit.
(5) As a method for detecting noise with a positive polarity pulse superimposed, a gate-grounded switching transistor is used, the switching transistor is turned on at high speed by comparing the source potential and the gate potential, and a pull-down (or pull-up) resistor is used. By adopting a method of detecting noise by quickly absorbing the noise in the formed path and detecting the potential change at one end of the pull-down (pull-up) resistor with a logic gate, Noise can be detected quickly and efficiently while protecting the circuit from destruction.
(6) A floating well switching transistor is used as a noise detection transistor, and a transistor for adjusting the potential of the substrate (well) region is provided to constantly stabilize the potential of the substrate (well region) immediately below the gate. By performing (optimizing), the input / output interface circuit of the present invention can be used with confidence without adversely affecting other circuits when noise is input.
(7) By optimizing the delay amount of the delay circuit and the resistance value of the resistance element, or adopting a timing adjustment circuit having a devised configuration, the on / off timing of the two switch circuits constituting the noise canceller can be easily achieved. Can be optimized.
(8) Since the input / output interface circuit of the present invention has a small number of elements and is compact, it can be easily arranged in an I / O cell such as a gate array or an internal logic circuit.
(9) According to the present invention, it is possible to provide an input interface circuit capable of preventing the electrostatic noise from being transmitted to the internal circuit when the electrostatic noise is applied to the signal input terminal. .
(10) According to the present invention, it is possible to reliably prevent malfunction caused by noise in the integrated circuit device and the electronic apparatus, and the reliability thereof is improved.
(11) The present invention is effective in improving ESD immunity (electrostatic discharge resistance) of integrated circuit devices, which have recently been particularly emphasized.

  In addition, although this embodiment was explained in full detail, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention.

  In the integrated circuit device, when noise is input to an input terminal due to ESD or the like, transmission of an erroneous signal (noise) generated due to the power supply noise is reliably prevented. Therefore, it is useful as an input / output interface circuit, an integrated circuit device, and an electronic device.

The block diagram which shows an example of the input-output interface circuit of this invention A circuit diagram showing an example of a specific circuit configuration of the input interface circuit (block A) of FIG. 3A and 3B are circuit diagrams showing the operation of the through latch. FIG. 2 is a timing chart showing the voltage change timing of each part in the input interface circuit of FIG. FIGS. 5A and 5B are diagrams for explaining potential adjustment during noise detection in the floating N-well region of the noise detection transistor. FIGS. 6A and 6B are diagrams for explaining potential adjustment in the floating N-well region of the noise detection transistor when noise is detected and when noise is not applied. The circuit diagram which shows the other example of the method of optimizing the timing which turns on / off complementarily the 1st and 2nd switch (SW1, SW2) The circuit diagram which shows the further another example of the method of optimizing the timing which turns on / off complementarily the 1st and 2nd switch circuit Schematic diagram showing an input interface circuit having a configuration in which a Schmitt circuit is inserted in a regular signal path. Circuit diagram showing the configuration of an input interface circuit having a noise canceller that cancels negative-polarity noise lower than the low-potential power supply voltage FIG. 10 is a timing chart showing the voltage change timing of each part of the input interface circuit of FIG. 12A and 12B are circuit diagrams showing a configuration example of a noise detection circuit using a floating P-well transistor. The figure for demonstrating the layout structural example of the integrated circuit device (IC) which mounts the input interface circuit of this invention 14 (A) and 14 (B) show that when a I / O cell equipped with the noise canceller of the present invention is provided only in the critical path, a floating well and a normal well with a fixed potential are selectively used. The figure for demonstrating the method of forming FIGS. 15A to 15C are diagrams each illustrating an external appearance of an example of an electronic device in which the malfunction prevention circuit of the present invention is mounted. Diagram for explaining an example of ESD immunity test Circuit diagram for explaining malfunction of circuit block caused by electrostatic noise being applied to signal input terminal

Explanation of symbols

100 input interface circuit (circuit block A),
110 internal logic circuit (circuit block B), 200 noise detection circuit,
300 switching circuit, 400 holding circuit (through latch),
500 noise canceller, SW1 first switch circuit transfer switch),
SW2 Second switch circuit (transfer switch),
SL Normal signal path voltage, NL noise detection path voltage, X input terminal,
Y output terminal, R1, R2 resistance elements MP, MN for detecting noise, noise detection transistors (floating well transistors),
M61 first potential adjustment transistor, M63 second potential adjustment transistor

Claims (18)

A noise detection circuit for detecting a noise at a voltage level exceeding the high potential power supply voltage applied to the input terminal or a noise at a voltage level lower than the low potential power supply and outputting a noise detection signal;
A noise canceller that is provided between the input terminal and a circuit that receives a signal from the input terminal, and that blocks signal transmission from the input terminal to the circuit when the noise detection signal is active. ,
The noise canceller is
A first switch circuit provided between the input terminal and the circuit and turned off when the noise detection signal is active and turned on when the noise detection signal is inactive; and turned on when the noise detection signal is active A second switch circuit that turns off when inactive,
When the first switch circuit is turned off and the second switch circuit is turned on, the voltage at the output terminal of the first switch circuit is held, and the held voltage is supplied to the circuit.
An input interface circuit characterized by that. The input interface circuit according to claim 1,
The noise detection circuit includes:
It is formed in a floating N well region whose potential is adjusted according to the voltage of the input terminal, the gate is connected to the node of the high potential power supply voltage, the source is connected to the input terminal, and a signal is output from the drain. A PMOS transistor for noise detection;
A resistance element for generating the noise detection signal, one end of which is connected to the drain of the PMOS transistor for noise detection and the other end of which is connected to a node of the low potential power source;
An input interface circuit comprising: The input interface circuit according to claim 1,
The noise detection circuit includes:
Noise that is formed in a floating P-well region whose potential is adjusted according to the voltage of the input terminal, the gate is connected to the node of the low-potential power source, the source is connected to the input terminal, and a signal is output from the drain A detection NMOS transistor;
One end of the noise detection NMOS transistor is connected to the drain, and the other end is connected to the node of the high-potential power supply voltage.
An input interface circuit comprising: An input interface circuit according to claim 2,
When the gate is connected to the node of the high potential power supply voltage, the source is connected to the input terminal, the drain is connected to the floating N well region, and the noise detection PMOS transistor is turned on, the applied voltage of the input terminal is An input having a first PMOS transistor for adjusting the potential of the floating N-well region, which is applied to the floating N-well region, thereby setting the potential of the floating N-well region to the potential of the input terminal. Interface circuit. An input interface circuit according to claim 3,
When the gate is connected to the low potential power source, the source is connected to the input terminal, the drain is connected to the floating P-well region, and the noise detection NMOS transistor is turned on, the voltage applied to the input terminal is changed to the floating P An input interface circuit comprising: a first NMOS transistor for adjusting the potential of the floating P well region, which is applied to the well region, thereby setting the potential of the floating P well region to the potential of the input terminal. An input interface circuit according to claim 4,
A gate is connected to the input terminal, a source is connected to the node of the high-potential power supply voltage, a drain is connected to the floating N well region, and a potential adjustment for the noise detecting PMOS transistor and the floating N well region is performed. An input further comprising: a second PMOS transistor for adjusting the potential of the floating N well region for applying the high potential power supply voltage to the floating N well region when both of the first PMOS transistors are turned off. Interface circuit. An input interface circuit according to claim 5,
A gate is connected to the input terminal, a source is connected to the low-potential power source, a drain is connected to the floating P well region, and a first potential adjusting first transistor for adjusting the potential of the noise detecting NMOS transistor and the floating P well region. An input interface circuit further comprising: a second NMOS transistor for adjusting the potential of the floating P well region, which applies the low potential power supply voltage to the floating P well region when both NMOS transistors are turned off. An input interface circuit according to any one of claims 2, 4, and 6,
The noise detection PMOS transistor is turned on when a voltage equal to or higher than a voltage obtained by adding the threshold voltage of the noise detection PMOS transistor to the high potential power supply voltage is applied to the source terminal connected to the input terminal. An input interface circuit characterized by: An input interface circuit according to any one of claims 3, 5, and 7,
In the noise detection NMOS transistor, a voltage equal to or lower than a voltage obtained by subtracting a threshold voltage of the noise detection NMOS transistor from the low potential power source is applied to the source terminal connected to the input terminal (X). An input interface circuit characterized by being turned on by. An input interface circuit according to any one of claims 1 to 9,
The noise canceller is
An input terminal is connected to a transfer gate as the first switch circuit, a transfer gate as the second switch circuit, an output terminal of the first switch circuit, and a common connection point of the second switch circuit. A first inverter, and a second inverter having an input terminal connected to an output terminal of the first inverter and an output terminal connected to an input terminal of the second switch circuit. The output signal of one switch circuit is passed through to the circuit, or the output signal of the first switch circuit is latched by a positive feedback path passing through the first and second inverters and the second switch circuit A through latch that can be switched
A third inverter for receiving the noise detection signal obtained from the resistance element; and a fourth inverter connected to an input terminal at an output terminal of the third inverter, and an output of the third inverter In order to complementarily turn on / off the first switch circuit and the second switch circuit from each of a common connection point between the terminal and the input terminal of the fourth inverter and an output terminal of the fourth inverter A switching circuit for generating a switching control signal of
An input interface circuit comprising: The input interface circuit according to any one of claims 1 to 10,
An input interface circuit, further comprising a timing adjustment delay circuit provided between the input terminal and the first switch. An input interface circuit according to claim 11,
At a second timing before the first timing at which the potential at the input terminal of the first switch circuit changes due to the application of noise to the input terminal, the first switch circuit is turned on. At a fourth timing after the third timing at which the potential at the input terminal of the first switch circuit changes due to the transition to the off state and no noise being applied to the input terminal. An input interface circuit, wherein a delay amount of the delay circuit and a resistance value of the resistance element are set so that the first switch circuit returns from an off state to an on state. An input interface circuit according to any one of claims 2 to 10,
A timing adjustment circuit connected to one end of the resistance element;
The timing adjustment circuit includes:
A first path having a delay amount larger than a delay amount of the delay circuit for timing adjustment, a second path having a delay amount smaller than the delay amount of the delay circuit, and a first path from the first path Receiving a signal and a signal from the second path and outputting one signal, and
When the noise detection transistor is turned on with the application of noise to the input terminal and the voltage level at one end of the resistance element changes, the voltage change is transmitted via the second path,
When the noise detecting transistor is turned off and the voltage level at one end of the resistance element changes as the noise is no longer applied to the input terminal, the voltage change passes through the first path. An input interface circuit characterized by being transmitted. An input interface circuit according to any one of claims 2 to 10,
A timing adjustment circuit provided between the input terminal and the first switch circuit;
The timing adjustment circuit includes:
A first delay path having a predetermined delay amount for timing adjustment, a second path having a delay amount smaller than the first delay path, a signal from the first path, and the second path A gate circuit that receives a signal from the path and outputs one signal,
When the voltage level of the input terminal of the timing adjustment circuit changes with the application of noise to the input terminal, the voltage change is transmitted via the first path,
When the voltage level at the input terminal of the timing adjustment circuit changes as the noise is no longer applied to the input terminal, the voltage change is transmitted via the second path. Input interface circuit. The input interface circuit according to any one of claims 1 to 14,
An input buffer having a hysteresis characteristic, inserted in a path connecting the input terminal and the first switch circuit, and a smoothing capacitor having one end connected to the output end of the input buffer. Input interface circuit. The input interface circuit according to any one of claims 1 to 15,
The input interface circuit, wherein the power supply voltage of the noise detection circuit and the power supply voltage of the circuit receiving the signal from the input terminal are power supply voltages of different systems.   An integrated circuit device comprising the input interface circuit according to claim 1.   An electronic apparatus comprising the integrated circuit device according to claim 17.

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