JP2008277640A - Nitride semiconductor device - Google Patents

Abstract

A nitride semiconductor device that is normally off type, has low gate leakage current, and low on-resistance is provided.
In a GaN-HFET provided with a channel layer 1 made of GaN, a barrier layer 2 made of AlGaN, a source electrode 3, a drain electrode 4 and a gate electrode 5, a source electrode 3 and a gate electrode on the upper surface of the barrier layer 2 are provided. A field insulating film 6 containing Si is formed so as to cover the region between the gate electrode 5 and the region between the gate electrode 5 and the drain electrode 4. On the other hand, a gate insulating film 7 containing no Si is formed between the gate electrode 5 and the barrier layer 2.
[Selection] Figure 1

Description

  The present invention relates to a nitride semiconductor device, and more particularly to a lateral power nitride semiconductor device.

  Since gallium nitride (GaN) has a larger band gap than silicon (Si), a semiconductor device using GaN has a higher critical electric field than a semiconductor device using Si, and it is easy to realize a small and high breakdown voltage device. For this reason, if a semiconductor element for power control is produced using GaN, an element with low on-resistance and low loss can be realized. In particular, a field effect transistor (HFET) using an AlGaN / GaN heterostructure can be expected to have good characteristics with a simple element structure.

  In such a GaN-HFET, an AlGaN layer is formed as a barrier layer on a GaN layer as a channel layer, and a source electrode, a gate electrode, and a drain electrode are provided thereon. Then, due to the dopant in the AlGaN layer and the polarization at the AlGaN / GaN hetero interface, a two-dimensional electron gas (2DEG) is generated at a high concentration in the vicinity of the interface with the AlGaN layer in the GaN layer, and the drain electrode using the 2DEG as a carrier A current can flow between the source electrode and the source electrode. Thereby, the GaN-HFET realizes a low on-resistance.

  In this case, 2DEG is generated on the entire surface of the heterointerface due to the dopant in the AlGaN layer and the polarization of the AlGaN / GaN heterointerface. For this reason, the GaN-HFET is normally a normally-on device. However, an element used for power control is desirably a normally-off element from the viewpoint of preventing an inrush current when a circuit is powered on.

  As means for realizing a normally-off type element, there is a method of reducing the thickness of the AlGaN layer to about several nm. If the AlGaN layer is made thinner, the 2DEG concentration at the AlGaN / GaN hetero interface is reduced and the gate threshold voltage is shifted to the positive side, so that a normally-off device can be realized. However, reducing the 2DEG concentration increases the on-resistance of the element.

On the other hand, by forming a passivation film containing Si, such as SiN or SiO ₂ , on the AlGaN layer, a bond between Si and N is generated at the interface between the AlGaN layer and the passivation film, and the same effect as when Si is doped is obtained. And the 2DEG concentration at the AlGaN / GaN heterointerface can be increased (see, for example, Non-Patent Document 1). This method can also control the 2DEG concentration. However, even in this case, if an insulating film containing Si such as SiN or SiO ₂ is formed under the gate electrode in order to reduce the gate leakage current, there is a problem that the 2DEG concentration increases and a normally-on type is obtained. .

Masataka Higashiwaki et. Al., "AlN / GaN Insulated-Gate HFETs Using Cat-CVD SiN" IEEE Electron Device Letters, Vol.27, No.9, September 2006, p.719-721

  An object of the present invention is to provide a nitride semiconductor device which is of a normally-off type, has a small gate leakage current and a low on-resistance.

  According to one aspect of the present invention, a first semiconductor layer made of an undoped nitride semiconductor and a nitride semiconductor provided on the first semiconductor layer and having a band gap forming the first semiconductor layer are provided. A second semiconductor layer made of a nitride semiconductor wider than a band gap; first and second main electrodes provided on the second semiconductor layer and connected to the second semiconductor layer; A control electrode provided between the first main electrode and the second main electrode on the second semiconductor layer, and provided at least between the lower part of the control electrode and the second semiconductor layer. A gate insulating film, a region between the lower portion of the control electrode and the first main electrode on the upper surface of the second semiconductor layer, and a region between the lower portion of the control electrode and the second main electrode; A field insulating film covering the field Enmaku comprises silicon, the gate insulating film is a nitride semiconductor device characterized by containing no silicon is provided.

  According to the present invention, it is possible to realize a normally-off type nitride semiconductor device having a small gate leakage current and a low on-resistance.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same or corresponding part in drawing.

(First embodiment)
FIG. 1 is a cross-sectional view schematically illustrating the configuration of a nitride semiconductor device according to the first embodiment of the invention.
As shown in FIG. 1, the nitride semiconductor device according to the present embodiment is a horizontal power semiconductor device. In this semiconductor element, a channel layer 1 made of an undoped nitride semiconductor is provided as a first semiconductor layer on a substrate (not shown), and a second semiconductor layer is formed on the channel layer 1. As shown, a barrier layer 2 made of a nitride semiconductor is provided. The band gap of the nitride semiconductor forming the barrier layer 2 is wider than the band gap of the nitride semiconductor forming the channel layer 1. On the barrier layer 2, a source electrode 3 as a first main electrode and a drain electrode 4 as a second main electrode are formed as ohmic electrodes.

  Further, a gate electrode 5 as a control electrode is provided between the source electrode 3 and the drain electrode 4 on the barrier layer 2. A gate insulating film 7 is provided between the barrier layer 2 and the gate electrode 5, and the gate electrode 5 is insulated from the barrier layer 2 by the gate insulating film 7. Furthermore, the region between the gate electrode 5 and the source electrode 3 on the upper surface of the barrier layer 2 and the region between the gate electrode 5 and the drain electrode 4 (hereinafter collectively referred to as “offset region”) It is covered with an insulating film 6. That is, the field insulating film 6 is in contact with the offset region on the upper surface of the barrier layer 2. In the present embodiment, the gate electrode 5 is provided only in the region immediately above the gate insulating film 7. Therefore, in the direction from the source electrode 3 to the drain electrode 4, the length of the gate electrode 5 is the length of the gate insulating film 7. Equal to length. The field insulating film 6 is thicker than the gate insulating film 7. For this reason, the lower part of the gate insulating film 5 is embedded in the field insulating film 6.

The film thickness of the barrier layer 2 itself is set to such a thin film thickness that does not generate a two-dimensional electron gas (2DEG) sufficient to make the nitride semiconductor device normally on the interface with the channel layer 1. ing. On the other hand, the field insulating film 6 contains silicon (Si). For example, the field insulating film 6 is formed of an insulating material containing Si such as silicon nitride (SiN), silicon oxide (SiO ₂ ), or silicon oxynitride (SiON). On the other hand, the gate insulating film 7 does not contain silicon. That is, the gate insulating film 7 is formed of an insulating material not containing Si, for example, a single layer film made of aluminum nitride (AlN), gallium nitride (GaN), or aluminum oxide (Al ₂ O ₃ ), or A multilayer film in which these single-layer films are laminated, for example, an (Al ₂ O ₃ / GaN) bilayer film or an (Al ₂ O ₃ / AlN) bilayer film.

In one example, the channel layer 1 is made of undoped GaN. The barrier layer 2 is made of undoped AlGaN. Therefore, the nitride semiconductor device according to this embodiment is a GaN-HFET having an AlGaN / GaN hetero interface. And when the composition of the barrier layer 2 is Al _X Ga _1-X N (0 ≦ X ≦ 1) and the film thickness of the barrier layer 2 is t (nm), the film thickness t satisfies the following formula 1. . For example, the Al composition ratio X is about 0.15 to 0.25, and the film thickness t is several nm.

t ≦ 1 / (1.15X ² + 0.326X + 0.01) (1)

Next, the operation of this embodiment will be described.
In FIG. 2, the horizontal axis represents the Al composition ratio X of the barrier layer, and the vertical axis represents the thickness t ₀ of the barrier layer when the threshold voltage of a GaN-HFET incorporating this barrier layer is zero. FIG. 5 is a graph illustrating the influence of the composition and thickness of the barrier layer on the threshold voltage of the GaN-HFET.
A curve L shown in FIG. In the lower left region of the curve L in FIG. 2, that is, in the region satisfying the above equation 1, the GaN-HFET is normally off, and in the upper right region of the curve L, that is, in the region not satisfying the above equation 1. The GaN-HFET is normally on.

t ₀ = 1 / (1.15X ² + 0.326X + 0.01) (2)

  In the present embodiment, the composition and film thickness of the barrier layer 2 satisfy the above mathematical formula 1, and correspond to the lower left region from the curve L in FIG. A sufficient amount of 2DEG is not generated at the interface with the layer 2 to make the GaN-HFET normally on.

  However, a field insulating film 6 containing Si is provided in the offset region on the barrier layer 2. As a result, an Si—N bond is generated at the interface between the field insulating film 6 and the barrier layer 2, and the same effect as when the barrier layer 2 is doped with Si is obtained. Since Si acts as an N-type dopant with respect to AlGaN constituting the barrier layer 2, this increases the 2DEG concentration at the interface between the channel layer 1 and the barrier layer 2. On the other hand, the field insulating film 6 is not provided immediately below the gate electrode 5, but the gate insulating film 7 containing no Si is provided. Accordingly, the 2DEG concentration does not increase immediately below the gate electrode 5. Thereby, the same effect as the case where Si is selectively doped in the offset region can be obtained.

  As a result, at the interface between the channel layer 1 and the barrier layer 2, the 2DEG concentration is relatively low in the region immediately below the gate electrode 5, and the offset region, that is, the region between the source electrode 3 and the gate electrode 5. In the region between the gate electrode 5 and the drain electrode 4, the 2DEG concentration is relatively high. As a result, when the potential of the gate electrode 5 is 0, the region immediately below the gate electrode 5 is depleted and the 2DEG concentration becomes 0. That is, the threshold voltage of the nitride semiconductor element becomes positive, and a normally-off operation is realized. On the other hand, in the offset region, since 2DEG having a sufficient concentration is generated, the resistance is small. Thereby, the on-resistance of the nitride semiconductor element can be reduced.

Next, the effect of this embodiment will be described.
As described above, in this embodiment, the combination of 1) the thin barrier layer 2, 2) the field insulating film 6 containing Si, and 3) the gate insulating film 7 not containing Si has a 2DEG concentration immediately below the gate electrode 5. Can be made relatively low, the 2DEG concentration in the offset region can be made relatively high, and both normally-off operation and low on-resistance can be achieved. For example, the normally-off operation can be surely realized by forming the barrier layer 2 of AlGaN and restricting the relationship between the Al composition ratio X and the film thickness t so as to satisfy the above formula 1.

  On the other hand, if the field insulating film containing Si is not provided simply by making the barrier layer thin, the 2DEG concentration is lowered in the entire region at the interface between the channel layer and the barrier layer. In this case, although a normally-off operation can be realized, the resistance in the offset region becomes high and the on-resistance becomes high. Further, when a field insulating film containing Si is provided over the entire area of the barrier layer, the 2DEG concentration is increased throughout the interface, and the on-resistance can be reduced, but a normally-off operation cannot be realized. Further, after thinning the AlGaN barrier layer, Si ions are selectively implanted only into the offset region, and activation annealing at about 1200 ° C. is performed to perform selective n-type doping, and the 2DEG concentration in the offset region It is also possible to increase the value. However, in this case, the interface between the barrier layer and the field insulating film is roughened by the high-temperature activation annealing, the interface state increases, and a stable operation cannot be obtained.

  In this embodiment, since the barrier layer 2 and the gate electrode 5 are insulated by the gate insulating film 7, even if a high gate voltage is applied to the gate electrode 5, the gate leakage current does not increase. . As a result, a large forward gate bias can be applied, the 2DEG concentration immediately below the gate electrode 5 can be increased in the ON state, and the channel resistance can be reduced. As a result, the on-resistance can be further reduced.

Furthermore, in this embodiment, the barrier layer 2 is formed of AlGaN, and the gate insulating film 7 is formed of GaN, AlN, Al ₂ O _3, or a multilayer film thereof, so that the barrier layer 2 and the gate insulating film are formed. 7 can form a stable interface.

(Modification of the first embodiment)
FIG. 3 is a cross-sectional view schematically illustrating the configuration of the nitride semiconductor device according to the modification of the first embodiment.
3 that are the same as or correspond to the components shown in FIG. 1 are assigned the same reference numerals as those in FIG. 1 and their detailed description is omitted. The same applies to other figures described later.

  As shown in FIG. 3, in the nitride semiconductor device according to this modification, the length of the gate electrode 5 is longer than the length of the gate insulating film 7 in the direction from the source electrode 3 to the drain electrode 4. Both ends of the gate electrode 5 run on the field insulating film 6. Thereby, a margin for alignment can be provided when the gate electrode 5 is formed. In this modification, a portion of the gate electrode 5 that effectively functions as a gate electrode for 2DEG is a portion under the gate electrode 5, that is, a portion embedded in the field insulating film 6. Therefore, the gate insulating film 7 only needs to be provided at least between the lower part of the gate electrode 5 and the barrier layer 2, and the offset region where the field insulating film 6 is in contact with the barrier layer 2 A region between the electrode 3 and a region between the lower portion of the gate electrode 5 and the drain electrode 4 are formed. The same applies to other embodiments described below and modifications thereof. Configurations, operations, and effects other than those described above in the present modification are the same as those in the first embodiment.

(Second Embodiment)
FIG. 4 is a cross-sectional view schematically illustrating the structure of a nitride semiconductor device according to the second embodiment of the invention.
As shown in FIG. 4, in the nitride semiconductor device according to the present embodiment, the gate insulating film 7 is formed so as to cover the field insulating film 6. As a result, portions other than the portion sandwiched between the lower portion of the gate electrode 5 and the barrier layer 2 in the gate insulating film 7 run on the field insulating film 6. Further, both end portions of the gate electrode 5 run over the field insulating film 6 and the gate insulating film 7.

  Hereinafter, a method for manufacturing the semiconductor element will be described. A channel layer 1 and a barrier layer 2 are formed on a substrate (not shown), and a field insulating film 6 is deposited on the entire surface of the barrier layer 2. Next, the field insulating film 6 is selectively removed from the region where the gate electrode 5 is to be formed. Next, a gate insulating film 7 is deposited on the entire surface so as to cover the field insulating film 6. Thereafter, the gate electrode 5 is formed in a region including the region from which the field insulating film 6 has been removed. Thereby, the nitride semiconductor device shown in FIG. 4 can be manufactured.

  In the first embodiment described above, the end surfaces of the gate electrode 5 and the gate insulating film 7 and the end surface of the field insulating film 6 are in contact with each other, so that the processing of the field insulating film 6, the gate insulating film 7 and the gate electrode 5 is performed. If this is not performed accurately, a gap is generated between the field insulating film 6 and the gate insulating film 7 or between the field insulating film 6 and the gate electrode 5. If a gap is generated between the field insulating film 6 and the gate insulating film 7, and the gate electrode 5 enters the gap, the gate leakage current increases. In addition, when a gap is generated between the field insulating film 6 and the gate electrode 5, the 2DEG concentration in the on state is lowered and the on-resistance is increased immediately below the gap. For this reason, high processing accuracy is required in the first embodiment described above.

  Further, when the gate insulating film 7 is formed first and then the field insulating film 6 is formed, the end of the field insulating film 6 is formed on the end of the gate insulating film 7 as shown in FIGS. The gate insulating film 7 may be inserted between the barrier layer 2 and the field insulating film 6. In this case, as shown in FIG. 5, even if the length of the gate electrode 5 is shorter than the length of the opening of the field insulating film 6, or the length of the gate electrode 5 is the field as shown in FIG. Even if it is longer than the length of the opening of the insulating film 6, there is a region in the barrier layer 2 that is not in contact with the field insulating film 6 and in which the gate electrode 5 is not in contact with the gate insulating film 7 immediately above it. End up. In such a region, since it is not in contact with the field insulating film 6, the concentration of 2DEG is originally low, and since there is no lower portion of the gate electrode 5 in the region immediately above, the action of attracting 2DEG by the gate electrode 5 is weak. In such a nitride semiconductor device, the on-resistance can be reduced as compared with the conventional nitride semiconductor device while realizing a normally-off operation, but the nitrided according to the first embodiment processed with high accuracy. Compared to a physical semiconductor device, the 2DEG concentration in the on state is slightly lower, and the on-resistance is slightly higher.

  On the other hand, according to the present embodiment, the gate insulating film 7 runs on the field insulating film 6 and the gate electrode 5 runs on the field insulating film 6 and the gate insulating film 7, so that the alignment is performed. Even if the margin can be sufficiently secured and the processing accuracy is not so high, no gap is formed and the gate insulating film 7 is not inserted between the barrier layer 2 and the field insulating film 6. As a result, the on-resistance can be stably reduced.

  In addition, by increasing the length of the portion of the gate electrode 5 on the field insulating film 6 and the gate insulating film 7 at the end on the drain electrode 4 side, that is, the portion protruding toward the drain electrode 4, this length is increased. The part serves as a field plate electrode. Thereby, the electric field concentration at the end of the gate electrode 5 can be suppressed, and a stable breakdown voltage can be obtained. Other configurations, operations, and effects of the present embodiment are the same as those of the first embodiment.

(Modification of the second embodiment)
FIG. 7 is a cross-sectional view schematically illustrating the structure of a nitride semiconductor device according to a modification of the second embodiment.
As shown in FIG. 7, the nitride semiconductor device according to this modification example has a two-layer gate insulating film 7 as compared with the nitride semiconductor device according to the second embodiment (see FIG. 4). Is different. That is, in the gate insulating film 7, a lower layer film 7a made of GaN or AlN and an upper layer film 7b made of Al ₂ O ₃ are laminated.

In this modification, a stable interface can be formed with the barrier layer 2 made of AlGaN by forming the lower layer film 7a with GaN or AlN. Further, by forming the upper layer film 7b with Al ₂ O ₃ , a high potential barrier can be realized and the gate leakage current can be reduced. Configurations, operations, and effects other than those described above in the present modification are the same as those in the second embodiment described above.

(Third embodiment)
FIG. 8 is a cross-sectional view schematically illustrating the structure of a nitride semiconductor device according to the third embodiment of the invention.
As shown in FIG. 8, in the nitride semiconductor device according to the present embodiment, in addition to the configuration of the nitride semiconductor device according to the second embodiment described above (see FIG. 4), the field insulating film 6 and the gate insulation are provided. A second field insulating film 8 is provided so as to cover the film 7 and the gate electrode 5, and a source field plate (FP) electrode 9 connected to the source electrode 3 is provided on the second field insulating film 8. Is provided. The source FP electrode 9 extends on the second field insulating film 8 from the region directly above the source electrode 3 to the region immediately above the gate electrode 5 and to the vicinity of the region directly above the drain electrode 4. That is, the source FP electrode 9 is provided in a region including the region immediately above the gate electrode 5 on the field insulating film 8.

  In the nitride semiconductor device according to this embodiment, the electric field concentration at the end of the gate electrode 5 can be reduced by forming the source FP electrode 9. Thereby, a high breakdown voltage can be obtained. Configurations, operations, and effects other than those described above in the present embodiment are the same as those in the second embodiment described above.

(Modification of the third embodiment)
FIG. 9 is a cross-sectional view schematically illustrating the structure of a nitride semiconductor device according to a modification of the third embodiment.
As shown in FIG. 9, in the nitride semiconductor device according to this modification, in addition to the configuration of the nitride semiconductor device according to the third embodiment described above (see FIG. 8), the second field insulating film 8 A drain FP electrode 10 connected to the drain electrode 4 is provided thereon. The drain FP electrode 10 protrudes from the region directly above the drain electrode 4 toward the region directly above the gate electrode 5 on the second field insulating film 8.

  In the present modification, by providing the drain FP electrode 10, the electric field concentration at the end of the drain electrode 4 is relaxed, and a higher breakdown voltage can be obtained. Configurations, operations, and effects other than those described above in the present modification are the same as those in the third embodiment described above.

(Fourth embodiment)
FIG. 10 is a cross-sectional view schematically illustrating the configuration of the nitride semiconductor device according to the fourth embodiment of the invention.
As shown in FIG. 10, in the nitride semiconductor device according to the present embodiment, in addition to the configuration of the nitride semiconductor device according to the second embodiment (see FIG. 4), the gate insulating film in the barrier layer 2 A p-type doped layer 11 is selectively formed in a region where 7 is in contact and an upper layer portion of the channel layer 1 located immediately below. The p-type doped layer 11 is formed by doping the channel layer 1 and the barrier layer 2 with a p-type dopant such as fluorine (F), magnesium (Mg), iron (Fe), or manganese (Mn). The conductivity type is p-type.

  In the present embodiment, since the p-type doped layer 11 is selectively formed directly under the gate electrode 5, 2DEG can be more strongly removed from the region directly under the gate electrode 5. That is, the effect of reducing the 2DEG concentration in the region immediately below the gate electrode 5 by thinning the barrier layer 2 and the effect of eliminating 2DEG from the region immediately below the gate electrode 5 by forming the p-type doped layer 11 are superimposed. Can be made. Thereby, the threshold voltage can be shifted to the plus side more largely without increasing the on-resistance. By shifting the threshold voltage to the plus side, the channel depletion layer is extended when the gate voltage is 0, and the channel leakage current can be suppressed. Configurations, operations, and effects other than those described above in the present embodiment are the same as those in the second embodiment described above.

(Fifth embodiment)
FIG. 11 is a cross-sectional view schematically illustrating the configuration of a nitride semiconductor device according to the fifth embodiment of the invention.
As shown in FIG. 11, the nitride semiconductor device according to the present embodiment has a p-type GaN layer 12 as a channel layer, as compared with the nitride semiconductor device according to the second embodiment (see FIG. 4). Is different. The p-type GaN layer 12 is formed by doping a GaN layer with a p-type impurity. According to the present embodiment, by making the channel layer p-type, generation of 2DEG can be suppressed, and the threshold voltage can be shifted more positively. Configurations, operations, and effects other than those described above in the present embodiment are the same as those in the second embodiment described above.

(Modification of the fifth embodiment)
FIG. 12 is a cross-sectional view schematically illustrating the configuration of a nitride semiconductor device according to a modification of the fifth embodiment.
As shown in FIG. 12, in the nitride semiconductor device according to this modification, in addition to the configuration of the nitride semiconductor device according to the fifth embodiment (see FIG. 11), the p-type GaN layer 12 and the AlGaN A GaN layer 13 is provided between the barrier layer 2 and the barrier layer 2.

  In this modification, by inserting the GaN layer 13 between the p-type GaN layer 12 and the barrier layer 2, it is possible to prevent the mobility of 2DEG as a carrier from being lowered due to the presence of the p-type GaN layer 12. The dopant contained in the p-type GaN layer 12 can be prevented from diffusing into the barrier layer 2. Other configurations, operations, and effects of the present modification are the same as those of the fifth embodiment described above.

  As described above, the present invention has been described with reference to the first to fifth embodiments and their modifications. However, the present invention is not limited to these examples, and besides this, it is easy for a technician in this technical field. All possible variations are applicable. For example, those in which those skilled in the art appropriately added, deleted, and changed the design of the above-described embodiments and modifications are included in the scope of the present invention as long as they include the gist of the present invention. Is done. Moreover, the above-described embodiments and modifications can be implemented in combination with each other.

  The present invention is not limited by the material of the support substrate for forming the channel layer 1, the barrier layer 2, and the like, and a sapphire substrate, SiC substrate, Si substrate, GaN substrate, or the like is used as the support substrate. it can. In addition, these support substrates may be insulative or conductive, and when conductive, the conductivity type may be P-type or N-type. Further, a buffer layer may be provided between the support substrate and the channel layer. The structure and material of the buffer layer are not particularly limited, and for example, an AlN layer, an AlGaN layer, or a stacked structure of an AlN layer and a GaN layer can be used.

  In each of the above-described embodiments and modifications, the example in which the combination of the materials of (barrier layer 2 / channel layer 1) is (AlGaN / GaN) has been described, but the present invention is not limited to this, , (GaN / InGaN), (AlN / AlGaN), or (BAlN / GaN), which is a combination of nitride semiconductors, where the band gap of the barrier layer is wider than the band gap of the channel layer Can be implemented.

  Furthermore, the present invention is not limited by the crystal plane orientation in the channel layer 1 and the barrier layer 2. For example, the present invention can be implemented using a semiconductor layer crystal-grown on the (0001) plane where polarization is likely to occur, or grown on the (1-101) plane or (11-20) plane where polarization does not occur. This can also be carried out using the above-described semiconductor layer. Furthermore, in order to realize normally-off, the barrier layer 2 is desirably an undoped layer. However, when the GaN buffer layer is doped p-type as shown in FIG. Even if the doping is performed on the mold, it is possible to realize normally-off by increasing the p-type doping concentration of the GaN buffer layer.

1 is a cross-sectional view illustrating a nitride semiconductor device according to a first embodiment of the invention. The horizontal axis represents the Al composition ratio X of the barrier layer, and the vertical axis represents the thickness t ₀ of the barrier layer when the threshold voltage of the GaN-HFET incorporating this barrier layer is 0, It is a graph which illustrates the influence which a composition and a film thickness have on the threshold voltage of GaN-HFET. 7 is a cross-sectional view illustrating a nitride semiconductor device according to a modification of the first embodiment. FIG. 5 is a cross-sectional view illustrating a nitride semiconductor device according to a second embodiment of the invention. FIG. FIG. 6 is a cross-sectional view illustrating a specific example of a nitride semiconductor device according to a second embodiment. 6 is a cross-sectional view illustrating another specific example of the nitride semiconductor device according to the second embodiment. FIG. 6 is a cross-sectional view illustrating a nitride semiconductor device according to a modification of the second embodiment. FIG. FIG. 6 is a cross-sectional view illustrating a nitride semiconductor device according to a third embodiment of the invention. FIG. 10 is a cross-sectional view illustrating a nitride semiconductor device according to a modification example of the third embodiment. FIG. 6 is a cross-sectional view illustrating a nitride semiconductor device according to a fourth embodiment of the invention. FIG. 7 is a cross-sectional view illustrating a nitride semiconductor device according to a fifth embodiment of the invention. FIG. 10 is a cross-sectional view schematically illustrating the configuration of a nitride semiconductor device according to a modification of the fifth embodiment.

Explanation of symbols

1 channel layer, 2 barrier layer, 3 source electrode, 4 drain electrode, 5 gate electrode, 6 field insulating film, 7 gate insulating film, 7a lower layer film, 7b upper layer film, 8 second field insulating film, 9 source FP electrode 10 drain FP electrode, 11 p-type doped layer, 12 p-type GaN layer, 13 GaN layer, L curve

Claims (5)

A first semiconductor layer made of an undoped nitride semiconductor;
A second semiconductor layer formed on the first semiconductor layer and made of a nitride semiconductor having a band gap wider than the band gap of the nitride semiconductor forming the first semiconductor layer;
First and second main electrodes provided on the second semiconductor layer and connected to the second semiconductor layer;
A control electrode provided between the first main electrode and the second main electrode on the second semiconductor layer;
A gate insulating film provided at least between the lower part of the control electrode and the second semiconductor layer;
A field insulating film covering a region between the lower portion of the control electrode and the first main electrode and a region between the lower portion of the control electrode and the second main electrode on the upper surface of the second semiconductor layer; ,
With
The field insulating film includes silicon;
The nitride semiconductor device, wherein the gate insulating film does not contain silicon. The first semiconductor layer is made of GaN;
The second semiconductor layer is made of Al _X Ga _1-X N (0 ≦ X ≦ 1),
2. The nitride semiconductor device according to claim 1, wherein when the film thickness of the second semiconductor layer is t (nm), the following mathematical formula is established.
t ≦ 1 / (1.15X ² + 0.326X + 0.01)   3. The nitride semiconductor device according to claim 1, wherein the field insulating film is made of one material selected from the group consisting of silicon nitride, silicon oxide, and silicon oxynitride.   The gate insulating film is a single-layer film selected from the group consisting of an aluminum nitride film, a gallium nitride film, and an aluminum oxide film, or a multilayer film in which two or more single-layer films are stacked. The nitride semiconductor device according to any one of claims 1 to 3, wherein   5. The nitride semiconductor device according to claim 1, wherein a part of the gate insulating film rides on the field insulating film.

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