JP2008259110A - Frequency synthesizer system - Google Patents

Abstract

A frequency synthesizer system capable of outputting all waveforms without increasing the amount of memory and reducing the side lobe is obtained.
A phase correction frequency data storage memory for storing phase correction frequency data for correcting a phase error caused by an analog circuit connected to a subsequent stage of the system, and the phase correction frequency data and a set start frequency are added. Adder 21, frequency accumulator 31 that outputs frequency data that changes at a frequency sweep step rate set every predetermined time, adder that adds the output data from adder 21 and the frequency data from frequency accumulator 31 32, and a phase accumulator 33 that increases and decreases the output according to the data value from the adder 32 and outputs phase data whose phase changes every time.
[Selection] Figure 1

Description

  The present invention corrects a phase error caused by a frequency characteristic of a system in a system that generates a frequency sweep waveform by using a DDS (Direct Digital Synthesizer) such as a radar transceiver, and reduces the phase linearity of the output waveform of the system. The present invention relates to a frequency synthesizer system having an improved function.

  Regarding frequency synthesizers, it is well known that various techniques have been proposed as methods for improving phase errors. As an example, there is a method having a function of synthesizing a spurious cancel signal from a phase error signal and subtracting it from an output sine wave signal inside the DDS (for example, see Patent Document 1).

  A conventional frequency synthesizer system will be described with reference to FIGS. FIG. 5 is a block diagram showing a configuration of a conventional frequency synthesizer system.

  In FIG. 5, the conventional frequency synthesizer system is provided with a control circuit 10 and a DDS 30.

  The control circuit 10 outputs a frequency sweep step set value (Δω) S1 and a start frequency set value (ω) S2.

  The DDS 30 is provided with a frequency accumulator 31, an adder 32, a phase accumulator 33, a phase / amplitude converter 34, and a D / A converter 35. An analog circuit 40 such as an amplifier or a filter is connected to the subsequent stage of the DDS 30.

  Next, the operation of the conventional frequency synthesizer system will be described with reference to the drawings. FIG. 6 is a diagram illustrating an example of a waveform after performing a pulse compression correlation process on a frequency sweep waveform in a conventional frequency synthesizer system. FIG. 7 is a diagram showing an example of a waveform after a pulse compression correlation process is performed on a waveform having a phase error in a conventional frequency synthesizer system.

  The frequency sweep step set value (Δω) S1 is input to the frequency accumulator 31, and the frequency accumulator 31 outputs frequency data S3 that changes at a constant value Δω (frequency sweep step set value) at every time t.

  The start frequency set value (ω) S 2 is added to the frequency data S 3 by the adder 32 to become data S 4 of the output frequency (ω + Δωt), and is input to the phase accumulator 33.

  The phase accumulator 33 increases or decreases the output S5 according to the value of the data S4 of the frequency (ω + Δωt), and outputs a waveform whose phase changes every time. However, when the data S4 changes to ω + Δωt with the time t, the DDS30 Frequency is swept. In a system that generates a frequency sweep waveform, correlation processing such as pulse compression is performed.

  FIG. 6 shows an example of a waveform obtained by subjecting the frequency sweep waveform to pulse compression correlation processing. In FIG. 6, the horizontal axis represents distance and the vertical axis represents amplitude.

  The frequency synthesizer as in Patent Document 1 improves the phase error of the DDS itself, but is not in the category of the improvement effect for the phase error of the entire frequency synthesizer system including the analog circuit 40 having an arbitrary frequency characteristic. For the ideal DDS30 output (Asin ((ω + Δωt / 2) t + Φ)) with no phase error, the phase is ωt + (1/2) when the frequency is ω + Δωt because the phase is determined by time integration of the frequency. * Δωt｀2 + Φ) After passing through the analog circuit 40, an output (Asin ((ω + Δωt / 2)) to which a phase error (Φs (ω)) due to the frequency characteristics of the entire frequency synthesizer system including the analog circuit 40 is added t + Φ + Φs (ω)) is output.

  FIG. 7 is an example of a waveform obtained by performing pulse compression correlation processing on a waveform having a phase error. In FIG. 7, the horizontal axis represents distance and the vertical axis represents amplitude. If there is a phase error, there is a drawback that the waveform spreads as shown in FIG.

  Another conventional frequency synthesizer system will be described with reference to FIG. FIG. 8 is a block diagram showing the configuration of another conventional frequency synthesizer system.

  In FIG. 8, another conventional frequency synthesizer system is provided with a control circuit 10, a waveform data memory 50, and a D / A converter 51.

  An ideal output (Asin ((ω + Δωt / 2) t + Φ)) can be obtained by storing the data obtained by correcting the frequency characteristics of the frequency synthesizer system in the waveform data memory 50, but storing all waveform data of a plurality of settings. For this reason, the data amount of the waveform data memory 50 becomes enormous, and the types of waveforms that can be generated are limited.

  Another conventional frequency synthesizer system will be described with reference to FIGS. FIG. 9 is a block diagram showing the configuration of another conventional frequency synthesizer system.

  In FIG. 9, another conventional frequency synthesizer system is provided with a control circuit 10, a DDS 30 having a phase offset function, and a phase correction value storage memory 52.

  The control circuit 10 outputs a frequency sweep step set value (Δω) S1 and a start frequency set value (ω) S2.

  The DDS 30 is provided with a frequency accumulator 31, an adder 32, a phase accumulator 33, an adder 39, a phase / amplitude converter 34, and a D / A converter 35. An analog circuit 40 such as an amplifier or a filter is connected to the subsequent stage of the DDS 30.

  In addition to the function of the DDS 30, an ideal output (Asin ((ω + Δωt / 2) t + Φ)) can be obtained by adding the phase correction value (−Φs (t)) by the adder 39 and the phase correction value storage memory 52. Since the correction data is stored for each of the plurality of settings, the amount of data in the phase correction value storage memory 52 becomes enormous. In addition, if the amount of memory is reduced by thinning out the phase correction data on the time axis, the phase correction value changes stepwise with time and cannot be completely corrected. There is a disadvantage that it causes the occurrence.

  FIG. 10 is a diagram for explaining that the phase error is corrected stepwise in another conventional frequency synthesizer system. In FIG. 10, the horizontal axis represents time, and the vertical axis represents phase. A thin sinusoidal line indicates a phase before correction, a broken line indicates a phase correction amount, and a thick line indicates a phase of a correction mark.

  FIG. 11 is a diagram illustrating an example of a waveform obtained by performing pulse compression correlation processing on a waveform that has been phase-corrected in another conventional frequency synthesizer system. In FIG. 11, the horizontal axis represents distance, and the vertical axis represents amplitude. When discontinuous phase correction is performed, there is a drawback that large side lobes are generated as shown in FIG.

JP-A-6-252645

  In other conventional frequency synthesizer systems as described above, the correction data is stored for each of a plurality of waveforms, and the amount of data in the memory becomes enormous. In addition, if the amount of memory is reduced by thinning out the phase correction data on the time axis, the phase correction value changes stepwise with time and cannot be completely corrected. There was a problem of causing it.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to synthesize a frequency synthesizer system that can output any waveform without increasing the amount of memory and can reduce side lobes. Is what you get.

  The frequency synthesizer system according to the present invention includes a phase correction frequency data storage memory for storing phase correction frequency data for correcting a phase error caused by an analog circuit connected to the latter stage of the system, the phase correction frequency data, and a set start A first adder for adding frequencies, a frequency accumulator for outputting frequency data that changes at a rate of a frequency sweep step set every predetermined time, output data from the first adder, and the frequency accumulator And a phase accumulator for increasing and decreasing the output depending on the value of the data from the second adder and outputting phase data whose phase changes with time. Is.

  The frequency synthesizer system according to the present invention can output all waveforms without increasing the amount of memory, and has the effect of reducing the side lobe.

Embodiment 1 FIG.
A frequency synthesizer system according to Embodiment 1 of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing a configuration of a frequency synthesizer system according to Embodiment 1 of the present invention. In the following, in each figure, the same reference numerals indicate the same or corresponding parts.

  1, the frequency synthesizer system according to the first embodiment of the present invention includes a control circuit 10, a phase correction frequency data storage memory 20, an adder (first adder) 21, and a DDS 30. Yes.

  The control circuit 10 outputs a frequency sweep step set value (Δω) S1, a start frequency set value (ω) S2, and phase correction frequency data.

  The DDS 30 includes a frequency accumulator 31, an adder (second adder) 32, a phase accumulator 33, a phase / amplitude converter 34, and a D / A converter 35. An analog circuit 40 such as an amplifier or a filter is connected to the subsequent stage of the DDS 30.

  Next, the operation of the frequency synthesizer system according to the first embodiment will be described with reference to the drawings.

  FIG. 2 is a diagram for explaining that the phase error is corrected by changing the set frequency in the frequency synthesizer system according to the first embodiment of the present invention. FIG. 3 is a diagram showing an example of a waveform obtained by performing pulse compression correlation processing on a waveform whose phase has been corrected in the frequency synthesizer system according to Embodiment 1 of the present invention.

  First, the frequency accumulator 31 outputs frequency data S5 that changes at a constant value Δω (frequency sweep step setting value S1) at each time t.

  The output S10 (Asin ((ω + Δωt / 2) t + Φ + Φs (t))) of the analog circuit 40 measured in advance is compared with a waveform (Asin ((ω + Δωt / 2) t + Φ) ideally having a linear frequency-phase characteristic, and the frequency is compared. The frequency response (Φs (t)) of the phase error of the entire synthesizer system is calculated.

  The phase correction frequency (−d / dt Φs (t)) obtained by time differentiation of the frequency response (Φs (t)) of the phase error is stored in the phase correction frequency data storage memory 20. Since the phase correction frequency data S3 is time-integrated by the phase accumulator 33, the output S7 of the phase accumulator 33 becomes phase correction data (−Φ (t)).

  Therefore, by inputting the phase correction frequency data S3 corresponding to the set start frequency to the adder 21, an output S4 in which the phase error is corrected can be obtained as shown in the following equation (1).

Asin ((ω + Δωt / 2) t + Φ + Φs (t) −Φs (t))
= Asin ((ω + Δωt / 2) t + Φ) Equation (1)

  The adder 32 outputs the data S6 obtained by adding the output S4 of the adder 21 and the frequency data S5 output from the frequency accumulator 31 to the phase accumulator 33.

  The phase accumulator 33 increases or decreases the output S7 according to the value of the data S6, and outputs a waveform whose phase changes every time. Therefore, the frequency of the DDS 30 is swept by changing the data S6 to ω + Δωt with time t. The phase / amplitude converter 34 converts the phase data S7 from the phase accumulator 33 into amplitude data S8, and the D / A converter 35 converts the amplitude data S8 into an analog signal S9 and outputs it to the analog circuit 40. To do.

  In FIG. 2, the horizontal axis represents time, and the vertical axis represents phase. A thin sinusoidal line indicates a phase before correction, a broken line indicates a phase correction amount, and a thick line indicates a phase of a correction mark.

  In FIG. 3, the horizontal axis represents distance, and the vertical axis represents amplitude. FIG. 3 is an example of a waveform obtained by performing pulse compression correlation processing on a phase-corrected waveform under the same phase error condition as in FIG. According to FIG. 3, when the phase correction is performed by changing the set frequency, there is an effect that the side lobe can be reduced as compared with FIG.

Embodiment 2. FIG.
A frequency synthesizer system according to Embodiment 2 of the present invention will be described with reference to FIG. FIG. 4 is a block diagram showing a configuration of a frequency synthesizer system according to Embodiment 2 of the present invention.

  4, the frequency synthesizer system according to the second embodiment of the present invention is provided with a control circuit 10, a group delay data storage memory 22, a multiplier 23, and a DDS 30.

  The control circuit 10 outputs a frequency sweep step set value (Δω) S1 and a start frequency set value (ω) S2.

  The DDS 30 includes a frequency accumulator 31, an adder (first adder) 32, an adder (second adder) 36, a phase accumulator 33, a phase / amplitude converter 34, and a D / A converter. 35 is provided. An analog circuit 40 such as an amplifier or a filter is connected to the subsequent stage of the DDS 30.

  Next, the operation of the frequency synthesizer system according to the second embodiment will be described with reference to the drawings.

  First, the frequency accumulator 31 outputs frequency data S3 that changes at a constant value Δω (frequency sweep step setting value S1) at each time t.

  The adder 32 adds the start frequency setting value (ω) S2 and the frequency data S3, and outputs the frequency data (ω + Δωt) S4 to the adder 36.

  A group delay characteristic (−d / dωΦs (ω)) of the analog circuit 40 measured in advance is stored in the group delay data storage memory 22, and a group delay time (−d / d) corresponding to the output S4 of the adder 32 is stored. Data S <b> 5 that is dωΦs (ω + Δωt)) is output to the multiplier 23.

  The multiplier 23 multiplies the data S5 and the frequency sweep step set value (Δω) S1. Since this frequency step set value corresponds to the time derivative of the frequency ω, the product of the group delay time (−d / dωΦs (ω + Δωt)) and the frequency sweep step Δω is the time difference of the phase error, that is, the frequency correction value (−d / DtΦs (t)).

  By inputting this to the adder 36 as a frequency correction value and adding it to the input of the phase accumulator 33, a correction output similar to that of the first embodiment can be obtained. In the second embodiment, the stored data of the group delay data does not depend on the frequency setting, so that it is possible to output any waveform without increasing the amount of memory.

It is a block diagram which shows the structure of the frequency synthesizer system which concerns on Embodiment 1 of this invention. It is a figure for demonstrating correcting a phase error by changing a setting frequency in the frequency synthesizer system which concerns on Embodiment 1 of this invention. It is a figure which shows the example of the waveform which carried out the pulse compression correlation process of the waveform which carried out the phase correction | amendment in the frequency synthesizer system which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structure of the frequency synthesizer system which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structure of the conventional frequency synthesizer system. It is a figure which shows the example of the waveform after carrying out the pulse compression correlation process of the frequency sweep waveform in the conventional frequency synthesizer system. It is a figure which shows the example of the waveform after carrying out the pulse compression correlation process of the waveform which has a phase error in the conventional frequency synthesizer system. It is a block diagram which shows the structure of another conventional frequency synthesizer system. It is a block diagram which shows the structure of the other conventional frequency synthesizer system. It is a figure for demonstrating correcting a phase error in steps in the other conventional frequency synthesizer system. It is a figure which shows the example of the waveform which carried out the pulse compression correlation process of the waveform which carried out the phase correction | amendment in the other conventional frequency synthesizer system.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 Control circuit, 20 Phase correction frequency data storage memory, 21 Adder, 22 Group delay data storage memory, 23 Multiplier, 31 Frequency accumulator, 32 Adder, 33 Phase accumulator, 34 Phase / amplitude converter, 35 A / D Converter, 36 adder, 40 analog circuit.

Claims (3)

A phase correction frequency data storage memory for storing phase correction frequency data for correcting a phase error caused by an analog circuit connected to the latter stage of the system;
A first adder for adding the phase correction frequency data and the set start frequency;
A frequency accumulator that outputs frequency data that changes at a rate of the frequency sweep step set every predetermined time;
A second adder for adding the output data from the first adder and the frequency data from the frequency accumulator;
A frequency synthesizer system comprising: a phase accumulator that increases and decreases an output according to a value of data from the second adder and outputs phase data whose phase changes every time. The phase correction frequency data storage memory is
It is obtained by comparing the output of the analog circuit measured in advance with a waveform having ideally linear frequency-phase characteristics, calculating the frequency response of the phase error of the entire system, and time-differentiating this frequency response. The frequency synthesizer system according to claim 1, wherein a phase correction frequency is stored. A group delay data storage memory for storing group delay characteristic data of analog circuits connected to the latter stage of the system, measured in advance;
A frequency accumulator that outputs frequency data that changes at a rate of the frequency sweep step set every predetermined time;
A first adder for adding the frequency data from the frequency accumulator and a set start frequency;
A multiplier for multiplying the group delay data from the group delay data storage memory according to the set frequency sweep step and the output of the first adder;
A second adder for adding the output data from the multiplier and the output data from the first adder;
A frequency synthesizer system comprising: a phase accumulator that increases and decreases an output according to a value of data from the second adder and outputs phase data whose phase changes every time.

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