JP2008251060A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor memory device which performs an independent address access operation without increasing addresses and control signals in two internal memories.
Data of an address specified from a common address signal line is input / output from / to each individual data signal line at a predetermined phase with respect to a rising edge of a clock signal input from each individual clock signal line. The first clock signal supplied to the first SDRAM is generated based on the first and second SDRAMs and the external clock signal, and the first clock signal is supplied to the second SDRAM and has a phase opposite to that of the first clock signal. A clock generation circuit for generating a second clock signal is provided.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor memory device capable of performing an address access operation independent of two memories provided in the semiconductor memory device.

  2. Description of the Related Art Semiconductor memory devices (memory devices) represented by DRAM (DYNAMIC RANDOM-ACCESS MEMORY) and the like are required to increase the data transfer rate and increase the data capacity. While the increase in data capacity of semiconductor memory devices has progressed, the data storage function used in the system is also required to be distributed, so that large capacity semiconductor memory devices can be used efficiently and cost-effectively. In the above, it is necessary to transfer data to a semiconductor memory device at high speed and to use the data transfer band in a time-sharing manner by a plurality of access requests.

  For example, as shown in the block diagram of the conventional semiconductor memory device in FIG. 10, the data storage function shown in FIG. 10A is distributed to the large-capacity semiconductor memory device shown in FIG. 10B. It is designed to have a function-intensive configuration.

  For this reason, various types of synchronous DRAM (SDRAM: SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY) that enable high-speed data transfer have been proposed. The SDRAM performs internal operations in a pipeline manner in synchronization with a clock signal supplied from the outside, and performs data input / output in synchronization with the external clock signal. The SDRAM transfers data in synchronization with the rising edge of the clock signal, and the data transfer cycle is the same as the clock cycle.

  On the other hand, by performing data transfer in synchronization with both the rising edge and falling edge of the clock signal, double data can be transferred at twice the speed of the conventional method in the same clock cycle. A data rate (DDR: Double Data Rate) type SDRAM (DDR-SDRAM) has been proposed. In the case of a DDR-SDRAM, data transfer can be performed at twice the speed as in the conventional case with the same clock cycle.

  Further, two DDR-SDRAMs are provided in one package, and are connected in common to the data input / output lines to form one semiconductor memory device from the external clock signal having the same frequency and the same phase as the external clock signal. A clock generation circuit for generating a first clock signal and a second clock signal having the same frequency as that of the external clock signal and a phase shift of ¼ phase is provided, and the first clock signal and the second clock signal are clocked to two DDR-SDRAMs. By supplying the two DDR-SDRAMs as signals, the data output unit of the first DDR-SDRAM operates at a predetermined phase from the rising edge and the falling edge of the first clock signal. Later, data is output for a period of 1/4 phase, and the data output circuit is in a high-impedance state during other periods. The data output unit of the second memory device outputs data for a period of ¼ phase after a predetermined phase from the rising edge and the falling edge of the second clock signal, and outputs data during the other periods. There has also been proposed a semiconductor memory device that can transfer data at twice the speed of DDR-SDRAM by using the configuration of a conventional DDR-SDRAM as it is by putting the circuit in a high impedance state (for example, Patent Document 1). ).

Japanese Patent Laid-Open No. 2002-15567 (FIGS. 3 and 9)

  A conventional SDRAM provides a memory device that realizes a plurality of data storage functions required by a system by performing transfer to a plurality of individual addresses in a time-sharing manner at a high speed.

  However, for example, as shown in FIG. 10, in order to aggregate distributed data storage functions into a large-capacity semiconductor storage device, not only the individual data input / output access average bandwidth to be configured but also all the data storage functions to be configured In order to ensure that data input / output continuity is not lost when the maximum data input / output access bandwidth is generated, it is necessary to provide a standby buffer memory having a required capacity for each data storage function to be configured. If there is a data storage function that requires a high maximum data input / output access bandwidth to increase the efficiency of CPU interface operation even if the average data input / output access bandwidth is low, there is no limit. Since a large-capacity standby buffer memory is desired, it may be configured to be integrated into one semiconductor memory device. There is a problem that becomes appropriate.

  In addition, memory device speedup has been achieved by reducing design rules, lowering wiring resistance, and reducing the number of circuit stages, but physical limits such as electronic speed have already begun to appear. The improvement of the conventional technology by reducing the design rule up to this point and reducing the resistance of the wiring has a problem that it is difficult to increase the speed further. Furthermore, in order to further increase the clock speed and data transfer with the memory device, it is required to increase the speed in the board design, which makes it difficult to cope with cost and reliability. There is.

  The present invention has been made in order to solve the above-described problems, and includes two SDRAMs having the same clock speed and the same internal operation speed in one package, and without increasing addresses and control signals. It is an object of the present invention to obtain a semiconductor memory device capable of two independent data transfer operations by performing independent address access operations on two SDRAMs.

  In the semiconductor memory device according to the present invention, the data of the address specified from the common address signal line is transmitted from the individual data signal line at a predetermined phase with respect to the rising edge of the clock signal input from the individual clock signal line. The first and second SDRAMs to be input / output and the first clock signal supplied to the first SDRAM based on the external clock signal are generated, and the first clock signal supplied to the second SDRAM is A clock generation circuit for generating a second clock signal having an opposite phase is provided.

  According to the present invention, two SDRAMs having the same clock speed and internal operation speed are included in one package, and two independent SDRAMs are operated by independent address access operations without increasing addresses and control signals. Data transfer operation is possible.

  The present invention particularly relates to a semiconductor memory device having two synchronous dynamic random access memories (SDRAMs) in one package and capable of independent address access operations for the two SDRAMs.

  In the present invention, a common address signal line is connected to two SDRAMs, and either a clock signal or a clock enable signal is individually connected. Control signal lines other than the address signal lines that are commonly connected include a CAS signal (column address designation signal), a RAS signal (row address designation signal), and a WE signal, which are signals for controlling the setting of reading data placed on the address line. (Write command signal) and the like are included. In addition, a write enable signal (write enable signal) and a read enable signal (read enable signal), which are signals for controlling input / output of data for each cycle of the clock signal, are individually connected to the SDRAM, and write and read data Specify the direction.

Embodiment 1 FIG.
In the first embodiment of the present invention, the first clock signal that is the same phase clock signal (normal phase clock signal) with respect to the external clock signal is sent to the SDRAM core 11 and the opposite phase clock signal (reverse phase clock signal). An example of a semiconductor memory device in which the second clock signal is input to the SDRAM core 12 will be described.

  FIG. 1 is a block diagram showing an example of the semiconductor memory device according to the first embodiment of the present invention.

  In FIG. 1, the semiconductor memory device 10 includes first and second SDRAM cores (SDRAMs) 11 and 12 and a clock generation circuit 13. The first SDRAM 11 and the second SDRAM 12 are configured so that individual address data designated by a common address signal line is separated from the rising edge of the clock signal inputted from the individual clock signal line with a predetermined phase. Input / output from signal line. The clock generation circuit 13 generates a first clock signal supplied to the first SDRAM based on the external clock signal, and supplies the second clock to the second SDRAM and has a phase opposite to that of the first clock signal. The clock signal is generated.

  Further, the semiconductor memory device 10 receives an address and a control signal from the outside and inputs / outputs input / output data to / from the outside. Therefore, the memory interface circuits (memory I / F) 21 and 22, a clock generation circuit 23, and a switching circuit 24 is provided outside. A memory interface circuit (memory I / F) 21 is connected to the SDRAM core 11 for writing / reading, and outputs and controls its address and control signal. The memory interface circuit (memory I / F) 22 is connected to the SDRAM core 12 for writing / reading, and outputs and controls its address and control signal. The clock generation circuit 23 generates a normal phase clock signal to be supplied to the memory interface circuit 21 based on the external clock signal, and is also supplied to the memory interface circuit 22 and has a negative phase clock signal having a phase opposite to that of the normal phase clock signal. And outputs a switching signal for switching between the address output from the memory interface circuits 21 and 22 and the control signal. The switching circuit 24 switches the address and control signal generated by the memory interface circuit 21 and the memory interface circuit 22 based on the switching signal output by the clock generation circuit 23 and outputs the switching signal to the semiconductor memory device 10.

  Note that the clock generation circuit 13 supplies the clock signals to the SDRAMs 11 and 12 based on the external clock signal, but the two clock signals only need to have opposite phases to each other, and the clock signal supplied to the SDRAM 11 is in relation to the external clock signal. Any of normal phase and reverse phase may be used. The clock generation circuit 23 supplies the clock signal to the memory interface circuits 21 and 22 based on the external clock signal. However, the clock signals supplied to the memory interface circuit 21 may be any two phase signals as long as the two clock signals have opposite phases. However, either the positive phase or the negative phase with respect to the external clock signal may be used. However, the clock generation circuit 13 and the clock generation circuit 23 use, for example, the phase of the clock signal of the SDRAM 11 and the memory interface circuit 21 as an external clock signal so that the data transfer between the SDRAMs 11 and 12 and the memory interface circuits 21 and 22 matches. You just have to match. In the following description, it is assumed that the phase of the clock signal of the SDRAM 11 and the memory interface circuit 21 is matched to the positive phase of the same phase with respect to the external clock signal.

  Next, the operation of the semiconductor memory device of the present invention will be described with reference to FIG. FIG. 2 is an explanatory diagram of operation timing when a write operation to the memory or a read operation from the memory is performed in the configuration of the block diagram of FIG.

  The memory interface circuit 21 operates at the rising edge of the external clock signal by a clock signal having a positive phase with respect to the external clock signal supplied from the clock generation circuit 23. The memory interface circuit 22 operates at the falling edge of the external clock signal by a clock signal having a phase opposite to that of the first clock signal supplied from the clock generation circuit 23.

  On the other hand, the clock generation circuit 13 in the semiconductor memory device 10 supplies clock signals to the SDRAM core 11 and the SDRAM core 12, respectively. The SDRAM core 11 operates at the rising edge of the external clock signal by connecting the positive clock first clock signal to the external clock signal output from the clock generation circuit 13. The SDRAM core 12 operates at the falling edge of the external clock signal by connecting a second clock signal having a phase opposite to that of the first clock signal output from the clock generation circuit 13.

  The address and control signal generated and output by the memory interface circuit 21 and the address and control signal generated and output by the memory interface circuit 22 are switched in time division by the switching signal output by the clock generation circuit 23, and the semiconductor memory The address and the control signal of the memory interface circuit 21 are input to the SDRAM core 11 at the rising edge of the external clock signal to the SDRAM core 11 and the SDRAM core 12 that are connected to the device 10 and commonly connected, and the memory interface at the falling edge of the external clock signal. The address and control signal of the circuit 22 are input to the SDRAM core 12. Here, the switching signal output from the clock generation circuit 23 is a signal that satisfies the hold and sampling timing conditions when sampling is performed at the rising and falling edge timings of the input external clock signal.

  In this manner, the memory interface circuit 21 and the SDRAM core 11 operate at the rising edge of the external clock signal, and the memory interface circuit 22 and the SDRAM core 12 operate at the falling edge of the external clock signal. The SDRAM core 11 and the SDRAM core 12 input and output data to and from the memory interface circuit 21 and the memory interface circuit 22 independently of each other.

  The external memory interface circuit 21 and the memory interface circuit 22 shown in the block diagram of FIG. 1 have been described as being provided independently. However, one memory interface circuit that functions as these two memory interface circuits. You may provide as. Further, the memory interface circuit integrated into one has a built-in switching circuit 24 therein, and receives the switching signal from the clock generation circuit 23 to transfer the address and control signal to the SDRAM core 11 and the SDRAM core. 12 may be output directly.

  As described above, in the semiconductor memory device according to the first embodiment of the present invention, the positive phase clock signal is connected to the external clock signal so that the first SDRAM core 11 operates at the rising edge of the external clock signal, Since the second SDRAM core 12 is connected to a clock signal having a phase opposite to that of the first clock signal so that the second SDRAM core 12 operates at the falling edge of the external clock signal, independent address access operations for the two SDRAM cores. Thus, the two SDRAM cores can perform independent data transfer operations.

  In the semiconductor memory device according to the first embodiment of the present invention, the address and control signal are commonly connected to the first SDRAM core 11 and the second SDRAM core 12, and the external clock signal is switched by switching the address and control signal. Since independent addresses and control signals are given independently at the rising edge and falling edge, an increase in the number of connection lines between the address and the control signal can be suppressed.

Embodiment 2. FIG.
In the second embodiment of the present invention, a clock selection signal is set in the memory register from the outside, and the second clock signal input to the SDRAM core 12 is a normal phase clock signal or a negative phase clock signal with respect to the first clock signal. An example of a semiconductor memory device that can be switched to any one of these will be described.

  FIG. 3 is a block diagram showing an example of the semiconductor memory device according to the second embodiment of the present invention.

  In FIG. 3, the semiconductor memory device 10 includes first and second SDRAM cores (SDRAMs) 11 and 12, a clock generation circuit 13a, and a memory register 14. As in the second embodiment of the present invention, the first SDRAM 11 and the second SDRAM 12 receive the address data specified from the common address signal line and the rising edges of the clock signals input from the individual clock signal lines. Are input and output from individual data signal lines at a predetermined phase. The memory register circuit (memory register) 14 sets a clock selection signal that specifies a clock signal to be supplied to the second SDRAM 12. The clock generation circuit 13a generates a first clock signal to be supplied to the first SDRAM based on the external clock signal, and outputs a negative phase clock signal having a reverse phase with the first clock signal as a normal phase clock signal. Based on the clock selection signal generated and set in the memory register 14, the normal phase clock signal or the reverse phase clock signal is selected and supplied to the second SDRAM 12 as the second clock signal.

  Therefore, the semiconductor memory device 10 of FIG. 3 is different from that of FIG. 1 in that the memory register 14 is provided in the semiconductor memory device 10, and the clock generation circuit 13 sets the contents of the memory register 14 (clock selection signal). ) To generate a second clock signal to the SDRAM 12. Although the semiconductor memory device 10 is common in FIGS. 3A and 3B, FIG. 3A shows a case where a clock selection signal for supplying a reverse-phase clock signal to the SDRAM 12 is designated in the memory register 14. FIG. 3B shows an example of the configuration and connection of an external circuit when a clock selection signal for supplying a normal phase clock signal to the SDRAM 12 is designated in the memory register 14.

  The external circuit in FIG. 3A has the same configuration as that in FIG. On the other hand, in the external circuit of FIG. 3B, the clock generation circuit 23 and the switching circuit 24 are omitted, and only one system of the memory interface circuit 20 in which the memory interface circuits 21 and 22 are integrated, and the external clock signal is transmitted to the memory interface circuit 20. Connected directly to.

  Next, the operation of the semiconductor memory device of the present invention will be described with reference to FIG.

  An address and a control signal connected from the outside of the semiconductor memory device 10 are commonly connected to the internal SDRAM core 11, SDRAM core 12 and memory register 14, and the memory register 14 has a first clock signal as in the SDRAM core 11. The operation is performed at the rising edge of the external clock signal, and the setting contents (clock selection signal) of the memory register 14 are updated with the address and control signal generated by the external memory interface circuit 21. The setting contents (clock selection signal) of the memory register 14 are connected to the clock generation circuit 13a, and the second clock signal output from the clock generation circuit 13a is a normal phase clock signal or a reverse phase clock with respect to the first clock signal. Switch to a signal.

  FIG. 3A shows an external circuit configuration in which the setting contents of the memory register 14 are switched so that the second clock signal output from the clock generation circuit 13a is a reverse-phase clock signal with respect to the first clock signal. And operates in the same manner as in the first embodiment.

  FIG. 3B shows the external circuit configuration when the setting contents of the memory register 14 are switched so that the second clock signal output from the clock generation circuit 13a is a positive phase clock signal with respect to the first clock signal. The memory interface circuit 21 and the memory interface circuit 22 input / output data to / from the memory having the same address with the external clock signal having the same phase, so that the two memory interface circuits are unified and the memory interface circuit 20 is shared. be able to. The SDRAM core 11 and the SDRAM core 12 perform the same address access operation according to the address and control signal generated by the memory interface circuit 20, and the SDRAM core 11 and the SDRAM core 12 are connected to the memory interface circuit 20 to input / output data. .

  As described above, in the semiconductor memory device according to the second embodiment of the present invention, the second clock signal connected to the SDRAM core 12 is supplied to the first clock by the memory register setting operation from the outside as in the first embodiment. Since it can be set to be a reverse-phase clock signal with respect to the signal, two independent data transfer operations can be performed by performing independent address access operations on the two SDRAMs, and the number of connection lines between the address and the control signal can be increased. Can be suppressed.

  In the semiconductor memory device according to the second embodiment of the present invention, the second clock signal connected to SDRAM core 12 by an external memory register setting operation is a normal phase clock signal or a reverse phase with respect to the first clock signal. Since the clock signal can be switched, the SDRAM core 11 and the SDRAM core 12 are accessed with independent individual addresses and control signals, and the SDRAM core 11 and the SDRAM core 12 are accessed with the same addresses and control signals. The same semiconductor memory device 10 can be applied to systems having different configurations.

Embodiment 3 FIG.
In the third embodiment of the present invention, a double-speed clock signal is connected to the SDRAM core 11 and the SDRAM core 12, and the first clock enable signal and the second clock signal that become significant according to the state change for each cycle of the input clock enable signal. An example of a semiconductor memory device capable of two independent data transfer operations by performing independent address access operations on two SDRAMs by connecting the clock enable signals to SDRAM core 11 and SDRAM core 12 will be described.

  FIG. 4 is a block diagram showing an example of the semiconductor memory device according to the second embodiment of the present invention.

  In FIG. 4, the semiconductor memory device 10 includes first and second SDRAM cores (SDRAMs) 11 and 12 and a clock enable generation circuit 15. The first SDRAM 11 and the second SDRAM 12 are clocks input from individual clock enable signal lines out of clock signals input from the common clock signal line, with the data at the address specified from the common address signal line. Input / output is performed from individual data signal lines at a predetermined phase with respect to the rising edge of the period of the clock signal enabled by the enable signal. The clock enable generation circuit 15 generates a first clock enable signal to be supplied to the first SDRAM based on a change in state of the external clock enable signal for each clock cycle, and is supplied to the second SDRAM. A second clock enable signal that switches between significant and insignificant exclusively with the first clock enable signal is generated.

  The semiconductor memory device 10 receives an address and a control signal from the outside and inputs / outputs input / output data to / from the outside. Therefore, the memory interface circuits (memory I / F) 31 and 32, a clock generation circuit 33, and a switching circuit are provided. 24 is provided outside. The memory interface circuit (memory I / F) 31 is connected to the SDRAM core 11 for writing / reading, and outputs and controls its address and control signal. The memory interface circuit (memory I / F) 32 is connected to the SDRAM core 12 for writing / reading, and outputs and controls its address and control signal. The clock generation circuit 33 generates a clock enable 1 to be supplied to the memory interface circuit 31 based on the external clock signal, and is also supplied to the memory interface circuit 32 to switch between significant and non-significant exclusively with the clock enable 1. The clock enable 2 is generated, and a double speed clock signal for the external clock signal supplied to the memory interface circuits 31 and 32 and the semiconductor memory device 10 is generated. The switching circuit 24 switches the address and control signal generated by the memory interface circuit 31 and the memory interface circuit 32 based on the switching signal output by the clock generation circuit 33 and outputs the same to the semiconductor memory device 10. Here, the switching signal input to the switching circuit 24 is the clock enable 1 output from the clock generation circuit 33.

  Note that the clock enable generation circuit 15 supplies the clock enable signals to the SDRAMs 11 and 12 based on the external clock signal, but the two clock enable signals only need to have mutually exclusive cycles, and the clock enable signal supplied to the SDRAM 11 The external clock enable signal (clock enable 1) may have the same period or an exclusive period. The clock generation circuit 33 supplies a clock enable signal to the memory interface circuits 31 and 32 based on the external clock signal, but the two clock enable signals may be in mutually exclusive cycles. However, the clock enable generation circuit 15 and the clock generation circuit 33 are, for example, significant and non-significant of clock enable signals of the SDRAM 11 and the memory interface circuit 31 so that data transfer between the SDRAMs 11 and 12 and the memory interface circuits 31 and 32 is suitable. What is necessary is just to match the state change. In the following description, it is assumed that significant and non-significant state changes of the clock enable signals of the SDRAM 11 and the memory interface circuit 31 are combined.

  Next, the operation of the semiconductor memory device of the present invention will be described with reference to FIG. FIG. 5 is an explanatory diagram of operation timing when a write operation to the memory or a read operation from the memory in the configuration of the block diagram of FIG. 4 is performed.

  The memory interface circuit 31 and the memory interface circuit 32 operate at the rising edge of the double speed clock signal generated from the external clock signal supplied by the clock generation circuit 33. The clock enable 1 supplied by the clock generation circuit 33 is significant for the memory interface circuit 31. The memory interface circuit 32 operates in a cycle in which the clock enable 2 supplied from the clock generation circuit 33 is in a significant state. Here, the clock enable 1 and the clock enable 2 become significant with each other in an exclusive period. On the other hand, an external clock signal is connected to the clock enable generation circuit 15 in the semiconductor memory device 10, and the SDRAM core 11 has a significant state in the same cycle as the clock enable signal input (clock enable 1) output from the clock enable generation circuit 15. The SDRAM core 12 operates at the rising edge of the double-speed clock signal by connecting the first clock enable signal, and the SDRAM core 12 is delayed by one cycle from the clock enable signal input (clock enable 1) output from the clock enable generation circuit 15 and The second clock enable signal is connected to operate at the rising edge of the double speed clock signal.

  FIG. 6 is an explanatory diagram of operation specifications and operation timings of the clock enable generation circuit 15 included in the semiconductor memory device according to the third embodiment of the present invention. The addresses and control signals generated and output by the memory interface circuit 31 and the addresses and control signals generated and output by the memory interface circuit 32 are semiconductors as addresses and control signals switched in a time division manner by the clock enable 1 output by the clock generation circuit 33. The SDRAM interface 11 and the SDRAM core 12 connected to the storage device 10 are connected to the memory interface circuit 31 at the rising edge of the double-speed clock signal having a period in which the clock enable 1 (the same phase as the first clock enable signal) is significant. The address and the control signal are input to the SDRAM core 11, and the address and the control signal of the memory interface circuit 32 are set to SD at the rising edge of the double speed clock signal having a period in which the clock enable 2 (the same phase as the second clock enable signal) is significant. Is input to the AM core 12. Here, the clock enable 1 and the clock enable 2 output from the clock generation circuit 33 are signals that satisfy the hold and sample timing conditions when sampling is performed at the rising edge timing of the double-speed clock signal.

  In this way, the memory interface circuit 31 and the SDRAM core 11 have the clock interface 1 and the SDRAM core 12 at the rising edge of the double-speed clock signal having a period in which the clock enable 1 (the same phase as the first clock enable signal) is significant. When the clock enable 2 (the same phase as the second clock enable signal) operates at the rising edge of the double-speed clock signal having a significant period, the memory interface circuit 31 and the memory interface circuit 32 receive the address and the control signal independently of each other. The SDRAM core 11 and the SDRAM core 12 input and output data to and from the memory interface circuit 31 and the memory interface circuit 32 independently of each other.

  The external memory interface circuit 31 and the memory interface circuit 32 shown in the block diagram of FIG. 4 have been described as being provided independently. However, one memory interface circuit that functions as these two memory interface circuits. You may provide as. Further, the memory interface circuit integrated into one further incorporates a switching circuit 24 therein, and receives the switching signal from the clock generation circuit 33, and transfers the address and control signal to the SDRAM core 11 and the SDRAM core. 12 may be output directly.

  As described above, in the semiconductor memory device according to the third embodiment, the first SDRAM core 11 and the second SDRAM core 12 operate in mutually exclusive cycles, so that the two SDRAM cores are independent. By performing an address access operation, a data transfer operation independent of the two SDRAM cores can be performed.

  In the semiconductor memory device according to the third embodiment of the present invention, the address and control signal are commonly connected to first SDRAM core 11 and second SDRAM core 12, and the clock enable signal is switched by switching the address and control signal. Since the address and the control signal are given according to the input state change, an increase in the number of connection lines of the address and the control signal can be suppressed.

Embodiment 4 FIG.
In the fourth embodiment of the present invention, the second clock enable signal connected to the SDRAM core 12 is connected to the SDRAM core 11 by providing a memory register capable of setting the clock enable selection signal from the outside and operating its contents. An example of a semiconductor memory device that can be switched to be in a significant state in the same cycle as the first clock enable signal to be described will be described.

  FIG. 7 is a block diagram showing an example of the semiconductor memory device according to the fourth embodiment of the present invention.

  In FIG. 7, the semiconductor memory device 10 includes first and second SDRAM cores (SDRAMs) 11 and 12, a clock enable generation circuit 15 a, and a memory register 14. As in the third embodiment of the present invention, the first SDRAM 11 and the second SDRAM 12 are configured so that the first SDRAM 11 and the second SDRAM 12 receive the data of the address designated from the common address signal line with the common clock. Of the clock signals input from the signal lines, the individual data signal lines have the predetermined phase with respect to the rising edge of the clock signal period that is enabled by the clock enable signal input from the individual clock enable signal line. Input and output. The memory register circuit (memory register) 14 sets a clock enable selection signal that specifies a clock enable signal to be supplied to the second SDRAM 12. The clock enable generation circuit 15a generates a first clock enable signal to be supplied to the first SDRAM based on a change in state of the external clock enable signal for each clock cycle, and is exclusive of the first clock enable signal. A clock enable signal having an exclusive period that switches between significant and non-significant, and a clock enable signal having the same period as the first clock enable signal or an exclusive period based on the clock enable selection signal set in the memory register The clock enable signal is selected and supplied to the second SDRAM as the second clock enable signal.

  Therefore, the semiconductor memory device 10 of FIG. 7 is different from that of FIG. 4 in that the memory register 14 is provided in the semiconductor memory device 10 and the clock enable generation circuit 15 sets the contents of the memory register 14 (clock The clock enable generation circuit 15a supplies a second clock enable signal to the SDRAM 12 based on the enable selection signal). Although the semiconductor memory device 10 is common in FIGS. 7A and 7B, FIG. 7A designates a clock enable selection signal for supplying an enable signal clock signal of an exclusive period to the SDRAM 12 to the memory register 14. FIG. 7B shows an example of the configuration and connection of an external circuit when the clock enable selection signal for supplying the clock enable signal having the same period to the SDRAM 12 is designated in the memory register 14.

  The external circuit in FIG. 7A has the same configuration as that in FIG. On the other hand, in the external circuit of FIG. 7B, the clock generation circuit 33 and the switching circuit 24 are omitted, and only one system of the memory interface circuit 30 in which the memory interface circuits 31 and 32 are integrated is used. The memory interface circuit 30 is directly connected. In the case of FIG. 7B, an external clock signal is input to the semiconductor memory device 10 and no double speed clock signal is supplied.

  Next, the operation of the semiconductor memory device of the present invention will be described with reference to FIG.

  Addresses and control signals connected from the outside of the semiconductor memory device 10 are commonly connected to the memory register 14 in addition to the internal SDRAM core 11 and SDRAM core 12, and the memory register 14 is connected to the SDRAM core 11 and SDRAM core 12. The operation is performed at the rising edge of the same clock signal, and the setting contents (clock enable selection signal) of the memory register 14 are updated by the address and control signal generated by the external memory interface circuit 31. The setting contents of the memory register 14 are connected to the clock generation circuit 15a, and the second clock enable signal output from the clock enable generation circuit 15a is set to a clock enable signal having the same cycle as that of the first clock enable signal or exclusively significant. Switching is made so that the clock enable signal has an exclusive period in which insignificance is switched.

  FIG. 7A shows the setting contents of the memory register 14 and the clock enable of an exclusive cycle in which the second clock enable signal output from the clock generation circuit 15a is switched between significant and insignificant exclusively with the first clock enable signal. An external circuit configuration when switching to be a signal is shown, and the same operation as in the third embodiment is performed. In this case, the second clock enable signal becomes a clock enable signal that becomes significant after being delayed by one cycle with respect to the first clock enable signal.

  FIG. 7B shows the setting contents of the memory register 14 and the clock enable signal having the same period in which the second clock enable signal output from the clock generation circuit 15a is switched between significant and insignificant in synchronization with the first clock enable signal. The memory interface circuit 30 is shared so that the memory interface circuit 31 and the memory interface circuit 32 output a clock enable signal that is in a significant state in the same cycle. be able to. The SDRAM core 11 and the SDRAM core 12 perform the same address access operation according to the address and control signal generated by the memory interface circuit 30, and the SDRAM core 11 and the SDRAM core 12 form a single system for inputting / outputting data to / from the memory interface circuit 30. .

  As described above, in the semiconductor memory device according to the fourth embodiment of the present invention, the second clock enable signal connected to the SDRAM core 12 is supplied to the first memory register setting operation from the outside in the same manner as in the third embodiment. Since the clock enable signal and the exclusive period can be set to be in a significant state, two independent data transfer operations can be performed by performing independent address access operations on the two SDRAMs, and the number of connection lines between the address and the control signal Increase can be suppressed.

  In the semiconductor memory device according to the fourth embodiment of the present invention, the second clock enable signal connected to the SDRAM core 12 by the memory register setting operation from the outside is significant and insignificant in synchronization with the first clock enable signal. Therefore, the SDRAM core 11 and the SDRAM core 12 can be set with independent individual addresses and control signals. The access configuration and the access configuration using the same address and control signal can be used separately, and the same semiconductor memory device 10 can be applied to systems having different configurations.

Embodiment 5. FIG.
In the fifth embodiment of the present invention, the first clock enable signal and the second clock enable signal in the operation specifications of the clock enable generation circuit 15 shown in FIG. 6 are the same as the operation specifications of the clock enable generation circuit 15a. By performing a clock enable signal input operation that makes the cycle significant, the SDRAM core 11 and the SDRAM core 12 are operated in the same cycle for the memory refresh operation and the memory register setting operation, and the write operation and the read operation are performed in an exclusive cycle. An example of a semiconductor memory device to be operated will be described.

  FIG. 8 is a block diagram showing an example of the semiconductor memory device according to the fifth embodiment of the present invention.

  In FIG. 8, the semiconductor memory device 10 has the same configuration as that of the fourth embodiment, and an external clock signal is connected to the external memory interface circuit 41, the memory interface circuit 42, the memory control circuit 44, and the semiconductor memory device 10, The memory interface circuit 41 is connected to the SDRAM core 11 for writing / reading data, the memory interface circuit 42 is connected to the SDRAM core 12 for writing / reading data, and the memory control circuit 44 is connected to the memory interface circuit 41. An address and a start request signal generated by the memory interface circuit 42 are input and a signal indicating an operation state is transmitted to the memory interface circuit 41 and the memory interface circuit 42, whereby an address and a control signal are output to the semiconductor memory device 10. It is a circuit.

  Next, the operation of the semiconductor memory device of the present invention will be described with reference to FIG. FIG. 9 is an explanatory diagram of operation timings when a memory register setting operation and a memory writing operation or a memory reading operation are performed in the configuration of the block diagram of FIG.

  The memory interface circuit 41 and the memory interface circuit 42 operate at the rising edge of the external clock signal, and the memory interface circuit 41 and the memory interface circuit 42 are linked to the operation state of the memory control circuit 44 to address and start request to the semiconductor memory device 10. Each signal is generated and output independently. The memory control circuit 44 determines the activation request signal from the memory interface circuit 41 and the memory interface circuit 42, and the memory interface circuit 41 and the memory interface circuit 42 according to the case where the common operation is requested and the case where the common operation is not requested. The operation cycle is adjusted using a signal indicating the operation state transmitted to the memory, and an address, a start request signal, and a clock enable signal are output to the semiconductor memory device 10.

  On the other hand, an external clock signal is connected to the clock enable generation circuit 15a in the semiconductor memory device 10, and the SDRAM core 11 is in a significant state in the same cycle as the clock enable signal input (clock enable 1) output from the clock enable generation circuit 15a. The SDRAM core 12 is delayed by one cycle from the clock enable signal input (clock enable 1) output from the clock enable generation circuit 15a and connected to the significant state. The second clock enable signal is connected to operate at the rising edge of the external clock signal. By continuously giving the significant state of the clock enable signal input, the SDRAM core 11 and the SDRAM core 12 input the address and the control signal output from the memory control circuit 44 in the same cycle, and the SDRAM core 11 and the SDRAM core 12 The same operation is executed in the same cycle, and data is input / output to / from the memory interface circuit 41 and the memory interface circuit.

  Here, the clock enable signal input changes from the insignificant state to the significant state, and after that, the significant state continues for the number of periods that require common operation, and then becomes insignificant. From the memory control circuit 44, a NOP (no operation) command is issued in the period in which the memory control circuit 44 first changed to the significant state and the period in which the significant state changed to the non-significant state. By alternately applying a significant state and a non-significant state to the clock enable signal input, the SDRAM core 11 and the SDRAM core 12 input / output data to / from the memory interface circuit 41 and the memory interface circuit 42 independently of each other.

  The external memory interface circuit 41 and the memory interface circuit 42 shown in the block diagram of FIG. 8 have been described as being provided independently. However, one memory interface circuit that performs the functions of these two memory interface circuits. You may provide as.

  As described above, in the semiconductor memory device according to the fifth embodiment of the present invention, as in the third embodiment, two independent data transfer operations can be performed by performing independent address access operations on two SDRAMs. And an increase in the number of connection lines of control signals can be suppressed.

  In the semiconductor memory device according to the fifth embodiment of the present invention, as in the fourth embodiment, the second clock enable signal connected to the SDRAM core 12 by the memory register setting operation from the outside is used as the first clock enable signal. Therefore, the SDRAM core 11 and the SDRAM core 12 can be used separately from the configuration in which the SDRAM core 11 and the SDRAM core 12 are accessed with independent individual addresses and control signals, and the configuration in which the SDRAM is accessed with the same addresses and control signals. The same semiconductor memory device 10 can be applied to systems having different configurations.

  Furthermore, in the semiconductor memory device according to the fifth embodiment of the present invention, the clock enable signal includes a configuration in which SDRAM core 11 and SDRAM core 12 are operated in the same cycle, and a configuration in which write operation and read operation are respectively operated in exclusive cycles. Since the operation can be performed by controlling the input, the memory access efficiency of the entire system can be improved.

  In the second embodiment, the fourth embodiment, and the fifth embodiment described so far, the memory register 14 for setting the clock selection signal or the clock enable selection signal indicated by 1 bit is dedicated to the inside of the semiconductor memory device 10. When it is configured to directly write / read by providing as a memory, it is not necessary to specify an address. Further, when the memory register 14 is arranged in the SDRAM memory mode register to perform writing / reading, it is necessary to designate an address on the memory mode register. As described above, the memory register 14 can be configured regardless of the necessity of address designation, and can be mounted on the semiconductor memory device 10.

  As described above, in the semiconductor memory device according to the embodiment of the present invention, two SDRAMs having the same clock speed and internal operation speed are included in one package, and the data input / output bus width of the memory device is doubled to increase the data transfer bandwidth. It is possible to perform two independent data transfer operations by performing independent address access operations on the two SDRAMs without increasing addresses and control signals.

1 is a block configuration diagram showing an example of a semiconductor memory device according to a first embodiment of the present invention. It is explanatory drawing which shows the operation | movement timing of the block block diagram which shows one Example of the semiconductor memory device in Embodiment 1 of this invention. It is a block block diagram which shows one Example of the semiconductor memory device in Embodiment 2 of this invention. It is a block block diagram which shows one Example of the semiconductor memory device in Embodiment 3 of this invention. It is explanatory drawing which shows the operation | movement timing of the block block diagram which shows one Example of the semiconductor memory device in Embodiment 3 of this invention. It is explanatory drawing which shows the operation | movement specification and operation | movement timing of a clock enable generation circuit contained in one Example of the semiconductor memory device in Embodiment 3 of this invention. It is a block block diagram which shows one Example of the semiconductor memory device in Embodiment 4 of this invention. It is a block block diagram which shows one Example of the semiconductor memory device in Embodiment 5 of this invention. It is explanatory drawing which shows the operation | movement timing of the block block diagram which shows one Example of the semiconductor memory device in Embodiment 5 of this invention. It is a block block diagram which shows the conventional semiconductor memory device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor memory device 11, 12 SDRAM core 13, 13a Clock generation circuit 14 Memory register circuit (memory register)
15, 15a Clock enable generation circuit 20, 21, 22 Memory interface circuit (memory I / F)
23 clock generation circuit 24 switching circuit 30, 31, 32 memory interface circuit (memory I / F)
33 Clock generation circuit 41, 42 Memory interface circuit (memory I / F)
44 Memory control circuit

Claims (4)

First and second input / output of address data designated by a common address signal line from the individual data signal lines at a predetermined phase with respect to the rising edge of the clock signal inputted from the individual clock signal lines SDRAM of
A second clock signal that generates a first clock signal to be supplied to the first SDRAM based on an external clock signal and is supplied to the second SDRAM and has a phase opposite to that of the first clock signal. A semiconductor memory device comprising a clock generation circuit for generating First and second input / output of address data designated by a common address signal line from the individual data signal lines at a predetermined phase with respect to the rising edge of the clock signal inputted from the individual clock signal lines SDRAM of
A memory register for setting the clock selection signal;
Generating a first clock signal to be supplied to the first SDRAM based on an external clock signal, generating a reverse phase clock signal having a reverse phase with the first clock signal as a normal phase clock signal, A clock generation circuit that selects the normal phase clock signal or the reverse phase clock signal based on a clock selection signal set in a memory register and supplies the selected clock signal to the second SDRAM as a second clock signal. A semiconductor memory device. The data of the address designated from the common address signal line is the clock signal valid from the clock enable signal inputted from the individual clock enable signal line among the clock signals inputted from the common clock signal line. First and second SDRAMs that input and output from individual data signal lines at a predetermined phase with respect to the rising edge;
A first clock enable signal to be supplied to the first SDRAM is generated based on a change in state of the external clock enable signal for each cycle of the clock signal, and the first clock enable signal is supplied to the second SDRAM. And a clock enable generation circuit for generating a second clock enable signal that is switched between significant and insignificant exclusively. The data of the address designated from the common address signal line is the clock signal valid from the clock enable signal inputted from the individual clock enable signal line among the clock signals inputted from the common clock signal line. First and second SDRAMs that input and output from individual data signal lines at a predetermined phase with respect to the rising edge;
A memory register for setting a clock enable selection signal;
A first clock enable signal to be supplied to the first SDRAM is generated based on a change in state of the external clock enable signal for each cycle of the clock signal, and is exclusively significant to the first clock enable signal. And a clock enable signal having an exclusive period in which the insignificant is switched, and based on a clock enable selection signal set in the memory register, the clock enable signal having the same period as the first clock enable signal or the exclusive period A semiconductor memory device comprising: a clock enable generation circuit that selects a clock enable signal and supplies the second SDRAM as a second clock enable signal.

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